Stacked integrated circuit devices

Abstract

A stacked integrated circuit device is disclosed. The stacked integrated circuit device can include a standard cell including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each standard cell can include an upper transistor and a lower transistor. The upper transistor can include an upper active region, an upper gate structure, and an upper source / drain region. The lower transistor can include a lower active region, a lower gate structure, and a lower source / drain region. Each standard cell can also include a power line and a power via electrically connecting the power line to the lower source / drain region. The power via of the first standard cell and the power via of the second standard cell can be aligned with each other along a first direction.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 034,525, filed June 4, 2020, entitled “STACKED DEVICES”, and U.S. Non-Provisional Application No. 16 / 947,241, filed July 24, 2020, entitled “STACKED INTEGRATED CIRCUIT DEVICES”, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to the field of electronics, and more specifically to stacked (or “stacked”) integrated circuit devices. Background Technology

[0003] Stacked integrated devices, including standard cells, have been studied due to their high integration density. However, stacked integrated devices require additional space adjacent to the cell boundaries for electrical isolation between components in adjacent standard cells, thus increasing the device size. Summary of the Invention

[0004] According to some embodiments of the present invention, an integrated circuit device may include a plurality of standard cells arranged on a substrate in multiple rows, all extending in a first direction. The plurality of standard cells may include a first standard cell in a first row and a second standard cell in a second row adjacent to the first row. Each of the plurality of standard cells may include an upper transistor and a lower transistor located between the substrate and the upper transistor. The upper transistor may include an upper active region, an upper gate structure located on the upper active region, and an upper source / drain region located on the upper active region. The lower transistor may include a lower active region, a lower gate structure located on the lower active region, and a lower source / drain region located on the lower active region. Each of the plurality of standard cells may further include a power line and a power via electrically connecting the power line to the lower source / drain region. The power vias of the first standard cell and the second standard cell may be aligned with each other along the first direction.

[0005] According to some embodiments of the present invention, an integrated circuit device may include a plurality of standard cells arranged on a substrate in multiple rows, all extending in a first direction. The plurality of standard cells may include a first standard cell in a first row and a second standard cell in a second row adjacent to the first row. The integrated circuit device may also include a common power line extending along the interface between the first and second rows. Each of the plurality of standard cells may include an upper transistor and a lower transistor located between the substrate and the upper transistor. The upper transistor may include an active region, an upper gate structure located on the active region, and a first upper source / drain region and a second upper source / drain region located on the active region. The lower transistor may include a lower active region, a lower gate structure located on the lower active region, and a first lower source / drain region and a second lower source / drain region located on the lower active region. Each of the plurality of standard cells may also include a power via electrically connecting the common power line to the first lower source / drain region and an output via electrically connecting the second lower source / drain region and the second upper source / drain region. The power via of the first standard unit can be spaced apart from the output via of the first standard unit by a first distance in a first direction, and the power via of the second standard unit can be spaced apart from the output via of the second standard unit by a second distance in a second direction perpendicular to the first direction, and the first distance can be different from the second distance.

[0006] According to some embodiments of the present invention, an integrated circuit device may include a plurality of first standard cells arranged in a first direction and a plurality of second standard cells arranged in the first direction and contacting the plurality of first standard cells. The interface between the plurality of first standard cells and the plurality of second standard cells may define a cell boundary. Each of the plurality of first standard cells and the plurality of second standard cells may include an upper transistor located on a substrate and a lower transistor located between the substrate and the upper transistor. The upper transistor may include an upper active region, an upper gate structure located on the upper active region, and an upper source / drain region located on the upper active region. The lower transistor may include a lower active region, a lower gate structure located on the lower active region, and a lower source / drain region located on the lower active region. The plurality of first standard cells and the plurality of second standard cells may further include output vias electrically connecting the lower source / drain region and the upper source / drain region. The plurality of first standard cells may include first standard cells, and the output vias of the first standard cells are superimposed on the cell boundary. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of an inverter according to some embodiments of the present invention.

[0008] Figure 2A and Figure 2B These are some embodiments of the concept of the present invention. Figure 1 A perspective view of an inverter.

[0009] Figure 3 This is a schematic layout of two standard units, each standard unit including... Figure 1 Inverter.

[0010] Figure 4 This is a schematic layout of an integrated circuit device comprising multiple standard units according to some embodiments of the present invention.

[0011] Figure 5A , Figure 5B and Figure 5C These are some embodiments of the concept of the present invention, respectively along... Figure 4 A sectional view taken from lines A-A', B-B', and C-C'.

[0012] Figure 6 This is a schematic layout of an integrated circuit device comprising multiple standard units according to some embodiments of the present invention.

[0013] Figure 7 This is a schematic layout of an integrated circuit device comprising multiple standard units according to some embodiments of the present invention.

[0014] Figure 8 It is along some embodiments of the concept of the present invention. Figure 7 A sectional view taken by line D-D'.

[0015] Figure 9 This is a circuit diagram of an inverter with double the height according to some embodiments.

[0016] Figure 10 This is a schematic layout of an integrated circuit device comprising multiple standard units according to some embodiments of the present invention.

[0017] Figure 11A and Figure 11B These are some embodiments of the concept of the present invention, respectively along... Figure 10 A sectional view taken from lines E-E' and F-F'.

[0018] Figure 12A and Figure 12B These are some embodiments of the concept of the present invention, respectively along... Figure 10 A sectional view taken from lines E-E' and F-F'. Detailed Implementation

[0019] Stacked (hereinafter referred to as "stacked") standard cells are introduced to reduce their area to approximately half that of their corresponding non-stacked standard cells. However, when two stacked standard cells that are adjacent to each other in the cell height direction both include their respective output vias adjacent to the cell boundary between them, additional space must be provided between the output vias to allow for electrical isolation of the output vias. According to some embodiments of the invention, stacked standard cells can be designed and arranged such that the output via of only one of two standard cells that are adjacent to each other in the cell height direction is placed adjacent to the cell boundary between them, thus eliminating the need for additional space between the output vias. As used herein, the phrase "two elements adjacent to each other" (or similar language) refers to a configuration in which two elements are adjacent to each other without any other similar elements positioned between them. For example, when no intermediate standard cell is provided between two standard cells in the cell height direction, the two standard cells are adjacent to each other in the cell height direction.

[0020] According to some embodiments of the present invention, a single integrated circuit device (e.g., a single chip) may include multiple standard cells. Standard cells may be, for example, inverters (or "NOT gates"), 2-input NAND gates, 3-input NAND gates, 2-input NOR gates, 3-input NOR gates, AND-OR-NOT gates (AOI), OR-AND-NOT gates (OAI), XNOR gates (XNOR gates), XOR gates (XOR gates), multiplexers (MUX), latches, or D flip-flops.

[0021] For ease of explanation, the standard cell of the integrated circuit device according to the exemplary embodiments of the present invention is described herein as an inverter. However, the integrated circuit device according to some embodiments of the present invention may include various standard cells, such as 2-input NAND gates and OAI gates. Furthermore, in most exemplary embodiments of the present invention, for ease of explanation, the standard cell is described as a horizontal channel device in which the channel current flows in a horizontal direction parallel to the surface of the substrate. However, in some embodiments, the standard cell may be a vertical channel device in which the channel current flows in a vertical direction perpendicular to the surface of the substrate. A vertical channel device may include a vertical field-effect transistor (VFET).

[0022] Figure 1 This is a circuit diagram of an inverter according to some embodiments of the present invention. Figure 2A and Figure 2B These are some embodiments of the concept of the present invention. Figure 1 A perspective view of an inverter. For simplicity, in... Figure 2A and Figure 2BThe diagram shows groups of elements for individual inverters, therefore Figure 2A and Figure 2B Each diagram in the image shows some (but not all) components of a single inverter.

[0023] Reference Figure 1 , Figure 2A and Figure 2B An inverter may include a lower transistor TR_L (e.g., an N-type transistor) and an upper transistor TR_U (e.g., a P-type transistor). The lower transistor TR_L and the upper transistor TR_U can be configured to receive a common input INPUT and can be configured to output a common output OUTPUT. Although in Figure 2A and Figure 2B Not shown, but various insulating layers can be provided between components (e.g., Figure 5A The first insulating layer 42, the second insulating layer 44 and the third insulating layer 46 are used for electrical isolation between these components.

[0024] The lower transistor TR_L can be connected to the first power supply line P1, and the upper transistor TR_U can be connected to the second power supply line P2. The first power supply line P1 can be connected to a first power source having a first voltage (e.g., source voltage). For example, the first voltage could be the electrical ground voltage. The second power supply line P2 can be connected to a second power source having a second voltage (e.g., leakage voltage). As used herein, the phrase "component A is connected to component B" (or similar language) means that component A is physically and / or electrically connected to component B.

[0025] In some embodiments, such as Figure 2A As shown, each of the first power line P1 and the second power line P2 may extend in a first direction X and may be spaced apart from each other in a second direction Y. The first direction X may be parallel to the substrate (e.g., Figure 5A The first direction (Y) is parallel to the surface of the substrate (100) and may be referred to as the first horizontal direction. The second direction (Y) may also be parallel to the surface of the substrate and may be referred to as the second horizontal direction. The first direction (X) may traverse the second direction. In some embodiments, the first direction (X) may be perpendicular to the second direction (Y). As used herein, “element A extends in direction B” (or similar language) means that element A extends longitudinally in direction B.

[0026] The lower transistor TR_L may include a lower active region 22_L and a first lower source / drain region 26_L1 and a second lower source / drain region 26_L2 located on the lower active region 22_L. In some embodiments, such as Figure 2AAs shown, the lower active region 22_L can extend in the first direction X. The first lower source / drain region 26_L1 and the second lower source / drain region 26_L2 can contact the lower active region 22_L and can be spaced apart from each other in the first direction X. As used herein, "active region" refers to the region that forms the channel of the transistor when the transistor is turned on. Therefore, "active region" can be interchanged with "channel region".

[0027] The first source / drain region 26_L1 can be electrically connected to the first power line P1 through a first power via 20. In some embodiments, the first power via 20 can contact the first power line P1 and can protrude from the first power line P1 in a third direction Z. The third direction Z can be perpendicular to both the first direction X and the second direction Y, and can be referred to as the vertical direction. In some embodiments, such as Figure 2B As shown, the first power via 20 can contact the first lower source / drain region 26_L1. However, in some embodiments, the first power via 20 and the first lower source / drain region 26_L1 can be connected via wiring contacts (e.g., Figure 5A The first lower wiring contact 27_L1 in the middle is electrically connected.

[0028] The upper transistor TR_U may include an upper active region 22_U and a first upper source / drain region 26_U1 and a second upper source / drain region 26_U2 located on the upper active region 22_U. In some embodiments, such as Figure 2A As shown, the upper active region 22_U can extend in the first direction X. The first upper source / drain region 26_U1 and the second upper source / drain region 26_U2 can contact the upper active region 22_U and can be spaced apart from each other in the first direction X.

[0029] although Figure 2A and Figure 2B Each of the lower active region 22_L and the upper active region 22_U is shown as a single active region with a specific shape, but the inventive concept is not limited thereto. In some embodiments, each of the lower active region 22_L and the upper active region 22_U may include a plurality of nanosheets stacked on a third-direction Z, and each of the lower transistor TR_L and the upper transistor TR_U may be a multi-bridge channel field-effect transistor (MBCFET).

[0030] The first source / drain area 26_U1 can be electrically connected to the second power line P2 via a vertical direct contact 28 and a second power via 30. In some embodiments, the vertical direct contact 28 can be omitted, and the first source / drain area 26_U1 can contact the second power via 30. The second power via 30 can contact the second power line P2 and can protrude from the second power line P2 in the third direction Z.

[0031] In some embodiments, such as Figure 2BAs shown, the second power via 30 can contact the first upper source / drain region 26_U1. However, in some embodiments, the second power via 30 and the first upper source / drain region 26_U1 can be connected via wiring contacts (e.g., Figure 5A The first upper wiring contact 27_U1 in the middle is electrically connected.

[0032] The inverter may further include a gate structure 24 located on the lower active region 22_L and the upper active region 22_U. In some embodiments, the gate structure 24 may contact both the lower active region 22_L and the upper active region 22_U, and therefore may be shared by the lower transistor TR_L and the upper transistor TR_U. The lower portion of the gate structure 24 may be located between the first lower source / drain region 26_L1 and the second lower source / drain region 26_L2, and may be referred to as the lower gate structure. The upper portion of the gate structure 24 may be located between the first upper source / drain region 26_U1 and the second upper source / drain region 26_U2, and may be referred to as the upper gate structure. Although Figure 2A The diagram shows that the lower and upper portions of the gate structure 24 are part of a single gate structure 24, but the inventive concept is not limited thereto. In some embodiments, the lower and upper portions of the gate structure 24 may be separate gate structures spaced apart from each other. Furthermore, although... Figure 2A The gate structure 24 is shown as a single layer, but the gate structure 24 may include multiple layers comprising gate insulators and gate electrodes sequentially stacked on the surface of the lower active region 22_L and the surface of the upper active region 22_U.

[0033] Gate structure 24 can be electrically connected to the input node via lower via 32, first metal via 34_1, and first metal line 36_1. The first metal line 36_1 can be connected as follows: Figure 2A As shown, it extends in the second direction Y, but the inventive concept is not limited thereto. In some embodiments, the first metal line 36_1 may extend in the first direction X. In some embodiments, the lower via 32 may be omitted, and the gate structure 24 may contact the first metal via 34_1.

[0034] The second lower source / drain region 26_L2 and the second upper source / drain region 26_U2 can be electrically connected to each other through an output via 10. In some embodiments, the output via 10 can contact both the second lower source / drain region 26_L2 and the second upper source / drain region 26_U2. In some embodiments, the second upper source / drain region 26_U2 can be connected through wiring contacts (e.g., Figure 5C The second upper wiring contact 27_U2 is electrically connected to the output via 10, and the second lower source / drain region 26_L2 can be connected via the wiring contact (e.g., Figure 5C The second lower wiring contact 27_L2 is electrically connected to the output via 10.

[0035] The second source / drain region 26_U2 can be electrically connected to the output node via the second metal via 34_2 and the second metal wire 36_2. The second metal wire 36_2 can be connected as follows: Figure 2B As shown, it extends in the second direction Y, but the inventive concept is not limited thereto. In some embodiments, the second metal wire 36_2 may extend in the first direction X.

[0036] Figure 3 This is a schematic layout of two standard cells (e.g., lower standard cell SC_L and upper standard cell SC_U), each standard cell including... Figure 1 An inverter. For simplicity of illustration, Figure 3 Only power lines (e.g., first power line P1 and second power line P2) and vias (output via 10, first power via 20, and second power via 30) are shown. Dashed lines indicate cell boundaries.

[0037] Reference Figure 3 When lower standard cells SC_L and upper standard cells SC_U, which are adjacent to each other in the second direction Y, have their output vias 10 adjacent to the cell boundary CB between them, a space must be provided between the output vias 10 for electrical isolation between them. The output vias 10 of the lower standard cell SC_L and the upper standard cell SC_U can be spaced apart from the cell boundary CB. Therefore, in some embodiments, the first width W1 of the power line between the standard cells (e.g., the second power line P2) can be larger than twice the second width W2 of each output via 10. The space between the output vias 10 of the lower standard cell SC_L and the upper standard cell SC_U can accommodate a cell height H of each of the lower standard cell SC_L and the upper standard cell SC_U. CELL Increase.

[0038] Figure 4 This is a schematic layout of an integrated circuit device comprising multiple standard units, according to some embodiments of the present invention. For the sake of simplicity, Figure 4 Only the power cord and vias are shown. Figure 5A , Figure 5B and Figure 5C These are some embodiments of the concept of the present invention, respectively along... Figure 4 A sectional view taken from lines A-A', B-B', and C-C'.

[0039] Reference Figure 4The integrated circuit device may include multiple standard cells (e.g., first standard cell SC1, second standard cell SC2, third standard cell SC3, fourth standard cell SC4, and fifth standard cell SC5) arranged in multiple rows. Each standard cell may extend in a first direction X and be spaced apart from each other in a second direction Y. The first row may include the first standard cell SC1 and the fourth standard cell SC4. The second row, which is adjacent to the first row in the second direction Y, may include the second standard cell SC2 and the third standard cell SC3. The third row, which is also adjacent to the first row in the second direction Y, may include the fifth standard cell SC5. The first row may be disposed between the second and third rows. The first row may contact the second row, and the interface between the first and second rows defines a cell boundary CB.

[0040] In some embodiments, the first standard unit SC1, the second standard unit SC2, and the third standard unit SC3 may be units of the same type. For example, each of the first standard unit SC1, the second standard unit SC2, and the third standard unit SC3 may include Figure 1 , Figure 2A and Figure 2B The inverter shown is an example. The fourth standard unit SC4 can be a 2-input NOR gate, and the fifth standard unit SC5 can be a standard unit with multiple outputs.

[0041] Output vias 10_1, 10_2, 10_3, 10_4, and 10_5 are the output vias of the first standard cell SC1, the second standard cell SC2, the third standard cell SC3, the fourth standard cell SC4, and the fifth standard cell SC5, respectively. According to some embodiments of the present invention, only one of two adjacent standard cells in the second direction Y can have its output via adjacent to the cell boundary CB between them, and these output vias can be... Figure 4 The arrangement shown is along the cell boundary CB.

[0042] The first standard unit SC1 and the third standard unit SC3 are adjacent to each other in the second direction Y, and only the first standard unit SC1 has its output via 10_1 adjacent to the unit boundary CB located between the first standard unit SC1 and the third standard unit SC3. The third standard unit SC3 has its output via 10_3 adjacent to the unit boundary CB opposite to the unit boundary CB between the first standard unit SC1 and the third standard unit SC3. Therefore, the additional space used for electrical isolation between the output via 10_1 of the first standard unit SC1 and the output via 10_3 of the third standard unit SC3 does not need to be set to be adjacent to the unit boundary CB between the first standard unit SC1 and the third standard unit SC3, and the unit height of each of the first standard unit SC1 and the third standard unit SC3 can be reduced. In some embodiments of the present invention, the third width W3 of the power line (e.g., the first power line P1) between the standard units (e.g., the first standard unit SC1 and the third standard unit SC3) can be narrower than twice the second width W2 of each of the output vias (e.g., 10_1 and 10_3). In some embodiments, the third width W3 of the power line can be equal to the second width W2 of the output via.

[0043] In some embodiments, the output via 10_1 of the first standard cell SC1 may be superimposed on the cell boundary CB between the first standard cell SC1 and the third standard cell SC3. In some embodiments, such as Figure 4 As shown, the center of the output via 10_1 of the first standard unit SC1 in the second direction Y can overlap with the unit boundary CB between the first standard unit SC1 and the third standard unit SC3. In some embodiments, such as Figure 4 As shown, the output vias (e.g., 10_1, 10_3, and 10_5) of the standard cells (e.g., first standard cell SC1, third standard cell SC3, and fifth standard cell SC5) arranged in the second direction Y can be aligned in the second direction Y. The phrase "element A stacked with element B" (or similar language) as used herein means that there exists a vertical line intersecting both element A and element B. Furthermore, the phrase "center of element A in the second direction Y" (or similar language) as used herein refers to the axis of element A centered in the second direction Y and extending in the first direction X.

[0044] Still refer to Figure 4The integrated circuit device may include a first power via 20_13 shared by the first standard unit SC1 and the third standard unit SC3, a first power via 20_24 shared by the second standard unit SC2 and the fourth standard unit SC4, a first power via 20_5 shared by the fifth standard unit SC5, a second power via 30_15 shared by the first standard unit SC1 and the fifth standard unit SC5, a second power via 30_2 shared by the second standard unit SC2, a second power via 30_3 shared by the third standard unit SC3, and a second power via 30_4 shared by the fourth standard unit SC4.

[0045] In some embodiments, such as Figure 4 As shown, the power vias (e.g., first power vias 20_13 and 20_24) of standard cells (e.g., first standard cell SC1 and second standard cell SC2) in two adjacent rows in the second direction Y can be aligned in the first direction X and can be spaced apart from each other by twice the contact polypropylene pitch (CPP) of the integrated circuit device. Furthermore, as... Figure 4 As shown, the power vias (e.g., second power vias 30_2 and 30_3) of the standard cells (e.g., second standard cell SC2 and third standard cell SC3) in the same row can be aligned in the first direction X and can be spaced apart from each other by twice the CPP of the integrated circuit device.

[0046] In some embodiments, one of the first power vias 20_5 of the fifth standard cell SC5 may be omitted, and the first power vias of the standard cells in the same row may be spaced apart from each other by a distance longer than 2CPP. In some embodiments, the integrated circuit device may include at least one power via (e.g., a second power via 30_4) that may not be shared by two standard cells that are adjacent to each other in the second direction Y.

[0047] The first power via 20_13 of the first standard unit SC1 can be spaced apart from the output via 10_1 of the first standard unit SC1 by a first distance in the first direction X, and the first power via 20_24 of the second standard unit SC2 can be spaced apart from the output via 10_2 of the second standard unit SC2 by a second distance in the second direction Y.

[0048] Reference Figure 4 and Figure 5A The first standard unit SC1 and the third standard unit SC3 can be disposed on the substrate 100. For example... Figure 5AAs shown, the first power line P1 and the second power line P2 may be disposed in the substrate 100, but the inventive concept is not limited thereto. In some embodiments, the first power line P1 and the second power line P2 may be disposed on the surface of the substrate 100, or may be spaced apart from the surface of the substrate 100 in a third direction Z. The first standard unit SC1 may contact the third standard unit SC3, and the interface between the first standard unit SC1 and the third standard unit SC3 may define the unit boundary CB.

[0049] The first standard cell SC1 and the third standard cell SC3 may share a first power via 20_13 (also referred to as a shared first power via or common first power via) and a first power line P1 (also referred to as a shared first power line or common first power line). The first power via 20_13 may be superimposed on the cell boundary CB located between the first standard cell SC1 and the third standard cell SC3. In some embodiments, such as Figure 4 and Figure 5A As shown, the center of the first power via 20_13 in the second direction Y can be aligned with the cell boundary CB located between the first standard cell SC1 and the third standard cell SC3 along the third direction Z. The first power line P1 can also overlap with the cell boundary CB located between the first standard cell SC1 and the third standard cell SC3. In some embodiments, as Figure 4 and Figure 5A As shown, the center of the first power line P1 in the second direction Y can be superimposed on the cell boundary CB located between the first standard cell SC1 and the third standard cell SC3.

[0050] The first lower source / drain region 26_L1 of the first standard unit SC1 and the first lower source / drain region 26_L1 of the third standard unit SC3 can be electrically connected to the first power via 20_13 via a first lower wiring contact 27_L1. In some embodiments, the first lower wiring contact 27_L1 can be omitted, and each of the first lower source / drain regions 26_L1 of the first standard unit SC1 and the third standard unit SC3 can contact the first power via 20_13.

[0051] The first standard unit SC1 may include a second power via 30_15 shared with the fifth standard unit SC5. For simplicity of illustration, in... Figure 5AThe components of the fifth standard unit SC5 are not shown. The first upper source / drain region 26_U1 of the first standard unit SC1 can be electrically connected to the second power via 30_15 via the first upper wiring contact 27_U1. The third standard unit SC3 may include a second power via 30_3 that can be electrically connected to the first upper source / drain region 26_U1 of the third standard unit SC3 via the first upper wiring contact 27_U1. In some embodiments, the first upper wiring contact 27_U1 of the first standard unit SC1 and the first upper wiring contact 27_U1 of the third standard unit SC3 may be omitted, and the first upper source / drain region 26_U1 of the first standard unit SC1 and the first upper source / drain region 26_U1 of the third standard unit SC3 may contact the second power vias 30_15 and 30_3, respectively.

[0052] Each of the second power vias 30_15 and 30_3 can be stacked with the cell boundary CB. In some embodiments, such as Figure 5A As shown, the center of each of the second power vias 30_15 and 30_3 in the second direction Y can be aligned with the corresponding cell boundary CB along the third direction Z.

[0053] The first standard unit SC1 and the third standard unit SC3 may further include a first insulating layer 42, a second insulating layer 44 and a third insulating layer 46 to electrically isolate the components therein (e.g., the first upper wiring contact 27_U1).

[0054] Reference Figure 5B The gate structure 24 of each of the first standard cell SC1 and the third standard cell SC3 may surround the lower active region 22_L and the upper active region 22_U. Each of the first standard cell SC1 and the third standard cell SC3 may include a first metal via 34_1 electrically connected to the gate structure 24. The gate structure 24 of the first standard cell SC1 and the gate structure 24 of the third standard cell SC3 may be electrically isolated from each other through a first insulating layer 42, a second insulating layer 44, and a third insulating layer 46.

[0055] Reference Figure 5CEach of the first standard unit SC1 and the third standard unit SC3 may include a second lower source / drain region 26_L2 and a second upper source / drain region 26_U2 electrically connected to each other through output vias 10_1 and 10_3. The second lower source / drain region 26_L2 and the second upper source / drain region 26_U2 may be electrically connected to output via 10_1 or output via 10_3 through a second lower wiring contact 27_L2 and a second upper wiring contact 27_U2, respectively. However, in some embodiments, the second lower wiring contact 27_L2 and the second upper wiring contact 27_U2 may be omitted, and the second lower source / drain region 26_L2 and the second upper source / drain region 26_U2 may contact output via 10_1 or output via 10_3. Each of the first standard unit SC1 and the third standard unit SC3 may also include a second metal via 34_2 electrically connected to the second upper wiring contact 27_U2.

[0056] Reference Figure 4 and 5C The first standard unit SC1 is a first type of standard unit including an output via 10_1 adjacent to the first power via 20_13 of the first standard unit SC1. In some embodiments, such as Figure 5C As shown, the output via 10_1 of the first standard unit SC1 can be stacked with the first power line P1 and with the cell boundary CB between the first standard unit SC1 and the third standard unit SC3. Conversely, the third standard unit SC3 is a second type of standard unit including an output via 10_3 adjacent to the second power via 30_3 of the third standard unit SC3. The second power via 30_3 can be stacked with the second power line P2 and with the cell boundary CB opposite to the cell boundary CB between the first standard unit SC1 and the third standard unit SC3. The second standard unit SC2 can also be a second type of standard unit including an output via 10_2 adjacent to the second power via 30_2 of the second standard unit SC2.

[0057] According to some embodiments of the present invention, different types of standard cells (e.g., first standard cell SC1 and third standard cell SC3) can be placed in two adjacent rows along the cell height direction (e.g., the second direction Y), so that the output vias of different types of standard cells can be spaced apart from each other in the cell height direction.

[0058] Figure 6 This is a schematic layout of an integrated circuit device comprising multiple standard units, according to some embodiments of the present invention. For the sake of simplicity, Figure 6 Only power lines and vias are shown. Except for the distance between two power vias in the same row, Figure 6 The integrated circuit device shown may be similar to that referenced herein. Figure 4, Figure 5A , Figure 5B and Figure 5C The integrated circuit device under discussion. (Refer to...) Figure 6 In some embodiments, two power vias of a standard cell in the same row (e.g., first power vias 20_13 and 20_24 or second power vias 30_3 and 30_2) may be spaced apart from each other in the first direction X by three times the contact polycrystalline pitch (CPP) of the integrated circuit device.

[0059] Figure 7 This is a schematic layout of an integrated circuit device comprising multiple standard units, according to some embodiments of the present invention. For the sake of simplicity, Figure 7 Only the power cable and via are shown. Except for the location of the second power via, Figure 7 The integrated circuit device shown may be similar to that referenced herein. Figure 4 , Figure 5A , Figure 5B and Figure 5C The integrated circuit device under discussion. Figure 8 It is along some embodiments of the concept of the present invention. Figure 7 A sectional view taken by line D-D'.

[0060] Reference Figure 7 and Figure 8 Each standard cell may include a first power via (e.g., first power via 20_13) and a second power via (e.g., second power via 30_13) superimposed on the first power via of each standard cell. The first standard cell SC1 and the third standard cell SC3 may share the second power via 30_13 (also referred to as a shared second power via or common second power via) and the third metal via 34_3 (also referred to as a shared third metal via or common third metal via). The first upper source / drain region 26_U1 of the first standard cell SC1 and the first upper source / drain region 26_U1 of the third standard cell SC3 can be electrically connected to a second power line P2 having a second voltage (e.g., a drain voltage) through the shared second power via 30_13 and the shared third metal via 34_3. The second power via 30_13 may be superimposed on the cell boundary CB between the first standard cell SC1 and the third standard cell SC3. In some embodiments, such as Figure 7 and Figure 8 As shown, the center of the second power via 30_13 in the second direction Y can overlap with the cell boundary CB between the first standard cell SC1 and the third standard cell SC3.

[0061] According to some embodiments of the present invention, an integrated circuit device may include a double-height standard cell having a wider channel width compared to a single height standard cell.

[0062] Figure 9 This is a circuit diagram of an inverter with double the height according to some embodiments. Figure 10 This is a schematic layout of an integrated circuit device comprising multiple standard units, according to some embodiments of the present invention. For the sake of simplicity, Figure 10 Only the power cord and vias are shown. Figure 11A and Figure 11B These are some embodiments of the concept of the present invention, respectively along... Figure 10 The cross-sectional views are taken along lines E-E' and F-F'. Except for the double-height standard element DSC, which is located in the positions of the first standard element SC1 and the third standard element SC3. Figure 10 , Figure 11A and Figure 11B The integrated circuit device shown may be similar to that referenced herein. Figure 4 , Figure 5A , Figure 5B and Figure 5C The described integrated circuit device.

[0063] In some embodiments, Figure 10 The double-height standard unit DSC in the middle can be Figure 9 The inverter. (Refer to...) Figure 9 An inverter may include a first inverter INV1 and a second inverter INV2. The first inverter INV1 may include a first P-type transistor PTR_1 as the upper transistor and a first N-type transistor NTR_1 as the lower transistor. The second inverter INV2 may include a second P-type transistor PTR_2 as the upper transistor and a second N-type transistor NTR_2 as the lower transistor. The first inverter INV1 and the second inverter INV2 may be configured to receive a common input INPUT and may be configured to output a common output OUTPUT.

[0064] Reference Figure 10 The first inverter INV1 of the double-height standard unit DSC can be located in the row where the second standard unit SC2 is placed, and the second inverter INV2 of the double-height standard unit DSC can be located in the row where the fourth standard unit SC4 is placed.

[0065] Reference Figure 11A The first power via 20_1 can be electrically connected to the first lower source / drain region 26_L1 of the first inverter INV1 and the first lower source / drain region 26_L1 of the second inverter INV2. (Refer to...) Figure 11B The output via 10_1 can be electrically connected to the second lower source / drain region 26_L2 and the second upper source / drain region 26_U2 of the first inverter INV1, as well as the second lower source / drain region 26_L2 and the second upper source / drain region 26_U2 of the second inverter INV2.

[0066] It will be understood that the inventive concept can also be applied to standard units with various heights (e.g., three-times-height standard units or four-times-height standard units).

[0067] Figure 12A and Figure 12B These are some embodiments of the concept of the present invention, respectively along... Figure 10 A sectional view taken along lines E-E' and F-F'. (Refer to...) Figure 9 , Figure 10 , Figure 12A and Figure 12B The double-height standard cell DSC is a vertical channel device. The portion of the double-height standard cell DSC above the second insulating layer 44 can correspond to the first P-type transistor PTR_1 and the second P-type transistor PTR_2. The portion of the double-height standard cell DSC below the second insulating layer 44 can correspond to the first N-type transistor NTR_1 and the second N-type transistor NTR_2. The double-height standard cell DSC may include an upper channel region 322_U extending in the second direction Y and a lower channel region 322_L extending in the second direction Y. Both the upper channel region 322_U and the lower channel region 322_L can intersect with the first power line P1. The first portion of the upper channel region 322_U can be the channel region of the first P-type transistor PTR_1, and the second portion of the upper channel region 322_U can be the channel region of the second P-type transistor PTR_2. The first part of the lower channel region 322_L can be the channel region of the first N-type transistor NTR_1, and the second part of the lower channel region 322_L can be the channel region of the second N-type transistor NTR_2.

[0068] In some embodiments, the first N-type transistor NTR_1 and the second N-type transistor NTR_2 may include a single first lower source / drain region 326_L1. The first lower source / drain region 326_L1 may be electrically connected to the first power line P1 via a first power via 20_1. In some embodiments, the first power via 20_1 may contact the first power line P1 and the first lower source / drain region 326_L1.

[0069] In some embodiments, each of the first P-type transistor PTR_1 and the second P-type transistor PTR_2 may include a first upper source / drain region 326_U1 located on the upper channel region 322_U. In some embodiments, the first upper source / drain region 326_U1 may contact the upper channel region 322_U. Each first upper source / drain region 326_U1 may be electrically connected to a second power via (e.g., 30_1 or 30_15) via a first upper wiring contact 327_U1. In some embodiments, the first upper wiring contact 327_U1 may be omitted, and each first upper source / drain region 326_U1 may contact the second power via (e.g., 30_1 or 30_15).

[0070] The double-height standard unit DSC may include a second upper source / drain region 326_U2 located below the upper channel region 322_U and electrically connected to the upper channel region 322_U. In some embodiments, the second upper source / drain region 326_U2 may contact the upper channel region 322_U. The double-height standard unit DSC may also include a second lower source / drain region 326_L2 located above the lower channel region 322_L and electrically connected to the lower channel region 322_L. In some embodiments, the second lower source / drain region 326_L2 may contact the lower channel region 322_L. Each of the second upper source / drain region 326_U2 and the second lower source / drain region 326_L2 may extend in a first direction X.

[0071] Reference Figure 12B Each of the second upper source / drain region 326_U2 and the second lower source / drain region 326_L2 can be electrically connected to the output via 10_1. The output via 10_1 can contact the second upper source / drain region 326_U2 and the second lower source / drain region 326_L2. In some embodiments, such as Figure 12B As shown, the output via 10_1 can surround the second upper source / drain region 326_U2 and the second lower source / drain region 326_L2.

[0072] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0073] Example embodiments of the inventive concept are described herein with reference to schematic illustrations as idealized embodiments and cross-sectional views of intermediate structures of exemplary embodiments. Thus, variations in the shapes illustrated due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the example embodiments of the inventive concept should not be construed as limited to the specific shapes shown herein, but rather include deviations in shape caused, for example, by manufacturing processes.

[0074] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0075] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will be further understood that the terms “comprising,” “including,” and / or variations thereof, when used in this specification, describe the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0076] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, a first element may be referred to as a second element.

[0077] The subject matter disclosed above is intended to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the inventive concept. Therefore, to the fullest extent permitted by law, the scope will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. An integrated circuit device, the integrated circuit device comprising: a plurality of standard cells arranged in a plurality of rows each extending in a first direction on a substrate, wherein the plurality of standard cells includes a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row, wherein each of the plurality of standard cells includes: an upper transistor including: an upper active region; an upper gate structure on the upper active region; and an upper source / drain region on the upper active region; a lower transistor between the substrate and the upper transistor, the lower transistor including: a lower active region; a lower gate structure on the lower active region; and a lower source / drain region on the lower active region; a power line; and a power via electrically connecting the power line to the lower source / drain region, wherein the power via of the first standard cell and the power via of the second standard cell are aligned with each other along the first direction.

2. The integrated circuit device of claim 1, wherein, the power via of the first standard cell and the power via of the second standard cell are aligned with each other along an interface between the first row and the second row.

3. The integrated circuit device of claim 1, wherein, the power line of the first standard cell includes a first portion of a common power line, and the power line of the second standard cell includes a second portion of the common power line, and wherein the common power line extends along the interface between the first row and the second row.

4. The integrated circuit device of claim 3, wherein, the power via of the first standard cell contacts and protrudes upward from the common power line, and the power via of the second standard cell contacts and protrudes upward from the common power line.

5. The integrated circuit device of claim 4, wherein, the power via of the first standard cell contacts a center of the common power line in a second direction perpendicular to the first direction, and the power via of the second standard cell contacts the center of the common power line in the second direction.

6. The integrated circuit device of claim 1, wherein, the upper source / drain region includes a first upper source / drain region, and the lower source / drain region includes a first lower source / drain region, wherein each of the plurality of standard cells further includes: a second upper source / drain region on the upper active region; a second lower source / drain region on the lower active region; and an output via electrically connecting the second lower source / drain region to the second upper source / drain region, wherein the output via of the first standard cell and the power via of the first standard cell are aligned with each other along the first direction.

7. The integrated circuit device of claim 1, wherein, the power line of the first standard cell includes a first portion of a common power line, and the power line of the second standard cell includes a second portion of the common power line, wherein the plurality of standard cells further includes a third standard cell in the second row, and wherein the power via of the first standard cell electrically connects the common power line to the lower source / drain region of the third standard cell.

8. The integrated circuit device of claim 1, wherein, the upper source / drain region includes a first upper source / drain region, and the lower source / drain region includes a first lower source / drain region, each of the plurality of standard cells further includes: a second upper source / drain region on the upper active region; a second lower source / drain region on the lower active region; and an output via electrically connecting the second lower source / drain region to the second upper source / drain region, the output via of the first standard cell overlaps an interface between the first row and the second row.

9. The integrated circuit device of claim 8, wherein, the first cell boundary of the second standard cell includes the interface between the first row and the second row, and the output via of the second standard cell overlaps a second cell boundary of the second standard cell opposite the first cell boundary.

10. An integrated circuit device comprising: a plurality of standard cells arranged in a plurality of rows extending in a first direction on a substrate, wherein the plurality of standard cells includes a first standard cell in a first row and a second standard cell in a second row adjacent to the first row; and a common power line extending along an interface between the first row and the second row, wherein each of the plurality of standard cells includes: an upper transistor including: an upper active region; an upper gate structure on the upper active region; and first and second upper source / drain regions on the upper active region; a lower transistor between the substrate and the upper transistor, the lower transistor including: a lower active region; a lower gate structure on the lower active region; and first and second lower source / drain regions on the lower active region; a power via electrically connecting the common power line to the first lower source / drain region; and an output via electrically connecting the second lower source / drain region and the second upper source / drain region, wherein the power via of the first standard cell is spaced apart from the output via of the first standard cell in the first direction by a first distance, the power via of the second standard cell is spaced apart from the output via of the second standard cell in a second direction perpendicular to the first direction by a second distance, and the first distance is different from the second distance.

11. The integrated circuit device of claim 10, wherein, The first standard cell and the second standard cell are the same kind of standard cell.

12. The integrated circuit device of claim 10, wherein, The power via of the first standard cell and the output via of the first standard cell are aligned with each other along the first direction.

13. The integrated circuit device of claim 10, wherein, The output via of the first standard cell is superposed with the interface between the first row and the second row.

14. The integrated circuit device of claim 13, wherein, The second standard cell includes a first cell boundary and a second cell boundary opposite to the first cell boundary, the first cell boundary including the interface between the first row and the second row, wherein the output via of the second standard cell is superposed with the second cell boundary of the second standard cell.

15. The integrated circuit device of claim 13, wherein, The power via of the second standard cell is superposed with the interface between the first row and the second row, The output via of the first standard cell and the power via of the second standard cell are aligned with each other along the first direction.

16. The integrated circuit device of claim 10, wherein, The plurality of standard cells further includes a third standard cell in the second row and contacting the first standard cell, wherein the power via of the first standard cell electrically connects the common power line to the first lower source / drain region of the third standard cell.

17. The integrated circuit device of claim 10, wherein, The power via of the first standard cell contacts the common power line and protrudes from the common power line in a vertical direction, and the power via of the second standard cell contacts the common power line and protrudes from the common power line in the vertical direction.

18. An integrated circuit device comprising: a plurality of first standard cells arranged in a first direction; and a plurality of second standard cells arranged in the first direction and contacting the plurality of first standard cells, wherein an interface between the plurality of first standard cells and the plurality of second standard cells defines a cell boundary; and wherein the plurality of first standard cells and the plurality of second standard cells each include: an upper transistor on a substrate, the upper transistor including: an upper active region; an upper gate structure on the upper active region; and an upper source / drain region on the upper active region; an upper transistor between the substrate and the lower transistor, the upper transistor comprising: an upper active region; an upper gate structure over the upper active region; and upper source / drain regions over the upper active region; and an output via electrically connecting the lower source / drain regions and the upper source / drain regions, wherein the plurality of first standard cells comprises a first standard cell, and an output via of the first standard cell overlaps the cell boundary.

19. The integrated circuit device of claim 18, wherein, the lower source / drain regions comprise a first lower source / drain region, the plurality of first standard cells and the plurality of second standard cells each further comprise: a second lower source / drain region over the lower active region; a power line; and a power via electrically connecting the power line to the first lower source / drain region, and wherein a power via of the first standard cell overlaps the cell boundary.

20. The integrated circuit device of claim 18, wherein, the plurality of second standard cells comprises a second standard cell, the second standard cell comprises a first cell boundary and a second cell boundary opposite the first cell boundary, the first cell boundary comprising the cell boundary, an output via of the second standard cell overlaps the second cell boundary of the second standard cell.

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