Power Module

Abstract

In the power module of the present invention, two semiconductor elements and a capacitor element are arranged at the vertices of a triangle, and the shortest first shortest path between the semiconductor elements, the shortest second shortest path between each of the two semiconductor elements and the capacitor element, and the third shortest path are (first shortest path) ≥ (second shortest path) and ((first shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2 , the first conductive metal pattern and the second conductive metal pattern have a thickness more than twice the skin depth through which current flows under the skin effect generated by the frequency characteristics of the following current path, wherein the current path has a first resonant frequency obtained according to the capacitance and inductance between the semiconductor elements, a second resonant frequency between one semiconductor element and the capacitive element, and a third resonant frequency between the other semiconductor element and the capacitive element.

Description

Technical Field

[0001] The present application relates to a power module. Background Art

[0002] In devices that perform power conversion, power modules that are modularized and have built-in power semiconductor elements are sometimes used. Power semiconductor elements include MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), or diodes. It is known that when two or more power semiconductor elements are connected in parallel and driven, oscillation occurs. The oscillation phenomenon has the following reasons, namely: caused by LC resonance of parasitic inductance and parasitic capacitance of gate signal lines or emitter signal lines; caused by the switch timing difference at turn-on and turn-off due to the gate threshold voltage difference between elements when driven in parallel; caused by the current difference caused by the busbar layout between elements or the deviation between elements.

[0003] In addition, phenomena of oscillation at a frequency higher than these oscillations include PETT (Plasma Extraction Transit Time Oscillation) and IMPATT (Impact Ionization Avalanshe Transit Time Oscillation) (see, for example, Non-Patent Document 1). Fig.12 This is a diagram showing an example of frequency distribution of PETT with respect to operating voltage in a bipolar power semiconductor element, using temperature as a parameter according to the equation shown in the figure. Bipolar power semiconductor elements include IGBT, PN junction diode, reverse conducting IGBT, and the like. Fig.13 This is a diagram showing an example of frequency distribution of IMPATT with respect to operating voltage in a power semiconductor element using temperature as a parameter according to the equation shown in the figure. The power semiconductor element is an IGBT, a MOSFET, a PN junction diode, a Schottky junction diode, a reverse conducting IGBT, etc. Fig.12 and Fig.13 The numerator of the equation shown is the saturation velocity that depends on the temperature, type and physical properties of the semiconductor carriers, and the denominator is the depletion layer thickness that depends on the impurity concentration, voltage and physical property dielectric constant. In applications where the operating voltage amplitude and operating temperature range are wide, the frequencies of PETT and IMPATT are widely distributed relative to the operating voltage and temperature. Fig.12 and Fig.13When an IGBT and a PN junction diode are coupled to form a power module, the frequency distribution of PETT and IMPATT varies from Fig.12 and Fig.13 The distribution shown shifts to a wider distribution. IMPATT requires the generation of a local breakdown threshold electric field (local avalanche) in the depletion layer, but even if the voltage is low, the current is large, and even if the current is small, the voltage is high, so it will enter the occurrence condition area, so the wide distribution situation will not change.

[0004] In the case of strong oscillation caused by PETT and IMPATT, the following problems may be induced: malfunction of the drive circuit due to the conduction of oscillation to the gate signal line or the ground line; destruction of the power semiconductor element due to the induction of vibration to the gate signal; or malfunction of the low-voltage operation LSI caused by the oscillation radiation being transmitted from space to the control substrate equipped with a microcomputer, power supply IC, and the drive circuit of the power semiconductor element and superimposing the vibration on the signal or ground line. Therefore, in recent years, the demand for suppressing the generation of PETT and IMPATT in power modules has become increasingly high. For the frequency determined by the time it takes for holes (holes, minority side carriers) to pass through the depletion layer when the IGBT or PN junction diode is turned off, a method for suppressing PETT is disclosed by modifying the layout of the lead frame and wire bonding so that the LC resonance frequency determined by the parasitic capacitance of the power semiconductor element and the parasitic inductance of the lead frame and wire bonding is inconsistent (for example, refer to patent document 1). Fig.14 This is a diagram showing an example of the frequency distribution of LC resonance and PETT in the upper and lower limit designs of the parasitic inductance when the lead frame design is modified.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2013-229383

[0008] Non-patent literature

[0009] Non-patent document 1: J. Lutz et al., Semiconductor Power Device, DOI 10.1007 / 978-3-642-11125-9_13, pages 475-495 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] In the above-mentioned patent document 1, Fig.14As shown in FIG. 1 , PETT can be suppressed only within a limited range of conditions. However, parasitic capacitance is a number that can be determined as long as the semiconductor element is determined, but the configuration structure of the power semiconductor element is determined by heat dissipation and insulation performance. In the design of a module in which a power semiconductor element with a frequency distribution that deviates from PETT and IMPATT is mounted, there is a problem that it is difficult to suppress vibration caused by PETT and IMPATT by simply modifying the layout of the lead frame and wire bonding.

[0012] Therefore, an object of the present application is to obtain a power module capable of suppressing vibration caused by PETT and IMPATT.

[0013] Technical means for solving technical problems

[0014] The power module disclosed in the present application includes: two semiconductor elements, one surface and the other surface of the two semiconductor elements respectively having electrodes; a flat-plate-shaped first conductive metal pattern, the first conductive metal pattern connected to the electrodes on one surface of each of the two semiconductor elements arranged side by side on the same plane; a flat-plate-shaped second conductive metal pattern, the second conductive metal pattern connected to the electrodes on the other surface of each of the two semiconductor elements; and a capacitor element, the capacitor element is arranged between the first conductive metal pattern and the second conductive metal pattern on the same plane, an electrostatic capacitor is formed between the first conductive metal pattern and the second conductive metal pattern, and the two semiconductor elements and the capacitor element are arranged in a triangular shape on the same plane. The first conductive metal pattern and the second conductive metal pattern are characterized in that they have a flat plate shape having an appearance including three vertices and three sides of a triangle, the shortest connection path length between two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern is set as a first shortest path, the shorter of the two shortest connection path lengths between the two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern and the capacitor element is set as a second shortest path, and the longer shortest connection path length is set as a third shortest path, then (first shortest path) ≥ (second shortest path) and ((first shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2, a resonant frequency obtained from two electrostatic capacitances parasitic between one surface and the other surface of the two semiconductor elements and two inductances generated between one surface and the other surface of the two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern is set as a first resonant frequency, a resonant frequency obtained from an electrostatic capacitance parasitic between one surface and the other surface of one element of the two semiconductor elements, an electrostatic capacitance generated by the capacitor element, and two inductances generated between one surface of one element of the semiconductor element in the first conductive metal pattern and the second conductive metal pattern and the capacitor element and between the other surface and the capacitor element is set as a second resonant frequency, and a resonant frequency obtained from an electrostatic capacitance parasitic between one surface and the other surface of the other element of the two semiconductor elements is set as a second resonant frequency. The resonant frequency obtained by the capacitance, the electrostatic capacitance generated by the capacitance element, and the two inductances generated between one surface of the other side element of the semiconductor element of the first conductive metal pattern and the second conductive metal pattern and between the capacitance element and the other surface is set to the third resonant frequency. The first conductive metal pattern and the second conductive metal pattern have a thickness more than twice the depth of the skin through which the current flows under the skin effect generated by the first resonant frequency, the second resonant frequency and the third resonant frequency of the current path. Through the first conductive metal pattern and the second conductive metal pattern and the capacitance element, the vibration caused by one of the first resonant frequency, the second resonant frequency and the third resonant frequency of the current path between any two elements of the two semiconductor elements and the capacitance element is also reduced.

[0015] Effects of the Invention

[0016] According to the power module disclosed in the present application, two semiconductor elements and a capacitor element are arranged at the vertices of a triangle between a first flat conductive metal pattern and a second flat conductive metal pattern, the conductive metal pattern includes the triangle as an outer shape, the shortest connection path length between the two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern is set as a first shortest path, the shorter of the two shortest connection path lengths between the two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern and the capacitor element is set as a second shortest path, and the longer shortest connection path length is set as a third shortest path, then (first shortest path) ≥ (second shortest path) and ((first shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2, the first conductive metal pattern and the second conductive metal pattern have a thickness more than twice the depth of the skin through which the current flows under the skin effect generated by the frequency characteristics of the following current path, the current path having a first resonant frequency, a second resonant frequency, and a third resonant frequency obtained according to respective capacitances and inductances, wherein the respective capacitances and inductances are obtained according to the capacitance parasitic between one electrode and the other electrode of the two semiconductor elements, the capacitance formed between two elements selected from three elements of the capacitance element, and the inductance extracted between the electrodes between the two elements currently selected, and there are three types of element selection, namely, two elements connected to the first to third shortest paths are selected from the three elements, therefore, with respect to the semiconductor The current vibration generated when the body element is turned on and off is generated by using the first conductive metal pattern, the second conductive metal pattern and the capacitor element. Regardless of which of the first resonant frequency, the second resonant frequency and the third resonant frequency of the current path between any two elements of the two semiconductor elements and the capacitor element causes the vibration, the vibration current will not be concentrated on a partial path of the lead frame 1 and the lead frame 2. In addition, for the vibration current caused by PETT and IMPATT located in the same frequency region, for example, at any of the first resonant frequency, the second resonant frequency and the third resonant frequency, the vibration current will not be concentrated on a partial path, thereby suppressing the vibration caused by PETT and IMPATT. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a perspective view schematically showing a main part of the power module according to the first embodiment.

[0018] Figure 2 This is a perspective view schematically showing a main part of another power module according to the first embodiment.

[0019] Figure 3 This is a diagram showing an example of frequency distribution of LC resonance and PETT with respect to the operating voltage of the power module according to the first embodiment.

[0020] Figure 4 1 is a diagram showing an example of frequency distribution of LC resonance and PETT with respect to an operating voltage of another power module according to the first embodiment.

[0021] Figure 5 This is a perspective view schematically showing a main part of a power module according to the third embodiment.

[0022] FIG. 6 is a perspective view schematically showing a main part of a power module according to a fourth embodiment.

[0023] Figure 7It is a plan view schematically showing a main part of a power module according to the fifth embodiment.

[0024] Figure 8 It is a plan view schematically showing a main part of a power module according to the sixth embodiment.

[0025] Fig. 9 It is a plan view schematically showing a main part of a power module according to the seventh embodiment.

[0026] FIG. 10 is a diagram illustrating a power module according to a comparative example.

[0027] FIG. 11 is a diagram illustrating another power module of a comparative example.

[0028] Fig.12 : is a diagram showing an example of the frequency distribution of PETT with respect to the operating voltage.

[0029] Fig.13 : is a diagram showing an example of frequency distribution of IMPATT with respect to the operating voltage.

[0030] Fig.14 is a diagram showing an example of frequency distribution of LC resonance and PETT in the upper and lower limits of a parasitic inductor. DETAILED DESCRIPTION

[0031] Hereinafter, a power module according to an embodiment of the present application will be described based on the drawings. In addition, the same or corresponding components and parts in each figure are denoted by the same reference numerals for description.

[0032] Implementation method 1.

[0033] Figure 1 is a perspective view schematically showing a main part of a power module 100 according to Embodiment 1. Figure 2 is a perspective view schematically showing the main parts of another power module 100, Figure 3 1 is a diagram showing an example of the frequency distribution of LC resonance and PETT with respect to the operating voltage of the power module 100. Figure 4 1 is a diagram showing an example of frequency distribution of LC resonance and PETT with respect to an operating voltage of another power module 100 . Figure 1 and Figure 2 1 is a diagram showing the insulating filler surrounding the semiconductor element 3 and the like inside the power module 100 without being removed. The insulating filler is, for example, a molding resin, or sometimes a gel. The gel is arranged around the semiconductor element and between the elements, and the resin is arranged on the outermost side. The power module 100 is a module equipped with two semiconductor elements 3, and constitutes an inverter circuit in an inverter device, for example.

[0034] <Power Module 100>

[0035] like Figure 1 As shown, the power module 100 includes two semiconductor elements 3, two capacitor elements 4, a lead frame 1 as a first conductive metal pattern, a lead frame 2 as a second conductive metal pattern, and a lead frame 5. The semiconductor element 3 has electrodes 6 on one surface and the other surface respectively. The electrode 6 on one surface is an upper surface electrode, which is an N pole, and the electrode on the other surface (not shown) is a lower surface electrode, which is a P pole. Each electrode 6 is not limited to one, and can also be divided. In the present embodiment 1, the electrode 6 is divided into two electrodes 6a and 6b. The two semiconductor elements 3 and the two capacitor elements 4 are arranged side by side on the same plane. The lead frame 1 is in the shape of a plate and is connected to the upper surface electrodes of each of the two semiconductor elements 3. The lead frame 1 includes a terminal portion 1a connected to other circuits (not shown). The lead frame 2 is in the shape of a plate and is connected to the lower surface electrodes of each of the two semiconductor elements 3. The lead frame 1 and the lead frame 2 are made of copper, for example, and the lead frame 2 is provided on a DBC (Direct Bonded Copper) substrate or an insulating resin not shown.

[0036] Two capacitor elements 4 are provided between lead frame 1 and lead frame 2, and an electrostatic capacitance is formed between lead frame 1 and lead frame 2. Two semiconductor elements 3 and two capacitor elements 4 are connected in parallel between lead frame 1 and lead frame 2. Two semiconductor elements 3 and two capacitor elements 4 are connected to lead frame 1 and lead frame 2 by solder, conductive paste or conductive adhesive material. Lead frame 1 and lead frame 2 are respectively connected to two semiconductor elements 3 and two capacitor elements 4 at the same potential. Lead frame 5 is connected to semiconductor element 3 by bonding wire (not shown). Lead frame 5 is a terminal connected to other circuits (not shown) and is supported by insulating filler. Other circuits connected to terminal portion 1a and lead frame 5 are, for example, a driving circuit for driving power module 100.

[0037] One or the other of the two semiconductor elements 3 and the two capacitor elements 4 is arranged at the vertices of a triangle on the same plane. When the two semiconductor elements 3 are connected in parallel and driven, oscillation occurs due to the resonance caused by the parasitic inductance and parasitic capacitance between the two semiconductor elements 3. When the two semiconductor elements 3 have the same type, the same size and the same characteristics, stronger oscillations occur. In order to suppress the oscillations, the capacitor element 4 is provided, and the two semiconductor elements 3 and the capacitor element 4 are arranged at the vertices of the triangle. In the following, the two semiconductor elements 3 sides are described as vibration sources, but the capacitor element 4 side can also be used as a vibration source.

[0038] When the shortest connection path length between the two semiconductor elements 3 in the lead frame 1 and the lead frame 2 is taken as the first shortest path, the shorter of the two shortest connection path lengths between the two semiconductor elements 3 in the lead frame 1 and the lead frame 2 and the capacitor element 4 is taken as the second shortest path, and the longer shortest connection path length is taken as the third shortest path, the positions of the triangle vertices are arranged so as to satisfy (first shortest path) ≥ (second shortest path) and ((first shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2 The relationship between. The former is taken as the first equation and the latter is taken as the second equation. When the lengths of the two shortest connection paths between the two semiconductor elements 3 and the capacitor element 4 are equal, either shortest connection path can be the second shortest path or the third shortest path. The distance between the elements is defined as the distance between the centers of the electrodes on the upper or lower surfaces of the two elements. In the case where the electrode is divided, the center of the part where the two divided electrodes are combined is taken as the center of the electrode. Figure 1 and Figure 2 The intersection of the dashed lines shown is the center of the electrode. When the shape of the electrode is different on the upper surface and the lower surface, the distance is also different on the upper surface and the lower surface, but the relationship between the first and second equations must hold true on both the upper surface and the lower surface. Figure 1 In the equation, when the semiconductor element 3 is used as the vibration source, the first equation becomes (the first shortest path 81) ≥ (the second shortest path 91), and the second equation becomes ((the first shortest path 81) 2 +(Second shortest path 91) 2 )≥(third shortest path 92) 2 In addition, Figure 1 In the equation, when the capacitor element 4 is used as the vibration source, the first equation becomes (the first shortest path 82) ≥ (the second shortest path 91), and the second equation becomes ((the first shortest path 82) 2 +(Second shortest path 91) 2 )≥(third shortest path 93) 2 .exist Figure 2 In the equation, when the semiconductor element 3 is used as the vibration source, the first equation becomes (the first shortest path 81) ≥ (the second shortest path 91), and the second equation becomes ((the first shortest path 81) 2 +(Second shortest path 91) 2 )≥(third shortest path 92) 2 .

[0039] Although in Figure 1 An example in which two capacitor elements 4 are provided is shown, but Figure 2As shown, the capacitor element 4 can also be one. In this case, two semiconductor elements 3 and one capacitor element 4 are arranged at the vertices of a triangle on the same plane. The semiconductor element 3 is, for example, a power semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The two semiconductor elements 3 can be set as IGBTs or bipolar transistors, and the capacitor element 4 can be set as a PN junction diode or a Schottky junction diode. Figure 1 and Figure 2 In the figure, the semiconductor element 3 is an IGBT, and the capacitor element 4 is a PN junction diode.

[0040] PETT and IMPATT are phenomena that oscillate at a relatively high frequency. PETT and IMPATT occur even in a single power semiconductor element, but when multiple elements of the same size and characteristics are connected in parallel and operated, due to the deviation of device thresholds, such as gate threshold Vth, a slight deviation in switching timing may sometimes cause particularly strong oscillations. Strong oscillation occurs in the following cases: Fig.12 or Fig.13 In the frequency distribution of the PETT or IMPATT inherent to the semiconductor element shown, the frequency of the PETT or IMPATT begins to shift, and a phase shift of the same frequency occurs, thereby generating a vibration current inherent to the element between the parallel-connected elements; and the vibration current is close to or consistent with the LC resonance frequency, where the LC resonance frequency is caused by the parasitic capacitance of the element connected in parallel with the parasitic inductance of the path through which the vibration current passes. The following only describes the occurrence of PETT when the IGBT is turned off. The same description can be given for the occurrence of PETT during the reverse recovery of a PN junction diode, the occurrence of IMPATT when a MOSFET or IGBT is turned off, and the occurrence of PETT during the reverse recovery of a PN junction diode or a Schottky junction diode.

[0041] <Comparative Example>

[0042] Before describing the lead frames 1 and 2 which are the main parts of the present application, a comparative example is described using FIGS. 10 and 11. FIG. 10 is a diagram illustrating a power module 200 of a comparative example, FIG. 10(a) is a stereoscopic diagram schematically showing the main parts of the power module 200, and FIG. 10(b) is a diagram showing the circuit of two semiconductor elements 3 of FIG. 10(a). FIG. 11 is a diagram illustrating another power module 300 of a comparative example, FIG. 11(a) is a stereoscopic diagram schematically showing the main parts of another power module 300, and FIG. 11(b) is a diagram showing the circuit of FIG. 11(a). As shown in FIG. 10(a), the lead frame 201 included in the power module 200 is not flat, and the two semiconductor elements 3 and the two capacitor elements 4 are connected by a thinner overlap portion 202. The semiconductor element 3 and the capacitor element 4 arranged in an inclined direction are not directly connected. As shown in Fig. 11(a), the lead frame 301 included in the power module 300 is not flat, and two semiconductor elements 3 are connected by a thinned overlap 302. In Figs. 10 and 11, the semiconductor element 3 is an IGBT, and the capacitor element 4 is a PN junction diode.

[0043] PETT is discussed in the operational range required as a product and in a wide operational voltage and temperature range. Even if the upper limit or lower limit design conditions are applied to the design of the lead frame, generally, there must be one or more frequencies of PETT and IMPATT that intersect the frequency domain of the LC resonance of the entire region obtained from the parasitic capacitance and parasitic inductance of the semiconductor element under certain voltage and temperature conditions, so the occurrence of PETT and IMPATT cannot be suppressed. Fig.14 1 is a diagram showing an example of the frequency distribution of LC resonance and PETT in the upper limit side and lower limit side limit design of parasitic inductance when the design of the lead frame is modified. Even if both the upper limit side and lower limit side limit design of parasitic inductance are used for the lead frame design, as Fig.14 As shown, the production of PETT and IMPATT could not be inhibited.

[0044] In FIG. 10( a), the lap joint 202 connecting the IGBTs is the shortest path of the vibrating current between the IGBTs arranged in parallel. The parasitic inductance of the lead frame 201 between the IGBTs arranged in parallel is considered based on the two paths, the lap joint 202 and the path via the diode. The parasitic inductance value is 8.4 nH between the IGBTs in the path via the diode only, and is 2.4 nH between the IGBTs in the lap joint 202 only. The parasitic inductance value between the IGBTs combining the two paths is 1.9 nH, which is close to the value of the lap joint 202 alone. The parasitic inductance value between the IGBTs combining the two paths and the resonant frequency of the parasitic capacitance of the IGBTs arranged in parallel generate strong oscillations on the path of the arrow shown in FIG. 10 . Figure 3 The LC resonance distribution between the two IGBTs and the LC resonance distribution between the IGBT and the diode in the comparative example are shown. Under the driving conditions of the power module at the location where the frequency distribution of the PETT relative to the operating voltage intersects with the distribution of the LC resonance between the IGBTs relative to the operating voltage, strong oscillation occurs. At the location indicated by the circle in the figure, the vibration was measured using a near-magnetic field probe, and the observed intensity is shown in the figure in a manner that the measured amplitude is proportional to the diameter of the circle. No strong oscillation occurs at the location where the frequency distribution of the PETT intersects with the LC resonance distribution between the IGBT and the diode. This is because the intersection is located in the PETT boundary area of ​​the operating area when the IGBT is the vibration source.

[0045] In FIG. 11( a ), the shortest path for the vibration current between the IGBTs arranged in parallel is the lap joint 302 connecting the IGBTs. The parasitic inductance of the lead frame 301 between the IGBTs arranged in parallel is considered based on the two paths, the lap joint 302 and the path through the diode. The parasitic inductance value is 4.3 nH between the IGBTs in the path only through the diode, and is 3.0 nH between the IGBTs in the lap joint 302 only, which are close values. The parasitic inductance value between the IGBTs obtained by merging the two paths is 1.8 nH. The vibration current is mostly distributed on the path through the diode, and mostly flows through the shortest path through the diode between the two IGBTs. The parasitic inductance value through the diode between the two IGBTs and the resonant frequency between the parasitic capacitance of the IGBT and the diode at the shortest distance not between the two IGBTs but between the IGBT and the diode strongly oscillate on the path of the dotted arrow shown in FIG. 11 . Furthermore, the resonant frequency due to the parasitic inductance value between the IGBTs arranged in parallel and the parasitic capacitance of the IGBTs arranged in parallel strongly oscillates on the path of the solid arrow shown in FIG. 11 . Figure 4The LC resonance distribution between two IGBTs and the LC resonance distribution between an IGBT and a diode in a comparative example are shown. Under the driving conditions of the power module at the location where the frequency distribution of the PETT relative to the operating voltage intersects with the distribution of the LC resonance between the IGBTs relative to the operating voltage, strong oscillations occur. At the location indicated by the circle in the figure, the vibration was measured using a near magnetic field probe, and the observed intensity is shown in the figure in a manner in which the measured amplitude is proportional to the diameter of the circle.

[0046] The possibility of strong oscillation is considered based on the resonant frequency generated by the parasitic inductance of the lead frame between the IGBT and the diode, the parasitic capacitance of the IGBT, and the parasitic capacitance of the diode, and the resonant frequency generated by the parasitic inductance of the lead frame between the two IGBTs and the parasitic capacitance of the two IGBTs. Figure 3 As shown in FIG. 11 , a strong oscillation occurs in the resonance between the two IGBTs. Figure 4 As shown, strong oscillation occurs in the resonance between the IGBT and the diode.

[0047] In the comparative example shown in FIG10 , the overlap 202 as the connection part between the IGBTs is thinner, and the current is concentrated in the path indicated by the arrow, which makes it easy to form a magnetic dipole. In the comparative example shown in FIG11 , similarly to FIG10 , the overlap 302 as the connection part between the IGBTs is thinner. In addition, the shortest path between the IGBTs via the diode appears to have a width, but from the shortest point of view, the path along the side of the outer periphery of the hole provided in the lead frame 301 becomes the path where the vibration current is concentrated. Since the concentrated current loop forms a certain area, it is easy to form a magnetic dipole. When a magnetic dipole is formed, oscillation and strong radiation are generated at the resonance point.

[0048] <Lead frame 1, 2>

[0049] A power module is obtained, characterized in that, at a first resonant frequency, a second resonant frequency, and a third resonant frequency, lead frame 1 and lead frame 2 have a thickness that is more than twice the depth of the skin through which current flows under the skin effect generated by the frequency characteristics of one of the first resonant frequency, the second resonant frequency, and the third resonant frequency based on the current path, wherein the first resonant frequency is obtained by an LC series connection of two electrostatic capacitors parasitic between one surface and the other surface of two semiconductor elements 3 and two inductors generated between one surface and the other surface of two semiconductor elements 3 on lead frame 1 and lead frame 2, and the second resonant frequency is obtained by an electrostatic capacitance parasitic between one surface and the other surface of one element of the two semiconductor elements 3, an electrostatic capacitance generated by capacitor element 4, and the LC series connection of lead frame 1 and lead frame 2. The third resonance frequency is obtained by the LC series connection of two inductances generated between one surface of the semiconductor element and the capacitor element 4 and between the other surface and the capacitor element 4, and the electrostatic capacitance generated by the capacitor element 4, which is parasitic between one surface and the other surface of the other surface of the two semiconductor elements 3, and the electrostatic capacitance generated by the capacitor element 4, and the LC series connection of two inductances generated between one surface and the other surface of the semiconductor element of the lead frame 1 and the lead frame 2 and the capacitor element 4, thereby allowing high-frequency current to flow easily in the lead frame 1 and the lead frame 2, and through the lead frame 1, the lead frame 2 and the capacitor element 4, it is also possible to suppress the vibration caused by the first resonance frequency, the second resonance frequency, and the third resonance frequency of the current path between any two elements of the two semiconductor elements 3 and the capacitor element 4. Assuming that the lead frame 1 and the lead frame 2 are made of copper and the current flowing to the lead frame 1 and the lead frame 2 is a high-frequency current of 150MHz, for example, the thickness of the lead frame 1 and the lead frame 2 becomes 32μm. This value can be achieved, for example, by using a 35 μm thick tape made of copper for the lead frame 1 or the lead frame 2 , or by ensuring a 35 μm thick copper pattern as the lead frame 2 on a printed circuit board.

[0050] In the case where an IGBT as a semiconductor element 3 and a diode as a capacitor element 4 are connected to the flat lead frame 1 and the flat lead frame 2, the inductance can be reduced. However, in the analysis of parasitic inductance, since there is a region where the frequency distribution of the PETT and the LC resonance between the elements intersect, an oscillation phenomenon may occur particularly in the intersecting region. Figure 3 Shows Figure 1 The distribution of LC resonance between two IGBTs in the power module 100 is shown. Figure 4 Show Figure 2The LC resonance distribution between two IGBTs and the LC resonance distribution between an IGBT and a diode in another power module 100 are shown. Any LC resonance intersects with the frequency distribution of the PETT and may cause oscillation.

[0051] If the vibration of the inductance value in the entire path is taken into account, the path of the vibration current is dispersed from the shortest path between the IGBTs to the path through the diode, the current density is dynamically distributed, and the vibration current between the IGBTs and the vibration current between the IGBT and the diode coexist. The vibration between the IGBTs moves in the direction absorbed by the parasitic capacitance of the diode, and the vibration between the IGBT and the diode moves in the direction absorbed by the parasitic capacitance side of the other IGBT. Therefore, on the basis of suppressing the vibration, the current flows at the shortest distance relative to the voltage difference of the electrodes of each component and is applied in the direction of eliminating the vibration, so that the current can be induced so that it is applied in the direction of suppressing both the vibration between the IGBTs and the vibration between the IGBT and the diode. By making the parasitic inductance value between the IGBTs and the parasitic inductance value between the IGBT and the diode close, the vibration current between the IGBTs and the vibration current between the IGBT and the diode, which have different resonance points, can be interfered to suppress the vibration.

[0052] By setting the lead frame 1 and the lead frame 2 to be flat, the shortest distance between the IGBTs and the shortest distance between the IGBTs via the diode are filled with flat plates, so that the parasitic inductance value between the IGBTs and the parasitic inductance value between the IGBTs via the diode can be close. The following situation is set as the first condition, that is, the IGBT and the diode are arranged at the vertex position of the triangle in a manner that the diode is not included in the path of the shortest distance between the IGBTs, and the parasitic inductance between one IGBT and one diode, or between another IGBT and one diode in the path between the IGBTs via the diode becomes less than the parasitic inductance of the shortest path between the IGBTs. The following situation is set as the second condition, that is, in the shortest path between the IGBTs and the path between the IGBTs via the diode, there is no part where the vibration current is concentrated when the vibration current passes through their respective shortest paths. By satisfying these conditions, the vibration caused by PETT and IMPATT can be suppressed.

[0053] In the comparative example shown in FIG. 10 , the parasitic inductance value is 8.4 nH between the IGBTs in the path only through the diode, and is 2.4 nH between the IGBTs in the bridge portion 202 only. Figure 1In the power module 100, the parasitic inductance value is reduced to 3.1nH between the IGBTs in the path only through the diode, and to 1.4nH between the IGBTs. By reducing the value of each parasitic inductance, the difference in inductance value between the paths is reduced, and the vibration current is dispersed. From the perspective of another IGBT, if the inductance value between the IGBT and the diode is equal to or less than the inductance value of the path between the other IGBT in the inductance of the shortest path to the other IGBT and the inductance of the path through the diode, the first condition is satisfied and the vibration current is diverted to the path through the diode. In addition, if the lead frame 1 and the lead frame 2 are set to a flat plate shape and the IGBT and the diode are connected so that the position where the vibration current is locally concentrated is not set, the second condition is satisfied, the vibration current between the IGBTs and the vibration current between the IGBT and the diode interfere with each other and disperse, and the oscillation will be suppressed regardless of the LC resonance frequency.

[0054] In order to avoid resonance, it is desirable that the electrostatic capacitance of the diode be far from the parasitic capacitance of the IGBT. Even if the electrostatic capacitance of the diode is not separated from the parasitic capacitance of the IGBT, these are not related as long as they are not components of the same type and characteristics. The reason is that since the parasitic capacitance changes with voltage and temperature and there is a manufacturing deviation, if the diode driven in parallel is not a component of the same type and characteristics, the diode will not have the same characteristics as the IGBT with respect to changes in voltage or temperature, and the characteristics of the IGBT and the diode will be inconsistent.

[0055] The first condition for making the parasitic inductance value between the IGBTs and the parasitic inductance value between the IGBT and the diode close to each other is shown. However, by arranging the IGBT and the diode at the vertices of the triangle, the shortest distance between the IGBTs and the shortest distance between the IGBT and the diode are filled with the flat lead frame 1 and the lead frame 2, so that the first condition for the parasitic inductance can be converted back into the magnitude relationship of the lengths of the following three distances: the shortest distance between the centers of the electrodes between the IGBTs, the shortest distance between the centers of one IGBT and the diode, and the shortest distance between the centers of the other IGBT and the diode. This magnitude relationship is the relationship between the first formula and the second formula shown above.

[0056] If the distance relationship shown in the first formula is satisfied, the parasitic inductance between an IGBT close to the diode and the diode can be said to be small relative to the parasitic inductance of the shortest distance between the IGBTs. The first formula is established, so that the vibration current is dispersed and flows easily. If the distance relationship shown in the first and second formulas is satisfied, the smaller angle formed at the intersection of the line segment formed by the shortest path between one IGBT and the diode and the line segment formed by the shortest path between the IGBTs is less than 90 degrees, and the smaller angle formed at the intersection of the line segment formed by the shortest path between another IGBT and the diode and the line segment formed by the shortest path between the IGBTs is also less than 90 degrees. The first and second formulas are established, so that in the path of the vibration current from the IGBT to the diode side, the vibration current is applied in the direction that makes the vibration current flow from one IGBT to the diode and flow toward another IGBT midway, so that the path of the vibration current is more effectively dispersed. The angle of 90 degrees is obtained from the comparative example. If the consideration is based on the line connecting the centers of the electrodes that first defines the shortest path, the angle formed by the two line segments may exceed 90 degrees depending on the size of the IGBT chip or the size of the diode, and depending on the design constraints of heat and wire bonding. However, when the extension lines of the outermost sides of the chip end and the device end are drawn, it can be converged within 90 degrees in the mutual configuration relationship between the components.

[0057] In the comparative example shown in FIG10 , the parasitic inductance value is 1.9 nH between the IGBTs, and if the path through the diode is divided path by path, it is 0.7 nH between the IGBT and the diode. In the analysis in which the lap joint 202 of the shortest path between the IGBTs is deleted, the inductance through the diode between the IGBTs is 8.4 nH. On the other hand, Figure 1 The parasitic inductance value in the power module 100 is 1.2nH when synthesized through all paths between the IGBTs, but when it is assumed that only the shortest path between the IGBTs is taken out with the width of the IGBT electrode, and the path on the diode side is cut off and disconnected, it is 1.4nH in the path between the IGBTs after being cut and flattened. The parasitic inductance value between an IGBT and the diode on the near side is 0.7nH, and the parasitic inductance value between the IGBT and the diode on the far side is 2.3nH. Since two paths are formed between the diodes on the near side and the far side, the parasitic inductance value obtained by adding the two is 3.0nH. The parasitic inductance obtained after removing the shortest path between the actual IGBTs is 3.1nH, which shows that there are not one but two bypass paths.

[0058] In the comparative example shown in FIG11 with one diode, the parasitic inductance value is 1.8 nH between the IGBTs, 0.9 nH between one IGBT and the diode, and 0.9 nH between the other IGBT and the diode. The parasitic inductance is evenly distributed between the IGBT and the diode at 0.9 nH. Figure 2 The parasitic inductance values ​​in another power module 100 are 1.1nH between IGBTs, 0.8nH between one IGBT and a diode, and 0.8nH between the other IGBT and a diode. The parasitic inductance value obtained by adding the two values ​​between the IGBT and the diode is 1.6nH, which is close to 1.1nH between the IGBTs. The oscillation is suppressed by providing a flat lead frame 1 and eliminating the path where the vibration current concentrates.

[0059] By setting the power module 100 to the above structure, since the inductance between one IGBT and the diode is smaller than the inductance of the shortest path between the IGBTs, an action occurs in which about half of the current of the oscillating vibration current between the IGBTs flows between one IGBT and the diode. After passing through the diode, the current branches into two paths, a path toward the other IGBT side and a path returning to one IGBT side. Between the IGBTs, there is a first path, the shortest path between the IGBTs, and a second path, the shortest path, via the diode. Even if the vibration current between the IGBTs is caused to amplify the vibration accompanied by the LC resonance formed by the parasitic inductance between the IGBTs and the parasitic capacitance between the IGBTs, the greater the voltage difference between the electrodes of the IGBTs and the electrodes of the diodes, the more the current flows to the diode side. In addition, by connecting the IGBTs and the diodes to the lead frames 1 and 2 on the flat plate, a path flowing in from the lead frame surface other than between the electrodes is ensured, thereby suppressing the action of the resonant current.

[0060] The above effect is explained using the numerical value of parasitic inductance. In the comparative example shown in Figure 10, the parasitic inductance value between the IGBT and the diode is 0.7nH, which is smaller than 1.9nH between the IGBTs. However, in order to form the second path, a path through the overlap 202 between the diodes must be formed. Therefore, the parasitic inductance value through the diode between the IGBTs becomes larger to 8.4nH, and the parasitic inductance value obtained by adding the two paths is 3.7nH. The vibrating current is concentrated in the shortest overlap 202 between the IGBTs and oscillates, forming a current flow path and generating radiation. On the other hand, Figure 1 The parasitic inductance value in the power module 100 is 1.2 nH between IGBTs, 3.0 nH between IGBTs via one diode, and 3.0 nH between IGBTs via one diode. Since a path is formed via two diodes, the vibration current does not need to be concentrated, and the vibration can be suppressed.

[0061] In the comparative example shown in FIG11 , since the overlap 302 between the IGBTs is slightly offset from the center of the electrode, the parasitic inductance between the IGBTs in the analysis with only the overlap 302 is 3.0 nH, and the parasitic inductance through the diode when the overlap 302 between the IGBTs is removed is 4.3 nH, and the parasitic inductance values ​​of the two are close. Therefore, the vibrating current is distributed to both paths. In addition, the current is concentrated in the thin overlap 302 between the IGBTs, and on the path side through the diode, the innermost peripheral side of the central part of the lead frame 301 becomes the shortest distance, so the vibrating current is concentrated in this part. The parasitic inductance value synthesized by the entire IGBT is 1.8 nH, and the parasitic inductance value between the IGBT and the diode is 0.9 nH, which generates oscillations on the two paths. On the other hand, Figure 2 The parasitic inductance value in another power module 100 is 1.1nH between IGBTs and 0.8nH between each IGBT and diode, and the two are close. Therefore, the vibration current is bifurcated, and there is no path where the vibration current is concentrated. Since the current flows due to the voltage difference between the electrodes of the two IGBTs and the diode, the vibration can be suppressed. In the sense that the inductance value is divided equally to make it close, the comparative example shown in Figure 11 is not very different from the other power module 100. However, by filling the hole of the lead frame 301, the shortest path along the overlap 302 between the IGBTs where the vibration current is concentrated in the comparative example and along the outer periphery of the hole of the lead frame 301 is deleted, and by setting it so that the current can flow on any path due to the voltage change between the IGBT and the diode, the distribution of the vibration current is expanded, and the vibration can be suppressed.

[0062] exist Figure 3 In the example, the LC resonance distribution between the two IGBTs in the power module 100 intersects with the frequency distribution of the PETT. Figure 4 In the LC resonance distribution between the two IGBTs and the LC resonance distribution between the IGBT and the diode in the other power module 100 intersect with the frequency distribution of the PETT. Although it is predicted that oscillation may occur at the intersection, no oscillation that can be identified by the near magnetic field probe occurs at these intersections. This is because the vibration current is not concentrated in any power module 100, thereby suppressing the vibration.

[0063] In the above, two IGBTs are described as vibration sources, but the same description can be given by replacing the vibration source connected in parallel with the diode side. In the comparative example shown in FIG10 , the parasitic inductance value between the diodes is 2.9 nH, and the parasitic inductance value between the diodes through the IGBT without the overlap 202 is 8.6 nH. Since there is a difference in the parasitic inductance values ​​of the two, the vibration current flows through the overlap 202 between the diodes, and oscillation occurs during the reverse recovery action of the diode. On the other hand, Figure 1 The parasitic inductance value in the power module 100 is 2.3nH between diodes and 3.7nH between diodes via IGBTs. Since the difference between the parasitic inductance values ​​of the two is reduced, the parasitic inductance value between the IGBT and the diode is reduced to 0.7nH, so the vibration current flows between the diodes via the IGBT, thereby suppressing the vibration on the diode side.

[0064] The lead frame 1 is arranged in a flat plate shape, but Figure 1 and Figure 2 As shown, the lead frame 1 has a through hole 1b at a position corresponding to between the IGBT and the diode. The power module 100 includes an insulating filler such as a gel or a molded resin surrounding the semiconductor element 3 and the like inside the power module 100 in order to ensure the insulation performance of the power module 100. Due to the viscosity of the insulating filler when filling, sometimes the insulating filler cannot be filled between the lead frame 1 and the lead frame 2, forming a gap of a certain size, and thus the insulation performance cannot be obtained in the power module 100. By providing the through hole 1b with a suitable viscosity when filling the insulating filler in the lead frame 1, the insulating filler can be filled in every corner between the lead frame 1 and the lead frame 2.

[0065] As described above, in the power module 100 involved in the first embodiment, the two semiconductor elements 3 and the capacitor element 4 are arranged at the vertices of the triangle between the flat lead frame 1 and the flat lead frame 2. When the shortest connection path length between the two semiconductor elements 3 in the lead frame 1 and the lead frame 2 is set as the first shortest path, the shorter of the two shortest connection path lengths between the two semiconductor elements 3 in the lead frame 1 and the lead frame 2 and the capacitor element 4 is set as the second shortest path, and the longer shortest connection path length is set as the third shortest path, (first shortest path) ≥ (second shortest path) and ((first shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2Lead frame 1 and lead frame 2 have a thickness more than twice the depth of the skin through which current flows under the skin effect generated by the frequency characteristics of the current path having the first resonant frequency, the second resonant frequency and the third resonant frequency, wherein the first resonant frequency is obtained based on the capacitance and inductance parasitic between the two semiconductor elements 3, the second resonant frequency is obtained based on the capacitance and inductance between one semiconductor element 3 of the two semiconductor elements 3 and a capacitor element 4, and the third resonant frequency is obtained based on the capacitance and inductance between the other semiconductor element 3 of the two semiconductor elements 3 and a capacitor element. Therefore, the vibration current caused by PETT and IMPATT will not be concentrated on part of the paths of lead frame 1 and lead frame 2, and the vibration caused by PETT and IMPATT can be suppressed.

[0066] In addition, since the vibration caused by PETT and IMPATT is suppressed, it is possible to suppress the malfunction of the drive circuit of the drive power module 100 and the destruction of the semiconductor element 3 due to the induction of gate vibration. In addition, even if the two semiconductor elements 3 are set as IGBTs or bipolar transistors, and the capacitor element 4 is set as a PN junction diode or a Schottky junction diode, the vibration current caused by PETT and IMPATT will not be concentrated on the partial path of the lead frame 1 and the lead frame 2, and the vibration caused by PETT and IMPATT can be suppressed.

[0067] Implementation method 2.

[0068] A power module 100 according to Embodiment 2 will be described. The power module 100 according to Embodiment 2 is configured to include a power semiconductor element in which a depletion layer is formed inside the semiconductor element 3 .

[0069] Will Figure 1 or Figure 2 The two semiconductor elements 3 provided in the power module 100 shown are two power semiconductor elements that form a depletion layer inside the semiconductor element 3 when the power module 100 is turned off or switched from forward bias to reverse bias. Since a local breakdown limit value electric field is generated inside the power semiconductor element when the power module 100 is turned off or switched to off, a frequency determined by the time it takes for majority-side carriers to move and be discharged through the depletion layer inside the power semiconductor element is used as a first natural vibration frequency, and when the power module 100 is turned off or switched to off, a frequency determined by the time it takes for minority-side carriers to move and be discharged through the depletion layer inside the bipolar power semiconductor element is used as a second natural vibration frequency.

[0070] The two power semiconductor elements connected in parallel are respectively a power semiconductor element having only the first natural vibration frequency or a power semiconductor element having both the first natural vibration frequency and the second natural vibration frequency. When the two power semiconductor elements are driven, the frequencies of the first natural vibration frequency and the second natural vibration frequency are widely distributed according to voltage and temperature conditions. Even if the first natural vibration frequency includes a frequency that matches any one of the first resonant frequency, the second resonant frequency, and the third resonant frequency shown in Embodiment 1, and the second natural vibration frequency also includes a frequency that matches any one of the first resonant frequency, the second resonant frequency, and the third resonant frequency shown in Embodiment 1, since the power module 100 has the structure shown in Embodiment 1, the vibration current caused by PETT and IMPATT will not be concentrated on a partial path in the lead frame 1 and the lead frame 2, and the vibration caused by PETT and IMPATT can be suppressed. That is, in the two power semiconductor elements having depletion layers formed therein, even if the first resonant frequency, the second resonant frequency, and the third resonant frequency are included in the frequency range of the first natural vibration frequency and the second natural vibration frequency distribution, the vibration caused by PETT and IMPATT can be suppressed.

[0071] As described above, in the power module 100 involved in embodiment 2, the two semiconductor elements 3 are two power semiconductor elements having a depletion layer formed therein, and the two power semiconductor elements are respectively power semiconductor elements having only the first natural vibration frequency, or power semiconductor elements having both the first natural vibration frequency and the second natural vibration frequency. Since the frequency range in which the first natural vibration frequency and the second natural vibration frequency are distributed includes the first resonant frequency, the second resonant frequency and the third resonant frequency, even if the semiconductor elements 3 are two power semiconductor elements having a depletion layer formed therein, vibrations caused by PETT and IMPATT can be suppressed.

[0072] Implementation method 3.

[0073] A power module 100 according to the third embodiment will be described. Figure 5 1 is a perspective view schematically showing a main part of a power module 100 according to Embodiment 3. The power module 100 according to Embodiment 3 has a structure different from that shown in Embodiment 1 and includes a semiconductor element 3 and a capacitor element 4 .

[0074] exist Figure 5 In the embodiment, the two semiconductor elements 3 are metal oxide film type field effect transistors or reverse conducting insulated gate bipolar transistors. The capacitor element 4 is a capacitor formed by an insulating filler provided between the plate-like lead frame 1 and the plate-like lead frame 2. The insulating filler may be an air layer, a resin material or a gel material if it has a uniform dielectric constant.

[0075] Although in Figure 5 An example of setting two capacitor elements 4 is shown, but the capacitor element 4 can also be one or more. In either case, the two semiconductor elements 3 and one capacitor element 4 are arranged at the vertices of the triangle on the same plane. In the lead frame 1, the lateral width is l and the longitudinal width is w, so that it has an area of ​​1×w, and the lead frame 1 is set to cover the center of each of the semiconductor element 3 and the capacitor element 4. The center position of each of the semiconductor element 3 and the capacitor element 4 is the intersection of the dotted lines shown in the figure. One surface and the other surface of the semiconductor element 3 and the capacitor element 4 are respectively provided with electrodes (not shown).

[0076] Regarding the distance between the centers of the components, such as Figure 5 As shown, the distance between semiconductor elements 3 is set to le11-12, the distance between one semiconductor element 3 and one capacitor element 4 is set to le11-21, the distance between one semiconductor element 3 and another capacitor element 4 is set to le11-22, the distance between another semiconductor element 3 and one capacitor element 4 is set to le12-21, and the distance between another semiconductor element 3 and another capacitor element 4 is set to le12-22. As long as these distances satisfy (le11-12) ≥ (le11-21) and ((le11-12) 2 +(le11-21) 2 )≥(le12-21) 2 , or (le11-12)≥(le12-22) and ((le11-12) 2 +(le12-22) 2 ≥(le11-22) 2 , it is possible to suppress the vibration caused by PETT and IMPATT.

[0077] As described above, in the power module 100 involved in the third embodiment, the two semiconductor elements 3 are metal oxide film type field effect transistors or reverse conducting insulated gate bipolar transistors. Even in the case where the capacitor element 4 is a capacitor formed by an insulating filler provided between the lead frame 1 and the lead frame 2, the vibration current caused by PETT and IMPATT will not be concentrated on the partial path of the lead frame 1 and the lead frame 2, and the vibration caused by PETT and IMPATT can be suppressed.

[0078] Implementation method 4.

[0079] A power module 100 according to Embodiment 4 will be described. Fig. 6 is a perspective view schematically showing a main part of the power module 100 according to Embodiment 4. The power module 100 according to Embodiment 4 is configured such that the lead frame 1 has a function of a planar antenna.

[0080] With respect to the voltage change of the two semiconductor elements 3 or the capacitor element 4 provided in the power module 100, the lead frame 1 is used as the flat antenna 11, and the lead frame 2 is used as the ground. FIG6(a) shows a power module 100 having an insulating dielectric 13 as the capacitor element 4 between the flat antenna 11 as the lead frame 1 and the ground 12 as the lead frame 2. The power supply point to the flat antenna 11 is set to the position of the black circle shown in FIG6(a), for example. FIG6(b) is a diagram illustrating the radiation frequency of the patch antenna as the flat antenna 11. Regarding the radiation frequency of the radio wave radiated by the patch antenna represented by the equation shown in FIG6(b), the voltage distribution and current distribution shown by the solid line and the dotted line in FIG6(b) are the fundamental wave. In the equation, c0 is the speed of light, ε is r is the dielectric constant of the dielectric, L e is the length of the long side of the patch antenna. The ground conductor plate in FIG6(b) corresponds to the lead frame 2 in FIG6(a), and the radiating element corresponds to the lead frame 1. When the radiation frequency represented by the formula shown in FIG6(b) is a higher frequency than the first resonant frequency, the second resonant frequency, and the third resonant frequency shown in Embodiment 1, that is, when the radiation frequency does not overlap with the PETT and IMPATT frequency distributions but is higher, the resonance between the lead frame 1 and the radiation frequency can be avoided.

[0081] As described above, in the power module 100 involved in the third embodiment, with respect to the voltage change of the two semiconductor elements 3 or the capacitor element 4 possessed by the power module 100, the lead frame 1 is used as the planar antenna 11, and the lead frame 2 is used as the ground. The radiation frequency of the radio wave represented by the formula shown in Figure 6(b) which is a characteristic of the planar antenna 11 is a frequency higher than the first resonant frequency, the second resonant frequency and the third resonant frequency. Therefore, the resonance between the lead frame 1 and the radiation frequency can be avoided, and the release of energy to the radiation side as the planar antenna 11 can be suppressed.

[0082] Implementation method 5.

[0083] A power module 100 according to the fifth embodiment will be described. Figure 7 1 is a plan view schematically showing a main part of a power module 100 according to Embodiment 5. The power module 100 according to Embodiment 5 is configured to include three semiconductor elements 3 .

[0084] like Figure 7As shown, the power module 100 includes three semiconductor elements 3a, 3b, 3c, a capacitor element 4, a flat lead frame 1 and a flat lead frame 2. The lead frame 1 is shown in outline only by a dotted line. Here, three semiconductor elements 3a, 3b, 3c are provided, but this is not limited to this, and n (where n is an integer greater than 3) semiconductor elements 3 may also be provided. Two adjacent semiconductor elements 3 and a capacitor element 4 selected from the three semiconductor elements 3 are arranged at the vertices of a triangle on the same plane.

[0085] When the shortest connection path length between two adjacent semiconductor elements 3 in lead frame 1 and lead frame 2 is set as the first shortest path, the shorter of the two shortest connection path lengths between two adjacent semiconductor elements 3 in lead frame 1 and lead frame 2 and capacitor element 4 is set as the second shortest path, and the longer shortest connection path length is set as the third shortest path, the positions of the triangle vertices are arranged to satisfy (first shortest path) ≥ (second shortest path) and ((first shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2 The relationship between the two. The former is the first equation and the latter is the second equation. Figure 7 In the equation, when the two adjacent semiconductor elements 3 are set as semiconductor elements 3a and 3b, the first equation becomes (first shortest path 81)≥(second shortest path 91), and the second equation becomes ((first shortest path 81) 2 +(Second shortest path 91) 2 )≥(third shortest path 92) 2 .

[0086] Lead frame 1 and lead frame 2 have a thickness more than twice the depth of the skin through which current flows under the skin effect generated by the frequency characteristics of the current path having a first resonant frequency, a second resonant frequency and a third resonant frequency, wherein the first resonant frequency is obtained based on the capacitance and inductance between two adjacent semiconductor elements 3, the second resonant frequency is obtained based on the capacitance and inductance between one semiconductor element 3 of the two adjacent semiconductor elements 3 and a capacitor element 4, and the third resonant frequency is obtained based on the capacitance and inductance between the other semiconductor element 3 of the two adjacent semiconductor elements 3 and a capacitor element 4.

[0087] As described above, in the power module 100 involved in embodiment 5, two adjacent semiconductor elements 3 selected from three semiconductor elements 3 and the capacitor element 4 are arranged at the vertices of a triangle between the flat lead frame 1 and the flat lead frame 2. If the relationship between the first equation and the second equation is satisfied, the lead frame 1 and the lead frame 2 have a thickness that is more than twice the depth of the skin through which the current flows under the skin effect. Then, the vibration current caused by PETT and IMPATT will not be concentrated on a partial path of the lead frame 1 and the lead frame 2, and the vibration caused by PETT and IMPATT can be suppressed.

[0088] Implementation method 6.

[0089] A power module 100 according to the sixth embodiment will be described. Figure 8 1 is a plan view schematically showing a main part of a power module 100 according to Embodiment 6. The power module 100 according to Embodiment 6 is configured such that one or both of the plate-shaped lead frames 1 and 2 include a through hole 7 .

[0090] The two semiconductor elements 3 and the capacitor element 4 are arranged at the vertices of the triangle on the same plane. Figure 8 As shown, one or both of lead frame 1 and lead frame 2 has two or more through holes 7 on a perpendicular line 14 extending from a portion where capacitor element 4 is connected to lead frame 1 or lead frame 2 to a shortest path 15 which is the shortest connection path between two semiconductor elements 3 . Figure 8 An example of having two through holes 7 in the lead frame 1 is shown. By having two through holes 7, the path of the vibration current flowing between the semiconductor elements 3 is not limited to the shortest path 15 between the semiconductor elements 3, i.e., the first path, and the capacitance path 16 via the capacitor element 4, i.e., the second path, and a bypass path 17 is also provided. By providing the bypass path 17, the vibration current is dispersed and does not concentrate on the first path or the second path. By increasing the number of through holes 7 or reducing the area of ​​the through holes 7, the effect of suppressing vibration can be improved. In addition, when the through hole 7 is provided with an insulating filler, it also plays the role of filling the insulating filler between the lead frame 1 and the lead frame 2.

[0091] As described above, in the power module 100 involved in the sixth embodiment, since one or both of the lead frame 1 and the lead frame 2 have two or more through holes 7 on the vertical line 14 hanging down from the connection position between the capacitor element 4 and the lead frame 1 or the lead frame 2 to the shortest connection path between the two semiconductor elements 3, a bypass path 17 is provided in the lead frame having the through holes 7. Therefore, the vibration current caused by PETT and IMPATT will not be concentrated on a part of the path in the lead frame having the through holes 7, and the vibration caused by PETT and IMPATT can be suppressed.

[0092] Implementation method 7.

[0093] A power module 100 according to the seventh embodiment will be described. Fig. 9 1 is a plan view schematically showing a main part of a power module 100 according to Embodiment 7. The power module 100 according to Embodiment 7 is configured to include a through hole 8 having a predetermined size.

[0094] The two semiconductor elements 3 and the capacitor element 4 arranged at the vertices of the triangle are rectangular. One long side of the capacitor element 4 is arranged on the side opposite to one long side of each of the two semiconductor elements 3. One or both of the lead frame 1 and the lead frame 2 have a through hole 8 between each of the two semiconductor elements 3 and the capacitor element 4. Fig. 9 An example is shown in which the lead frame 1 is provided with the through hole 8 .

[0095] The value obtained by subtracting the hole width 26 from the partial length of the bypass path width 23 from the outer periphery of the capacitor element 4 to the line segment 21 in the vertical line 22 is more than 1 / 2 of the short side length of the capacitor element 4, wherein the above-mentioned vertical line 22 hangs down from the center of the connection part between the capacitor element 4 and the lead frame 1 or the lead frame 2 to the line segment 21, and the above-mentioned line segment 21 connects the corner closest to the capacitor element 4 of one semiconductor element 3a arranged at a position close to the capacitor element 4 among the two semiconductor elements 3, and the end of the long side of the other semiconductor element 3b opposite to the capacitor element 4, that is, the corner on the side away from the capacitor element 4, and the above-mentioned hole width 26 is the distance between the two vertical lines 24 and 25 hanging down from the farthest circumferential part of the through hole 8 to the vertical line 22 when viewed in the direction of the vertical line.

[0096] The value obtained by subtracting the hole width 26 from the bypass path width 23 is the bypassable width 27 through which the vibration current can flow. The vibration current flowing between the two semiconductor elements 3 passes through the capacitance path 29 through the capacitor element 4 and the bypass path 30 through the bypassable width 27 in addition to the shortest path 28 between the two semiconductor elements 3. All the vibration currents flowing from the semiconductor element 3 to the capacitor element 4 do not flow toward the capacitor element 4, and the vibration currents pass through the bypass path 30, thereby dispersing the vibration currents and further suppressing the vibrations.

[0097] Setting the bypassable width 27 to be greater than 1 / 2 of the short side length of the capacitor element 4 is described. Here, the semiconductor element 3 is set as an IGBT and the capacitor element 4 is set as a diode for description. In the case where the capacitor element 4 is installed in the power module 100 only as a diode function, the width of the lead frame 1 when installed on the electrode of the diode is sufficient as long as it has the width of the short side of the diode, and does not need to exceed the width of the short side of the diode. Even if the current flowing through the coupled IGBT is considered as the original function of rectification when the IGBT is turned off, it will not flow away from the electrode of the diode, and the maximum width of the short side of the diode is directly designed as the width of the lead frame 1.

[0098] Here, the value obtained by subtracting the hole width 26 from the bypass path width 23 is zero or more, which means that it has a purpose other than rectification when the IGBT is turned off. In fact, there is also a problem with working accuracy. As the final shape with a margin of several mm, 1 / 2 of the short side length of the capacitor element 4 has a purpose path for releasing current between the IGBTs in addition to the current flowing between the IGBT and the diode. The conclusion is that when considering a diode that does not have a function other than rectification when the IGBT is turned off, it has no purpose other than suppressing noise caused by vibration.

[0099] In the comparative example shown in FIG11 , the value obtained by subtracting the hole width from the bypass path width is zero. In this case, there is a path where the vibration current is concentrated along the periphery of the hole. The vibration current is a current that causes vibration due to the parasitic capacitance between the IGBT and the diode. By setting the bypass width 27 to more than 1 / 2 of the short side length of the capacitor element 4, the vibration current can pass through the bypass path 30 that is not the capacitor via the path 29 and the shortest path 28, which can help suppress vibration.

[0100] As described above, in the power module 100 according to the seventh embodiment, one or both of the lead frame 1 and the lead frame 2 have a through hole 8 between each of the two semiconductor elements 3 and the capacitor element 4, and a value obtained by subtracting the distance between the two vertical lines 24 and 25 from the length of the portion of the vertical line 22 from the periphery of the capacitor element 4 to the line segment is greater than 1 / 2 of the short side length of the capacitor element 4, wherein the vertical line 22 is suspended from the center of the connection portion of the lead frame 1 or the lead frame 2 of the capacitor element 4 toward the line segment 21, and the line segment 21 connects the two semiconductor elements 3 arranged at the connection point. The corner of a semiconductor element 3a at a position near the capacitor element 4, which is closest to the capacitor element 4, and the end of the long side of the other semiconductor element 3b on the side opposite to the capacitor element 4, which is the corner, on the side away from the capacitor element 4, the above two vertical lines 24 and 25 hang down from the part of the circle farthest away from the through hole 8 to the vertical line 22 when viewed along the direction of the vertical line. Therefore, the vibration current can pass through the bypass path 30 that is not the capacitor path 29 and the shortest path 28, and the vibration current is dispersed, which can suppress the vibration caused by PETT and IMPATT.

[0101] In addition, although the present application describes various exemplary embodiments and examples, the various features, methods and functions described in one or more embodiments are not limited to application to specific embodiments, but can also be applied to the embodiments alone or in various combinations.

[0102] Therefore, it is considered that numerous modifications not shown in the examples are also included in the technical scope disclosed in the present specification, for example, including the case where at least one component is modified, added or omitted, and the case where at least one component is extracted and combined with components of other embodiments.

[0103] Description of symbols

[0104] 1 Lead frame

[0105] 1a Terminal section

[0106] 1b Through hole

[0107] 2 Lead frame

[0108] 3 Semiconductor components

[0109] 4 Capacitor components

[0110] 5 Lead frame

[0111] 6 Electrodes

[0112] 7 Through hole

[0113] 8 Through holes

[0114] 11. Flat panel antenna

[0115] 12. Grounding

[0116] 13 Insulating dielectric

[0117] 14 Vertical Line

[0118] 15 Shortest Path

[0119] 16 Capacitor via path

[0120] 17 Bypass Path

[0121] 21 Line segment

[0122] 22 Vertical Line

[0123] 23 Bypass path width

[0124] 24 Vertical Line

[0125] 25 Vertical Line

[0126] 26 hole width

[0127] 27 Bypassable Width

[0128] 28 Shortest Path

[0129] 29 Capacitor via path

[0130] 30 Bypass path

[0131] 100 Power Module

[0132] 200 Power Module

[0133] 201 Lead frame

[0134] 202 Overlap

[0135] 300 Power Module

[0136] 301 lead frame

[0137] 302 Overlap joint.

Claims

1. A power module, characterized in that: include: Two semiconductor elements, each of which has electrodes on one surface and the other surface thereof; a first conductive metal pattern in the form of a plate, the first conductive metal pattern being connected to the electrodes on one surface of each of the two semiconductor elements arranged side by side on the same plane; a second conductive metal pattern in the form of a plate, the second conductive metal pattern being connected to the electrodes on the other surfaces of the two semiconductor elements; and a capacitor element, the capacitor element being disposed between the first conductive metal pattern and the second conductive metal pattern, and forming an electrostatic capacitor between the first conductive metal pattern and the second conductive metal pattern, The two semiconductor elements and the capacitor element are arranged at the vertices of a triangle on the same plane. The first conductive metal pattern and the second conductive metal pattern are characterized by having a flat plate shape having an outer shape including three vertices and three sides of the triangle, The shortest connection path length between the two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern is set as the first shortest path, the shorter of the two shortest connection path lengths between the two semiconductor elements in the first conductive metal pattern and the second conductive metal pattern and the capacitor element is set as the second shortest path, and the longer of the two shortest connection path lengths is set as the third shortest path, then (first shortest path) ≥ (second shortest path), and ((First shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2 , a resonance frequency obtained from two electrostatic capacitances parasitic between one surface and the other surface of the two semiconductor elements and two inductances generated between one surface and the other surface of the two semiconductor elements of the first conductive metal pattern and the second conductive metal pattern as a first resonance frequency; a resonance frequency obtained from electrostatic capacitances parasitic between one surface and the other surface of one element of the two semiconductor elements, electrostatic capacitances generated by the capacitance element, and two inductances generated between one surface and the capacitance element and between the other surface of the one element of the semiconductor element of the first conductive metal pattern and the second conductive metal pattern as a second resonance frequency; a resonance frequency obtained from electrostatic capacitances parasitic between one surface and the other surface of the other element of the two semiconductor elements, electrostatic capacitances generated by the capacitance element, and two inductances generated between one surface and the capacitance element and between the other surface of the other element of the semiconductor element of the first conductive metal pattern and the second conductive metal pattern as a third resonance frequency, the first conductive metal pattern and the second conductive metal pattern have a thickness greater than twice the depth of skin through which current flows under the skin effect generated by the first resonant frequency, the second resonant frequency, and the third resonant frequency of the current path, Vibration caused by any one of the first resonant frequency, the second resonant frequency and the third resonant frequency of a current path between any two elements of the two semiconductor elements and the capacitive element is also reduced through the first conductive metal pattern, the second conductive metal pattern and the capacitive element.

2. The power module according to claim 1, characterized in that: include: n semiconductor elements, each of which has electrodes on one side and the other side, wherein n is an integer greater than or equal to 3; a first conductive metal pattern in the form of a plate, the first conductive metal pattern being connected to the electrodes on one surface of each of the n semiconductor elements arranged side by side on the same plane; a second conductive metal pattern in a flat plate shape, the second conductive metal pattern being connected to the electrode on the other surface of each of the n semiconductor elements; and a capacitor element, the capacitor element being disposed between the first conductive metal pattern and the second conductive metal pattern, and forming an electrostatic capacitor between the first conductive metal pattern and the second conductive metal pattern, Two adjacent semiconductor elements selected from the n semiconductor elements and the capacitor element are arranged at the vertices of a triangle on the same plane. The first conductive metal pattern and the second conductive metal pattern are characterized by having a flat plate shape having an outer shape including three vertices and three sides of the triangle, The shortest connection path length between two adjacent semiconductor elements in the first conductive metal pattern and the second conductive metal pattern is set as a first shortest path, the shorter of the two shortest connection path lengths between two adjacent semiconductor elements in the first conductive metal pattern and the second conductive metal pattern and the capacitor element is set as a second shortest path, and the longer of the two shortest connection path lengths is set as a third shortest path, then (first shortest path) ≥ (second shortest path), and ((First shortest path) 2 +(Second shortest path) 2 )≥(third shortest path) 2 , a resonance frequency obtained by two electrostatic capacitances parasitic between one surface and the other surface of the two adjacent semiconductor elements and two inductances generated between one surface and the other surface of the two semiconductor elements of the first conductive metal pattern and the second conductive metal pattern as a first resonance frequency; a resonance frequency obtained by electrostatic capacitances parasitic between one surface and the other surface of one element of the two adjacent semiconductor elements, electrostatic capacitances generated by the capacitance element, and two inductances generated between one surface and the capacitance element and between the other surface of one element of the semiconductor element of the first conductive metal pattern and the second conductive metal pattern as a second resonance frequency; a resonance frequency obtained by electrostatic capacitances parasitic between one surface and the other surface of the other element of the two adjacent semiconductor elements, electrostatic capacitances generated by the capacitance element, and two inductances generated between one surface and the capacitance element and between the other surface of the other element of the semiconductor element of the first conductive metal pattern and the second conductive metal pattern as a third resonance frequency, The first conductive metal pattern and the second conductive metal pattern have a thickness greater than twice the depth of the skin through which the current flows under the skin effect generated by the first resonant frequency, the second resonant frequency, and the third resonant frequency of the current path, Through the first conductive metal pattern, the second conductive metal pattern and the capacitor element, the vibration caused by any one of the first resonant frequency, the second resonant frequency and the third resonant frequency of the current path between the two adjacent semiconductor elements and any two elements of the capacitor element is also reduced in two adjacent semiconductor elements among the n semiconductor elements, the two conductive metal patterns and the capacitor element near the semiconductor element.

3. The power module according to claim 2, characterized in that: The two adjacent semiconductor elements are two power semiconductor elements that form a depletion layer inside the semiconductor element when the semiconductor element is turned off or when the switching from the forward bias to the reverse bias stops. The frequency determined by the time it takes for majority-side carriers to move and escape through the depletion layer inside the power semiconductor element when the switching is turned off or stopped is set as a first natural frequency. The frequency determined by the time for minority carriers to move and be discharged through the depletion layer inside the bipolar power semiconductor element at the time of the cut-off or the time of the switching stop is set as the second natural vibration frequency. The two adjacent power semiconductor elements are respectively the power semiconductor element having only the first natural vibration frequency, or the power semiconductor element having both the first natural vibration frequency and the second natural vibration frequency. The frequency range in which the first natural vibration frequency and the second natural vibration frequency are distributed includes the first resonant frequency, the second resonant frequency and the third resonant frequency. The vibration generated by the proximity of the first natural vibration frequency, the second natural vibration frequency and any one of the first resonant frequency, the second resonant frequency and the third resonant frequency and thus reinforcing each other is also suppressed.

4. The power module according to claim 2, characterized in that: The two semiconductor elements are two insulated gate bipolar transistors, two bipolar transistors or two metal oxide film type field effect transistors, and the capacitor element is a PN junction diode or a Schottky junction diode, or, The two semiconductor elements are two PN junction diodes or two Schottky junction diodes, and the capacitive element is an insulated gate bipolar transistor, a bipolar transistor, or a metal oxide film type field effect transistor.

5. The power module according to claim 2, characterized in that: The two adjacent semiconductor elements are metal oxide film type field effect transistors or reverse conducting insulated gate bipolar transistors, The capacitive element is a capacitor formed by an insulating filler provided between the first conductive metal pattern and the second conductive metal pattern.

6. The power module according to claim 2, characterized in that: The first conductive metal pattern becomes a planar antenna with the second conductive metal pattern as ground in response to the voltage change of the two semiconductor elements or the capacitor element. The basic radiation frequency of the radio wave derived from the vertical and horizontal dimensions of the planar antenna is fr=c0 / (2L e √ε r ) is a frequency higher than the first resonant frequency, the second resonant frequency and the third resonant frequency, wherein c0 is the speed of light, ε r is the dielectric constant of the element, L e is the length of the long side of the flat antenna.

7. The power module according to claim 2, characterized in that: One or both of the first conductive metal pattern and the second conductive metal pattern have two or more through holes on a vertical line extending from a connection point between the capacitor element and the first conductive metal pattern or the second conductive metal pattern to the shortest connection path between the two adjacent semiconductor elements.

8. The power module according to claim 2, characterized in that: The two adjacent semiconductor elements and the capacitor element arranged at the vertices of a triangle are rectangular. One long side of the capacitor element is arranged on a side opposite to one long side of each of the two adjacent semiconductor elements. One or both of the first conductive metal pattern and the second conductive metal pattern have a through hole between each of the two adjacent semiconductor elements and the capacitor element. The value obtained by subtracting the distance between two perpendicular lines hanging from the farthest circumferential part of the through hole to the perpendicular line when observed along the direction of the perpendicular line from the length of the portion of the perpendicular line hanging from the center of the connection part between the capacitor element and the first conductive metal pattern or the second conductive metal pattern, and which is greater than 1 / 2 of the length of the short side of the capacitor element, is obtained. The line segment connects the corner closest to the capacitor element of one of the two adjacent semiconductor elements arranged at a position close to the capacitor element, and the corner of the long side of the other semiconductor element on the side opposite to the capacitor element, which is away from the capacitor element.

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