Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device is disclosed, comprising: a substrate having PMOSFET and NMOSFET regions spaced apart in a direction; a device isolation layer disposed on the substrate, the device isolation layer defining first and second active patterns on the PMOSFET and NMOSFET regions, respectively; a gate electrode spanning the first and second active patterns; first and second source / drain patterns disposed on the first and second active patterns, respectively, and proximate the gate electrode, respectively; and an active contact extending in the direction and coupled to the first and second source / drain patterns. The active contact includes first and second body portions disposed on the first and second source / drain patterns, respectively, and a first protrusion and a recess disposed between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recess has an upwardly recessed bottom.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Korean Patent Application No. 10-2020-0067618, filed on June 4, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more specifically, to semiconductor devices including field-effect transistors and methods of manufacturing the same. Background Technology

[0004] Due to their small size, versatility, and / or low cost, semiconductor devices have become essential components in the electronics industry. Semiconductor devices can be broadly categorized into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that combine both memory and logic elements. With the continued development of the electronics industry, there is a growing demand for semiconductor devices with enhanced characteristics such as high reliability, high performance, and / or versatility. To meet this demand, the complexity and / or integration density of semiconductor devices have increased. Summary of the Invention

[0005] Embodiments of the present invention provide semiconductor devices including field-effect transistors with improved electrical characteristics and methods for manufacturing the same.

[0006] An embodiment of the present invention provides a semiconductor device comprising: a substrate having a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction; a device isolation layer on the substrate, the device isolation layer defining a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region; a gate electrode extending in the first direction and spanning the first active pattern and the second active pattern; a first source / drain pattern and a second source / drain pattern, respectively on the first active pattern and the second active pattern, each of the first source / drain pattern and the second source / drain pattern being adjacent to a side of the gate electrode; and a first active contact extending in the first direction and coupled to the first source / drain pattern and the second source / drain pattern. The first active contact may include: a first body portion on the first source / drain pattern; a second body portion on the second source / drain pattern; and a first protrusion and a recess between the first body portion and the second body portion. The first protruding portion and the recessed portion are above the device isolation layer between the PMOSFET region and the NMOSFET region, and the recessed portion of the first active contact has a bottom surface recessed in a second direction away from the device isolation layer.

[0007] Embodiments of the present invention also provide a semiconductor device comprising: a first logic unit and a second logic unit, on a substrate and adjacent to each other in a first direction, wherein each of the first logic unit and the second logic unit may have a first active region and a second active region, the first active region being one of a PMOSFET region and an NMOSFET region, and the second active region being the other of the PMOSFET region and the NMOSFET region; and an active contact extending from the first active region of the first logic unit to the first active region of the second logic unit. The active contact may include: a first body portion on the first active region of the first logic unit; a second body portion on the first active region of the second logic unit; and a first protrusion and a recess between the first body portion and the second body portion. The first protrusion and the recess are located above a device isolation layer between the first active region of the first logic unit and the first active region of the second logic unit. The bottom surface of the recess may be higher than the bottom surface of the first protrusion and lower than the bottom surface of the first body portion.

[0008] An embodiment of the present invention also provides a semiconductor device, comprising: a logic cell on a substrate, the logic cell having a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction, the logic cell having a first boundary, a second boundary, a third boundary, and a fourth boundary, the first boundary and the second boundary being opposite to each other in a second direction intersecting the first direction, the third boundary and the fourth boundary being opposite to each other in the first direction; a device isolation layer on the substrate, the device isolation layer defining a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region, the first active pattern and the second active pattern extending in the second direction, the upper portions of the first active pattern and the second active pattern protruding above the device isolation layer; a gate electrode extending in the first direction and crossing the first active pattern and the second active pattern; a first source / drain pattern and a second source / drain pattern on the upper portions of the first active pattern and the second active pattern, respectively, and the first source / drain pattern and the... Each of the second source / drain patterns is adjacent to a side of the gate electrode; a separation structure is on at least one of the first boundary and the second boundary; a gate spacer is on at least one side surface of the gate electrode; a gate capping pattern is on the top surface of the gate electrode; an interlayer insulating layer is on the gate capping pattern; an active contact is penetrated through the interlayer insulating layer and coupled to the first source / drain pattern and the second source / drain pattern; a silicide pattern is located between the active contact and each of the first source / drain pattern and the second source / drain pattern; a gate contact is penetrated through the interlayer insulating layer and the gate capping pattern and coupled to the gate electrode; a first metal layer is on the interlayer insulating layer, the first metal layer including: a first power line and a second power line extending in the second direction on the third boundary and the fourth boundary respectively, and a first interconnect between the first power line and the second power line, the first interconnect being electrically connected to the active contact and the gate contact respectively; and a second metal layer is above the first metal layer. The second metal layer may include: a second interconnect extending in the first direction and electrically connected to the first metal layer. The active contact may include: a first main body portion on the first source / drain pattern; a second main body portion on the second source / drain pattern; and a first protruding portion and a recessed portion between the first main body portion and the second main body portion. The first protruding portion and the recessed portion are on the device isolation layer between the PMOSFET region and the NMOSFET region, and the recessed portion of the active contact has a bottom surface recessed in a direction away from the device isolation layer.

[0009] Embodiments of the present invention also provide a method for manufacturing a semiconductor device, comprising: forming a first active pattern and a second active pattern on a PMOSFET region and an NMOSFET region of a substrate, respectively; forming a device isolation layer on the substrate, the device isolation layer exposing the upper portions of the first active pattern and the second active pattern; forming a first source / drain pattern and a second source / drain pattern in the upper portions of the first active pattern and the second active pattern, respectively; forming a gate electrode spanning the first active pattern and the second active pattern and extending in a first direction; forming an insulating layer on the gate electrode; forming a hard mask pattern on the insulating layer, the hard mask pattern having an opening vertically overlapping the first source / drain pattern and the second source / drain pattern; using the hard mask pattern as an etching mask to etch the insulating layer to expose the first source / drain pattern and the second source / drain pattern; and forming active contacts on the exposed first source / drain pattern and the second source / drain pattern. The insulating layer exposed by the opening may have a first top surface at a first height and a second top surface at a second height higher than the first height. The first top surface may be located above each of the first source / drain pattern and the second source / drain pattern, and the second top surface may be located above the device isolation layer between the PMOSFET region and the NMOSFET region.

[0010] An embodiment of the present invention also provides a semiconductor device comprising: a first source / drain pattern on a first active pattern of a substrate; a second source / drain pattern on a second active pattern of the substrate, the first source / drain pattern being spaced apart from the second source / drain pattern in a first direction extending parallel to an upper surface of the substrate; and an active contact portion extending in the first direction and contacting a top surface of the first source / drain pattern and a top surface of the second source / drain pattern. The active contact portion includes: a first protrusion extending on an inclined surface of the first source / drain pattern facing the second source / drain pattern; a second protrusion extending on an inclined surface of the second source / drain pattern facing the first source / drain pattern; and a recessed portion between the first protrusion and the second protrusion. The bottom surface of the recessed portion is higher than the bottom surfaces of the first and second protrusions in a second direction, and the bottom surface of the recessed portion is lower than the top surfaces of the first and second source / drain patterns in the second direction, wherein the second direction extends orthogonally to the upper surface of the substrate. Attached Figure Description

[0011] Figure 1 A conceptual diagram of a logic unit of a semiconductor device according to an embodiment of the present invention is shown.

[0012] Figure 2 A conceptual diagram of a logic unit of a semiconductor device according to an embodiment of the present invention is shown.

[0013] Figure 3 A conceptual diagram of a logic unit of a semiconductor device according to an embodiment of the present invention is shown.

[0014] Figure 4 A plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0015] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E Showing along respectively Figure 4 The cross-sectional views of lines AA′, BB′, CC′, DD′ and EE′.

[0016] Figure 6 The edge of the semiconductor device according to the comparative example is shown. Figure 4 The cross-sectional view taken by line CC′.

[0017] Figure 7 A plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention is shown.

[0018] Figure 8A , Figure 8B , Figure 8C and Figure 8D Showing along respectively Figure 7 Cross-sectional views of lines AA′, BB′, CC′ and DD′.

[0019] Figure 9 A plan view is shown illustrating another method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention.

[0020] Figure 10A , Figure 10B , Figure 10C and Figure 10D Showing along respectively Figure 9 Cross-sectional views of lines AA′, BB′, CC′ and DD′.

[0021] Figure 11 A plan view is shown illustrating another method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention.

[0022] Figure 12A , Figure 12B and Figure 12C Showing along respectively Figure 11 The cross-sectional views of lines AA′, BB′ and CC′.

[0023] Figure 13 A plan view is shown illustrating another method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention.

[0024] Figure 14A , Figure 14B and Figure 14C Showing along respectively Figure 13 The cross-sectional views of lines AA′, BB′ and CC′.

[0025] Figure 15 A plan view is shown illustrating another method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention.

[0026] Figure 16A , Figure 16B and Figure 16C Showing along respectively Figure 15 The cross-sectional views of lines AA′, BB′ and CC′.

[0027] Figure 17 , Figure 18 , Figure 19 and Figure 20 A cross-sectional view is shown of a method for forming an opening according to an embodiment of the present invention.

[0028] Figure 21 The edge of the semiconductor device shown is an embodiment of the concept of the present invention. Figure 4 The cross-sectional view taken by line CC′.

[0029] Figure 22A , Figure 22B , Figure 22C and Figure 22D The semiconductor device shown in the embodiment of the present invention has separate edges Figure 4 Cross-sectional views of lines AA′, BB′, CC′ and EE′. Detailed Implementation

[0030] Figures 1 to 3 A conceptual diagram of a logic unit of a semiconductor device according to an embodiment of the present invention is shown.

[0031] Reference Figure 1 The diagram illustrates a single-height cell (SHC). Specifically, a first power line M1_R1 and a second power line M1_R2 can be disposed on the substrate 100. The first power line M1_R1 can be a path providing a drain voltage VDD (e.g., a power supply voltage). The second power line M1_R2 can be a path providing a source voltage VSS (e.g., a ground voltage).

[0032] The single-height cell SHC can be defined between the first power line M1_R1 and the second power line M1_R2. The single-height cell SHC may include a PMOSFET region PR and an NMOSFET region NR. In other words, the single-height cell SHC may have a CMOS structure and be disposed between the first power line M1_R1 and the second power line M1_R2.

[0033] Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as the first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first power line M1_R1 and the second power line M1_R2.

[0034] Single-height cells (SHCs) can form a single logic unit. It should be understood that, in this document, a logic unit can refer to a logic device (e.g., AND, OR, XOR, XNOR, inverter, etc.) configured to perform a specific function. In other words, a logic unit can include transistors and interconnects connected to each other to form a logic device.

[0035] Reference Figure 2 The diagram illustrates a double-height cell DHC. Specifically, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 can be disposed on the substrate 100. The first power line M1_R1 can be disposed between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 can be a path that provides a drain voltage VDD to it.

[0036] The double-height unit DHC can be defined between the second power line M1_R2 and the third power line M1_R3. The double-height unit DHC may include: a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0037] The first NMOSFET region NR1 can be adjacent to the second power line M1_R2. The second NMOSFET region NR2 can be adjacent to the third power line M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 can be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 can be positioned between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0038] The length of the double-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1The height of the first height HE1 is approximately twice that of the second height DHC. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the double-height unit DHC can be combined to serve as a single PMOSFET region.

[0039] Therefore, the channel size of the PMOS transistor in a double-height cell DHC can be larger than [the required value]. Figure 1 The channel size of the PMOS transistor in a single-height cell SHC is [not specified]. For example, the channel size of the PMOS transistor in a double-height cell DHC can be approximately twice that of the PMOS transistor in a single-height cell SHC. In this case, the double-height cell DHC can operate at a higher speed than the single-height cell SHC. In an embodiment, [not specified] Figure 2 The double-height cell DHC shown can be defined as a multi-height cell. Although not shown, multi-height cells can include: triple-height cells whose cell height is approximately three times the height of the single-height cell SHC.

[0040] Reference Figure 3 The first single-height unit SHC1, the second single-height unit SHC2, and the double-height unit DHC are shown as being arranged in two dimensions on the substrate 100. The first single-height unit SHC1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The second single-height unit SHC2 may be disposed between the first power line M1_R1 and the third power line M1_R3. The second single-height unit SHC2 may be adjacent to the first single-height unit SHC1 in the first direction D1.

[0041] The double height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The double height unit DHC can be adjacent to the first single height unit SHC1 and the second single height unit SHC2 in the second direction D2.

[0042] The separation structure DB can be disposed between the first single-height unit SHC1 and the double-height unit DHC, and between the second single-height unit SHC2 and the double-height unit DHC. The active region of the double-height unit DHC can be electrically separated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 through the separation structure DB.

[0043] Figure 4 A plan view of a semiconductor device according to an embodiment of the present invention is shown. Figures 5A to 5E Showing along respectively Figure 4 The cross-sectional views of lines AA′, BB′, CC′, DD′ and EE′. Figure 4 and Figures 5A to 5E Show Figure 3Examples of the specific structures of the first single-height unit SHC1 and the second single-height unit SHC2.

[0044] Reference Figure 4 and Figures 5A to 5E The first single-height unit SHC1 and the second single-height unit SHC2 can be disposed on the substrate 100. Logic transistors constituting the logic circuit can be disposed on each of the first single-height unit SHC1 and the second single-height unit SHC2. The substrate 100 can be a semiconductor substrate, including, for example, silicon, germanium, silicon-germanium, or a compound semiconductor substrate. As an example, the substrate 100 can be a silicon wafer.

[0045] The substrate 100 may include: a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. For example, each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may be as follows: Figure 4 Extending in the second direction D2 (or along the second direction D2).

[0046] The first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 can be defined by a second trench TR2, which is formed in the upper part of the substrate 100. For example, the second trench TR2 can be located between the first NMOSFET region NR1 and the first PMOSFET region PR1. The second trench TR2 can also be located between the first PMOSFET region PR1 and the second PMOSFET region PR2. The second trench TR2 can also be located between the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0047] The first active pattern AP1 can be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0048] The first active pattern AP1 and the second active pattern AP2 may extend parallel to each other in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 (e.g., vertically projecting portions). The first trench TR1 may be defined between adjacent first active patterns AP1 in the first active pattern AP1 and between adjacent second active patterns AP2 in the second active pattern AP2. The first trench TR1 may be shallower than the second trench TR2.

[0049] A device isolation layer ST can be configured to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include, for example, a silicon oxide layer. The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may be a protruding pattern that extends vertically above the device isolation layer ST (e.g., see...). Figure 5E The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may have a fin shape. The device isolation layer ST may not cover the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover the lower surface of each of the first active pattern AP1 and the second active pattern AP2.

[0050] The first source / drain pattern SD1 can be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The first source / drain pattern SD1 can be disposed on the upper part of each of the first active patterns AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). The first channel pattern CH1 can be located between each pair of first source / drain patterns SD1 that are adjacent to each other in the second direction D2.

[0051] The second source / drain pattern SD2 can be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The second source / drain pattern SD2 can be disposed on the upper part of each of the second active patterns AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 can be located between each pair of second source / drain patterns SD2 that are adjacent to each other in the second direction D2.

[0052] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. As an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 can have top surfaces that are coplanar with the top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0053] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor substrate 100. In this case, compressive stress may be applied to the first source / drain pattern SD1 on the first channel pattern CH1 between them. In an embodiment, the second source / drain pattern SD2 may be formed of or comprise the same semiconductor material as the substrate 100 (e.g., Si).

[0054] A gate electrode GE can be configured to span the first active pattern AP1 and the second active pattern AP2 and extend in a first direction D1. The gate electrode GE can be arranged in a second direction D2 with a first spacing. When viewed in a plan view, the gate electrode GE can overlap with the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE can be configured to face the top surface and the opposite side surface of each of the first channel pattern CH1 and the second channel pattern CH2.

[0055] Refer again Figure 5E The gate electrode GE can be disposed on the first top surface TS1 of the first channel pattern CH1 and at least one first side surface SW1 of the first channel pattern CH1. The gate electrode GE can also be disposed on the second top surface TS2 of the second channel pattern CH2 and at least one second side surface SW2 of the second channel pattern CH2. In other words, the transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., FinFET), wherein the gate electrode GE is configured to three-dimensionally surround the channel patterns CH1 and CH2.

[0056] As an example, the first single-height unit SHC1 may have a first boundary BD1 and a second boundary BD2, which are opposite to each other in a second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The first single-height unit SHC1 may also have a third boundary BD3 and a fourth boundary BD4, which are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0057] The gate dicing pattern CT can be disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The gate dicing pattern CT can also be disposed on the boundary of each of the first single-height cells SHC1 and the second single-height cell SHC2 in the second direction D2. The gate dicing pattern CT can be arranged along the third boundary BD3 at a first spacing. The gate dicing pattern CT can also be arranged along the fourth boundary BD4 at a first spacing. When viewed in a plan view, the gate dicing patterns CT on the third boundary BD3 and the fourth boundary BD4 can be configured to overlap with the gate electrode GE, respectively. The gate dicing pattern CT can be formed of or comprise at least one of an insulating material (e.g., silicon oxide or silicon nitride).

[0058] The gate electrode GE on the first single-height unit SHC1 can be spaced apart from the gate electrode GE on the second single-height unit SHC2 by a gate cutting pattern CT. The gate cutting pattern CT can be located between the gate electrodes GE on the first single-height unit SHC1 and the second single-height unit SHC2 that are aligned with each other in the first direction D1. In other words, the gate electrode GE extending in the first direction D1 can be divided into multiple gate electrodes GE by the gate cutting pattern CT.

[0059] Refer again Figure 4 and Figures 5A to 5E A pair of gate spacers GS can be disposed on opposite side surfaces of each of the gate electrodes GE. The gate spacers GS can extend along the gate electrodes GE in a first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrodes GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, as will be described below. The gate spacers GS can be formed of, for example, at least one of SiCN, SiCON, or SiN, or include at least one of them. In an embodiment, the gate spacers GS can be a multi-layered structure comprising at least two different materials selected from SiCN, SiCON, and SiN.

[0060] A gate capping pattern GP can be provided on each of the gate electrodes GE. The gate capping pattern GP can extend along the gate electrode GE in a first direction D1. The gate capping pattern GP can be formed of or include at least one material that has etch selectivity for the first interlayer insulating layer 110 and the second interlayer insulating layer 120, as will be described below. Specifically, the gate capping pattern GP can be formed of or include at least one of SiON, SiCN, SiCON or SiN, for example.

[0061] The gate dielectric pattern GI may be located between the gate electrode GE and the first active pattern AP1, and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along and be on the bottom surface of the gate electrode GE. As an example, the gate dielectric pattern GI may cover the first top surface TS1 and the first side surface SW1 of the first channel pattern CH1. The gate dielectric pattern GI may also cover the second top surface TS2 and the opposing second side surface SW2 of the second channel pattern CH2. The gate dielectric pattern GI may cover the top surface of the device isolation layer ST below the gate electrode GE (see, for example, [reference needed]). Figure 5E ).

[0062] In an embodiment, the gate dielectric pattern GI may be formed of or comprise a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0063] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate dielectric pattern GI and may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include a work function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized.

[0064] The first metal pattern may be formed of or comprise a metal nitride. For example, the first metal pattern may comprise at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), and nitrogen (N). The first metal pattern may also comprise carbon (C). The first metal pattern may comprise multiple stacked work function metal layers.

[0065] The second metal pattern may include a metallic material with a lower electrical resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0066] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS, the first source / drain pattern SD1, and the second source / drain pattern SD2. The top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate cap pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In an embodiment, at least one of the first interlayer insulating layers 110 to the fourth interlayer insulating layer 140 may include a silicon oxide layer.

[0067] A pair of separate structures DB can be disposed on both sides of each of the first single-height unit SHC1 and the second single-height unit SHC2, facing each other in the second direction D2. For example, the pair of separate structures DB can be disposed on the first boundary BD1 and the second boundary BD2 of the first single-height unit SHC1, respectively. The separate structures DB can extend in the first direction D1 and be parallel to the gate electrode GE. The spacing between the separate structures DB and the adjacent gate electrode GE can be equal to the first spacing.

[0068] The separation structure DB can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB can penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB can electrically separate the active region of each of the first single-height unit SHC1 and the second single-height unit SHC2 from the active region of the adjacent unit.

[0069] The active contact AC can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. Each of the active contacts AC can be disposed between a pair of gate electrodes GE. When viewed in a plan view, each of the active regions AC can be a strip or line pattern extending in the first direction D1.

[0070] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed using a gate cap pattern GP and a gate spacer GS through a self-aligned process. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC can cover a portion of the top surface of the gate cap pattern GP.

[0071] The silicide pattern SC can be located between the active contact AC and the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The active contact AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC, respectively. The silicide pattern SC can be formed of or include at least one of a metal-silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0072] The active contact AC may include a first active contact AC1, a second active contact AC2, and a third active contact AC3. The first active contact AC1 on the first single-height unit SHC1 can electrically connect the first source / drain pattern SD1 of the first PMOSFET region PR1 to the second source / drain pattern SD2 of the first NMOSFET region NR1. The first active contact AC1 can extend from the second source / drain pattern SD2 of the first NMOSFET region NR1 to the first source / drain pattern SD1 of the first PMOSFET region PR1 in the first direction D1.

[0073] The second active contact AC2 can connect the first source / drain pattern SD1 of the first PMOSFET region PR1 to the first source / drain pattern SD1 of the second PMOSFET region PR2. The second active contact AC2 extends from the first source / drain pattern SD1 of the first PMOSFET region PR1 to the first source / drain pattern SD1 of the second PMOSFET region PR2 in the first direction D1. The second active contact AC2 can cross the boundary (e.g., the third boundary BD3) between the first single-height unit SHC1 and the second single-height unit SHC2, and can be jointly coupled to the first PMOSFET region PR1 of the first single-height unit SHC1 and the second PMOSFET region PR2 of the second single-height unit SHC2. The second active contact AC2 can be electrically connected to the first power line M1_R1 of the first metal layer M1 through the first via VI1.

[0074] The third active contact AC3 on the second single-height unit SHC2 can be partially disposed on the first source / drain pattern SD1 of the second PMOSFET region PR2 or the second source / drain pattern SD2 of the second NMOSFET region NR2. Unlike the first active contact AC1 and the second active contact AC2 described above, the third active contact AC3 can be positioned on a single active region and can be provided without connecting adjacent active regions to each other.

[0075] When viewed in a plan view, the length of the third active contact AC3 in the first direction D1 can be less than the length of each of the first active contact AC1 and the second active contact AC2 in the first direction D1. For example, the length of the third active contact AC3 can be less than half the length of each of the first active contact AC1 and the second active contact AC2.

[0076] The gate contact GC, electrically connected to the gate electrode GE, can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP. When viewed in a plan view, the gate contact GC on the first single-height cell SHC1 can be configured to overlap with the first PMOSFET region PR1. In other words, the gate contact GC on the first single-height cell SHC1 can be disposed on the first active pattern AP1 (see, for example, [reference needed]). Figure 5A ).

[0077] Meanwhile, the gate contact GC can be freely disposed on the gate electrode GE without any restrictions on its position. For example, the gate contact GC on the second single-height unit SHC2 can be disposed on the second PMOSFET region PR2, the second NMOSFET region NR2, and the device isolation layer ST that fills the second trench TR2, respectively.

[0078] In the embodiments, reference is made to Figure 5A , Figure 5C and Figure 5D The upper portion of each active contact AC adjacent to the gate contact GC can be filled using an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP can be lower than the bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC can be formed by the upper insulating pattern UIP at a height lower than the bottom surface of the gate contact GC (see, for example, see...). Figure 5A Therefore, it is possible to prevent the gate contact GC and its adjacent active contact AC from coming into contact with each other, thereby preventing short circuit problems. For example, in Figure 5D In the second active contact AC2 shown, two upper insulating patterns UIP can be extended in the active contact AC in the first direction D1.

[0079] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a blocking pattern BM surrounding the conductive pattern FM. The conductive pattern FM may be formed of or include at least one of the metals selected from, for example, aluminum, copper, tungsten, molybdenum, or cobalt. The blocking pattern BM may cover the side and bottom surfaces of the conductive pattern FM. The blocking pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of, for example, titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0080] The first metal layer M1 may be disposed in the third interlayer insulating layer 130. For example, the first metal layer M1 may include: a first power line M1_R1, a second power line M1_R2, a third power line M1_R3, and a first interconnect line M1_I. The lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1 may extend in the second direction D2 to be parallel to each other.

[0081] Specifically, the first power line M1_R1 and the second power line M1_R2 can be respectively disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height unit SHC1. The first power line M1_R1 can extend along the third boundary BD3 and in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 and in the second direction D2.

[0082] The first interconnect M1_I of the first metal layer M1 can be arranged along the first direction D1 with a second spacing. The second spacing can be smaller than the first spacing. The line width of each of the first interconnect M1_I can be smaller than the line width of each of the first power lines to the third power lines M1_R1, M1_R2 and M1_R3.

[0083] The first metal layer M1 may further include a first via VI1. The first via VI1 may be disposed below lines M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1, respectively. The active contact AC and the interconnect line of the first metal layer M1 may be electrically connected to each other through the first via VI1. The gate contact GC and the interconnect line of the first metal layer M1 may be electrically connected to each other through the first via VI1.

[0084] The interconnects of the first metal layer M1 and the first via VI1 beneath it can be formed by separate processes. For example, each of the interconnects of the first metal layer M1 and the first via VI1 can be formed by a single damascene process. The semiconductor device according to this embodiment can be manufactured using a sub-20nm process.

[0085] The second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second interconnects M2_I. Each of the second interconnects M2_I in the second metal layer M2 may be a linear or strip pattern extending along the first direction D1. In other words, the second interconnects M2_I may extend in the first direction D1 parallel to each other.

[0086] The second metal layer M2 may further include a second via VI2, which is disposed below the second interconnect M2_I. The interconnects of the first metal layer M1 and the second metal layer M2 can be electrically connected to each other through the second via VI2. The interconnects of the second metal layer M2 and the second via VI2 below it can be formed together using a dual damascene process.

[0087] The interconnects of the first metal layer M1 and the second metal layer M2 can be formed of the same conductive material or different conductive materials, or include the same conductive material or different conductive materials. For example, the interconnects of the first metal layer M1 and the second metal layer M2 can be formed of or include at least one metallic material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Although not shown, multiple metal layers (e.g., M3, M4, M5, ..., Mn) can be additionally stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers can include interconnects for wiring between cells.

[0088] Reference Figure 5C The first active contact AC1 is described in more detail. The first active contact AC1 may include: a first body portion BP1 on a first source / drain pattern SD1 and a second body portion BP2 on a second source / drain pattern SD2. The first body portion BP1 can be connected to the top surface of the first source / drain pattern SD1 via a silicide pattern SC, and the second body portion BP2 can be connected to the top surface of the second source / drain pattern SD2 via a silicide pattern SC.

[0089] The first active contact AC1 may further include at least one protruding portion PP1 or PP2 and at least one recessed portion RP, located between the first body portion BP1 and the second body portion BP2. For example, the first active contact AC1 may include a first protruding portion PP1, a second protruding portion PP2, and a recessed portion RP between the first protruding portion PP1 and the second protruding portion PP2. The first protruding portion PP1, the second protruding portion PP2, and the recessed portion RP may be disposed on (or above) the device isolation layer ST, and between the first PMOSFET region PR1 and the first NMOSFET region NR1.

[0090] The first protruding portion PP1 may extend from the first body portion BP1 toward the device isolation layer ST along the inclined side surface of the first source / drain pattern SD1. The second protruding portion PP2 may extend from the second body portion BP2 toward the device isolation layer ST along the inclined side surface of the second source / drain pattern SD2. The recessed portion RP may be part of the first active contact AC1, the bottom of which is recessed in a direction away from the device isolation layer ST.

[0091] The bottom surface BS3 of the first protruding portion PP1 may be lower than the bottom surface BS1 of the first main body portion BP1. The bottom surface BS3 of the first protruding portion PP1 may be located at a height higher than the device isolation layer ST. For example, the first protruding portion PP1 may be vertically spaced from the device isolation layer ST, with a first interlayer insulation layer 110 inserted between them.

[0092] The bottom surface BS4 of the second protruding portion PP2 may be lower than the bottom surface BS2 of the second main body portion BP2. The bottom surface BS4 of the second protruding portion PP2 may be located at a height higher than the device isolation layer ST. For example, the second protruding portion PP2 may be vertically spaced from the device isolation layer ST, with a first interlayer insulation layer 110 inserted between them.

[0093] The bottom surface BS5 of the recessed portion RP may be higher than the bottom surface BS3 of the first protruding portion PP1, and may also be higher than the bottom surface BS4 of the second protruding portion PP2. The bottom surface BS5 of the recessed portion RP may be lower than the bottom surface BS1 of the first main body portion BP1, and may also be lower than the bottom surface BS2 of the second main body portion BP2.

[0094] The first active contact AC1 can be connected to the top surface of the first source / drain pattern SD1 via the first main body portion BP1, and can also be connected to the inclined side surface of the first source / drain pattern SD1 via the first protruding portion PP1. In other words, due to the first protruding portion PP1, the contact area between the first active contact AC1 and the first source / drain pattern SD1 can be increased. Therefore, the resistance between the first active contact AC1 and the first source / drain pattern SD1 can be reduced. Similarly, due to the second protruding portion PP2, the contact area between the first active contact AC1 and the second source / drain pattern SD2 can be increased. Therefore, the resistance between the first active contact AC1 and the second source / drain pattern SD2 can be reduced. Therefore, the operating characteristics (e.g., operating speed) of the semiconductor device according to the embodiment of the present invention can be improved.

[0095] Figure 6 The edge of the semiconductor device according to the comparative example is shown. Figure 4 The cross-sectional view taken by line CC′. (Refer to...) Figure 6 ,and Figure 5C The first active contact AC1 is different. Figure 6 The first active contact AC1 may include only one protruding portion PP between the first main body portion BP1 and the second main body portion BP2. For example, the first active contact AC1 may not include the recessed portion RP.

[0096] The protruding portion PP of the first active contact AC1 can extend very close to the height of the device isolation layer ST. When the protruding portion PP extends deeply in the downward direction, the parasitic capacitance between the first source / drain pattern SD1 and the protruding portion PP may increase. Similarly, the parasitic capacitance between the second source / drain pattern SD2 and the protruding portion PP may also increase. Therefore, as described above, if the protruding portion PP of the first active contact AC1 extends deeply in the downward direction, the resistance can be reduced; however, the operating characteristics of the device may deteriorate due to the increased parasitic capacitance.

[0097] However, in embodiments conceived according to the present invention Figure 5C In the semiconductor device, because the first active contact AC1 includes a recessed portion RP, the parasitic capacitance between the first source / drain pattern SD1 and the first active contact AC1 can be reduced. Similarly, the parasitic capacitance between the second source / drain pattern SD2 and the first active contact AC1 can also be reduced. That is, according to the embodiments of the present invention, both the resistance and parasitic capacitance between the contact and the source / drain pattern can be reduced. In other words, the operating characteristics and operating speed of the semiconductor device can be improved.

[0098] like Figure 5D As shown, the second active contact AC2 can have the same characteristics as the previously referenced... Figure 5C The first active contact AC1 described has a substantially identical bottom profile. The second active contact AC2 may include: a first body portion BP1 on the first source / drain pattern SD1 of the second PMOSFET region PR2 and a second body portion BP2 on the first source / drain pattern SD1 of the first PMOSFET region PR1. The second active contact AC2 may also include: a first protrusion PP1 and a second protrusion PP2, located between the first body portion BP1 and the second body portion BP2; and a recessed portion RP disposed between the first protrusion PP1 and the second protrusion PP2.

[0099] Due to the first protrusion PP1 and the second protrusion PP2, the contact resistance between the second active contact AC2 and the first source / drain pattern SD1 can be reduced. Due to the recessed portion RP, the parasitic capacitance between the second active contact AC2 and the first source / drain pattern SD1 can be reduced. Therefore, the operating characteristics and operating speed of the device can be improved.

[0100] Figure 7 , Figure 9 , Figure 11 , Figure 13 and Figure 15 A plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention is shown. Figure 8A , Figure 10A , Figure 12A , Figure 14A and Figure 16A Showing along respectively Figure 7 , Figure 9 , Figure 11 , Figure 13 and Figure 15 The cross-sectional view taken by line AA′. Figure 8B , Figure 10B , Figure 12B , Figure 14B and Figure 16B Showing along respectively Figure 7 , Figure 9 , Figure 11 , Figure 13 and Figure 15 The cross-sectional view taken from line BB′. Figure 8C , Figure 10C , Figure 12C , Figure 14C and Figure 16C Showing along respectively Figure 7 , Figure 9 , Figure 11 , Figure 13 and Figure 15 The cross-sectional view taken by line CC′. Figure 8D and 10D Showing along respectively Figure 7 and Figure 9 The cross-sectional view of the line DD′.

[0101] Reference Figure 7 and Figures 8A to 8D A substrate 100 may be provided having a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. The first NMOSFET region NR1 and the first PMOSFET region PR1 may define a first single-height unit SHC1, and the second NMOSFET region NR2 and the first PMOSFET region PR2 may define a second single-height unit SHC2.

[0102] The substrate 100 can be patterned to form a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0103] A device isolation layer ST may be formed on the substrate 100. The device isolation layer ST may be formed of or comprise an insulating material (e.g., silicon oxide). The device isolation layer ST may be recessed to expose the upper portion of each of the first active pattern AP1 and the second active pattern AP2. Thus, the upper portion of each of the first active pattern AP1 and the second active pattern AP2 may protrude vertically over the device isolation layer ST.

[0104] A sacrificial pattern SAP can be formed to span the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern SAP can be a linear or strip pattern extending in the first direction D1.

[0105] Specifically, forming a sacrificial pattern SAP may include: forming a sacrificial layer on a substrate 100; forming a mask pattern MA on the sacrificial layer; and patterning the sacrificial layer using the mask pattern MA as an etch mask. The sacrificial layer may be formed of or comprise polysilicon.

[0106] A pair of gate spacers GS can be formed on opposite side surfaces of each in the sacrificial pattern SAP. Forming the gate spacers GS may include: conformally forming a gate spacer layer to cover the entire top surface of the substrate 100; and anisotropically etching the gate spacer layer. The gate spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. Alternatively, the gate spacer layer may be, for example, a multi-layered structure including at least two of SiCN, SiCON, or SiN.

[0107] The first source / drain pattern SD1 can be formed on the upper part of each of the first active patterns AP1. A pair of first source / drain patterns SD1 can be formed on both sides of each of the sacrificial patterns SAP.

[0108] Specifically, the first recess can be formed by etching the upper portion of the first active pattern AP1 using a mask pattern MA and a gate spacing GS as an etching mask. During the etching of the upper portion of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 can be recessed, such as... Figure 8C As shown.

[0109] The first source / drain pattern SD1 can be formed by performing a selective epitaxial growth process using the inner surface of the first recess of the first active pattern AP1 as a seed layer. As a result of forming the first source / drain pattern SD1, a first channel pattern CH1 can be defined between each pair of first source / drain patterns SD1. The selective epitaxial growth process can include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The first source / drain pattern SD1 can be formed of or include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor material of the substrate 100. Each of the first source / drain patterns SD1 can be a multilayer structure comprising multiple semiconductor layers.

[0110] In one embodiment, during the selective epitaxial growth process used to form the first source / drain pattern SD1, the first source / drain pattern SD1 may be doped with impurities in situ. In another embodiment, after the formation of the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0111] A second source / drain pattern SD2 can be formed in the upper part of the second active pattern AP2. A pair of second source / drain patterns SD2 can be formed on both sides of each of the sacrificial patterns SAP.

[0112] Specifically, the second recess can be formed by etching the upper portion of the second active pattern AP2 using a mask pattern MA and a gate spacing GS as an etching mask. The second source / drain pattern SD2 can be formed by performing a selective epitaxial growth process using the inner surface of the second recess of the second active pattern AP2 as a seed layer. As a result of forming the second source / drain pattern SD2, a second channel pattern CH2 can be defined between each pair of second source / drain patterns SD2. In an embodiment, the second source / drain pattern SD2 can be formed of or comprise the same semiconductor material as the substrate 100 (e.g., Si). The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

[0113] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed sequentially using different processes. In other words, the first source / drain pattern SD1 and the second source / drain pattern SD2 do not need to be formed at the same time.

[0114] Reference Figure 9 and Figures 10A to 10D A first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the mask pattern MA, and the gate spacing GS. As an example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0115] The first interlayer insulating layer 110 can be planarized to expose the top surface of the sacrificial pattern SAP. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. All mask patterns MA can be removed during the planarization process. Therefore, the top surface of the first interlayer insulating layer 110 can be coplanar with the top surface of the sacrificial pattern SAP and the top surface of the gate spacer GS.

[0116] The sacrificial pattern SAP can be replaced with a gate electrode GE. Specifically, the exposed sacrificial pattern SAP can be selectively removed. As a result of removing the sacrificial pattern SAP, a blank space can be formed. The gate dielectric pattern GI, the gate electrode GE, and the gate cap pattern GP can be formed in each of the blank spaces. The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be formed of a work function metal capable of adjusting the threshold voltage of the transistor, and the second metal pattern can be formed of a metal material with low resistance.

[0117] During the replacement of the sacrificial pattern SAP with the gate electrode GE, a gate cleaving pattern CT can be formed on the gate electrode GE. The gate cleaving pattern CT can be formed to divide each gate electrode GE into multiple gate electrodes GE.

[0118] The second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may be formed of silicon oxide or include silicon oxide. A pair of discrete structures DB may be formed on both sides of the first single-height cell SHC1, respectively. The discrete structures DB may overlap with the gate electrode GE, which is formed on both sides of the first single-height cell SHC1. For example, the formation of the discrete structures DB may include: forming a hole that extends through the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and the gate electrode GE into the first active pattern AP1 and the second active pattern AP2; and then filling the hole with an insulating layer.

[0119] Reference Figure 11 and Figures 12A to 12C The hard mask pattern HMP and the mask layer ML can be formed on the second interlayer insulating layer 120. Specifically, the hard mask layer and the mask layer ML can be formed sequentially on the second interlayer insulating layer 120. Multiple openings (OPs) can be formed in the mask layer ML by a photolithography process. The hard mask pattern HMP with multiple openings (OPs) can be formed by patterning the hard mask layer using the mask layer ML. The hard mask pattern HMP may include a metal nitride layer (e.g., a titanium nitride layer), and the mask layer ML may include a silicon oxide layer.

[0120] The apertures (OPs) of a hard mask pattern (HMP) may include: a first aperture (OP1), a second aperture (OP2), and a third aperture (OP3). The first to third apertures (OP1, OP2, and OP3) can each define a previously referenced area. Figure 4 The first active contact portion to the third active contact portion AC1, AC2 and AC3 are described.

[0121] A first molding layer MLD1 can be formed on the mask layer ML. The first molding layer MLD1 can have a flat top surface. A second molding layer MLD2 can be formed on the first molding layer MLD1. The second molding layer MLD2 can be patterned by photolithography to remain only on the device isolation layer ST that fills the second trench TR2. In other words, when viewed in a planar view, the second molding layer MLD2 can extend on the device isolation layer ST that fills the second trench TR2 in the second direction D2.

[0122] The first molding layer MLD1 can be patterned using the second molding layer MLD2 as a mask. (See again...) Figure 12C In the first opening OP1, the first molding layer MLD1 can be in direct contact with the top surface of the second interlayer insulating layer 120. The first molding layer MLD1 may include a carbon-containing layer (e.g., SOH). The second molding layer MLD2 may be formed of or include silicon nitride or silicon oxynitride.

[0123] Reference Figure 13 and Figures 14A to 14C A first etching process can be performed on substrate 100. The first etching process can be an anisotropic etching process. The second interlayer insulating layer 120 exposed through opening OP can be etched by the first etching process. The first etching process can be performed until the top surface of the first interlayer insulating layer 110 is exposed through opening OP. However, the first etching process is not limited to this example and can be performed such that a portion of the second interlayer insulating layer 120 is retained or the upper portion of the first interlayer insulating layer 110 is etched.

[0124] The mask layer ML can be removed during the first etching process, thus exposing the hard mask pattern HMP (see [link]). Figure 14A The second molding layer MLD2 can be removed during the first etching process, thus exposing the first molding layer MLD1.

[0125] Refer again Figure 14CDue to the first etching process, the height of the top surface of the interlayer insulating layer exposed through the first opening OP1 can vary depending on its position. For example, the top surface of the interlayer insulating layer on the first PMOSFET region PR1 and the first NMOSFET region NR1 (i.e., the top surface of the first interlayer insulating layer 110) can be located at a first height LV1. In contrast, the top surface of the interlayer insulating layer on the device isolation layer ST that fills the second trench TR2 (i.e., the top surface of the second interlayer insulating layer 120) can be located at a second height LV2. The second height LV2 can be higher than the first height LV1.

[0126] Reference Figure 15 and Figures 16A to 16C The exposed first molding layer MLD1 can be selectively removed. Removing the first molding layer MLD1 may include performing an ashing process.

[0127] Subsequently, a second etching process can be performed using a hard mask pattern (HMP) as an etching mask. The second etching process can be an anisotropic etching process. The first interlayer insulating layer 110 exposed through the opening (OP) can be etched using the second etching process. The second etching process can be performed until the first source / drain pattern SD1 and the second source / drain pattern SD2 are exposed through the opening (OP). The upper portion of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be removed during the second etching process.

[0128] Refer again Figure 16C As a result of the second etching process, a first opening OP1 can be formed to expose a first source / drain pattern SD1 and a second source / drain pattern SD2. The first opening OP1 can expose a first interlayer insulating layer 110 between the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0129] In an embodiment, the second etching process can be performed in an over-etch manner to remove the upper portion of each of the first source / drain pattern SD1 and the second source / drain pattern SD2, and in this case, the first interlayer insulating layer 110 between the first source / drain pattern SD1 and the second source / drain pattern SD2 can be recessed to a deeper height compared to the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the lowest height of the first opening OP1 can be a third height LV3, which is lower than the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0130] Meanwhile, the highest height of the first interlayer insulating layer 110 on the device isolation layer ST that fills the second trench TR2 can be a fourth height LV4. The fourth height LV4 can be higher than the third height LV3.

[0131] That is, in this embodiment, the top surface of the first interlayer insulating layer 110 between the first source / drain pattern SD1 and the second source / drain pattern SD2 can be formed at a fourth height LV4, which is higher than the third height LV3. This may be because the top surface of the interlayer insulating layer of the device isolation layer ST that fills the second trench TR2 is formed at a relatively high height, as previously referred to. Figure 14C As stated above. In other words, due to... Figure 14C The structure shown, in which a portion of the top surface of the second interlayer insulating layer 120 at the second height LV2 is located above the second trench TR2, can prevent the top surface of the first interlayer insulating layer 110 between the first source / drain pattern SD1 and the second source / drain pattern SD2 from being excessively recessed during the second etching process. Therefore, it is possible to prevent the first active contact AC1 from having the previously referenced... Figure 6 The structure that causes the parasitic capacitance problem.

[0132] Refer again Figure 4 and Figures 5A to 5E The active contact AC can be formed by filling the opening OP with conductive material. The upper insulating pattern UIP can be formed by replacing the upper part of each of the active contacts AC with insulating material. The gate contact GC can be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and is respectively connected to the gate electrode GE.

[0133] The third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. The first metal layer M1 may be formed in the third interlayer insulating layer 130. Forming the first metal layer M1 may include forming a first power line M1_R1, a second power line M1_R2, a third power line M1_R3, and a first interconnect line M1_I.

[0134] A fourth interlayer insulating layer 140 may be formed on the first metal layer M1. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140. The formation of the second metal layer M2 may include forming a second interconnect M2_I. In an embodiment, the second interconnect M2_I may be formed using a dual damascene process.

[0135] Figure 17 , Figure 18 , Figure 19 and Figure 20 A cross-sectional view illustrating a method for forming an opening according to an embodiment of the concept of the present invention is shown. In the following description, reference will be made to the preceding text. Figures 7 to 16C The components described can be identified by the same reference numerals, and will not be repeated hereafter.

[0136] Reference Figure 17 , can Figure 10CA hard mask pattern HMP and a mask layer ML are formed on the final structure. Subsequently, a first molding layer MLD1 can be formed. The first molding layer MLD1 can be selectively formed only on the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2.

[0137] Reference Figure 18 A second molding layer MLD2 can be formed on the first molding layer MLD1. The second molding layer MLD2 can be formed to cover the entire top surface of the substrate 100. The second molding layer MLD2 can be formed of silicon oxide or include silicon oxide.

[0138] Reference Figure 19 The second molding layer MLD2 can be selectively etched back to expose the upper part of the first molding layer MLD1. Because the second molding layer MLD2 is recessed, the first molding layer MLD1 can be exposed.

[0139] Reference Figure 20 The exposed first molding layer MLD1 can be selectively removed. Removing the first molding layer MLD1 may include an ashing process.

[0140] Since the first molding layer MLD1 is removed, the height of the top surface of the oxide layer exposed through the first opening OP1 can vary depending on the location. For example, the top surface of the oxide layer on the first PMOSFET region PR1 and the first NMOSFET region NR1 (i.e., the top surface of the second interlayer insulating layer 120) can be located at a first height LV1. In contrast, the top surface of the oxide on the device isolation layer ST that fills the second trench TR2 (i.e., the top surface of the second molding layer MLD2) can be located at a second height LV2. In an embodiment, the second height LV2 can be higher than the first height LV1.

[0141] Subsequently, an anisotropic etching process using a hard mask pattern (HMP) as the etching mask can be performed to form an anisotropic etching process with... Figure 16C The same structure.

[0142] Figure 21 The edge of the semiconductor device shown is an embodiment of the concept of the present invention. Figure 4 The cross-sectional view taken by line CC′. In the following description, refer to the previous... Figure 4 and Figures 5A to 5E The components described can be identified by the same reference numerals, and will not be repeated hereafter.

[0143] Reference Figure 4 and Figure 21The bottom surface BS1 of the first main body portion BP1 of the first active contact AC1 can be located at the fifth height LV5. The bottom surface BS2 of the second main body portion BP2 of the first active contact AC1 can be located at the sixth height LV6. The fifth height LV5 can be lower than the sixth height LV6. In other words, as previously referred to... Figure 15 and Figures 16A to 16C During the described etching process, the first source / drain pattern SD1 can be etched more than the second source / drain pattern SD2. Therefore, the bottom surface BS1 of the first body portion BP1 can be lower than the bottom surface BS2 of the second body portion BP2.

[0144] The maximum width of the first protruding portion PP1 of the first active contact AC1 in the first direction D1 can be the second width W2. The maximum width of the second protruding portion PP2 of the first active contact AC1 in the first direction D1 can be the third width W3. The third width W3 can be greater than the second width W2. The bottom surface BS3 of the first protruding portion PP1 can be located at the seventh height LV7. The bottom surface BS4 of the second protruding portion PP2 can be located at the eighth height LV8. The eighth height LV8 can be lower than the seventh height LV7.

[0145] Figures 22A to 22D The semiconductor device shown in the embodiment of the present invention has separate edges Figure 4 The cross-sectional views are taken from lines AA′, BB′, CC′, and EE′. In the following description, refer to the previous... Figure 4 and Figures 5A to 5E The components described can be identified by the same reference numerals, and will not be repeated hereafter.

[0146] Reference Figure 4 and Figures 22A to 22D A substrate 100 may be provided, comprising a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 in the upper portion of the substrate 100. The first active pattern AP1 may be defined on each of the first PMOSFET region PR1 and the second PMOSFET region PR2, and the second active pattern AP2 may be defined on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0147] The first active pattern AP1 may include vertically stacked first channel patterns CH1. The stacked first channel patterns CH1 may be spaced apart from each other in a third direction D3. When viewed in a plan view, the stacked first channel patterns CH1 may overlap each other. The second active pattern AP2 may include vertically stacked second channel patterns CH2. The stacked second channel patterns CH2 may be spaced apart from each other in a third direction D3. When viewed in a plan view, the stacked second channel patterns CH2 may overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may be formed or include at least one of silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In an embodiment, the third direction D3 may be characterized as extending orthogonally to the upper surface of the substrate 100, and the first direction D1 and the second direction D2 may be characterized as extending parallel to the upper surface of the substrate 100.

[0148] The first active pattern AP1 may further include a first source / drain pattern SD1. A stacked first channel pattern CH1 may be located between each pair of adjacent first source / drain patterns SD1. The stacked first channel pattern CH1 may connect each pair of adjacent first source / drain patterns SD1 to each other.

[0149] The second active pattern AP2 may also include a second source / drain pattern SD2. A stacked second channel pattern CH2 may be positioned between each pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2 may connect each pair of adjacent second source / drain patterns SD2 to each other.

[0150] A gate electrode GE can be configured to span the first channel pattern CH1 and the second channel pattern CH2 and extend in the first direction D1. When viewed in a plan view, the gate electrode GE can overlap with the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS can be provided on opposite side surfaces of the gate electrode GE. A gate capping pattern GP can be provided on the gate electrode GE.

[0151] The gate electrode GE can be configured to surround each of the first channel pattern CH1 and the second channel pattern CH2 (see, for example, see...). Figure 22D The gate electrode GE can be disposed on the top surface TS, at least one side surface SW, and bottom surface BS of each of the first channel pattern CH1 and the second channel pattern CH2. In other words, the gate electrode GE can be configured to face the top surface TS, bottom surface BS, and opposite side surface SW of each of the first channel pattern CH1 and the second channel pattern CH2. The transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., a multi-bridge field-effect transistor (MBCFET)), wherein the gate electrode GE is configured to surround the channel patterns CH1 and CH2 in three dimensions.

[0152] The gate dielectric pattern GI can be disposed between each of the first channel pattern CH1 and the second channel pattern CH2 and the gate electrode GE. The gate dielectric pattern GI can be disposed around each of the first channel pattern CH1 and the second channel pattern CH2.

[0153] On the first NMOSFET region NR1 and the second NMOSFET region NR2, the insulating pattern IP can be positioned between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE can be separated from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. In contrast, the insulating pattern IP can be omitted on the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0154] The first interlayer insulating layer 110 and the second interlayer insulating layer 120 can be disposed on the substrate 100. The active contact AC can be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The gate contact GC can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and be connected to the gate electrode GE, respectively. The active contact AC and the gate contact GC can be compared with a reference... Figure 4 and Figures 5A to 5E The ones described in the previous embodiments are substantially the same.

[0155] The third interlayer insulation layer 130 can be disposed on the second interlayer insulation layer 120. The fourth interlayer insulation layer 140 can be disposed on the third interlayer insulation layer 130. The first metal layer M1 can be disposed in the third interlayer insulation layer 130. The second metal layer M2 can be disposed in the fourth interlayer insulation layer 140. The first metal layer M1 and the second metal layer M2 can be referenced. Figure 4 and Figures 5A to 5E The ones described in the previous embodiments are substantially the same.

[0156] In the semiconductor device according to embodiments of the present invention, both the resistance and parasitic capacitance between the active contact and the source / drain pattern can be reduced, thereby improving the operating speed of the device. In other words, a semiconductor device with improved electrical characteristics can be provided.

[0157] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The substrate has PMOSFET regions and NMOSFET regions spaced apart from each other in a first direction; A device isolation layer is provided on the substrate, the device isolation layer defining a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region; A gate electrode extends in the first direction and spans the first active pattern and the second active pattern; A first source / drain pattern and a second source / drain pattern are respectively located on the first active pattern and the second active pattern, and each of the first source / drain pattern and the second source / drain pattern is adjacent to the side of the gate electrode. as well as A first active contact extends in the first direction and is coupled to the first source / drain pattern and the second source / drain pattern. The first active contact portion includes: The first main body portion on the first source / drain pattern, The second main body portion on the second source / drain pattern, and The first protruding portion and the recessed portion between the first main body portion and the second main body portion, The first protruding portion and the recessed portion are above the device isolation layer between the PMOSFET region and the NMOSFET region, and The recessed portion of the first active contact has a bottom surface that is recessed in a second direction away from the device isolation layer.

2. The semiconductor device according to claim 1, wherein, The bottom surface of the recessed portion is higher than the bottom surface of the first protruding portion and lower than the bottom surface of the first main body portion.

3. The semiconductor device according to claim 1, wherein, The first protruding portion is located between the first main body portion and the recessed portion, and The first active contact portion further includes a second protruding portion between the recessed portion and the second main body portion.

4. The semiconductor device according to claim 3, wherein, The height of the bottom surface of the first protruding portion is different from the height of the bottom surface of the second protruding portion, and The maximum width of the first protrusion in the first direction is different from the maximum width of the second protrusion in the first direction.

5. The semiconductor device according to claim 1, wherein, The height of the bottom surface of the first main body part is lower than the height of the bottom surface of the second main body part.

6. The semiconductor device according to claim 1, wherein, The first protruding portion extends from the first body portion toward the device isolation layer along the inclined side surface of the first source / drain pattern.

7. The semiconductor device according to claim 6, wherein, The first main body portion is electrically connected to the top surface of the first source / drain pattern, and The first protruding portion is electrically connected to the inclined side surface of the first source / drain pattern.

8. The semiconductor device according to claim 1, further comprising: A gate contact is located on the PMOSFET region and coupled to the gate electrode. The first active contact portion further includes an upper insulating pattern in the upper part of the first main body portion, and The upper insulating pattern is adjacent to the gate contact portion.

9. The semiconductor device according to claim 1, further comprising: An interlayer insulating layer is present on the gate electrode; A first metal layer is disposed on the interlayer insulating layer; as well as A second metal layer is placed above the first metal layer. The first active contact penetrates the interlayer insulation layer and is coupled to the first source / drain pattern and the second source / drain pattern. The first metal layer includes at least one first interconnect line electrically connected to the first active contact, and The second metal layer includes at least one second interconnect that is electrically connected to the at least one first interconnect.

10. The semiconductor device according to claim 1, further comprising: The third source / drain pattern is set on the first active pattern; as well as The second active contact is coupled to the third source / drain pattern. Wherein, the length of the second active contact portion in the first direction is less than half the length of the first active contact portion in the first direction.

11. A semiconductor device, comprising: A first logic unit and a second logic unit are on a substrate and are adjacent to each other in a first direction. Each of the first logic unit and the second logic unit has a first active region and a second active region. The first active region is one of a PMOSFET region and an NMOSFET region, and the second active region is the other of the PMOSFET region and the NMOSFET region. as well as An active contact portion extends from the first active region of the first logic unit to the first active region of the second logic unit. The active contact portion includes: The first main body portion on the first active region of the first logic unit, The second main body portion on the first active region of the second logic unit, and The first protruding portion and the recessed portion between the first main body portion and the second main body portion, The first protruding portion and the recessed portion are located above the device isolation layer between the first active region of the first logic unit and the first active region of the second logic unit, and The bottom surface of the recessed portion is higher than the bottom surface of the first protruding portion and lower than the bottom surface of the first main body portion.

12. The semiconductor device according to claim 11, further comprising: The first metal layer above the active contact portion. The first metal layer includes a first power line electrically connected to the active contact portion, and The first power line extends along the boundary between the first logic unit and the second logic unit and in a second direction that intersects the first direction.

13. The semiconductor device according to claim 11, wherein, The first protruding portion is located between the first main body portion and the recessed portion, and The active contact portion further includes a second protruding portion between the recessed portion and the second main body portion.

14. The semiconductor device according to claim 13, wherein, The height of the bottom surface of the first protruding portion is different from the height of the bottom surface of the second protruding portion, and The maximum width of the first protrusion in the first direction is different from the maximum width of the second protrusion in the first direction.

15. The semiconductor device according to claim 13, wherein, The first logic unit includes: a source / drain pattern on the first active region. The first main body portion is electrically connected to the top surface of the source / drain pattern. The first protruding portion extends from the first body portion toward the device isolation layer along the inclined side surface of the source / drain pattern, and The first protruding portion is electrically connected to the inclined side surface of the source / drain pattern.

16. A semiconductor device, comprising: A logic cell on a substrate has a PMOSFET region and an NMOSFET region spaced apart from each other in a first direction. The logic cell has a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary are opposite to each other in a second direction intersecting the first direction, and the third boundary and the fourth boundary are opposite to each other in the first direction. A device isolation layer is provided on the substrate, the device isolation layer defining a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region, the first active pattern and the second active pattern extending in the second direction, the upper portions of the first active pattern and the second active pattern protruding above the device isolation layer; A gate electrode extends in the first direction and spans the first active pattern and the second active pattern; The first source / drain pattern and the second source / drain pattern are respectively located in the upper part of the first active pattern and the second active pattern, and each of the first source / drain pattern and the second source / drain pattern is adjacent to the side of the gate electrode. A separation structure is provided on at least one of the first boundary and the second boundary; A gate spacer portion is located on at least one side surface of the gate electrode; A gate capping pattern is formed on the top surface of the gate electrode; An interlayer insulating layer is present on the gate cap pattern; An active contact portion penetrates the interlayer insulating layer and is coupled to the first source / drain pattern and the second source / drain pattern; A silicide pattern is located between the active contact portion and each of the first source / drain pattern and the second source / drain pattern; The gate contact penetrates the interlayer insulating layer and the gate capping pattern, and is coupled to the gate electrode; A first metal layer, on the interlayer insulating layer, includes: a first power line and a second power line extending respectively on the third boundary and the fourth boundary and in the second direction; and a first interconnection line between the first power line and the second power line, the first interconnection line being electrically connected to the active contact and the gate contact, respectively. A second metal layer is placed above the first metal layer. The second metal layer includes a second interconnect line extending in the first direction and electrically connected to the first metal layer. The active contact portion includes: The first main body portion on the first source / drain pattern, The second main body portion on the second source / drain pattern, and The first protruding portion and the recessed portion between the first main body portion and the second main body portion, The first protruding portion and the recessed portion are above the device isolation layer between the PMOSFET region and the NMOSFET region, and The recessed portion of the active contact has a bottom surface that is recessed upwards on a third side away from the device isolation layer.

17. The semiconductor device according to claim 16, wherein, The bottom surface of the recessed portion is higher than the bottom surface of the first protruding portion and lower than the bottom surface of the first main body portion.

18. The semiconductor device according to claim 16, wherein, The first protruding portion is located between the first main body portion and the recessed portion, and The active contact portion further includes a second protruding portion between the recessed portion and the second main body portion.

19. The semiconductor device according to claim 18, wherein, The height of the bottom surface of the first protruding portion is different from the height of the bottom surface of the second protruding portion, and The maximum width of the first protrusion in the first direction is different from the maximum width of the second protrusion in the first direction.

20. The semiconductor device according to claim 16, wherein, The height of the bottom surface of the first main body part is lower than the height of the bottom surface of the second main body part.

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