Heterojunction Bipolar Transistor

Abstract

The present disclosure relates to a semiconductor structure, and more particularly to a heterojunction bipolar transistor and a manufacturing method thereof. The structure comprises: a first semiconductor layer, which comprises a device region; a second semiconductor layer, which is located below the first semiconductor layer; a conductive material layer, which is located between the first semiconductor layer and the second semiconductor layer; at least one contact, which extends to and contacts the conductive material layer; and a device, which is located in the device region above the conductive material layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to heterojunction bipolar transistors and methods of manufacturing the same. Background Art

[0002] A heterojunction bipolar transistor (HBT) is a bipolar junction transistor (BJT) that uses different semiconductor materials for the emitter and base regions or the collector and base regions to form a heterojunction. Si / SiGe HBTs are used in power amplifier applications that require low collector-base capacitance (Ccb), low base resistance (Rb), high cutoff frequency fT / fMAX, and high breakdown voltage (BVceo, BVcbo, BVebo).

[0003] In high performance Si / SiGe HBT technology, some integration schemes result in high Rc (collector resistance), which is a major component of HBT performance. For example, high Rc is a concern in bipolar technology because it limits device scaling for improved fT / fMAX. To address such issues, integration schemes rely on heavy doping, for example, doping to its solubility limit, but this results in higher Ccb (collector-base capacitance). Summary of the invention

[0004] In one aspect of the present disclosure, a structure includes: a first semiconductor layer, which includes a device region; a second semiconductor layer, which is located below the first semiconductor layer; a conductive material layer, which is located between the first semiconductor layer and the second semiconductor layer; at least one contact, which extends to and contacts the conductive material layer; and a device, which is located in the device region above the conductive material layer.

[0005] In one aspect of the present disclosure, a structure includes: a first semiconductor layer; a second semiconductor layer located below the first semiconductor layer; a deep trench isolation structure extending through the first semiconductor layer and the second semiconductor layer and defining a device region; a transistor located within the device region; a conductive material layer located between the first semiconductor layer and the second semiconductor layer and extending below the transistor; and at least one contact extending through the first semiconductor layer and contacting the conductive material layer.

[0006] In one aspect of the present disclosure, a method includes: forming a first semiconductor layer; forming a conductive material layer on the first semiconductor layer; forming a second semiconductor layer on the conductive material layer; forming an opening in the second semiconductor layer, the opening extending to the conductive material layer; filling the opening with a conductive material; and forming a device on the second semiconductor layer above the conductive material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 A top view of a substrate having an opening and a corresponding manufacturing process is shown, among other features, according to aspects of the present disclosure.

[0009] Figure 2 Shown is a view taken along line 2-2. Figure 1 A cross-sectional view of the structure.

[0010] Figure 3 An air gap disposed between semiconductor layers and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0011] Figure 4 Conductive materials within air gaps and openings and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0012] Figure 5 A heterojunction bipolar transistor having contacts to an emitter, an extrinsic base, and a sub-collector region and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0013] The present disclosure relates to semiconductor structures, and more particularly to heterojunction bipolar transistors and methods of manufacturing. More particularly, the present disclosure relates to heterojunction bipolar transistors having buried conductive (e.g., metal) features in sub-collector and collector regions of a substrate. Advantageously, the buried conductive (e.g., metal) features of the heterojunction bipolar transistor result in reduced collector resistance and increased fT / fMAX in the sub-collector region.

[0014] The heterojunction bipolar transistors disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing heterojunction bipolar transistors disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned by a photolithography process on top of the wafer. Specifically, the manufacture of heterojunction bipolar transistors uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film to the mask.

[0015] Figure 1A top view of a substrate having an opening and a corresponding manufacturing process is shown, among other features, according to aspects of the present disclosure. Figure 2 Shown is a view taken along line 2-2. Figure 1 More specifically and with reference to Figure 1 and Figure 2 , structure 10 includes semiconductor layers 12, 14. In an embodiment, semiconductor layers 12, 14 may be composed of single crystal silicon; however, other materials are also contemplated herein. For example, semiconductor layer 14 may be a high resistivity bulk silicon wafer with a resistivity greater than or equal to 1 kOhm-cm. Other materials may include, but are not limited to, SiC, GaAs, InAs, InP, and other III / V or II / VI group compound semiconductors.

[0016] A semiconductor layer 16 is disposed between the semiconductor layers 12 and 14. In an embodiment, the semiconductor layer 16 is epitaxially grown over the semiconductor layer 14 using the semiconductor layer 14 as a growth seed, and the semiconductor layer 12 is epitaxially grown over the semiconductor layer 16 using the semiconductor layer 16 as a growth seed. The semiconductor layer 16 may be composed of SiGe or other materials having etching selectivity to the semiconductor layers 12 and 14 (e.g., silicon). As used herein, the term "selective" is used for a material removal process (e.g., etching), and by appropriate etchant selection, the material removal rate (i.e., etching rate) of the target material is greater than the removal rate of at least another material on which the material removal process is performed.

[0017] In an embodiment, semiconductor layer 16 may be composed of SiGe, which includes a percentage of Ge that enables an etch rate higher than silicon. In other embodiments, semiconductor layer 16 may have a thickness t1 less than or equal to 50 nanometers; and semiconductor layer 12 may have a thickness less than or equal to 500 nanometers, such that the top surface of semiconductor layer 16 is spaced apart from the top surface 11 of semiconductor layer 16 by a distance less than or equal to 500 nanometers; however, other dimensions are also contemplated herein.

[0018] Still refer to Figure 1 and Figure 2 A deep trench isolation structure 18 is provided in the substrate, and the deep trench isolation structure 18 extends in the semiconductor layers 12, 14, and 16. More specifically, the deep trench isolation structure 18 extends from the top surface 11 of the semiconductor layer 12 through the semiconductor layers 12, the semiconductor layers 16, and to a shallow depth in the semiconductor layer 14. The deep trench isolation structure 18 surrounds a portion of the semiconductor layer 12 to define a device region 19 that can be used in a front-end-of-line (FEOL) device (e.g., a heterojunction bipolar transistor (HBT)).

[0019] The deep trench isolation structure 18 can be formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, a resist formed above the semiconductor layer 12 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) is used to form one or more trenches in the semiconductor layers 12, 14, 16 through the openings in the resist. After the resist is removed by an oxygen ashing process or other known stripping agent, the insulator material (e.g., SiO 2 ) can be deposited in the trenches by any conventional deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation, etc.). Any residual material on the surface of the semiconductor layer 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0020] Figure 1 and Figure 2 Also shown is an opening 22 formed in device region 19. Opening 22 extends to semiconductor layer 16. In alternative embodiments, opening 22 may partially penetrate semiconductor layer 16. In further alternative embodiments, opening 22 may completely penetrate semiconductor layer 16 and into underlying semiconductor layer 14. In either of these cases, semiconductor layer 16 will be exposed for later removal.

[0021] In an embodiment, to form the opening 22, an etching mask 20 shown in dashed lines is formed over the top surface 11 of the semiconductor layer 12 and the deep trench isolation structure 18, and the etching mask 20 is arranged to cover the device region 19. The etching mask 20 may include a photoresist that is applied as a coating by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to form an opening. A directional etching process (e.g., RIE) is used to form the opening 22 at the opening position in the etching mask 20. The opening 22 completely penetrates the semiconductor layer 12, thereby exposing the material of the semiconductor layer 16.

[0022] The openings 22 may be arranged in a regular array or another pattern across the top surface 11 of the device region 19, or the arrangement of the openings 22 may be placed at random locations. The number and size of the openings 22 may also vary depending on design parameters and / or the ability of the etchant chemistry to remove the semiconductor layer 16 in subsequent processing steps. In an embodiment, and as will be appreciated by those skilled in the art, the etching process will selectively remove the material of the semiconductor layer 12 to the material of the semiconductor layer 16, so that the semiconductor layer 16 may serve as an etch stop layer.

[0023] Figure 3An air gap 24 is shown, which is arranged vertically between the device region 19 of the semiconductor layer 12 and the semiconductor layer 14, and extends within the region of the deep trench isolation structure 18 (e.g., which defines the collector region and sub-collector region of the heterojunction bipolar formed in the device region 19). To form the air gap 24, the semiconductor layer 16 is selectively removed from below the device region 19 using an anisotropic etching process through the opening 22 to the material of the semiconductor layers 12, 14 and the deep trench isolation structure 18.

[0024] It will be appreciated by those skilled in the art that the anisotropic etching process includes a lateral etching component that etches the sacrificial layer (e.g., semiconductor layer 16) starting at the location of each opening 22 and expanding outward until the various etched volumes merge together to form air gaps 24. In an embodiment, the height of the air gaps 24 may be equal to the thickness of the semiconductor layer 16. In an embodiment, the etchant may be a material having, for example, hot ammonia (NH 3 ) and / or hydrochloric acid (HCl) vapor etchant chemical dry etching.

[0025] In further embodiments, the device region 19 is attached to the deep trench isolation structure 18 around its perimeter (e.g., the entire perimeter). The deep trench isolation structure 18 surrounding the device region 19 may apply an inward compressive stress to the device region 19 at the sidewalls of the device region 19. The inward compressive stress physically and structurally supports the device region 19 and prevents it from collapsing after forming the air gap 24. The semiconductor layer 16 outside the deep trench isolation structure 18 is not removed and also surrounds the air gap 24 on all sides.

[0026] refer to Figure 4 In the embodiment, the mask 20 is removed and the openings 22 and the air gaps 24 are filled with a conductive material 26. The mask 20 may be removed by any conventional etching technique or stripping process known to those skilled in the art, and thus further explanation is not required to fully understand the present disclosure.

[0027] In an embodiment, opening 22 and air gap 24 are filled with a conductive material 26 (e.g., a metal material deposited through opening 22 and formed laterally in air gap 24). Conductive material 26 can be any one of a series of conductors, metals, metal alloys (e.g., Al, Co, Ni, W, TiN, Ta, Pt, etc.). In an embodiment, the conductive material should have a resistivity of about 10 μΩ-cm; however, other resistivities are contemplated herein. Conductive material 26 can be deposited by any conventional deposition method known for deposition purposes, including, for example, CVD or atomic layer deposition (ALD). As Figure 5 As shown, forming the air gap 24 and filling the air gap 24 with the conductive material 26 may be performed before or after forming the heterojunction bipolar transistor 28 .

[0028] Figure 5 A heterojunction bipolar transistor having contacts to an emitter, an extrinsic base, and a sub-collector region and a corresponding manufacturing process are shown, among other features, according to aspects of the present disclosure. More specifically, a heterojunction bipolar transistor 28 is disposed between deep trench isolation structures 18 and within a device region 19. In this non-limiting example, the heterojunction bipolar transistor 28 includes an emitter 30, an extrinsic base 32, and a collector region 34 in a semiconductor layer 12 defined by shallow trench isolation regions 36. The sub-collector region 38 is disposed below the collector region 34 in electrical contact with the conductive material 26.

[0029] As a non-limiting example, and as will be appreciated by one of ordinary skill in the art, the extrinsic base 32 may be a raised extrinsic base 32 comprising, for example, Si or SiGe. Also, as will be appreciated by one of ordinary skill in the art, in one exemplary embodiment, the raised extrinsic base 32 may be grown as a single crystalline semiconductor material above the single crystalline material of the semiconductor layer 12 (wherein a polycrystalline material is grown above the shallow trench isolation region 36). The emitter 30 may also be a single crystalline epitaxial material having a sidewall structure (e.g., a nitride-based sidewall). The collector region 34 may include a semiconductor material, such as an undoped Si material, that is in electrical contact with the sub-collector region 38. It will be appreciated that providing Figure 5 The heterojunction bipolar transistor 28 in FIG. 1 is provided as an illustrative, non-limiting example of such a device, and other configurations of the heterojunction bipolar transistor 28 are also contemplated herein.

[0030] Figure 5 Also shown are contacts 40 to the emitter 30 and the raised extrinsic base 32, and a collector contact 40a to the sub-collector region 38. In an embodiment, the collector contact 40a is in electrical contact with the collector region 34 by means of the conductive material 26 within the sub-collector region 38. The collector contact 40a is located between the heterojunction bipolar transistor 28 and the deep trench isolation structure 18, and more specifically, between the shallow trench isolation structure 36 and the deep trench isolation structure 18. In addition, the electrical connection using the conductive material within the sub-collector region 38 will effectively reduce the resistance to the collector region 34 and improve fT / fMAX.

[0031] Prior to forming the contacts, silicide contacts are formed that contact the emitter 30 and the extrinsic base 32. As will be appreciated by those skilled in the art, the silicide process begins with the deposition of a thin transition metal layer, such as nickel, cobalt, or titanium, over a fully formed and patterned semiconductor material. After the material is deposited, the structure is heated to cause the transition metal to react with the exposed silicon (or other semiconductor material described herein) to form a low resistance transition metal silicide contact. After the reaction, any remaining transition metal is removed by chemical etching, leaving behind the silicide contact.

[0032] A dielectric material 42 is deposited over the structure, and then a lithography, etching, and deposition process (e.g., a metallization process) is performed to form the contact 40. For example, the dielectric material 42 is deposited by a CVD process, and then a lithography and etching (e.g., RIE) process is performed to form a trench in the dielectric material 42. A metal material (e.g., aluminum or tungsten) is deposited in the trench to form contacts 40, such as collector contacts, emitter region contacts, and extrinsic base contacts. Any residual metal material can be removed from the surface of the dielectric material 38 by a conventional chemical mechanical planarization process.

[0033] Heterojunction bipolar transistors can be utilized in system-on-chip (SoC) technology. It should be understood by those skilled in the art that an SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0034] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0035] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a first semiconductor layer including a device region; a second semiconductor layer, located below the first semiconductor layer; a conductive material layer located between the first semiconductor layer and the second semiconductor layer; at least one contact extending through the first semiconductor layer and contacting the layer of conductive material; as well as A device is located in the device region above the conductive material layer, the device comprising at least a non-intrinsic base composed of semiconductor material located on the first semiconductor layer and away from the at least one contact. 2 . The semiconductor structure according to claim 1 , further comprising a deep trench isolation structure surrounding the device region.

3. The semiconductor structure according to claim 2, wherein: The conductive material is a metal material extending within the sub-collector region and the collector region of the heterojunction bipolar transistor.

4. The semiconductor structure according to claim 3, wherein: The metal material is one of Al, Co, Ni, Pt, Ta, W and TiN.

5. The semiconductor structure according to claim 3, wherein: The sub-collector region and the collector region are located in the first semiconductor layer.

6. The semiconductor structure according to claim 3, wherein: The at least one contact is a collector contact of the heterojunction bipolar transistor.

7. The semiconductor structure according to claim 6, wherein: The collector contact is located between the heterojunction bipolar transistor and the deep trench isolation structure.

8. The semiconductor structure according to claim 7, wherein: The collector contact is located between the shallow trench isolation structure and the deep trench isolation structure.

9. The semiconductor structure according to claim 1, wherein: The conductive material layer is defined by the first semiconductor layer, the second semiconductor layer, and a deep trench isolation structure.

10. A semiconductor structure comprising: a first semiconductor layer; a second semiconductor layer, located below the first semiconductor layer; a deep trench isolation structure extending through the first semiconductor layer and the second semiconductor layer and defining a device region; a transistor located in the device region, the transistor comprising at least a non-intrinsic base located above the first semiconductor layer; a conductive material layer located between the first semiconductor layer and the second semiconductor layer and extending below the transistor; as well as At least one contact extends through the first semiconductor layer, away from the extrinsic base, and contacts the conductive material layer.

11. The semiconductor structure according to claim 10, wherein: The transistor is a heterojunction bipolar transistor, and the conductive material is a metallic material extending within a sub-collector region and a collector region of the heterojunction bipolar transistor.

12. The semiconductor structure according to claim 11, wherein: The metal material is one of Al, Co, Ni, W and TiN.

13. The semiconductor structure according to claim 11, wherein: The sub-collector region and the collector region are located in the first semiconductor layer.

14. The semiconductor structure according to claim 11, wherein: The at least one contact is a collector contact of the heterojunction bipolar transistor, located between the heterojunction bipolar transistor and the deep trench isolation structure.

15. The semiconductor structure according to claim 14, wherein: The collector contact is located between the shallow trench isolation structure and the deep trench isolation structure.

16. The semiconductor structure according to claim 10, wherein: The conductive material layer is defined by the first semiconductor layer, the second semiconductor layer, and the deep trench isolation structure.

17. The semiconductor structure according to claim 10, wherein: The first semiconductor layer and the second semiconductor layer include Si material.

18. The semiconductor structure according to claim 10, wherein: The at least one contact fills an opening in the first semiconductor layer at a side of the transistor.

19. A method of manufacturing a semiconductor structure, comprising: forming a first semiconductor layer; forming a conductive material layer on the first semiconductor layer; forming a second semiconductor layer on the conductive material layer; forming an opening in the second semiconductor layer, the opening extending to the conductive material layer; filling the opening with a conductive material; as well as A device is formed on the second semiconductor layer above the conductive material layer, wherein the device at least includes an extrinsic base composed of a semiconductor material and located on the second semiconductor layer and away from the conductive material in the opening.

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