Semiconductor device

Abstract

A semiconductor device (1) comprises: a mounting substrate (20); and a semiconductor element (10) which is arranged on the mounting substrate (20) via a metal bump (30), wherein the semiconductor element (10) has a semiconductor stacked structure (11) and a first electrode, and the mounting substrate (20) has a second electrode, and the metal bump (30) has a first layer (31) in contact with the first electrode of the semiconductor element (10), and a second layer (32) located on the opposite side of the first electrode, wherein the average grain size of the crystals constituting the first layer (31) is larger than the average grain size of the crystals constituting the second layer (32), and the second layer (32) is located at a position separated from the first electrode of the semiconductor element (10).

Description

[0001] This application is a divisional application of Chinese patent application No. 201880088260.5, which entered the Chinese national phase with PCT / JP2018 / 047041 filed on December 20, 2018. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element and a mounting substrate are bonded together via metal bumps. Background Art

[0003] Semiconductor light-emitting diodes (LEDs), such as light-emitting diodes (LEDs), are used as light sources in various devices. For example, LEDs are used as in-vehicle light sources in vehicle-mounted lighting devices such as DRLs (Daytime Running Lights) and HLs (Head Lamps). In particular, the market for in-vehicle light sources using high-power LEDs with a light output of 1W or more is booming, and the use of LEDs in halogen lamps and HID (High-Intensity Discharge) lamps is rapidly expanding.

[0004] With increasing demands for space savings and improved design in automotive lighting, LEDs are trending towards miniaturization, higher current, and greater integration. Therefore, dissipating the heat generated by LEDs is crucial to ensuring LED reliability.

[0005] To achieve miniaturization, high current, and integration of semiconductor chips such as LED chips, flip-chip bonding (flip-chip bonding) is a technology for bonding semiconductor chips to mounting substrates. This involves bonding the semiconductor chip to the mounting substrate face-down. This method flips the semiconductor chip over and uses metal bumps to directly bond the wiring on the mounting substrate to the electrodes or wiring on the semiconductor chip. Compared to face-up bonding, where the semiconductor wiring of the semiconductor chip faces upward and is connected by wires, this method is more flexible in terms of wire diameter and routing, making it suitable for high current, high integration, and high-output applications. It is used in automotive light sources as a mounting method.

[0006] Patent Document 1 discloses a semiconductor device in which a semiconductor element and a mounting substrate are bonded by metal bumps by flip-chip bonding, wherein a semiconductor layer of a semiconductor element is connected to an electrode post, and the tip of the electrode post is bonded to wiring on a mounting substrate via solder.

[0007] Figure 28 This is a cross-sectional view of a semiconductor device 200 disclosed in Patent Document 1.

[0008] Figure 28 As shown, semiconductor device 200 includes a semiconductor layer 210 composed of a p-type layer 211, an active layer 212, and an n-type layer 213; a p-side electrode 220 connected to p-type layer 211; an n-side electrode 230 connected to n-type layer 213; a p-side seed layer 241 and a p-side electrode column 242 stacked on p-side electrode 220; an n-side seed layer 251 and an n-side electrode column 252 stacked on n-side electrode 230; and a sealing resin body 260 covering these components. In the p-side electrode column 242 and the n-side electrode column 252, the crystal grain size at the first end portion on the semiconductor layer 210 side is smaller than the crystal grain size at the second end portion on the opposite side of the semiconductor layer 210. This allows thermal stress to be absorbed compared to a case where the crystal grain size of the p-side electrode column 242 and the n-side electrode column 252 is larger overall, resulting in a semiconductor device 200 with high thermal stress tolerance.

[0009] (Prior art literature)

[0010] (Patent Document)

[0011] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-38886

[0012] However, the semiconductor device disclosed in Patent Document 1 suffers from damage such as electrode failure during long-term reliability testing, resulting in a problem of poor long-term reliability. Summary of the Invention

[0013] An object of the present disclosure is to provide a semiconductor device having excellent long-term reliability.

[0014] One embodiment of the first semiconductor device disclosed herein comprises: a mounting substrate; and a semiconductor element arranged on the mounting substrate via a metal bump, the semiconductor element having a semiconductor stacked structure and a first electrode, the mounting substrate having a second electrode, the metal bump having a first layer in contact with the first electrode, and a second layer located on the opposite side of the first electrode, the average grain size of the crystals constituting the first layer being larger than the average grain size of the crystals constituting the second layer, and the second layer being located at a position separated from the first electrode.

[0015] One embodiment of the second semiconductor device disclosed herein comprises: a mounting substrate; and a semiconductor element arranged on the mounting substrate via a metal bump, the semiconductor element having a semiconductor stacked structure and a first electrode, the mounting substrate having a second electrode, the metal bump having a first layer connected to the first electrode, and a second layer located on the opposite side of the first electrode, the first layer having an equiaxed grain structure.

[0016] One scheme of the third semiconductor device involved in the present disclosure comprises: a mounting substrate; and a semiconductor element, which is arranged on the mounting substrate via a metal bump, the semiconductor element having a semiconductor stacked structure and a first electrode, the mounting substrate having a second electrode, the metal bump having a first layer made of gold in contact with the first electrode, and a second layer located on the opposite side of the first electrode, the average grain size of the crystals constituting the first layer is larger than the average grain size of the crystals constituting the second layer, the first electrode is composed of at least two layers including a surface layer, the surface layer is in contact with the metal bump and is made of gold, the thickness of the surface layer is set to A, the average grain size of the surface layer is set to B, the thickness of the first layer is set to C, and when the maximum height roughness of the interface between the first layer and the second layer is set to Rz, the following relationship is satisfied: C>Rz / 2+1-A×B / 8.

[0017] A scheme of the fourth semiconductor device involved in the present disclosure comprises: a mounting substrate; and a semiconductor element, which is arranged on the mounting substrate via a metal bump formed by multiple metal layers, the semiconductor element having a semiconductor stacked structure and a first electrode, and the mounting substrate having a second electrode. In a cross-section of the semiconductor element, the mounting substrate, and the metal bump in a direction perpendicular to the mounting substrate, when a virtual rectangle having the same area and the same height as the cross-sectional shape of the metal bump is defined, at least either the width of the junction between the first layer connected to the first electrode and the first electrode, i.e., the first junction, and the width of the junction between the third layer connected to the second electrode and the second electrode, i.e., the second junction, is longer than the length of the base of the rectangle.

[0018] According to the present disclosure, when bonding a semiconductor element and a mounting substrate via metal bumps, it is possible to suppress the occurrence of defects caused by bonding of the metal bumps, such as electrode damage and peeling, thereby achieving a semiconductor device with excellent long-term reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0020] Figure 2 This is a diagram showing an enlarged cross-sectional view of a metal bump of the semiconductor device according to the first embodiment and the height position dependency of the crystal grain size in the metal bump.

[0021] Figure 3A This is a diagram showing a step of preparing a substrate in the first step of the method for manufacturing a semiconductor device according to the first embodiment.

[0022] Figure 3BThis is a diagram showing a step of forming a semiconductor stacked structure in the first step of the method for manufacturing a semiconductor device according to the first embodiment.

[0023] Figure 4A This is a diagram showing a step of etching the semiconductor stacked structure in the second step of the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Figure 4B This is a diagram showing a step of forming an insulating film in the second step of the method for manufacturing the semiconductor device according to the first embodiment.

[0025] Figure 4C This is a diagram showing a step of forming an ohmic contact layer and a barrier electrode of a first n-side electrode in the second step of the method for manufacturing a semiconductor device according to the first embodiment.

[0026] Figure 4D This is a diagram showing a step of forming a reflective electrode as the first p-side electrode in the second step of the method for manufacturing the semiconductor device according to the first embodiment.

[0027] Figure 4E This is a diagram showing a step of forming a barrier electrode for the first p-side electrode in the second step of the method for manufacturing the semiconductor device according to the first embodiment.

[0028] Figure 4F This is a diagram showing a step of forming a seed crystal film in the second step of the method for manufacturing a semiconductor device according to the first embodiment.

[0029] Figure 4G This is a diagram showing a step of forming a protective material in the second step of the method for manufacturing a semiconductor device according to the first embodiment.

[0030] Figure 4H This is a diagram showing a step of forming a covering electrode for the first p-side electrode and the first n-side electrode in the second step of the method for manufacturing the semiconductor device according to the first embodiment.

[0031] Figure 4I This is a diagram showing a step of removing the protective material in the second step of the method for manufacturing the semiconductor device according to the first embodiment.

[0032] Figure 5A This is a diagram showing a step of forming a protective material having an opening in the third step of the method for manufacturing the semiconductor device according to the first embodiment.

[0033] Figure 5B This is a diagram showing a step of forming a gold plating film in the third step of the method for manufacturing the semiconductor device according to the first embodiment.

[0034] Figure 5C This is a diagram showing a step of removing the protective material in the third step of the method for manufacturing the semiconductor device according to the first embodiment.

[0035] Figure 5D This is a diagram showing a step of removing a portion of the seed crystal film to divide the electrode into pn electrodes in the third step of the method for manufacturing the semiconductor device according to the first embodiment.

[0036] Figure 5E This is a diagram showing a step of performing heat treatment in the third step of the method for manufacturing the semiconductor device according to the first embodiment.

[0037] Figure 6A This is a diagram showing a step of arranging a semiconductor element on a mounting substrate in the fourth step of the method for manufacturing a semiconductor device according to the first embodiment.

[0038] Figure 6B This is a diagram showing a step of mounting a semiconductor element on a mounting substrate and performing ultrasonic bonding in the fourth step of the method for manufacturing a semiconductor device according to the first embodiment.

[0039] Figure 7A yes Figure 5D Magnified view of region VIIA.

[0040] Figure 7B yes Figure 5E Magnified view of region VIIB.

[0041] Figure 7C It is shown from Figure 7B state, and a diagram showing a state in which the grains are more coarsened.

[0042] Figure 8 This is a diagram for explaining the method of measuring the crystal grain size.

[0043] Figure 9 This is a graph showing the relationship between the average crystal grain size of the gold plating film and the hardness of the single-layer gold plating film.

[0044] Figure 10 This is a timing chart of ultrasonic bonding when a semiconductor element is mounted on a mounting substrate in the first embodiment.

[0045] Figure 11A This is a diagram showing a cross section around a metal bump before ultrasonic bonding in the first embodiment.

[0046] Figure 11B It shows Figure 10 A diagram showing the bonding state between the metal bump and the second electrode of the mounting substrate immediately after Step 1.

[0047] Figure 11CIt shows Figure 10 A diagram showing the bonding state between the metal bump and the second electrode of the mounting substrate midway through Step 2 (approximately 300 ms after the start of the process).

[0048] Figure 11D It shows Figure 10 A diagram showing the bonding state between the metal bump and the second electrode of the mounting substrate at the end of Step 2.

[0049] Figure 12 This is a diagram showing the distribution of crystal grain sizes of metal bumps in the semiconductor device according to the first embodiment.

[0050] Figure 13 A diagram for explaining a method of observing an electrode surface of a semiconductor device.

[0051] Figure 14A This is a diagram showing a state before a load is applied to a shear sensor in a method of measuring the shear strength of a semiconductor device.

[0052] Figure 14B This is a diagram showing a state after a load is applied to a shear sensor in a method of measuring the shear strength of a semiconductor device.

[0053] Figure 15 is with Figure 12 The region XV surrounded by the dot-dash line corresponds to the SIM image of the portion.

[0054] Figure 16 yes Figure 1 An enlarged cross-sectional view of a region XVI surrounded by a dashed line.

[0055] Figure 17 This figure shows a region where no bump mark occurs on the first electrode when a semiconductor element is mounted on a mounting substrate.

[0056] Figure 18 This is a cross-sectional view of a semiconductor device according to a second embodiment.

[0057] Figure 19 This is a diagram showing an enlarged cross-sectional view of a metal bump of a semiconductor device according to the second embodiment and the height position dependency of the crystal grain size in the metal bump.

[0058] Figure 20A This is a diagram showing a step of forming a protective material having an opening in the third step of the method for manufacturing a semiconductor device according to the second embodiment.

[0059] Figure 20B This is a diagram showing a step of forming a gold plating film in the third step of the method for manufacturing a semiconductor device according to the second embodiment.

[0060] Figure 20C This is a diagram showing a step of removing the protective material in the third step of the method for manufacturing a semiconductor device according to the second embodiment.

[0061] Figure 20D This is a diagram showing a step of removing a portion of the seed crystal film to perform pn separation on the electrodes in the third step of the method for manufacturing a semiconductor device according to the second embodiment.

[0062] Figure 21A This is a diagram showing a step of arranging a semiconductor element on a mounting substrate in the fourth step of the method for manufacturing a semiconductor device according to the second embodiment.

[0063] Figure 21B This is a diagram showing a step of mounting a semiconductor element on a mounting substrate and performing ultrasonic bonding in the fourth step of the method for manufacturing a semiconductor device according to the second embodiment.

[0064] Figure 22 This is a timing chart of ultrasonic bonding when mounting a semiconductor element on a mounting substrate in the second embodiment.

[0065] Figure 23A This is a diagram showing a cross section around the gold plating film before ultrasonic bonding in the second embodiment.

[0066] Figure 23B It shows Figure 22 A diagram showing the bonding state between the gold-plated film and the second electrode of the mounting substrate immediately after Step 1 in [1].

[0067] Figure 23C It shows Figure 22 A diagram showing the bonding state between the gold-plated film and the second electrode of the mounting substrate midway through Step 2 (approximately 300 ms after the start of the process).

[0068] Figure 23D It is shown in Figure 22 A diagram showing the bonding state between the gold-plated film and the second electrode of the mounting substrate at the end of Step 2.

[0069] Figure 24 This is a cross-sectional view of a semiconductor device according to a third embodiment.

[0070] Figure 25 This is a diagram showing an enlarged cross-sectional view of a metal bump of a semiconductor device according to a third embodiment and the height position dependency of the crystal grain size in the metal bump.

[0071] Figure 26AThis is a diagram showing a step of forming a second p-side electrode and a second n-side electrode on a mounting substrate in a step of manufacturing a mounting substrate in a method of manufacturing a semiconductor device according to a third embodiment.

[0072] Figure 26B This is a diagram showing a step of forming a protective material having an opening in a step of manufacturing a mounting substrate in a method of manufacturing a semiconductor device according to a third embodiment.

[0073] Figure 26C This is a diagram showing a step of forming a gold plating film in a step of manufacturing a mounting substrate in a method of manufacturing a semiconductor device according to a third embodiment.

[0074] Figure 26D This is a diagram showing a step of removing a protective material in the process of manufacturing a mounting substrate in the method of manufacturing a semiconductor device according to the third embodiment.

[0075] Figure 26E This is a diagram showing a heat treatment step in the process of manufacturing a mounting substrate in the method of manufacturing a semiconductor device according to the third embodiment.

[0076] Figure 27A This is a diagram showing a step of arranging a semiconductor element on a mounting substrate in the fourth step of the method for manufacturing a semiconductor device according to the third embodiment.

[0077] Figure 27B This is a diagram showing a step of mounting a semiconductor element on a mounting substrate and performing ultrasonic bonding in the fourth step of the method for manufacturing a semiconductor device according to the third embodiment.

[0078] Figure 28 is a cross-sectional view showing a semiconductor device disclosed in Patent Document 1.

[0079] Figure 29A This is a cross-sectional view of a semiconductor device according to a comparative example in which a semiconductor element is mounted on a mounting substrate by flip-chip bonding (a state before flip-chip bonding).

[0080] Figure 29B This is a cross-sectional view of a semiconductor device according to a comparative example in which a semiconductor element is mounted on a mounting substrate by flip-chip bonding (a state after flip-chip bonding). DETAILED DESCRIPTION

[0081] (Process of Obtaining a Solution of the Present Disclosure)

[0082] As semiconductor light-emitting elements such as LEDs become smaller and their currents increase, semiconductor light-emitting devices including these elements are required to have an increasingly higher level of reliability.

[0083] The semiconductor device disclosed in Patent Document 1 boasts high thermal stress tolerance. However, the present inventors have discovered that, as semiconductor light-emitting elements become smaller and higher currents are used, they can suffer from electrode failure and other damage during long-term reliability testing. This is likely due to stress from pressing metal bumps during bonding, which can cause the electrodes of the semiconductor light-emitting element to warp, leading to electrode failure and other issues.

[0084] Here, use Figure 29A as well as Figure 29B , explaining the reasons why the electrodes of semiconductor light-emitting elements are skewed. Figure 29A as well as Figure 29B 1 is a cross-sectional view of a semiconductor device 100 according to a comparative example in which a semiconductor element 10 is mounted on a mounting substrate 20 by flip-chip bonding. Figure 29A Shows the state before flip chip soldering, Figure 29B The state after flip chip bonding is shown.

[0085] like Figure 29B As shown, the semiconductor device 100 includes a semiconductor element 10 having a semiconductor stacked structure 11, and a mounting substrate 20. The semiconductor element 10 and the mounting substrate 20 are bonded via a metal bump 130. Specifically, the first electrode (first p-side electrode 12, first n-side electrode 13) formed in the semiconductor stacked structure 11 of the semiconductor element 10 and the second electrode (second p-side electrode 22, second n-side electrode 23) of the mounting substrate 20 are bonded via the metal bump 130. The metal bump 130 is equivalent to, Figure 28 Patent Document 1 discloses a semiconductor device 200 having a p-side electrode column 242 and an n-side electrode column 252 .

[0086] When the semiconductor element 10 is mounted on the mounting substrate 20, as shown in FIG. Figure 29A As shown, a semiconductor element 10 (e.g., an LED) is positioned so that the second electrodes (second p-side electrode 22 and second n-side electrode 23) disposed on the mounting substrate 20 face metal bumps 130 formed on the first electrodes (first p-side electrode 12 and first n-side electrode 13) of the semiconductor element 10. Subsequently, a load is applied from the semiconductor element 10 toward the mounting substrate 20 (in a direction perpendicular to the mounting substrate 20) while ultrasonic waves are applied. This ultrasonically bonds the gold on the outermost surface of the second electrode of the mounting substrate 20 to the gold on the outermost surface of the metal bumps 130. Consequently, the semiconductor element 10 and the mounting substrate 20 are bonded via the metal bumps 130.

[0087] However, it was discovered that the metal bumps 130 were pressed against the first electrodes (first p-side electrode 12 and first n-side electrode 13) on the semiconductor element 10 side by the pressure of the load during mounting, causing the first electrodes of the semiconductor element 10 to warp. This warping of the electrodes of the semiconductor element 10 caused cracks or bump marks to form on the first electrodes of the semiconductor element 10, leading to electrode failures during long-term reliability testing.

[0088] With the miniaturization and high current consumption of semiconductor components, especially LEDs, the development of electrodes and bumps that maintain the strength of semiconductor components during mounting while preventing them from warping during mounting has become increasingly important. Furthermore, the mechanical stress-related issues identified in this disclosure are not discussed in Patent Document 1.

[0089] Therefore, the present inventors have studied a structure and a construction method for preventing the electrodes and bumps of the semiconductor element from being warped during mounting even when the semiconductor element is mounted on a mounting substrate via metal bumps by flip-chip bonding.

[0090] Moreover, as a result of repeated research, the inventors have discovered the following: in a semiconductor device in which a semiconductor element and a mounting substrate are joined via a metal bump, a first layer connected to the electrode of the semiconductor element and a second layer connected to the first layer are provided in the metal bump, and the grain size of one of the first and second layers is set to be larger than the grain size of the other, so that the metal bump absorbs and mitigates the impact during mounting, thereby suppressing damage to the electrode caused by the semiconductor element.

[0091] Furthermore, it was discovered that, regarding the metal bump, a soft layer is provided at the portion in contact with the electrode of the semiconductor element (or mounting substrate), so that due to the pressure during mounting, the soft layer is compressed, and the joint portion on at least one side of the semiconductor element side and the mounting substrate side becomes a shape that gradually expands downward, thereby increasing the bonding area between the metal bump and the electrode of the semiconductor element (or mounting electrode), and increasing the bonding strength between the metal bump and the electrode of the semiconductor element.

[0092] The semiconductor device according to the present disclosure is proposed based on such a concept.

[0093] Specifically, the first semiconductor device involved in the present disclosure comprises: a mounting substrate; and a semiconductor element, which is arranged on the mounting substrate via a metal bump, the semiconductor element having a semiconductor stacked structure and a first electrode, the mounting substrate having a second electrode, the metal bump having a first layer connected to the first electrode, and a second layer located on the opposite side of the first electrode, the average grain size of the crystals constituting the first layer is larger than the average grain size of the crystals constituting the second layer, and the second layer is located at a position separated from the first electrode.

[0094] Furthermore, in the first semiconductor device according to the present disclosure, the first layer may include a transition region on the second layer side, and the average grain size of the transition region gradually approaches the average grain size of the second layer from the average grain size of the first layer.

[0095] Furthermore, in the first semiconductor device according to the present disclosure, the maximum height roughness of the interface between the first layer and the second layer may be equal to or greater than the average crystal grain size of the second layer.

[0096] In this case, the average crystal grain size of the first layer may be equal to or larger than the maximum height roughness of the interface.

[0097] In addition, the first semiconductor device involved in the present disclosure may be that the first electrode is composed of at least two layers including a surface layer, the surface layer is connected to the metal bump and is made of gold, when the thickness of the surface layer is set to A, the average grain size of the surface layer is set to B, the thickness of the first layer is set to C, and the maximum height roughness of the interface between the first layer and the second layer is set to Rz, the following relationship is satisfied: C>Rz / 2+1-A×B / 8.

[0098] Furthermore, in the first semiconductor device according to the present disclosure, the first layer may have an equiaxed grain structure.

[0099] Furthermore, in the first semiconductor device according to the present disclosure, the second layer may have a multi-axial grain structure.

[0100] In addition, the first semiconductor device involved in the present disclosure may be that, when a virtual rectangle having the same area and the same height as the cross-sectional shape of the metal bump is defined in the cross-section of the semiconductor element, the mounting substrate, and the metal bump in a direction perpendicular to the mounting substrate, the width of the joint between the first layer connected to the first electrode and the first electrode, i.e., the first joint, is longer than the length of the base of the rectangle.

[0101] In addition, the first semiconductor device involved in the present disclosure may be that the metal bump has a third layer connected to the second electrode, and when a virtual rectangle having the same area and the same height as the cross-sectional shape of the metal bump is defined in the cross-section of the semiconductor element, the mounting substrate and the metal bump in a direction perpendicular to the mounting substrate, the width of the junction between the third layer and the second electrode, i.e., the second junction, is longer than the length of the base of the rectangle.

[0102] Furthermore, in the first semiconductor device according to the present disclosure, the width of the second layer may be shorter than the length of the base of the rectangle.

[0103] Furthermore, in the first semiconductor device according to the present disclosure, the semiconductor stacked structure may include a substrate, and a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked in this order from the substrate side.

[0104] Furthermore, in the first semiconductor device according to the present disclosure, the first electrode may include a metal film, the metal film being arranged in contact with the second conductivity-type semiconductor layer and reflecting light from the active layer.

[0105] In addition, the second semiconductor device involved in the present disclosure comprises: a mounting substrate; and a semiconductor element, which is arranged on the mounting substrate via a metal bump, the semiconductor element having a semiconductor stacked structure and a first electrode, the mounting substrate having a second electrode, the metal bump having a first layer connected to the first electrode, and a second layer located on the opposite side of the first electrode, the first layer having an equiaxed grain structure.

[0106] Furthermore, in the second semiconductor device according to the present disclosure, the second layer may have a multi-axial grain structure.

[0107] In addition, the third semiconductor device involved in the present disclosure comprises: a mounting substrate; and a semiconductor element, which is arranged on the mounting substrate via a metal bump, the semiconductor element having a semiconductor stacked structure and a first electrode, the mounting substrate having a second electrode, the metal bump having a first layer made of gold in contact with the first electrode, and a second layer located on the opposite side of the first electrode, the average grain size of the crystals constituting the first layer is larger than the average grain size of the crystals constituting the second layer, the first electrode is composed of at least two layers including a surface layer, the surface layer is in contact with the metal bump and is made of gold, the thickness of the surface layer is set to A, the average grain size of the surface layer is set to B, the thickness of the first layer is set to C, and when the maximum height roughness of the interface between the first layer and the second layer is set to Rz, the following relationship is satisfied: C>Rz / 2+1-A×B / 8.

[0108] In addition, the fourth semiconductor device involved in the present disclosure comprises: a mounting substrate; and a semiconductor element, which is arranged on the mounting substrate via a metal bump formed by multiple metal layers, the semiconductor element having a semiconductor stacked structure and a first electrode, and the mounting substrate having a second electrode. In the cross-section of the semiconductor element, the mounting substrate and the metal bump in a direction perpendicular to the mounting substrate, when a virtual rectangle having the same area and the same height as the cross-sectional shape of the metal bump is defined, at least either one of the width of the junction between the first layer connected to the first electrode and the first electrode, i.e., the first junction, and the width of the junction between the third layer connected to the second electrode and the second electrode, i.e., the second junction, is longer than the length of the base of the rectangle.

[0109] Furthermore, in the fourth semiconductor device according to the present disclosure, the metal bump may include a second layer between the first layer and the third layer, the second layer having a width shorter than a length of a bottom side of the rectangle.

[0110] (Implementation Method)

[0111] Hereinafter, the embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, the embodiments described below are all specific examples of the present disclosure. Therefore, the numerical values, shapes, materials, constituent elements, the configuration positions of the constituent elements and the connection forms, as well as the processes and the order of the processes shown in the following embodiments are examples, and the main purpose is not to limit the present disclosure. In addition, among the constituent elements in the following embodiments, the constituent elements that are not recorded in the technical solution showing the highest concept are described as arbitrary constituent elements.

[0112] In addition, each figure is a schematic diagram and is not a strict illustration. Therefore, the scale etc. in each figure are not consistent. In addition, in each figure, the same symbols are given to substantially the same structure, and repeated descriptions are omitted or simplified.

[0113] (Implementation Method 1)

[0114] [Semiconductor devices]

[0115] First, use Figure 1 The configuration of the semiconductor device 1 according to the first embodiment will be described. Figure 1 This is a cross-sectional view of the semiconductor device 1 according to the first embodiment.

[0116] like Figure 1 As shown, the semiconductor device 1 according to the first embodiment includes a semiconductor element 10 , a mounting substrate 20 , and metal bumps 30 .

[0117] The semiconductor element 10 is arranged on the mounting substrate 20 via the metal bumps 30 . In other words, the semiconductor element 10 is bonded to the mounting substrate 20 via the metal bumps 30 .

[0118] In this embodiment, the semiconductor element 10 is a light emitting diode (LED) chip. Therefore, the semiconductor device 1 is a semiconductor light emitting device including an LED chip.

[0119] The semiconductor element 10 includes a semiconductor stacked structure 11, and a first p-side electrode 12 and a first n-side electrode 13 as first electrodes formed on the semiconductor stacked structure 11. The first p-side electrode 12 and the first n-side electrode 13 are composed of at least two layers, including a surface layer made of gold that contacts the metal bump 30.

[0120] In this specification, the first p-side electrode 12 and the first n-side electrode 13 are collectively referred to as the first electrode of the semiconductor element 10 unless they need to be specifically distinguished in description.

[0121] The semiconductor stack structure 11 includes a substrate 11a, an n-type semiconductor layer 11b (first conductivity-type semiconductor layer), an active layer 11c, and a p-type semiconductor layer 11d (second conductivity-type semiconductor layer). The n-type semiconductor layer 11b, the active layer 11c, and the p-type semiconductor layer 11d form a semiconductor stack in contact with the substrate 11a and are stacked in this order from the substrate 11a side. Specifically, the n-type semiconductor layer 11b, the active layer 11c, and the p-type semiconductor layer 11d are stacked on the substrate 11a in this order.

[0122] The first p-side electrode 12 and the first n-side electrode 13 are formed on the semiconductor stack structure 11. The first p-side electrode 12 is formed on the p-type semiconductor layer 11d. Furthermore, the first n-side electrode 13 is formed on the n-type semiconductor layer 11b. Specifically, the first n-side electrode 13 is formed in an exposed region formed by removing portions of the p-type semiconductor layer 11d and the active layer 11c, thereby exposing a portion of the n-type semiconductor layer 11b.

[0123] In this embodiment, an oxide film 14 is formed as an insulating film on the semiconductor stack structure 11. The first p-side electrode 12 is formed on the p-type semiconductor layer 11d exposed through the opening in the oxide film 14, and the first n-side electrode 13 is formed on the n-type semiconductor layer 11b exposed through the opening in the oxide film 14.

[0124] The first p-side electrode 12 includes a reflective electrode 12a, a barrier electrode 12b, a seed layer 12c, and a cover electrode 12d, stacked sequentially from the semiconductor stack structure 11 side. Specifically, the reflective electrode 12a, the barrier electrode 12b, the seed layer 12c, and the cover electrode 12d are stacked in this order on the semiconductor stack structure 11. In the first p-side electrode 12, the reflective electrode 12a is a metal film that reflects light from the active layer 11c of the semiconductor stack structure 11. It is arranged in contact with the p-type semiconductor layer 11d (second conductivity-type semiconductor layer) of the semiconductor stack structure 11.

[0125] Furthermore, the first n-side electrode 13 includes an ohmic contact layer 13 a , a barrier electrode 13 b , a seed layer 13 c , and a cover electrode 13 d stacked in this order from the semiconductor stack structure 11 side.

[0126] In the first p-side electrode 12 and the first n-side electrode 13, the cover electrodes 12d and 13d are gold surface layers in contact with the metal bumps 30. Specifically, the cover electrodes 12d and 13d are gold-plated films formed with the seed layers 12c and 13c as base layers.

[0127] The mounting substrate 20 includes a substrate 21 and a second p-side electrode 22 and a second n-side electrode 23 as second electrodes formed on one surface of the substrate 21. The second p-side electrode 22 and the second n-side electrode 23 are extraction electrodes for applying current to the semiconductor element 10.

[0128] The second p-side electrode 22 is bonded to the first p-side electrode 12 of the semiconductor element 10 via the metal bump 30. Similarly, on the n-side, the second n-side electrode 23 is bonded to the first n-side electrode 13 of the semiconductor element 10 via the metal bump 30.

[0129] In this specification, the second p-side electrode 22 and the second n-side electrode 23 are collectively referred to as the second electrode of the mounting substrate 20 unless there is no need to distinguish them.

[0130] Metal bumps 30 are formed on the semiconductor element 10. The p-side metal bumps 30 and the n-side metal bumps 30 have the same structure. In other words, the metal bumps 30 between the first p-side electrode 12 of the semiconductor element 10 and the second p-side electrode 22 of the mounting substrate 20 and the metal bumps 30 between the first n-side electrode 13 of the semiconductor element 10 and the second n-side electrode 23 of the mounting substrate 20 have the same structure. In this embodiment, the metal bumps 30 are gold bumps formed by gold plating.

[0131] Specifically, the metal bump 30 has multiple metal layers, including a first layer 31 located on the first electrode (first p-side electrode 12, first n-side electrode 13) side, and a second layer 32 located on the opposite side of the first electrode. In this embodiment, the metal bump 30 has two layers: the first layer 31 and the second layer 32.

[0132] The first layer 31 is in contact with the first electrode (the first p-side electrode 12 and the first n-side electrode 13 ). Specifically, the first layer 31 is directly bonded to the covering electrode 12 d of the first p-side electrode 12 or the covering electrode 13 d of the first n-side electrode 13 .

[0133] On the other hand, the second layer 32 is in contact with the first layer 31 and is also in contact with the second electrodes (the second p-side electrode 22 and the second n-side electrode 23) of the mounting substrate 20. Specifically, the second layer 32 is directly bonded to the second p-side electrode 22 or the second n-side electrode 23. Therefore, the second layer 32 is located at a position separated from the first electrodes (the first p-side electrode 12 and the first n-side electrode 13). Specifically, the first layer 31 is located between the second layer 32 and the first electrode.

[0134] The first layer 31 is wider than the second layer 32. In this embodiment, the first layer 31 and the second layer 32 are both substantially cylindrical, and the first layer 31 is cylindrical with a larger diameter than the second layer 32.

[0135] Figure 2 : is an enlarged cross-sectional view of the metal bump 30 of the semiconductor device 1 according to the first embodiment and a diagram showing the height position dependency of the crystal grain size in the metal bump 30. Figure 2 In FIG. 1 , the vertical axis represents the height of the metal bump 30 , and the horizontal axis represents the crystal grain size of the metal bump 30 .

[0136] like Figure 2 As shown, in the metal bump 30, the average grain size of the crystals constituting the first layer 31 is larger than the average grain size of the crystals constituting the second layer 32. In other words, the metal bump 30 is composed of the first layer 31 and the second layer 32 having different metal grain sizes.

[0137] Here, we explain the relationship between the grain size and hardness of metals. Generally, there is a negative correlation between the grain size and hardness of metals. In other words, the smaller the grain size, the higher the hardness. Conversely, the larger the grain size, the lower the hardness. This is because the hardness of a metal is determined by the amount of plastic deformation it undergoes when a load is applied, and the amount of plastic deformation is affected by the proliferation of dislocations, obstacles to movement, the length of the slip plane, and the direction of the metal's crystallization.

[0138] The slip plane of a metal crystal is determined by a specific direction in the crystal lattice. When stress is applied, the metal slips in this direction, causing plastic deformation. Specifically, metal crystals with large grain sizes have long slip lines. When stress is applied, stress concentrates at the crystal boundaries, making them more susceptible to plastic deformation. In other words, this is called softness.

[0139] Conversely, metal crystals with small grain sizes have smaller slip planes within each grain. When a certain stress is applied, there are more slip planes that are misaligned with the stress direction. Consequently, these crystals resist slipping, making plastic deformation difficult. In other words, metal crystals with small grain sizes are considered hard.

[0140] As will be discussed later, the relationship between crystal grain size and hardness also applies to gold-plated films. Specifically, for metal bumps 30 formed from gold-plated films, there is a negative correlation between crystal grain size and hardness. In other words, the larger the average crystal grain size of the gold-plated film, the lower the hardness.

[0141] Furthermore, in the metal bump 30 of this embodiment, the first layer 31 is recrystallized by heating after gold plating, resulting in a coarsened crystal grain size. In other words, in the metal bump 30, the first layer 31, which has a relatively large average crystal grain size, is softer than the second layer 32, which has a relatively small average crystal grain size.

[0142] In the semiconductor device 1 thus configured, when the semiconductor element 10 having the metal bumps 30 formed thereon is mounted on the mounting substrate 20, the metal bumps 30 can mitigate the impact between the semiconductor element 10 and the mounting substrate 20. Consequently, when the semiconductor element 10 is mounted on the mounting substrate 20, damage to the first electrodes (first p-side electrode 12 and first n-side electrode 13) of the semiconductor element 10 can be suppressed.

[0143] [Method for Manufacturing Semiconductor Device]

[0144] Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to the drawings.

[0145] The method for manufacturing the semiconductor device 1 according to the first embodiment includes the following steps: a first step of forming the semiconductor stacked structure 11 of the semiconductor element 10 ( Figure 3A-3B ), followed by a second step of forming the first electrode of the semiconductor element 10 ( Figures 4A to 4I ), then the third step of forming the metal bump 30 on the semiconductor element 10 ( Figure 5A a~ Figure 5D ), and then the fourth step ( Figure 6A-6B ).

[0146] [First Step (Step of Forming a Semiconductor Stacked Structure)]

[0147] First, through Figure 3A-3B According to the illustrated process, the semiconductor stacked structure 11 of the semiconductor element 10 is formed. Figure 3A-3B 1 is a diagram showing a process for forming the semiconductor stacked structure 11 of the semiconductor element 10 .

[0148] Specifically, if Figure 3A As shown, a substrate 11a is prepared first. In this embodiment, the substrate 11a is a light-transmitting substrate made of a semiconductor, and a wafer made of GaN (GaN substrate) is used.

[0149] Then, if Figure 3B As shown, an n-type semiconductor layer 11b, an active layer 11c, and a p-type semiconductor layer 11d are sequentially stacked on a substrate 11a by using the MOVPE (Metal Organic Vapor Phase Epitaxy) method to form a semiconductor stack structure 11.

[0150] In this embodiment, n-type semiconductor layer 11b is an n-type nitride semiconductor layer (e.g., a GaN layer), active layer 11c is a nitride light-emitting layer, and p-type semiconductor layer 11d is a p-type nitride semiconductor layer. The nitride light-emitting layer constituting active layer 11c contains at least Ga and N and, if necessary, an appropriate amount of In to achieve the desired emission wavelength. In this embodiment, active layer 11c is an InGaN layer, and the In composition ratio is set so that the peak emission wavelength is 450 nm.

[0151] [Second step (first electrode formation step)]

[0152] Then, through Figures 4A to 4I In the illustrated process, the first electrodes (the first p-side electrode 12 and the first n-side electrode 13 ) of the semiconductor element 10 are formed. Figures 4A to 4I It is a diagram showing a flow for forming the first electrode of the semiconductor element 10 .

[0153] Specifically, first, Figure 4A As shown, with respect to the semiconductor stacked structure 11 formed in the first step, dry etching is performed to remove a portion of the p-type semiconductor layer 11d, the active layer 11c, and the n-type semiconductor layer 11b, thereby exposing a portion of the n-type semiconductor layer 11b from the p-type semiconductor layer 11d and the active layer 11c. This forms an exposed region in a portion of the n-type semiconductor layer 11b.

[0154] Then, if Figure 4BAs shown, an oxide film 14 is formed as an insulating film on the entire upper surface of the semiconductor stacked structure 11 including the exposed region of the n-type semiconductor layer 11 b .

[0155] Thereafter, although not shown, a protective material is applied on the oxide film 14 , and openings are formed in the protective material at positions corresponding to the exposed regions of the n-type semiconductor layer 11 b by photolithography. The oxide film 14 in the openings of the protective material is then removed by etching using hydrofluoric acid.

[0156] Then, if Figure 4C As shown, the n-side electrode forming material used to form the first n-side electrode 13 is formed into a film using the EB (Electron Beam) evaporation method, and the protective material and excess n-side electrode forming material are removed by the protective material stripping method. In the area where the oxide film 14 is removed, a part of the first n-side electrode 13 is formed.

[0157] In this embodiment, as n-side electrode forming materials, an Al layer (thickness 0.3 μm) serving as the ohmic contact layer 13a and a Ti layer (thickness 0.1 μm) serving as the barrier electrode 13b are sequentially formed from the side closest to the n-type semiconductor layer 11b toward the side away from it. Thus, a stacked structure of the Al-based ohmic contact layer 13a and the Ti-based barrier electrode 13b can be formed as part of the first n-side electrode 13.

[0158] Furthermore, the Al layer of the first n-side electrode 13, stacked directly on the n-type semiconductor layer 11b, functions as an ohmic contact layer for the n-type semiconductor layer 11b. The material of the ohmic contact layer can be, for example, Ti, V, Al, or an alloy containing any of these metals. Furthermore, the Ti layer used in the barrier electrode 13b acts as a barrier, preventing the underlying Al layer from reacting with the upper Au layer formed in a subsequent step.

[0159] Afterwards, although not shown, a protective material is applied to cover the first n-side electrode 13 and the oxide film 14, an opening is formed in the protective material of the p-type semiconductor layer 11d by photolithography, and the oxide film 14 in the opening of the protective material is removed by etching using hydrofluoric acid.

[0160] Then, if Figure 4D As shown, the p-side electrode forming material for forming the first p-side electrode 12 is formed into a film using the EB evaporation method, and the protective material and excess p-side electrode forming material are removed by the protective material stripping method, thereby forming a reflective electrode 12a as a part of the first p-side electrode 12 in the area where the oxide film 14 is removed on the p-type semiconductor layer 11d.

[0161] In this embodiment, a 0.2 μm-thick Ag layer is formed as the reflective electrode 12a (p-side electrode forming material). The reflective electrode 12a is formed so as to be spaced apart from the oxide film 14. In other words, the p-type semiconductor layer 11d is exposed between the reflective electrode 12a and the oxide film 14.

[0162] The reflective electrode 12a can be made of a metal film made of a metal material with high reflectivity such as Ag, Al, or Rh to reflect light from the active layer 11c. The reflective electrode 12a can be formed by not only EB deposition but also sputtering.

[0163] Then, if Figure 4E As shown, a barrier electrode 12b is formed to cover the upper surface and side surfaces of the reflective electrode 12a. In this embodiment, a 0.8μm-thick Ti layer is formed as the barrier electrode 12b using sputtering. Materials such as Ti, Ni, Pt, and TiW can be used to protect the reflective electrode 12a. The barrier electrode 12b is formed to cover the exposed p-type semiconductor layer 11d between the oxide film 14 and the reflective electrode 12a, as well as the end of the oxide film 14 on the n-type semiconductor layer 11b.

[0164] Then, if Figure 4F As shown, a seed film 12S is formed by EB evaporation over the entire surface of the wafer where the barrier electrode 12b of the first p-side electrode 12 and the barrier electrode 13b of the first n-side electrode 13 are formed. The seed film 12S is a metal film that serves as the seed layer 12c of the first p-side electrode 12 and the seed layer 13c of the first n-side electrode 13, and is used as a gold-plated base electrode. In this embodiment, the seed film 12S has a stacked structure consisting of a Ti layer and an Au layer stacked from the side closest to the barrier electrodes 12b and 13b toward the side away from them.

[0165] Then, if Figure 4G As shown, the protective material 15 is formed on the seed film 12S in the boundary region between the barrier electrode 12 b corresponding to the first p-side electrode 12 and the barrier electrode 13 b corresponding to the first n-side electrode 13 .

[0166] Then, if Figure 4HAs shown, in an area on the wafer where protective material 15 is not formed (protective material non-formed area), seed film 12S is used as a base electrode, and metal is deposited by electrolytic gold plating to form gold-plated films, namely cover electrodes 12d and 13d. Cover electrode 12d is formed on seed film 12S on barrier electrode 12b, and cover electrode 13d is formed on seed film 12S on barrier electrode 13b. An example of the conditions for forming the gold-plated films on cover electrodes 12d and 13d is to use a non-cyanide Au plating solution at a gold plating temperature of 50°C and a deposition rate of 0.5μm / min, forming a 1.0μm thick gold-plated film on cover electrodes 12d and 13d.

[0167] Here, Au or a material containing Au is used for cover electrodes 12d and 13d to improve corrosion resistance. Furthermore, when semiconductor element 10 is viewed from the side of cover electrode 12d (cover electrode 13d), cover electrode 12d is formed so as to enclose barrier electrode 12b, and cover electrode 13d is formed so as to enclose barrier electrode 13b. Furthermore, an oxide film 14 is disposed on the semiconductor stack structure 11 side between cover electrodes 12d and 13d.

[0168] Then, if Figure 4I As shown, the protective material 15 is removed. For example, the protective material 15 on the seed crystal film 12S is removed using an organic solvent or the like.

[0169] [Third step (Metal bump formation step)]

[0170] Then, if Figures 5A to 5D In the illustrated process, metal bumps 30 are formed on the semiconductor device 10 . Figures 5A to 5D The diagram shows a flow for forming the metal bump 30 on the semiconductor element 10 .

[0171] Figure 1 The metal bump 30 shown includes a first bump on the p-side corresponding to the first p-side electrode 12, and a second bump on the n-side corresponding to the first n-side electrode 13. The first bump is formed on the first p-side electrode 12, and the second bump is formed on the first n-side electrode 13. In this embodiment, the metal bump 30 is a gold-plated bump formed using a gold plating method. Furthermore, the metal bump 30 is composed of multiple metal layers and has a laminated structure of at least two layers of gold-plated films with different crystal grain sizes. The following describes a method for forming the metal bump 30.

[0172] After the second step, a photolithography protective material is first applied to cover the entire surface of the cover electrodes 12d and 13d, and then heat treated at 140°C for about 20 minutes to harden the protective material. Figure 5AAs shown, openings 16a with a diameter of 25 μm are formed by photolithography in the protective material 16 in predetermined regions where metal bumps 30 are formed on the covering electrode 12 d of the first p-side electrode 12 and the covering electrode 13 d of the first n-side electrode 13 .

[0173] Then, if Figure 5B As shown, gold is deposited through the openings 16a of the protective material 16 by electrolytic gold plating, thereby forming a gold-plated film 30X that becomes the metal bump 30. Specifically, the gold-plated film 30X is simultaneously formed on the cover electrode 12d of the first p-side electrode 12 and on the cover electrode 13d of the first n-side electrode 13, both exposed through the openings 16a of the protective material 16. As an example of the conditions for forming the gold-plated film 30X, a non-cyanide Au plating solution with a plating temperature of 50°C and a deposition rate of 0.5 μm / min is used to form the gold-plated film 30X with a height (thickness) of 5 μm. The crystalline structure of the gold-plated film 30X immediately after formation is a collection of fine grains.

[0174] Then, if Figure 5C As shown, the protective material 16 is removed. For example, the protective material 16 is removed using an organic solvent. Consequently, a columnar gold plating film 30X having a diameter of 25 μm and a height of 5 μm is formed in predetermined regions on the cover electrode 12 d of the first p-side electrode 12 and on the cover electrode 13 d of the first n-side electrode 13.

[0175] Then, if Figure 5D As shown, a portion of the seed film 12S on the oxide film 14 between the barrier electrode 12b of the first p-side electrode 12 and the barrier electrode 13b of the first n-side electrode 13 is removed. In this embodiment, the seed film 12S has a stacked structure of Au and Ti layers. First, the Au layer, which is the upper layer of the seed film 12S, is removed using an iodine solution. Then, the Ti layer, which is the lower layer of the seed film 12S, is removed using dilute hydrofluoric acid, exposing the oxide film 14. As a result, the seed film 12S is divided into the seed layer 12c and the seed layer 13c on the oxide film 14, achieving pn-type separation of the electrodes. Specifically, the first p-side electrode 12, which is a stacked structure composed of the reflective electrode 12a, the barrier electrode 12b, the seed layer 12c, and the cover electrode 12d, can be separated from the first n-side electrode 13, which is a stacked structure composed of the ohmic contact layer 13a, the barrier electrode 13b, the seed layer 13c, and the cover electrode 13d.

[0176] Then, if Figure 5EAs shown, a wafer having a gold-plated film 30X formed thereon is subjected to a heat treatment at 150°C for one hour in an air atmosphere. This heat treatment changes the grain size of the lower region within the gold-plated film 30X and the covering electrodes 12d and 13d. Consequently, a metal bump 30 is obtained, which is composed of two layers: a first layer 31 and a second layer 32 having the same composition but different grain sizes. In the metal bump 30, the first layer 31 on the side closer to the semiconductor stack structure 11 has a larger grain size than the second layer 32 on the side farther from the semiconductor stack structure 11. Furthermore, the grain size of the crystals constituting the first layer 31 of the metal bump 30 is the same as the grain size of the crystals constituting the covering electrodes 12d and 13d.

[0177] Here, regarding the change in grain size due to heat treatment, Figures 7A to 7C Let's explain in detail. Figure 7A yes Figure 5D Magnified view of region VIIA. Figure 7B yes Figure 5E Magnified view of region VIIB. Figure 7C It is shown from Figure 7B The state of the grains is more coarsened. Figures 7A to 7C One gold plating film 30X or metal bump 30 on the first p-side electrode 12 and a region corresponding to a portion of the cover electrode 12 d of the first p-side electrode 12 located therebelow are shown.

[0178] Figure 7A FIG. 4 shows a cross section of the gold-plated film 30X immediately after the gold-plated film 30X is formed. Figure 7A As shown, the gold plating film 30X immediately after formation is entirely composed of an aggregate of fine crystal grains.

[0179] When the wafer having the gold-plated film 30X is heat-treated in an atmosphere furnace, as shown in FIG. Figure 7B As shown in FIG. 1 , heat is efficiently transferred from the first p-side electrode 12 (covering electrode 12d) side to the gold-plated film 30X in the direction of the arrow. The heat transferred to the gold-plated film 30X becomes the driving energy for the recrystallization of the gold constituting the gold-plated film 30X, causing the grains on the first p-side electrode 12 side to grow larger. As the heat treatment continues, the grains coarsen from the first p-side electrode 12 side toward the front end of the gold-plated film 30X, and finally, as shown in FIG. Figure 7C As shown in FIG. 1 , coarsened crystal grains are distributed throughout the entire gold plating film 30X. The higher the heat treatment temperature or the longer the heat treatment time, the coarser the crystal grains become.

[0180] In this embodiment, the heat treatment conditions for forming the metal bump 30 (heat treatment at 150° C. for 1 hour) are as follows: Figure 7B The conditions for stopping the coarsening of the crystal grains in the middle of the gold plating film 30X are not as follows. Figure 7CThe following diagram shows the conditions for coarsening the gold-plated film 30X through recrystallization to the tip. Specifically, the gold-plated film 30X is heat-treated at 150°C for 1 hour in an air atmosphere. The resulting metal bump 30 has a roughly two-layer structure, differentiated by grain size. Specifically, the metal bump 30 comprises a first layer 31, a layer with coarsened grains located closer to the first p-side electrode 12, and a second layer 32, a layer with relatively smaller grains located on the opposite side of the first p-side electrode 12.

[0181] Furthermore, the same grain changes as those in the gold-plated film 30X formed on the first p-side electrode 12 also occur in the gold-plated film 30X formed on the first n-side electrode 13. In other words, by heat treatment at 150°C for 1 hour, the gold-plated film 30X formed on the first n-side electrode 13 changes into two layers with different grain sizes, as shown in FIG. Figure 7B As shown, a metal bump 30 is formed having a first layer 31 and a second layer 32 . The first layer 31 is a layer with coarsened grains located on the side close to the first n-side electrode 13 , and the second layer 32 is a layer with relatively small grains located on the opposite side of the first n-side electrode 13 .

[0182] The following describes a method for measuring the grain size of the gold plating film 30X and the metal bump 30 used in this embodiment. In this embodiment, after forming a cross-section of the gold plating film 30X or the metal bump 30 using a focused ion beam (FIB), the observed area of the Scannig Ion Microscopy image (SIM image) is observed using a scanning microscope, and the grain size is measured using the interception method.

[0183] At this time, if Figure 8 As shown in the figure, if there are n crystals with an average grain size of d in a square with a side of L, the area of the square is L. 2 , the area of one grain is π(d / 2) 2 Moreover, for grains, when the observation area is relatively large, there are n grains in a square. 2 So the total area occupied by the grains is n 2 ×π(d / 2) 2 , the area of the square = the area occupied by all the crystal grains, so L 2 =n 2 ×π(d / 2) 2 When it is expressed as d, d=2L / n / (π) 1 / 2 Using this relationship, draw a straight line ( Figure 8The number of grain boundaries intersecting the straight line is taken as the number n of crystals, and the average grain size d in the horizontal direction and the height direction of the gold plating film 30X and the metal bump 30 is obtained.

[0184] Here, the horizontal direction refers to a direction parallel to the upper surface of the covering electrodes 12d and 13d, and the height direction refers to a direction perpendicular to the upper surface of the covering electrodes 12d and 13d. Figure 8 In the figure, the dot-dashed straight line intersects 6 grain boundaries, so n=6.

[0185] In this embodiment, the cross section of the metal bump 30 having the first layer 31 and the second layer 32 with different crystal grain sizes is Figure 7B In this case, when the crystal grain size of the metal bump 30 is measured according to the above method, the average crystal grain size in the horizontal direction is 8 μm in the first layer 31 and 1 μm in the second layer 32. In addition, the average crystal grain size in the height direction is 3 μm in the first layer 31 and 2 μm in the second layer 32.

[0186] Here, we conducted an experiment on the relationship between the average crystal grain size of the gold-plated film and the hardness of the single-layer gold-plated film. Figure 9 To explain. Figure 9 This is a graph showing the relationship between the average crystal grain size of the gold plating film and the hardness of the single-layer gold plating film.

[0187] In this experiment, a non-cyanide Au plating solution with a gold plating liquid temperature of 50°C was used, and the precipitation rate was set to 0.5μm / min to produce a single-layer gold-plated film with a thickness of 10μm. By changing the heat treatment conditions of the single-layer gold-plated film, the average crystal grain size was controlled, and the relationship between the average crystal grain size of the gold-plated film after heat treatment and the hardness of the single-layer gold-plated film before heat treatment was investigated. The average crystal grain size of the gold-plated film after heat treatment was determined using the crystal grain size determination method. In this case, the average crystal grain size in the horizontal direction was measured. In addition, the hardness of the single-layer gold-plated film before heat treatment was measured using Vickers hardness. In addition, in the subsequent description, unless otherwise specified, the average crystal grain size refers to the average crystal grain size in the horizontal direction.

[0188] like Figure 9 As shown in Figure 1, the relationship between the average crystal grain size of the gold-plated film and the hardness of the single-layer gold-plated film is negatively correlated. In other words, the smaller the average crystal grain size of the crystals constituting the gold-plated film, the higher the hardness. Conversely, the larger the average crystal grain size of the crystals constituting the gold-plated film, the lower the hardness. Thus, as the average crystal grain size of the gold-plated film increases, the hardness of the gold-plated film decreases, and as the average crystal grain size of the gold-plated film decreases, the hardness of the gold-plated film increases.

[0189] Here, as Figure 9 As shown, when the average grain size of the crystals constituting the gold plating film is 8 μm, the hardness of the gold plating film is approximately 0.8 GPa. In other words, the hardness of the first layer 31 of the metal bump 30 formed under the above heat treatment conditions, which has an average grain size of 8 μm, is approximately 0.8 GPa.

[0190] Furthermore, when the average grain size of the crystals constituting the gold plating film is 1 μm, the hardness of the gold plating film is approximately 1.9 GPa. In other words, the hardness of the second layer 32 of the metal bump 30 formed under the above heat treatment conditions, which has an average grain size of 1 μm, is approximately 1.9 GPa.

[0191] By comparing the average crystal grain sizes, the film with the larger crystal grain size becomes a softer layer, while the film with the smaller crystal grain size becomes a harder layer. In other words, the gold-plated film (first layer 31) with an average crystal grain size of 8 μm is a softer film than the gold-plated film (second layer 32) with an average crystal grain size of 1 μm.

[0192] [Step 4 (Step of Mounting a Semiconductor Element on a Mounting Substrate)]

[0193] Then, through Figure 6A-6B In the illustrated process, the semiconductor element 10 is mounted on the mounting substrate 20 by flip-chip bonding via the metal bumps 30 . Figure 6A-6B 1 and 2 are diagrams showing a process of mounting the semiconductor element 10 on the mounting substrate 20 via the metal bumps 30 .

[0194] First, a mounting substrate 20 for mounting the semiconductor element 10 is prepared. Specifically, a substrate 21 having a second p-side electrode 22 and a second n-side electrode 23 formed thereon is prepared as the mounting substrate 20. In this embodiment, the substrate 21 is a ceramic substrate made of a sintered AlN body. Furthermore, the second p-side electrode 22 and the second n-side electrode 23 are gold-plated films formed using a non-cyanide Au plating solution. Although not shown, a seed layer is formed between each of the second p-side electrode 22 and the second n-side electrode 23 and the substrate 21, separating the second p-side electrode 22 and the second n-side electrode 23.

[0195] Moreover, if Figure 6A As shown, a semiconductor element 10 having metal bumps 30 formed thereon is prepared in advance. With the metal bumps 30 facing the mounting substrate 20, the semiconductor element 10 is vacuum-adsorbed by a holding metal pipe 40 of a mounting machine. In this embodiment, a semiconductor element 10 measuring 800 μm long, 800 μm wide, and 100 μm thick is used.

[0196] Then, if Figure 6BAs shown, the metal bump 30 of the semiconductor element 10 is brought into contact with the second electrode (the second p-side electrode 22, the second n-side electrode 23) of the mounting substrate 20 while being heated at approximately 200°C. A load of 30N is applied in a direction perpendicular to the mounting substrate 20 (the direction of the arrow X in the figure: the first direction) by maintaining the metal tube 40, and ultrasonic vibrations are applied for 200ms in a direction horizontal to the mounting substrate 20 (the direction of the arrow Y in the figure: the second direction), thereby ultrasonically bonding the metal bump 30 to the second electrode (the second p-side electrode 22, the second n-side electrode 23) of the mounting substrate 20.

[0197] Here, regarding the changes that occur in the metal bump 30 when the metal bump 30 is bonded to the second electrode of the mounting substrate 20 by ultrasonic bonding, the following is explained: Figure 10 as well as Figures 11A to 11D Provide detailed explanation.

[0198] Figure 10 This is a timing diagram of ultrasonic bonding when the semiconductor element 10 is mounted on the mounting substrate 20 in the first embodiment. Figure 10 In the figure, the horizontal axis represents time, and the vertical axis represents load. Note that 0 ms (milliseconds) represents the time before the start of treatment (or at the start of treatment), 300 ms corresponds to the ultrasonic bonding treatment time in this embodiment, and 400 ms corresponds to the ultrasonic bonding treatment time in this embodiment extended by 100 ms of ultrasonic application time.

[0199] like Figure 10 As shown, the load is gradually increased over a period of 100ms (Step 1) after the semiconductor element 10 and mounting substrate 20 begin bonding. In Step 1, only the load is applied, without ultrasonic waves. Furthermore, between 100ms and 400ms (Step 2), ultrasonic waves are applied while maintaining a constant load. By performing the bonding process shown in this timing diagram, the semiconductor element 10 and mounting substrate 20 are ultrasonically bonded via the metal bump 30.

[0200] In this case, respectively Figures 11A to 11D The cross-section of the connection portion between the semiconductor element 10 and the mounting substrate 20, specifically, the connection portion between the metal bump 30 and the second electrode of the mounting substrate 20, is shown at 0 ms, 100 ms, 300 ms, and 400 ms after the start of the bonding process between the semiconductor element 10 and the mounting substrate 20. Figures 11A to 11D In FIG. 1 , among the second electrodes of the mounting substrate 20 , only the bonding portion on the second p-side electrode 22 is shown. The same applies to the bonding portion on the second n-side electrode 23 .

[0201] Figure 11A This is a diagram showing a cross section around the metal bump 30 before ultrasonic bonding in the present embodiment. Figure 11A As shown, the gold (Au) crystal grains constituting the first layer 31 and the second layer 32 of the metal bump 30 maintain substantially the same grain size within each layer, and the metal bump 30 as a whole has a cylindrical shape with the same diameter.

[0202] Figure 11B It shows Figure 10 FIG. 1 is a diagram showing the bonding state of the metal bump 30 and the second electrode of the mounting substrate 20 immediately after Step 1. Specifically, Figure 11B The figure shows the state after applying only a load in the direction perpendicular to the mounting substrate 20 (the direction of the arrow X in the figure). In Step 1, as the load is applied, the first layer 31, which is relatively softer than the second layer 32, is flattened. As a result, the shape of the first layer 31 expands in the horizontal direction to become a wine glass shape. At this time, the second layer 32, which is relatively harder than the first layer 31, is not flattened and generally maintains the shape before the process begins. In addition, the surface shape of the second electrode (second p-side electrode 22, second n-side electrode 23) of the mounting substrate 20 also maintains the shape before the process begins.

[0203] Figure 11C It shows Figure 10 FIG. 2 shows the bonding state of the metal bump 30 and the second electrode of the mounting substrate 20 in the middle of Step 2 (about 300ms after the start of the process and 200ms after the start of the ultrasonic vibration). Figure 11C It shows a state in which the semiconductor element 10 is bonded to the second electrode of the mounting substrate 20 when a certain load of 30N is applied in a direction perpendicular to the mounting substrate 20 (in the direction of the arrow mark X in the figure) and ultrasonic vibrations are applied in a direction horizontal to the mounting substrate 20 (in the direction of the arrow mark Y in the figure).

[0204] In this way, the application of ultrasonic waves causes the metal bump 30 to vibrate in a direction horizontal to the mounting substrate 20, heating the interface between the second layer 32 of the metal bump 30 and the second electrode of the mounting substrate 20 through friction. This results in solid-state bonding and integration of the metal bump 30 and the second electrode of the mounting substrate 20. At this point, the Au grains in the surface layer of the second electrode of the mounting substrate 20 and the Au grains in the second layer 32 of the metal bump 30 partially lose their original shape and become integrated, resulting in a loss of clarity between the second layer 32 of the metal bump 30 and the second electrode of the mounting substrate 20.

[0205] Figure 11D It shows Figure 10FIG. 2 shows the bonding state between the metal bump 30 and the second electrode of the mounting substrate 20 at the end of Step 2 (approximately 400 ms after the start of the process and 300 ms after the start of the ultrasonic vibration).

[0206] exist Figure 11D In the bonding state, at the bonding interface between the second layer 32 of the metal bump 30 and the second electrode of the mounting substrate 20, the Au grains from the second layer 32 and the Au grains from the second electrode are integrated. Moreover, the Au grains are integrated to form a third layer 33 as a layer of coarsened Au grains. The third layer 33 is formed in a manner that coarsens the Au grains, so it is soft. In addition, the third layer 33 is formed by applying ultrasonic vibration in a direction horizontal to the mounting substrate 20 (the direction of the arrow mark Y in the figure), so it is wider in the horizontal direction than the second layer 32.

[0207] In this embodiment, the ultrasonic bonding of the semiconductor element 10 and the mounting substrate 20 is carried out under the following conditions: Figure 11C The ultrasonic wave is applied to 200ms. In this case, the cross section through the center of the metal bump 30 becomes the Figure 2 Cross section shown.

[0208] The result, such as Figure 2 As shown, the metal bump 30 including the first layer 31 and the second layer 32 is formed in the shape of a wine glass with the first layer 31 side expanded.

[0209] In this embodiment, the thickness (height) of the relatively soft first layer 31 in the metal bump 30 is 2 μm before connection and 1 μm after connection, becoming thinner by 1 μm before and after connection. In contrast, the thickness of the relatively hard second layer 32 in the metal bump 30 remains unchanged at 3 μm before and after connection. In this way, the thickness of the first layer 31, which has a large crystal grain size and is soft, remains 1 μm after connection, so that the corners of the crystals inside the second layer 32 do not reach the covering electrodes 12d and 13d of the first electrode. Therefore, it can be imagined that when the semiconductor element 10 is mounted on the mounting substrate 20, the impact is mitigated.

[0210] Furthermore, the width of the metal bump 30 at the bonding surface between the first electrode and the first layer 31 is 30 μm (width W1), and the width of the second layer 32 is 25 μm (width W2). In other words, the shape of the metal bump 30 after ultrasonic bonding is a wine glass, with the width W1 of the bonding surface on the first electrode side being wider than the width W2 of the second layer 32.

[0211] Here, as Figure 2As shown by the dashed line, in the cross section of the semiconductor element 10, the mounting substrate 20, and the metal bump 30 perpendicular to the mounting substrate 20, a virtual bump 30R having a virtual rectangular cross section with the same area and height as the cross-sectional shape of the metal bump 30 is virtually defined. The length L of the base of the rectangle of the virtual bump 30R is 25.6 μm. When comparing this virtual bump 30R with the metal bump 30 in this embodiment, the width W1 of the first joint, i.e., the joint (joining surface) between the first electrode of the semiconductor element 10 and the first layer 31 of the metal bump 30, is longer than the length L of the base of the virtual bump 30R. Therefore, the metal bump 30 is expected to have higher bonding strength than the virtual bump 30R having the same cross-sectional area. Furthermore, the second layer 32 of the metal bump 30 has a width shorter than the length L of the base of the rectangle of the virtual bump 30R.

[0212] Here, the results of detailed confirmation of the horizontal grain size distribution within the metal bump 30 after ultrasonic bonding are as follows: Figure 12 As shown, it can be seen that the average grain size of the crystals constituting the first layer 31 gradually decreases as the distance from the first electrode (first p-side electrode 12, first n-side electrode 13) on the first layer 31 side increases. In other words, the first layer 31 has a transition region 31a on the second layer 32 side, and in the transition region 31a, the average grain size gradually approaches the average grain size of the second layer 32 from the average grain size of the first layer 31. This transition region is the area in the first layer 31 that contacts the second layer 32 and has a hardness intermediate between the first layer 31 and the second layer 32.

[0213] When such a transition region exists in the metal bump 30, the transition region has an intermediate deformation amount between the first layer 31 and the second layer 32, so Figure 2 Compared to the metal bump 30 shown above, which has a structure where the grain size decreases dramatically from the first layer 31 to the second layer 32, the transition region further reduces direct damage to the first electrode. This prevents interlayer delamination when the semiconductor element 10 is subjected to impact during mounting. In other words, the presence of the transition region mitigates even greater impacts.

[0214] [Verification of the effect]

[0215] Next, the effects of the semiconductor device 1 according to the first embodiment were verified and compared with the semiconductor device 100 of the comparative example. The verification results are described below. Figure 29B The semiconductor device shown has the same structure, but the hardness of the metal bump 130 is increased.

[0216] In the semiconductor device 100 of the comparative example, after forming the gold-plated film 30X in the method for manufacturing the semiconductor device 1 according to this embodiment, no heat treatment is performed to coarsen the crystal grains of the gold-plated film 30X. Instead, the gold-plated film 30X is used as is as the metal bump 130. Here, the metal bump 130 is formed to have a thickness of 5 μm and a diameter of 25 μm. Thus, in the semiconductor device 100 of the comparative example, since no heat treatment is performed after forming the gold-plated film 30X, the crystal grain size of the metal bump 130 is very small, with an average crystal grain size in the horizontal direction of 0.8 μm. Furthermore, the hardness of the metal bump 130 is approximately 1.9 GPa.

[0217] Furthermore, the semiconductor device 100 of the comparative example was mounted on the mounting substrate 20 by flip chip bonding in the same manner as the semiconductor device 1 of the first embodiment. The damage to the first p-side electrode 12 caused by the impact during the mounting was compared between the semiconductor device 100 of the comparative example and the semiconductor device 1 of the first embodiment. The damage to each semiconductor device was as follows. Figure 13 As shown, after mounting, the electrode surface of the first p-side electrode 12 was optically observed through the substrate 11a for evaluation. The evaluation results are shown below.

[0218] In the comparative example semiconductor device 100, contrast changes were observed at locations where metal bump 130 was projected onto the electrode surface of the first p-side electrode 12. This is because the metal bump 130, when pressed, exerts localized pressure on the first p-side electrode 12, causing deformation and partial thinning of the reflective electrode 12a, resulting in a decrease in reflectivity and visible contrast changes. This phenomenon was also observed in the ohmic contact layer 13a of the first n-side electrode 13, where deformation was observed. These locations where contrast changes are referred to as bump marks and serve as indicators of damage.

[0219] On the other hand, the same experiment was conducted on the semiconductor device 1 according to the first embodiment, and no bump marks were observed in the semiconductor device 1 according to the first embodiment. The following reasons are considered.

[0220] The metal bump 30 of the semiconductor device 1 according to the first embodiment comprises a first layer 31 with a large, soft crystal grain size, and a second layer 32 with a small, hard crystal grain size. Consequently, the soft first layer 31 absorbs the impact of the load applied during mounting, deforms during mounting, and acts as a shock absorber, preventing bump marks. In this case, it is conceivable that the hard second layer 32 would penetrate the soft first layer 31 due to the load applied during mounting. However, in this embodiment, the first layer 31 has a thickness of 1 μm, so it is clear that the second layer 32 does not penetrate the first layer 31. In reality, when viewed from any position in the cross section, the first layer 31 is present between the second layer 32 and the first p-side electrode 12.

[0221] In addition, in the semiconductor device 1 involved in embodiment 1, the first p-side electrode 12 is formed on the area where the p-type semiconductor layer 11d, the active layer 11c and the n-type semiconductor layer 11b are stacked. This is a structure that is prone to electrical failures such as poor conduction between pn due to damage to the first p-side electrode 12 due to impact during installation, but such electrical failure did not occur.

[0222] Next, the bonding strength of the metal bump 30 of the semiconductor device 1 according to the first embodiment will be described. In this case, the strength of the bonding portion between the metal bump 30 and the mounting substrate 20 is measured and evaluated using shear strength. Figure 14A as well as Figure 14B , explain the method for determining shear strength.

[0223] First, if Figure 14A As shown in FIG. 1 , the semiconductor device 1 is fixed to the metal stand 50, and the shear sensor 60 presses the semiconductor element 10 from the side of the semiconductor element 10. Figure 14B As shown, the shear sensor 60 is slid in the lateral direction, and a load is applied until the semiconductor element 10 deviates from the mounting substrate 20. At this time, the maximum load until the semiconductor element 10 deviates is defined as the shear strength.

[0224] As a result, the shear strength of the semiconductor device 100 of the comparative example was 5 kgF. On the other hand, the shear strength of the semiconductor device 1 according to the first embodiment was 8 kgF.

[0225] In addition, the reason why the semiconductor device 1 involved in embodiment 1 has higher shear strength than the semiconductor device 100 of the comparative example can be considered that the cross-sectional shape of the metal bump 30 of the semiconductor device 1 involved in embodiment 1 is a wine glass shape, and the bonding area between the first p-side electrode 12 and the first n-side electrode 13 and the metal bump 30 is increased.

[0226] Specifically, in Figure 29B In the semiconductor device 100 of the comparative example shown, the width W1 of the junction surface between the first p-side electrode 12 and the first n-side electrode 13 and the metal bump 130 is 25 μm. Figure 1 In the semiconductor device 1 according to the first embodiment shown, the width W1 of the junction surface between the first p-side electrode 12 and the first n-side electrode 13 and the metal bump 30 (see FIG. Figure 2) is 30 μm. Thus, in the semiconductor device 1 according to the first embodiment, the area of the junction between the metal bump 30 and the mounting substrate 20 is increased to form a wine glass shape, thereby increasing the width W1 of the junction surface between the first p-side electrode 12 and the first n-side electrode 13 and the metal bump 130. Consequently, the shear strength is also increased from 5 kgF to 8 kgF.

[0227] In the metal bump 30 of the semiconductor device 1 according to the first embodiment, Figure 2 As shown, the width W1 of the joint surface between the first electrode (the first p-side electrode 12, the first n-side electrode 13) and the metal bump 30 is greater than the length L of the bottom side of the virtual bump 30R with the same cross-sectional area of the metal bump 30. This is a shape feature, and it can be considered that this feature plays an important role in improving the shear strength.

[0228] Use here Figure 15 The following describes the results of observation of the Au crystal grains of the metal bump 30 of the semiconductor device 1 according to the first embodiment using a SIM image of a scanning microscope. Figure 15 is with Figure 12 The region XV surrounded by the dot-dash line corresponds to the SIM image of the portion.

[0229] The SIM image observation uses a cross section of the metal bump 30 formed by FIB. This method allows the difference in crystal orientation of the metallographic structure to be observed as a difference in contrast.

[0230] like Figure 15 As shown, it can be seen that the layer observed as a single contrast is separated from the layer observed as an aggregate of multiple contrasts.

[0231] Specifically, the portion corresponding to the first layer 31 located on the semiconductor stack structure 11 side exhibits a uniformly oriented, equiaxed grain structure with a single contrast. This portion undergoes grain coarsening and abnormal grain growth due to heat treatment after the gold plating, significantly reducing inter-grain boundaries. Consequently, it becomes a soft layer that is easily plastically deformed.

[0232] On the other hand, the portion corresponding to the second layer 32 on the mounting substrate 20 side is a collection of multiple contrasts, a collection of grains with misaligned crystal axes. In other words, the portion corresponding to the second layer 32 exhibits a multi-axial grain structure. Even after the heat treatment following the formation of the gold plating film, this portion exhibits no abnormal grain growth, resulting in numerous grain boundaries. Consequently, these grain boundaries act as a resistor against stress, forming a hard layer that resists plastic deformation.

[0233] Between the second layer 32 having a multi-axial grain structure and the first p-side electrode 12 and the first n-side electrode 13, there is a first layer 31 having an equiaxial grain structure, so that the first layer 31 can be considered to work as an impact relief layer based on plastic deformation, and it can be expected to suppress the occurrence of bump marks.

[0234] Furthermore, Figure 15 As shown, the interface between the first layer 31 and the second layer 32 inside the metal bump 30 has a concavo-convex shape, forming a concavo-convex interface. This concavo-convex shape increases the area of the interface between the first layer 31 and the second layer 32, thereby improving the adhesion between the layers.

[0235] Furthermore, as described above, in the semiconductor device 1 according to Embodiment 1, the first layer 31 may have a transition region where the average grain size changes toward the second layer 32. This transition region varies depending on the size of the unevenness at the interface between the first layer 31 and the second layer 32. Specifically, when there are no unevenness at the interface between the first layer 31 and the second layer 32, there is no transition region in the first layer 31. The larger the unevenness at the interface between the first layer 31 and the second layer 32, the larger the transition region becomes. Here, multiple semiconductor devices with varying thicknesses of transition regions were fabricated and the shear strength of each was measured. In this case, when the sum of the height of the highest peak of the unevenness at the interface between the first layer 31 and the second layer 32 and the depth of the lowest valley of the unevenness at the interface between the first layer 31 and the second layer 32 is defined as the maximum height roughness Rz in the transition region, and when the height of the metal bump 30 is the same, the greater the maximum height roughness Rz, the higher the shear strength. In particular, when the maximum height roughness Rz at the interface between the first layer 31 and the second layer 32 is larger than the average grain size of the second layer 32, the shear strength is higher.

[0236] In addition, when the average grain size of the first layer 31 is greater than the maximum height roughness Rz of the interface between the first layer 31 and the second layer 32, the hard second layer 32 will not penetrate the first layer 31 due to the impact during installation and cause damage to the first electrode (the first p-side electrode 12, the first n-side electrode 13), so the effect of the buffer material against the impact during installation is more significantly exerted.

[0237] Furthermore, a high-temperature, high-humidity conduction test was conducted on the semiconductor device 1 according to Embodiment 1, which does not have bump marks, and the semiconductor device 100 of the comparative example, which does have bump marks. Specifically, 15 samples of each of the semiconductor device 1 and the semiconductor device 100 were prepared and subjected to the conduction test for 1000 hours under the conditions of an ambient temperature of 85°C, a current of 0.35A, a humidity of 85%, and Tj = 150°C.

[0238] As a result, the number of defects in the semiconductor device 100 of the comparative example was 5 / 15, while the number of defects in the semiconductor device 1 according to Embodiment 1 was 0 / 15. In other words, no defects occurred in the semiconductor device 1 according to Embodiment 1.

[0239] A short circuit failure was confirmed as the cause of the failure in the comparative example semiconductor device 100. Analysis of the defective comparative example semiconductor device 100 identified the short circuit location as the bump mark. Furthermore, cross-sectional analysis of the short circuit location revealed a crack extending to the surface of the semiconductor stack structure 11 at the bump mark location of the first p-side electrode 12. When subjected to high temperature and high humidity, moisture intruded through the crack in the first p-side electrode 12, corroding the semiconductor layers of the semiconductor stack structure 11 and short-circuiting the PN junction, resulting in a short circuit failure.

[0240] On the other hand, in the semiconductor device 1 according to the first embodiment, a soft first layer 31 is present within the metal bump 30. Therefore, as described above, the impact on the first electrode during installation is mitigated, and the occurrence of bump marks can be suppressed. Furthermore, the soft first layer 31 expands relative to the surface of the first electrode, increasing the area of the joint between the first electrode and the metal bump 30, thereby increasing the bonding strength. Furthermore, the greater the maximum height roughness Rz of the interface between the first layer 31 and the second layer 32, the greater the area of the interface, thereby improving the adhesion between the first layer 31 and the second layer 32. In this case, when the grain size of the first layer 31 is larger than the maximum height roughness Rz, the effect of the buffer material against the impact during installation becomes more pronounced.

[0241] Furthermore, the present inventors studied the conditions for preventing bump marks during mounting, and the results of their study are described below. Through repeated studies, the present inventors investigated the correlation between the parameters of each layer during mounting by flip-chip bonding and discovered the conditions for preventing bump marks.

[0242] Specifically, in Figure 6A as well as Figure 6B As shown, the metal bump 30 formed on the semiconductor element 10 is brought into contact with the second electrode (the second p-side electrode 22 and the second n-side electrode 23) of the mounting substrate 20 and heated. Ultrasonic vibrations are applied while applying a load using a holding metal tube 40, thereby ultrasonically bonding the metal bump 30 and the second electrode of the mounting substrate 20. The conditions for generating bump marks in this case are described below.

[0243] When defining the conditions for preventing bump marks, the parameters of each layer are of concern. When the thickness A of the covering electrode 12d (the surface layer of the first electrode), the average grain size B of the covering electrode 12d, the thickness C of the first layer 31 on the semiconductor element 10 side, and the maximum height roughness Rz of the interface between the first layer 31 and the second layer 32 are defined, the conditions for preventing bump marks are within the range expressed below (Formula 1).

[0244] C>Rz / 2+1-A×B / 8···(Formula 1)

[0245] This is explained by the following mechanism.

[0246] Figure 16 yes Figure 1 An enlarged cross-sectional view of a region XVI surrounded by a dashed line.

[0247] exist Figure 16 The layer that serves as a buffer material for preventing bump marks is composed of two layers covering the electrode 12 d and the first layer 31 .

[0248] If the thickness D (= Rz / 2) of the interface irregularities between the first layer 31 and the second layer 32 is subtracted from the total thickness of the two layers (A + C) and the value is greater than 1 μm, the tips of the hard interface irregularities of the crystal grains in the second layer 32 will not penetrate the first layer 31, which acts as a buffer, and will not contact the reflective electrode 12a or the barrier electrode 12b, thus preventing deformation of the first electrode. This condition is considered to prevent the formation of bump marks. This condition is expressed by the following (Equation 2).

[0249] A×α+C-Rz / 2>1···(Formula 2)

[0250] Here, the variable α is a function of the crystal grain size B of the cover electrode 12 d that is associated with the hardness of the cover electrode 12 d , and is expressed by the following (Equation 3) using a constant k.

[0251] α=B×k···(Formula 3)

[0252] When (Formula 2) is transformed using (Formula 3), the following (Formula 4) is obtained.

[0253] C>Rz / 2+1-A×B×k···(Formula 4)

[0254] Here, in order to obtain k, the condition for confirming the bump mark as a boundary condition is substituted into the following (Formula 5) as the following condition (I).

[0255] Condition (I): Rz=2μm, A=1μm, B=8μm, C=1μm

[0256] C=Rz / 2+1-A×B×k···(Formula 5)

[0257] As a result, the following (Formula 6) is obtained.

[0258] 1=2 / 2+1-1×8×k···(Formula 6)

[0259] When solving (Formula 6), k=1 / 8.

[0260] Therefore, the condition under which a bump mark is confirmed, that is, the boundary condition for the occurrence of a bump mark, is expressed by the following (Equation 7).

[0261] C=Rz / 2+1-A×B / 8···(Formula 7)

[0262] Therefore, the condition for preventing bump marks from occurring can be expressed by the aforementioned (Formula 1).

[0263] Here, in order to illustrate the case where B=8 μm and Rz=2 μm of the condition (I), these are substituted into (Formula 1) to obtain the following (Formula 8).

[0264] C>2 / 2+1-A×8 / 8···(Formula 8)

[0265] This (Formula 8) is organized into the following (Formula 9).

[0266] C>2-A···(Formula 9)

[0267] The relationship (Equation 9) is shown in the figure Figure 17 .exist Figure 17 ,The shaded area indicates the area where no bump marks occur.

[0268] Thus, the inventors' research has identified areas where bump marks, which are the cause of reliability problems, do not occur. This allows for process design that takes into account variations in various parameters during mass production of semiconductor devices 1, thereby improving the mechanical reliability of semiconductor devices 1.

[0269] According to the semiconductor device 1 of this embodiment, when using gold-plated bump technology, which offers a high degree of design flexibility in thickness and bonding area, flip-chip bonding can reduce damage to the semiconductor element 10 and prevent short-circuit failures caused by bump marks on the first electrode of the semiconductor element 10. Furthermore, the adhesion and bonding strength between the semiconductor element 10 and the mounting substrate 20 can be improved. Consequently, when the semiconductor element 10 is mounted on the mounting substrate 20, failures such as damage or peeling of the first and second electrodes caused by the bonding of the metal bumps can be suppressed, thereby improving the mechanical reliability level. Consequently, a semiconductor device 1 with excellent long-term reliability can be obtained.

[0270] Furthermore, the semiconductor device 1 having such excellent long-term reliability is very suitable as a light source for miniaturized, high-current, and integrated vehicle applications.

[0271] (Implementation Method 2)

[0272] Next, regarding the semiconductor device 1A according to the second embodiment, Figure 18 as well as Figure 19 Provide explanation. Figure 18 It is a cross-sectional view of a semiconductor device 1A according to the second embodiment. Figure 19 1 is an enlarged cross-sectional view of the metal bump 30A of the semiconductor device 1A, and a diagram showing the height position dependency of the crystal grain size in the metal bump 30A. Figure 19 The vertical axis represents the height of the metal bump 30A, and the horizontal axis represents the crystal grain size of the metal bump 30A.

[0273] like Figure 18 As shown, a semiconductor device 1A according to Embodiment 2 includes a semiconductor element 10, a mounting substrate 20, and a metal bump 30A. The semiconductor element 10 and the mounting substrate 20 are bonded via the metal bump 30A. In this embodiment, the structures of the semiconductor element 10 and the mounting substrate 20 are the same as those in Embodiment 1. Furthermore, in this embodiment, the metal bump 30A, like the metal bump 30 in Embodiment 1, includes a first layer 31A located on the semiconductor element 10 side and a second layer 32A located on the mounting substrate 20 side. In this embodiment, the first layer 31A is in contact with the first electrode (first p-side electrode 12, first n-side electrode 13) of the semiconductor element 10.

[0274] The semiconductor device 1A according to the present embodiment differs from the semiconductor device 1 according to the first embodiment in the structure of the metal bump 30A.

[0275] Specifically, in the metal bump 30 of the first embodiment, the first layer 31 has a larger diameter than the second layer 32, but in the metal bump 30A of this embodiment, Figure 19 As shown, the first layer 31A has a smaller diameter than the second layer 32A.

[0276] Furthermore, in the metal bump 30 of the first embodiment, the average crystal grain size of the crystals constituting the first layer 31 is larger than the average crystal grain size of the crystals constituting the second layer 32. However, in the metal bump 30A of the present embodiment, the average crystal grain size of the crystals constituting the second layer 32A is larger than the average crystal grain size of the crystals constituting the first layer 31A. In other words, in the metal bump 30A of the present embodiment, the first layer 31A located on the semiconductor element 10 side has a smaller average crystal grain size than the second layer 32A located on the mounting substrate 20 side.

[0277] Furthermore, the width of the junction between the second layer 32A of the metal bump 30A and the second electrode (the second p-side electrode 22 and the second n-side electrode 23) of the mounting substrate 20 is greater than the width of the first layer 31A. The outer shape of the metal bump 30A is formed into a shape that gradually expands downward from the semiconductor element 10 side toward the mounting substrate 20 side.

[0278] In this manner, the semiconductor device 1A having the metal bump 30A having a cross-sectional shape that gradually expands downward has a large bonding area between the metal bump 30A and the second electrode of the mounting substrate 20, thereby increasing the bonding strength between the metal bump 30A and the mounting substrate 20. This improves the resistance of the metal bump 30A and the second electrode (the second p-side electrode 22 and the second n-side electrode 23) of the mounting substrate 20 to peeling when thermal stress occurs.

[0279] Next, a method for manufacturing the semiconductor device 1A according to the second embodiment will be described with reference to the drawings.

[0280] The manufacturing method of the semiconductor device 1A involved in embodiment 2 includes a first step of forming a semiconductor stacked structure 11 of a semiconductor element 10, a second step of forming a first electrode of the semiconductor element 10, a third step of forming a gold-plated film 30Y as a bump on the semiconductor element 10, and a fourth step of mounting the semiconductor element 10 on a mounting substrate 20 by flip-chip bonding.

[0281] The first step and the second step are the same as those in the first embodiment, and therefore their descriptions are omitted.

[0282] In this embodiment, regarding the third step of forming the gold plating film 30Y, Figures 20A to 20D process to proceed. Figures 20A to 20D 1 is a diagram showing a flow for forming the gold plating film 30Y on the semiconductor element 10 .

[0283] In this embodiment, the gold-plated film 30Y formed as bumps includes a first bump on the p-side corresponding to the first p-side electrode 12, and a second bump on the n-side corresponding to the first n-side electrode 13. The first bump is formed on the first p-side electrode 12, and the second bump is formed on the first n-side electrode 13. Furthermore, the gold-plated film 30Y is a gold-plated bump formed by a gold plating method. Specifically, the gold-plated film 30Y is a gold-plated bump having an average crystal grain size of 1 μm or less. The following describes a method for forming the gold-plated film 30Y.

[0284] After the second step, a photolithography protective material is first applied to cover the entirety of the cover electrodes 12d and 13d, and then heat treated at 140°C for about 20 minutes to harden the protective material. Figure 20AAs shown, openings 16a with a diameter of 25 μm are formed by photolithography in the protective material 16 in predetermined areas where the gold plating film 30Y is formed on the covering electrode 12d of the first p-side electrode 12 and the covering electrode 13d of the first n-side electrode 13.

[0285] Then, if Figure 20B As shown, gold is deposited from the opening 16a of the protective material 16 by electrolytic gold plating, thereby forming a gold-plated film 30Y. Specifically, the gold-plated film 30Y is simultaneously formed on the covering electrode 12d of the first p-side electrode 12 and on the covering electrode 13d of the first n-side electrode 13 exposed in the opening 16a of the protective material 16. As an example of the conditions for forming the gold-plated film 30Y, a non-cyanide Au plating solution with a gold plating liquid temperature of 50°C and a deposition rate of 0.5μm / min is used to form a gold-plated film 30Y with a height (thickness) of 5μm. The crystal structure of the gold-plated film 30Y immediately after formation is an aggregate of fine grains. In addition, the gold-plated film 30Y formed in this way has an average crystal grain size of 0.8μm and a hardness of approximately 1.9GPa.

[0286] Then, if Figure 20C As shown, the protective material 16 is removed with an organic solvent. Thus, a cylindrical gold plating film 30Y having a diameter of 25 μm and a height of 5 μm is formed in predetermined regions on the covering electrode 12 d of the first p-side electrode 12 and on the covering electrode 13 d of the first n-side electrode 13.

[0287] Then, if Figure 20D As shown, a portion of the seed film (Au / Ti) 12S on the oxide film 14 between the barrier electrode 12b of the first p-side electrode 12 and the barrier electrode 13b of the first n-side electrode 13 is removed. Specifically, first, the upper layer of the seed film 12S, that is, the Au layer, is removed using an iodine solution. Then, the lower layer of the seed film 12S, that is, the Ti layer, is removed using dilute hydrofluoric acid, exposing the oxide film 14. As a result, the seed film 12S can be separated into the seed layer 12c and the seed layer 13c, enabling pn electrode separation. In this way, the following semiconductor element 10 can be formed, in which a metal bump composed of a cylindrical gold-plated film 30Y with a diameter of 25 μm is formed on the first p-side electrode 12 and the first n-side electrode 13.

[0288] After the third step, the fourth step is performed, which is to mount the semiconductor element 10 on the mounting substrate 20 by flip chip bonding. Figures 21A and 21B The process shown is carried out. Figures 21A and 21B This figure shows a process of mounting the semiconductor element 10 on the mounting substrate 20 via the gold plating film 30Y.

[0289] First, a mounting substrate 20 for mounting the semiconductor element 10 is prepared. Specifically, a substrate 21 having a second p-side electrode 22 and a second n-side electrode 23 formed thereon is prepared as the mounting substrate 20. In this embodiment, the substrate 21 is a ceramic substrate made of an AlN sintered body. Furthermore, the second p-side electrode 22 and the second n-side electrode 23 are gold-plated films formed using a non-cyanide Au plating solution. Furthermore, a seed layer may be formed between each of the second p-side electrode 22 and the second n-side electrode 23 and the substrate 21 to separate the second p-side electrode 22 and the second n-side electrode 23.

[0290] The mounting substrate 20, with the second p-side electrode 22 and the second n-side electrode 23 formed thereon, was then heat treated in an ambient atmosphere at 200°C for 1 hour. This heat treatment coarsens the Au grains constituting the second p-side electrode 22 and the second n-side electrode 23. As a result, the second p-side electrode 22 and the second n-side electrode 23 become soft layers. Furthermore, the coarsened Au grains in the second p-side electrode 22 and the second n-side electrode 23 have a particle size of 8 μm.

[0291] Moreover, if Figure 21A As shown, a semiconductor element 10 with a gold plating film 30Y pre-formed as a bump is prepared. With the gold plating film 30Y facing the mounting substrate 20, the mounting machine's holding metal pipe 40 vacuum-adsorbs the semiconductor element 10. In this embodiment, a semiconductor element 10 measuring 800 μm long, 800 μm wide, and 100 μm thick is used.

[0292] Then, if Figure 21B As shown, the gold-plated film 30Y of the semiconductor element 10 is brought into contact with the second electrode (the second p-side electrode 22, the second n-side electrode 23) of the mounting substrate 20 while being heated at approximately 200°C. A load of approximately 30N is applied in a direction perpendicular to the mounting substrate 20 (the direction of the arrow X in the figure: the first direction) by holding it with a metal tube 40, and ultrasonic vibration is applied for 300ms in a direction horizontal to the mounting substrate 20 (the direction of the arrow Y in the figure: the second direction), thereby ultrasonically bonding the gold-plated film 30Y to the second electrode (the second p-side electrode 22, the second n-side electrode 23) of the mounting substrate 20.

[0293] Here, regarding the changes that occur when the gold plating film 30Y is bonded to the second electrode of the mounting substrate 20 by ultrasonic bonding to form the metal bump 30A, the following is explained. Figure 22 as well as Figures 23A to 23D Provide detailed explanation.

[0294] Figure 22 This is a timing diagram of ultrasonic bonding when the semiconductor element 10 is mounted on the mounting substrate 20 in the second embodiment. Figure 22In the figure, the horizontal axis represents time, and the vertical axis represents load. 0 ms represents the time before the process begins (or at the start of the process), 300 ms corresponds to the time during the ultrasonic bonding process in this embodiment (the ultrasonic bonding process time in Embodiment 1), and 400 ms corresponds to the ultrasonic bonding process time in this embodiment (the ultrasonic bonding process time in Embodiment 1 is extended by 100 ms of ultrasonic application time).

[0295] like Figure 22 As shown in the figure, after the bonding process between semiconductor element 10 and mounting substrate 20 begins (Step 1), the load is gradually increased for 100 ms. In Step 1, only the load is applied, without ultrasonic waves. Furthermore, between 100 ms and 400 ms (Step 2), ultrasonic waves are applied while maintaining a constant load. By performing the bonding process shown in this timing diagram, semiconductor element 10 and mounting substrate 20 are ultrasonically bonded, using metal film 30Y as a bump.

[0296] In this case, respectively Figures 23A to 23D The cross-section of the connection portion between the semiconductor element 10 and the mounting substrate 20, specifically, the connection portion between the gold plating film 30Y and the second electrode of the mounting substrate 20, is shown at 0ms, 100ms, 300ms, and 400ms after the start of the bonding process between the semiconductor element 10 and the mounting substrate 20. Figures 23A to 23D In FIG. 1 , among the second electrodes of the mounting substrate 20 , only the bonding portion on the second p-side electrode 22 is shown. The same applies to the bonding portion on the second n-side electrode 23 .

[0297] Figure 23A This is a diagram showing a cross section around the gold plating film 30Y before ultrasonic bonding in this embodiment. Figure 23A As shown, the Au crystal grains constituting the gold plating film 30Y have substantially the same particle size, and the gold plating film 30Y as a whole has a cylindrical shape with the same diameter.

[0298] Figure 23B It shows Figure 22 FIG. 1 shows the bonding state of the gold plating film 30Y and the second electrode of the mounting substrate 20 immediately after Step 1. Specifically, Figure 23B The figure shows a state where only a load is applied in a direction perpendicular to the mounting substrate 20 (direction of arrow X in the figure). The Au on the surface of the second electrode of the mounting substrate 20 and the Au on the gold plating film 30Y are in a pressure-bonded state, with a clear boundary between the interfaces being maintained.

[0299] Figure 23C It shows Figure 22FIG. 2 shows the bonding state of the gold plated film 30Y and the second electrode of the mounting substrate 20 in the middle of Step. 2 (about 300ms after the start of the process and 200ms after the start of the ultrasonic vibration). Figure 23C It shows a state in which a certain load of 30N is applied in a direction perpendicular to the mounting substrate 20 (in the direction of the arrow mark X in the figure), and ultrasonic vibration is applied in a direction horizontal to the mounting substrate 20 (in the direction of the arrow mark Y in the figure), and the semiconductor element 10 is bonded to the second electrode of the mounting substrate 20.

[0300] As a result, the gold-plated film 30Y is bonded to the second electrode of the mounting substrate 20 to form the metal bump 30A. The application of ultrasonic waves causes the gold-plated film 30Y to vibrate in a direction horizontal to the mounting substrate 20, heating the interface between the gold-plated film 30Y and the second electrode of the mounting substrate 20 through friction. This results in a solid-state bond between the metal bump 30 and the second electrode of the mounting substrate 20, resulting in their integration. At this point, the Au crystal grains in the surface layer of the second electrode of the mounting substrate 20 and the Au crystal grains in the gold-plated film 30Y partially lose their original shape and become integrated, losing their clear boundary between the gold-plated film 30Y and the second electrode of the mounting substrate 20.

[0301] Figure 23D 1 and 2 are diagrams showing the bonding state between the gold plating film 30Y and the second electrode of the mounting substrate 20 at the end of Step 2 (approximately 400 ms after the start of the process and 300 ms after the start of the ultrasonic vibration).

[0302] exist Figure 23D In the bonded state, at the bonding interface between the metal bump 30A and the second electrode of the mounting substrate 20, the Au crystal grains from the gold-plated film 30Y are integrated with the Au crystal grains from the second electrode of the mounting substrate 20. Furthermore, the Au crystal grains are integrated with each other, forming a second layer 32A as a layer of coarsened Au crystal grains. Furthermore, the portion of the gold-plated film 30Y that is not integrated with the Au crystal grains from the second electrode of the mounting substrate 20 forms the first layer 31A.

[0303] The second layer 32A is formed with coarsened Au crystal grains, so this layer is soft. On the other hand, the first layer 31A has no coarsened Au crystal grains, so this layer is hard.

[0304] Furthermore, the second layer 32A is formed by applying ultrasonic vibration in a direction horizontal to the mounting substrate 20 (the direction of the arrow Y in the figure), so it expands in the lateral direction compared to the first layer 31A. Figure 19 As shown, the metal bump 30A including the first layer 31A and the second layer 32A is formed in a shape that gradually expands downward and spreads toward the second layer 32B.

[0305] Measuring the widths of various portions of the formed metal bump 30A revealed that the width W1 of the junction surface between the first electrode of the semiconductor element 10 and the first layer 31A was 25 μm, and the width W2 of the junction surface between the second electrode of the mounting substrate 20 and the second layer 32A (the width of the second layer 32A) was 30 μm. In other words, the metal bump 30A exhibited a shape that gradually expanded downward, expanding toward the mounting substrate 20. Furthermore, measuring the grain size of the metal bump 30A revealed an average grain size of 0.8 μm for the first layer 31A and 8 μm for the second layer 32A.

[0306] Here, as Figure 19 As shown by the dashed line, a virtual bump 30AR is virtually defined as a cross section of the semiconductor element 10, the mounting substrate 20, and the metal bump 30A perpendicular to the mounting substrate 20, having a virtual rectangular cross section with the same area and height as the cross-sectional shape of the metal bump 30A. When comparing this virtual bump 30AR with the metal bump 30A in this embodiment, the width W2 of the second joint portion (joining surface) between the second electrode of the mounting substrate 20 and the second layer 32A of the metal bump 30A is longer than the length L of the base of the virtual bump 30AR. Therefore, the metal bump 30A is expected to have higher bonding strength than a virtual bump 30AR having the same cross-sectional area. Furthermore, the first layer 31A of the metal bump 30A has a width that is shorter than the length L of the base of the rectangle of the virtual bump 30AR.

[0307] Next, the bonding strength of the metal bump 30A in the semiconductor device 1A according to Embodiment 2 was measured, as described below. Specifically, the strength of the bond between the metal bump 30A and the mounting substrate 20 was measured as shear strength using the same method as in Embodiment 1.

[0308] In order to verify the effect of shear strength, Figure 29B The shear strength of the semiconductor device 100 of the comparative example shown was checked and found to be 5 kgF. In contrast, the shear strength of the semiconductor device 1A according to the second embodiment was 8 kgF.

[0309] Thus, the reason why the semiconductor device 1A of embodiment 2 has higher shear strength than the semiconductor device 100 of the comparative example can be considered as follows: the shape of the metal bump 30A is a shape that expands toward one side of the mounting substrate 20 and gradually unfolds downward, and the bonding area between the metal bump 30A and the mounting substrate 20 is increased.

[0310] Specifically, in Figure 29BIn the semiconductor device 100 of the comparative example shown, the diameter of the bonding surface between the second electrode of the mounting substrate 20 and the cylindrical metal bump 130 is 25 μm. In contrast, in the semiconductor device 1A involved in this embodiment, the diameter of the bonding surface between the second electrode of the mounting substrate 20 and the metal bump 30A is 30 μm.

[0311] Thus, in the semiconductor device 1A of this embodiment, the metal bump 30A has a downwardly flared shape that increases the bonding area with the mounting substrate 20. The increased bonding area between the metal bump 30A and the mounting substrate 20 increases the shear strength from 5 kgF to 8 kgF.

[0312] The semiconductor device 1A of this embodiment can achieve the same effects as the semiconductor device 1 of the first embodiment. Specifically, the semiconductor device 1A of this embodiment can reduce damage to the semiconductor element 10 when the semiconductor element 10 is mounted on the mounting substrate 20 by flip-chip bonding, thereby preventing short-circuit failures caused by bump marks on the first electrode of the semiconductor element 10. Furthermore, the adhesion and bonding strength between the semiconductor element 10 and the mounting substrate 20 can be improved. Consequently, when the semiconductor element 10 is mounted on the mounting substrate 20, failures such as damage or peeling of the first and second electrodes due to bonding with the metal bumps can be suppressed, thereby improving the mechanical reliability level. Consequently, a semiconductor device 1A with excellent long-term reliability can be obtained.

[0313] In this embodiment, the gold-plated film 30Y is not subjected to heat treatment (annealing). However, as in the first embodiment, the gold-plated film 30Y may be heat treated after formation. This allows both the grain size of the metal bump 30A layer on the semiconductor element 10 side to be coarsened, and the longer ultrasonic bonding time in this embodiment allows the grain size of the metal bump 30A layer on the mounting substrate 20 side to be coarsened. This increases the bonding area of both the top and bottom surfaces of the metal bump 30A. Consequently, the bonding strength between the semiconductor element 10 and the mounting substrate 20 can be further improved, resulting in a semiconductor device 1A with even higher bonding strength. Consequently, a semiconductor device 1A with even better long-term reliability can be achieved.

[0314] In this case, the layer of the portion of the metal bump 30A that is connected to the semiconductor element 10 may be the same as the second layer 32 of the metal bump 30A in the second embodiment.

[0315] (Implementation 3)

[0316] Next, the semiconductor device 1B according to the third embodiment is Figure 24 as well as Figure 25Provide explanation. Figure 24 It is a cross-sectional view of a semiconductor device 1B according to the third embodiment. Figure 25 1 is an enlarged cross-sectional view of the metal bump 30B of the semiconductor device 1B, and a diagram showing the height position dependency of the crystal grain size in the metal bump 30B. Figure 25 The vertical axis represents the height of the metal bump 30B, and the horizontal axis represents the crystal grain size of the metal bump 30B.

[0317] like Figure 24 As shown, a semiconductor device 1B according to the third embodiment includes a semiconductor element 10, a mounting substrate 20, and metal bumps 30B. The semiconductor element 10 and the mounting substrate 20 are bonded via the metal bumps 30B. In this embodiment, the structure of the semiconductor element 10 is the same as that of the first embodiment.

[0318] The semiconductor device 1B according to the present embodiment differs from the semiconductor device 1 according to the first embodiment in the structure of the metal bump 30B.

[0319] Specifically, in the first embodiment, the metal bump 30 is composed of two layers: a first layer 31 having a large diameter and a second layer 32 having a small diameter. However, the metal bump 30B of this embodiment is Figure 25 As shown, the semiconductor device 10 includes five layers, namely, a first layer 31 , a second layer 32 , a fifth layer 35 , a fourth layer 34 , and a third layer 33 , in this order from the semiconductor element 10 side.

[0320] Furthermore, the first layer 31, the second layer 32, the fifth layer 35, the fourth layer 34, and the third layer 33 are all substantially cylindrical in shape, and the diameters of the first layer 31, the third layer 33, and the fifth layer 35 are larger than the diameters of the second layer 32 and the fourth layer 34. Furthermore, the diameters of the first layer 31, the third layer 33, and the fifth layer 35 may be the same or different. Furthermore, the diameters of the second layer 32 and the fourth layer 34 may be the same or different.

[0321] In this embodiment, the first layer 31 is in contact with the first electrode (first p-side electrode 12, first n-side electrode 13) of the semiconductor element 10, and the second layer 32 is in contact with the first layer 31. Furthermore, the third layer 33 is in contact with the second electrode (second p-side electrode 22, second n-side electrode 23) of the mounting substrate 20, and the fourth layer 34 is in contact with the third layer 33. The fifth layer 35 is sandwiched between the second layer 32 and the fourth layer 34.

[0322] In the metal bump 30B, the average crystal grain size of the crystals constituting the first layer 31 is larger than the average crystal grain size of the crystals constituting the second layer 32. Furthermore, the average crystal grain size of the crystals constituting the third layer 33 is larger than the average crystal grain size of the crystals constituting the fourth layer 34. Furthermore, the average crystal grain size of the crystals constituting the fifth layer 35 is larger than the average crystal grain size of each of the crystals constituting the second layer 32 and the fourth layer 34.

[0323] In addition, the width of the joint between the first layer 31 of the metal bump 30B and the first electrode (the first p-side electrode 12, the first n-side electrode 13) of the semiconductor element 10 is larger than the width of the second layer 32, and the outer shape of the semiconductor element 10 side portion of the metal bump 30B formed by the first layer 31 and the second layer 32 becomes a gradually unfolding shape that expands from the mounting substrate 20 side to the semiconductor element 10 side.

[0324] In addition, the width of the joint between the third layer 33 of the metal bump 30B and the second electrode (the second p-side electrode 22, the second n-side electrode 23) of the mounting substrate 20 is larger than the width of the fourth layer 34, and the outer shape of the mounting substrate 20 side portion of the metal bump 30B formed by the third layer 33 and the fourth layer 34 becomes a gradually unfolding shape that expands from the semiconductor element 10 side to the mounting substrate 20 side.

[0325] Furthermore, the width of the fifth layer 35 located between the second layer 32 and the fourth layer 34 is larger than the widths of the second layer 32 and the fourth layer 34 adjacent thereto.

[0326] In this manner, the semiconductor device 1B having the metal bump 30B having a multi-step cross-sectional shape has a large bonding area between the metal bump 30B and the second electrode of the mounting substrate 20, and also a large bonding area between the metal bump 30B and the first electrode of the semiconductor element 10. This increases the bonding strength between the metal bump 30B and each of the first and second electrodes. This improves the resistance to peeling between the metal bump 30B and the semiconductor element 10 and the mounting substrate 20, specifically, the resistance to peeling between the metal bump 30B and the first and second electrodes, when thermal stress occurs.

[0327] Next, a method for manufacturing the semiconductor device 1B according to the third embodiment will be described with reference to the drawings.

[0328] The manufacturing method of the semiconductor device 1B involved in embodiment 3 includes: a first step of forming a semiconductor stacked structure 11 of a semiconductor element 10, followed by a second step of forming a first electrode of the semiconductor element 10, followed by a third step of forming a metal bump 30 on the semiconductor element 10, and then a fourth step of mounting the semiconductor element 10 on a mounting substrate 20 by flip-chip welding.

[0329] The first to third steps are the same as those in Embodiment 1, and their descriptions are omitted. The metal bumps 30 on the semiconductor element 10 side are referred to as first metal bumps, and the metal bumps 30C on the mounting substrate 20 side are referred to as second metal bumps.

[0330] Before the fourth step of mounting the semiconductor element 10 on the mounting substrate 20 , first, as the mounting substrate 20 for mounting the semiconductor element 10 , a mounting substrate 20 on which the metal bumps 30C are formed is prepared.

[0331] Regarding the method for manufacturing the mounting substrate 20 having the metal bumps 30C formed thereon, Figures 26A to 26E To explain. Figures 26A to 26E 1 and 2 are diagrams showing a process for producing the mounting substrate 20 on which the metal bumps 30C are formed.

[0332] First, if Figure 26A As shown, a substrate 21 having a second p-side electrode 22 and a second n-side electrode 23 formed thereon is prepared as a mounting substrate 20. In this embodiment, the substrate 21 is a ceramic substrate made of an AlN sintered body. Furthermore, the second p-side electrode 22 and the second n-side electrode 23 are gold-plated films formed using a non-cyanide Au plating solution. Although not shown, a seed layer is formed between each of the second p-side electrode 22 and the second n-side electrode 23 and the substrate 21. The seed layer is, for example, a laminated structure of an upper Au layer and a lower Ti layer.

[0333] Next, the substrate 21, on which the second p-side electrode 22 and the second n-side electrode 23 were formed, was heat treated in an air atmosphere at 200°C for 1 hour. This heat treatment coarsens the Au grains constituting the second p-side electrode 22 and the second n-side electrode 23. As a result, the second p-side electrode 22 and the second n-side electrode 23 become soft layers. Furthermore, the coarsened Au grains in the second p-side electrode 22 and the second n-side electrode 23 have a particle size of 8 μm.

[0334] Next, a photolithography protective material is applied so as to completely cover the second p-side electrode 22 and the second n-side electrode 23, and a heat treatment is performed at 140°C for about 20 minutes to harden the protective material. Figure 26B As shown, openings 24 a with a diameter of 25 μm are formed by photolithography in the protective material 24 in predetermined regions where the metal bumps 30C (second metal bumps) are formed on the second p-side electrode 22 and the second n-side electrode 23 .

[0335] Then, if Figure 26CAs shown, gold is deposited in the openings 24a of the protective material 24 by electrolytic gold plating, thereby forming a gold-plated film 30Z that becomes the metal bump 30C. Specifically, the gold-plated film 30Z is simultaneously formed on the second p-side electrode 22 and the second n-side electrode 23 exposed in the openings 24a of the protective material 24. As an example of the conditions for forming the gold-plated film 30Z, a non-cyanide Au plating solution with a plating temperature of 50°C and a deposition rate of 0.5 μm / min is used to form a gold-plated film 30Z with a height (thickness) of 5 μm. The crystalline structure of the gold-plated film 30Z immediately after formation is an aggregate of fine grains.

[0336] Then, if Figure 26D As shown, the protective material 24 is removed by an organic solvent. Thus, cylindrical metal bumps 30C having a diameter of 25 μm and a height of 5 μm are formed in predetermined regions on the second p-side electrode 22 and the second n-side electrode 23 .

[0337] Afterwards, although not shown, a portion of the seed layer on the substrate 21 between the second p-side electrode 22 and the second n-side electrode 23 is removed. In this embodiment, the seed layer comprises a stacked structure of Au and Ti layers. Therefore, the Au layer on the upper side of the seed layer is first removed with an iodine solution, followed by the Ti layer on the lower side of the seed layer with dilute hydrofluoric acid, exposing the substrate 21. This separates the seed layer, enabling pn separation of the second p-side electrode 22 and the second n-side electrode 23.

[0338] Then, if Figure 26E As shown, the mounting substrate 20, having the gold plating film 30Z formed thereon, is subjected to a heat treatment at 150°C for 1 hour in an ambient atmosphere. This heat treatment changes the grain size of the gold plating film 30Z, resulting in a metal bump 30C composed of two layers: a third layer 33 and a fourth layer 34 having the same composition but different grain sizes. In the metal bump 30C, the third layer 33 on the side closer to the substrate 21 has a larger grain size than the fourth layer 34 on the side farther from the substrate 21.

[0339] Then, through Figures 27A and 27B In the illustrated process, the semiconductor element 10 is mounted on the mounting substrate 20 by flip-chip bonding via the metal bumps 30 and 30C. Figures 27A and 27B 1 and 2 are diagrams showing a process of mounting the semiconductor element 10 on the mounting substrate 20 via the metal bumps 30 and 30C.

[0340] First, if Figure 27AAs shown, the mounting machine's holding metal tube 40 vacuum-adsorbs the semiconductor device 10, which has metal bumps 30 pre-formed thereon. At this point, the holding metal tube 40 vacuum-adsorbs the semiconductor device 10 so that the metal bumps 30 (first metal bumps) formed on the semiconductor device 10 face the metal bumps 30C (second metal bumps) formed on the mounting substrate 20. In this embodiment, a semiconductor device 10 measuring 800 μm long, 800 μm wide, and 100 μm thick is used.

[0341] Then, if Figure 27B As shown, while the second layer 32 of the metal bump 30 formed on the semiconductor element 10 is brought into contact with the fourth layer 34 of the metal bump 30C formed on the mounting substrate 20, they are heated at approximately 200°C, and a load of approximately 30N is applied in a direction perpendicular to the mounting substrate 20 (the direction of the arrow X in the figure: the first direction) by holding the metal tube 40, and ultrasonic vibration is applied for 300ms in a direction horizontal to the mounting substrate 20 (the direction of the arrow Y in the figure: the second direction), thereby ultrasonically bonding the second layer 32 of the metal bump 30 formed on the semiconductor element 10 and the fourth layer 34 of the metal bump 30C formed on the mounting substrate 20.

[0342] At this time, at the bonding interface between the second layer 32 of the metal bump 30 of the semiconductor element 10 and the fourth layer 34 of the metal bump 30C of the mounting substrate 20, the Au crystal grains of the second layer 32 and the fourth layer 34 are integrated. Furthermore, due to the integration of the Au crystal grains of both layers, a fifth layer 35 is formed as a layer with coarsened Au crystal grains. Since the fifth layer 35 is formed with coarsened Au crystal grains, it is soft.

[0343] Furthermore, the fifth layer 35 is formed by applying ultrasonic vibration in a direction horizontal to the mounting substrate 20 (in the direction of arrow Y in the figure), and therefore expands more laterally than the second layer 32 and the fourth layer 34. In other words, the width of the fifth layer 35 is greater than the width of the second layer 32 and the width of the fourth layer 34. Thus, a multi-stepped metal bump 30B is formed for connecting the semiconductor element 10 to the mounting substrate 20.

[0344] The results of measuring the widths of the various parts of the formed metal bump 30B show that the width of the joint surface between the first electrode and the first layer 31 formed on the semiconductor element 10 is 30 μm, the width of the second layer 32 is 25 μm, the width of the joint surface between the second electrode and the third layer 33 formed on the mounting substrate 20 is 30 μm, the width of the fourth layer 34 is 25 μm, and the width of the fifth layer 35 is 28 μm.

[0345] The metal bump 30B formed in this way has an expanding and gradually unfolding shape both on the semiconductor element 10 side and on the mounting substrate 20 side. The fifth layer 35, which is the joint between the metal bump 30 formed on the semiconductor element 10 and the metal bump 30C formed on the mounting substrate 20, is also a shape that is wider than the second layer 32 and the fourth layer 34.

[0346] The thickness of each portion of the metal bump 30B is: the first layer 31 is 1 μm, the second layer 32 is 2 μm, the third layer 33 is 1 μm, the fourth layer 34 is 2 μm, and the fifth layer 35 is 2 μm.

[0347] Here, as Figure 25 As shown by the dashed line, in a cross section of the semiconductor element 10, mounting substrate 20, and metal bump 30B perpendicular to mounting substrate 20, a virtual bump 30BR is virtually defined having a virtual rectangular cross section with the same area and height as the cross-sectional shape of metal bump 30B. In this case, the length L of the base of the rectangle of virtual bump 30BR is 27 μm. Comparing this virtual bump 30BR with metal bump 30B in this embodiment, the width W1 of the first joint portion, which is the junction (joining surface) between the first electrode of semiconductor element 10 and the first layer 31 of metal bump 30B, is longer than the length L of the base of virtual bump 30BR. Furthermore, the width of the second joint portion, which is the junction between the second electrode of mounting substrate 20 and the third layer 33 of metal bump 30B, is also longer than the length L of the base of the rectangle of virtual bump 30BR. Therefore, it can be expected that metal bump 30B has a higher bonding strength than a virtual bump 30BR of the same cross-sectional area. Furthermore, the width of the second layer 32 and the fourth layer 34 of the metal bump 30 is shorter than the length L of the base of the rectangle of the dummy bump 30BR.

[0348] Next, the following describes the measurement of the bonding strength of the metal bump 30B in the semiconductor device 1B according to Embodiment 3. Specifically, the strength of the bond between the metal bump 30B and the mounting substrate 20 is measured by shear strength using the same method as in Embodiment 1.

[0349] As a result, the shear strength of the semiconductor device 1B according to this embodiment is 8 kgF. Figure 29B The shear strength of the semiconductor device 100 of the comparative example shown is 5 kgF. Therefore, it can be seen that the semiconductor device 1B according to the present embodiment has improved shear strength compared with the semiconductor device 100 of the comparative example.

[0350] Thus, the reasons why the semiconductor device 1B of embodiment 3 has higher shear strength than the semiconductor device 100 of the comparative example are as follows: first, the metal bump 30B is in a gradually unfolded shape not only on the mounting substrate 20 side but also on the semiconductor element 10 side; second, the fifth layer 35 of the joint between the metal bump 30 formed on the semiconductor element 10 and the metal bump 30C formed on the mounting substrate 20 is also in an unfolded shape, thereby increasing the bonding area of each joint that is prone to peeling.

[0351] By increasing the bonding strength of the metal bumps 30B, the resistance to electrode peeling during thermal stress is improved. Therefore, the semiconductor device 1B of this embodiment is particularly suitable for use as a light source for automotive applications. In the future, semiconductor devices such as LEDs will become smaller, have higher currents, and be more integrated, and the stress caused by heat is expected to become more pronounced.

[0352] As described above, the semiconductor device 1B according to this embodiment can achieve the same effects as the semiconductor device 1 according to the first embodiment. Specifically, the semiconductor device 1B according to this embodiment reduces damage to the semiconductor element 10 when the semiconductor element 10 is mounted on the mounting substrate 20 by flip-chip bonding, thereby preventing short-circuit failures caused by bump marks on the first electrode of the semiconductor element 10. Furthermore, the adhesion and bonding strength between the semiconductor element 10 and the mounting substrate 20 can be improved. Consequently, when the semiconductor element 10 is mounted on the mounting substrate 20, failures caused by bonding with metal bumps, such as damage or peeling of the first and second electrodes, can be reduced, thereby improving the mechanical reliability level. Consequently, a semiconductor device 1B with excellent long-term reliability can be obtained.

[0353] (Variation)

[0354] As mentioned above, the semiconductor device according to the present disclosure has been described based on Embodiments 1 to 3. However, the present disclosure is not limited to the above-mentioned embodiments.

[0355] For example, in the above embodiments, LED chips are shown as semiconductor elements 10. However, this is not limiting and other solid-state light-emitting elements such as laser elements may also be used. Furthermore, semiconductor elements 10 are not limited to light-emitting elements. For example, power semiconductor elements such as compound field-effect transistors made of GaN, SiC, or the like may also be used.

[0356] In addition, the present disclosure includes forms obtained by implementing various modifications conceived by those skilled in the art for each embodiment, as well as forms achieved by arbitrarily combining the constituent elements and functions in each embodiment without departing from the spirit of the present disclosure.

[0357] The semiconductor device according to the present disclosure has excellent long-term reliability and is applicable to various equipment such as in-vehicle applications.

[0358] Explanation of symbols

[0359] 1, 1A, 1B semiconductor devices

[0360] 10 semiconductor components

[0361] 11 Semiconductor stacked structure

[0362] 11a base plate

[0363] 11b n-type semiconductor layer

[0364] 11c Active layer

[0365] 11d p-type semiconductor layer

[0366] 12 1st p-side electrode

[0367] 12a Reflective electrode

[0368] 12b, 13b barrier electrodes

[0369] 12c, 13c seed layer

[0370] 12d, 13d covering electrodes

[0371] 12S seed film

[0372] 13 1st n-side electrode

[0373] 13a Ohmic contact layer

[0374] 14 Oxide film

[0375] 15, 16, 24 protective materials

[0376] 16a, 24a opening

[0377] 20 Mounting base plate

[0378] 21 substrate

[0379] 22 2nd p-side electrode

[0380] 23 2nd n-side electrode

[0381] 30, 30A, 30B, 30C metal bumps

[0382] 30X, 30Y, 30Z gold-plated film

[0383] 30R, 30AR, 30BR virtual bumps

[0384] 31, 31A, 1st floor

[0385] 31a Transitional Area

[0386] 32, 32A, 2nd floor

[0387] 33 3rd floor

[0388] 34 4th floor

[0389] 35 5th floor

[0390] 40 Metal tube for holding

[0391] 50 Metal Table

[0392] 60 Shear Sensor

Claims

1. A semiconductor device, The semiconductor device comprises: mounting substrate; and The semiconductor element is arranged on the mounting substrate via metal bumps. The semiconductor element has a semiconductor stacked structure and a first electrode. The mounting substrate has a second electrode. The first electrode is composed of a stacked structure including a barrier electrode. The metal bump, which is arranged at a position overlapping with the barrier electrode in the thickness direction, is a single-form component, and includes a second layer in contact with the second electrode, a first layer located on the opposite side of the second electrode, and a transition region located between the first layer and the second layer. The average crystal grain size of the crystals constituting the second layer is larger than the average crystal grain size of the crystals constituting the first layer, The average grain size of the transition region gradually approaches the average grain size of the second layer from the first layer side toward the second layer side. The first layer is located at a position spaced apart from the second electrode.

2. The semiconductor device according to claim 1, The semiconductor stacked structure includes a substrate, and a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer stacked in order from the substrate side.

3. A semiconductor device, The semiconductor device comprises: mounting substrate; and The light emitting diode chip is arranged on the mounting substrate via metal bumps made of gold. The light-emitting diode chip has a semiconductor stacked structure and a first electrode. The semiconductor stacked structure includes a substrate, and a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer stacked in sequence from the substrate side. The first electrode is arranged in contact with the second conductive type semiconductor layer. The mounting substrate comprises a ceramic substrate and a second electrode. The metal bump includes a second layer in contact with the second electrode and a first layer located on the opposite side of the second electrode. The average crystal grain size of the crystals constituting the second layer is larger than the average crystal grain size of the crystals constituting the first layer, The first layer is located at a position separated from the second electrode, The maximum height roughness of the interface between the first layer and the second layer is equal to or greater than the average crystal grain size of the first layer.

4. The semiconductor device according to claim 3, The average crystal grain size of the second layer is equal to or larger than the maximum height roughness of the interface.

5. The semiconductor device according to any one of claims 1 to 4, In the cross-section of the semiconductor element, the mounting substrate, and the metal bump in a direction perpendicular to the mounting substrate, when the cross-sectional area of the metal bump is set to S and the height of the metal bump is set to H, the width of the joint between the second layer connected to the second electrode and the second electrode, i.e., the second joint, is longer than S / H.

6. The semiconductor device according to claim 5, The width of the first layer is shorter than the S / H.

7. The semiconductor device according to any one of claims 1 to 4, The bonding interface between the second layer and the second electrode is integrated.

8. The semiconductor device according to any one of claims 2 to 4, The first electrode includes a metal film, which is arranged in contact with the second conductive type semiconductor layer and reflects light from the active layer.

9. The semiconductor device according to any one of claims 1 to 4, The barrier electrode is made of Ti.

10. The semiconductor device according to any one of claims 1 to 4, The mounting substrate is a ceramic substrate formed of a sintered body of AlN.

11. The semiconductor device according to any one of claims 1 to 4, The thickness of the second layer is 1 μm.

12. The semiconductor device according to claim 5, The thickness of the second layer is 1 μm.

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