Memory device interface and method

Abstract

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems, and methods include a buffer interface to convert high-speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower and wider DRAM interface can be configured to substantially match the capacity of a narrower, higher-speed host interface. In some examples, the buffer interface can be configured to provide multiple subchannel interfaces, each subchannel interface coupled to one or more regions within a memory structure and configured to facilitate data recovery in the event of a failure of a portion of the memory structure. Selected example memory devices, systems, and methods include individual DRAM dies, or a stack of one or more DRAM dies coupled to a buffer die.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 809,281, filed on February 22, 2019, U.S. Provisional Application No. 62 / 816,731, filed on March 11, 2019, and U.S. Provisional Application No. 62 / 826,422, filed on March 29, 2019, the entireties of which are incorporated herein by reference. Background Art

[0003] The present description generally relates to example structures and methods for interfacing a first memory interface to multiple respective second memory interfaces to interface with one or more memory devices; and more particularly to a memory system operable to perform such reallocation, including a buffer (in some examples, a buffer die or a buffer assembly). In some examples, the buffer may be configured to perform the reallocation to allow the second memory interface to be wider than the first interface and to operate at a slower data rate than the first interface. The described buffer may be used in a variety of configurations of memory interfaces, may be used with a variety of memory structures, including individual memory devices, any of a plurality of configurations of stacked memory devices, or other arrangements of a plurality of memory devices.

[0004] A memory device is a semiconductor circuit that provides electronic data storage for a host system (e.g., a computer or other electronic device). A memory device may be volatile or nonvolatile. Volatile memory requires power to maintain data, and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Nonvolatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (e.g., phase change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM)), etc.

[0005] The host system typically includes a host processor, a first amount of main memory (e.g., typically volatile memory such as DRAM) for supporting the host processor, and one or more storage systems (e.g., typically non-volatile memory such as flash memory) in addition to or independent of the main memory that provide additional storage for retaining data.

[0006] A memory system, such as a solid-state drive (SSD), may include a memory controller and one or more memory devices, including several dies or logical units (LUNs). In some instances, each die may include several memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller may include an interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) through a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may receive commands or operations associated with memory operations or instructions (e.g., read or write operations for transferring data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory device and the host device, erase operations for erasing data from the memory device), perform drive management operations (e.g., data migration, garbage collection, block reclamation), etc. from the host system.

[0007] It would be desirable to provide improved main memory, such as DRAM memory. Features of the desired improved main memory include, but are not limited to, higher capacity, higher speed, and lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0009] Figure 1A A system including a memory device according to some example embodiments is described.

[0010] Figure 1B Another system including a memory device according to some example embodiments is described.

[0011] Figure 2 An example memory device is described according to some example embodiments.

[0012] Figure 3 A buffer die in block diagram form is illustrated according to some example embodiments.

[0013] Figure 4 Another memory device according to some example embodiments is described.

[0014] Figure 5A Another memory device according to some example embodiments is described.

[0015] Figure 5B Another memory device according to some example embodiments is described.

[0016] Figure 5CAnother memory device according to some example embodiments is described.

[0017] Figure 5D Another memory device according to some example embodiments is described.

[0018] Figure 6 Another memory device according to some example embodiments is described.

[0019] Figure 7 Another memory device according to some example embodiments is described.

[0020] Fig. 8A Another memory device according to some example embodiments is described.

[0021] Figure 8B Another memory device according to some example embodiments is described.

[0022] Fig. 9A DRAM die configurations according to some example embodiments are described.

[0023] Fig. 9B Another DRAM die configuration is illustrated according to some example embodiments.

[0024] Fig. 9C Another DRAM die configuration is illustrated according to some example embodiments.

[0025] Fig. 10A An example method flow diagram is illustrated according to some example embodiments.

[0026] Fig. 10B Another example method flow diagram is illustrated in accordance with some example embodiments.

[0027] Fig.11A Example embodiments illustrating alternative configurations and functionality of memory systems.

[0028] Fig. 11B Explain the instance failure condition Fig.11A memory system.

[0029] Fig.12 illustrate Fig.11A An example configuration of a portion of a memory system.

[0030] Fig.13 An example method flow diagram is illustrated according to some example embodiments.

[0031] Fig.14 Example method flow diagrams are described according to other example embodiments.

[0032] Fig.15 Example embodiments depicting alternative configurations and functionality of memory systems.

[0033] Fig.16 An example block diagram illustrating an information handling system in accordance with some example embodiments. DETAILED DESCRIPTION

[0034] The following description and the accompanying drawings sufficiently illustrate the specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process and other changes. Portions and features of some embodiments may be included in other embodiments or replaced by those of other embodiments. The embodiments set forth in the claims encompass all available equivalents of those claims.

[0035] Various embodiments are described below that incorporate a memory system in which an external memory interface operates to transfer data at a first rate, but the memory operates internally at a second data rate that is slower than the first data rate. In the examples described below, this operation may be accomplished by using a buffer interface that communicates with an external memory interface (which may be, for example, a host interface), and rerouting the data connections (DQs) of the external interface to a greater number of data connections that communicate with one or more memory devices (and / or one or more memory banks) that operate at a slower clock rate than the clock rate of the external memory interface.

[0036] In embodiments as described below, the buffer interface may exist in a separate die located between the host (or other) interface and one or more memory dies. In an example embodiment, the buffer die (or other form of buffer interface) may include a host physical interface that includes connections for at least one memory channel (or subchannel), including command / address connections and data connections. Control logic in the buffer interface may be implemented to reallocate the connections for the memory channels to at least two (or more) memory subchannels, the connections extending to the DRAM physical interface of each subchannel, each subchannel physical interface including command / address connections and data connections. The DRAM physical interface of each subchannel is then connected to one or more memory dies.

[0037] Also described below is a stacked memory structure as may be used in one of the described memory systems, in which multiple memory dies may be laterally offset from one another and connected to another memory die, a logic die, or another structural connection / device by wire bonding connections. As described below, in some examples, one or more of the memory dies may include a redistribution layer (RDL) to distribute contact pads near the edges of the die to facilitate the described wire bonding.

[0038] In some embodiments, a buffer interface as described above may be used to reallocate a host (or other) interface including a DQ, including a data connection, a plurality of ECC connections, and a plurality of parity connections. In some such embodiments, the buffer interface may be used in combination with one or more memory devices configured to allocate data, ECC, and parity connections within the memory device(s) in a manner that prevents failures within portions of a memory array or data path associated with a corresponding DRAM physical interface, as discussed in more detail below. Such fault protection may be implemented in a manner that improves the reliability of a memory system, generally similar to techniques known in the industry such as Chipkill (a trademark of IBM) or Single Device Data Correction (SDDC) (a trademark of Intel). Such fault protection may be implemented to recover from multi-bit errors, such as those affecting a memory region (e.g., a subarray) or data and / or control paths to a subarray region (i.e., a subchannel of a memory), as will be apparent to one skilled in the art having the benefit of this disclosure.

[0039] Figure 1A An electronic system 100 is shown having a processor 106 coupled to a substrate 102. In some examples, the substrate 102 may be a system motherboard, or in other examples, the substrate 102 may be coupled to another substrate, such as a motherboard. The electronic system 100 also includes first and second memory devices 120A, 120B. The memory devices 120A, 120B are also shown as being supported by the substrate 102 adjacent to the processor 106, but are depicted as being coupled to a secondary substrate 124 in an example configuration. In other examples, the memory devices 120A, 120B may be directly coupled to the same substrate 102 as the processor 106.

[0040] Memory devices 120A, 120B, each including a buffer assembly, here in the example form of a buffer die 128, are coupled to a secondary substrate 124. Although the term "buffer die" is used herein to refer to a buffer assembly, any such "buffer die" described herein may be in the form of an assembly including, for example, one or more semiconductor dies or other devices and / or other discrete components (whether or not packaged together) that provide the described functionality. Therefore, unless otherwise expressly indicated in a particular use, the term "buffer die" as used herein also refers to a "buffer assembly" and / or a "buffer device". The memory devices 120A, 120B may be individual dies, or in some cases may each include a respective stack of memory devices (in this example, DRAM dies 122). For the purposes of the present description, the memory devices 120A, 120B will be described in an example configuration of a stacked memory device. Additionally, the memory devices 120A, 120B will be described in one example configuration in which the devices are dynamic random access memory (DRAM) dies 122A, 122B each coupled to a secondary substrate 124. Other types of memory devices may be used in place of DRAM, including, for example, FeRAM, phase change memory (PCM), 3D XPoint TM In some cases, a single memory device may include one or more memory dies using a first memory technology (e.g., DRAM) and a second memory die using a second memory technology different from the first memory technology (e.g., SRAM, FeRAM, etc.).

[0041] A DRAM die stack 122 is shown in block diagram form in FIG1 . Other figures in the following description show more details of the die stack and various stacking configurations. Figure 1A In the example of FIG. 1 , several wire bonds 126 are shown coupled to the DRAM die stack 122. Additional circuitry (not shown) is included on or within the secondary substrate 124. The additional circuitry completes the connection between the DRAM die stack 122, through the wire bonds 126, to the buffer die 120. Selected examples may include through silicon vias (TSVs) instead of wire bonds 126, as will be described in more detail in subsequent figures.

[0042] Substrate wiring 104 is shown coupling memory device 120A to processor 106. Figure 1BIn the example of , an additional memory device 120B is shown. Although two memory devices 120A, 120B are shown for the depicted example, a single memory structure may be used, or a number of memory devices greater than two may be used. The examples of memory devices as described in the present disclosure provide increased capacity of close memory with increased speed and reduced manufacturing costs.

[0043] Figure 1B An electronic system 150 is shown having a processor 156 coupled to a substrate 152. The system 150 also includes first and second memory devices 160A, 160B. Figure 1A In comparison, Figure 1B In the embodiment, the first and second memory devices 160A, 160B are directly connected to the same substrate 102 as the processor 156 without any intermediate substrate or interposer. Figure 1A This configuration provides additional speed and component reduction compared to the previous example. Figure 1A Similar to the example of , a buffer assembly or buffer die 168 is shown adjacent to the DRAM die stack 162. Wire bonds 166 are shown as an example interconnect structure, however other interconnect structures such as TSVs may also be used.

[0044] Figure 2 Show and from Figure 1B The electronic system 200 is similar to the memory device 118A or 118B of the embodiment of the present invention. The electronic system 200 includes a buffer die 202 coupled to a substrate 204. The electronic system 200 also includes a DRAM die stack 210 coupled to the substrate 204. Figure 2 In the example of DRAM die stack 210, specifically, individual die in DRAM die stack 210 are laterally offset from one or more vertically adjacent die, and in the depicted example, each die is laterally offset from two vertically adjacent die. As an example, the die can be staggered in at least one staircase configuration. Figure 2 The example of shows two different staggered orientations in a stair-step stack 210 of DRAM dies. In the illustrated double stair configuration, the exposed surface portion 212 of each die is used for several wirebond interconnects.

[0045] A plurality of wire bond interconnects 214, 216 are shown from the dies in the DRAM die stack 210 to the substrate 204. Additional conductors (not shown) on or within the substrate 204 further couple the wire bond interconnects 214, 216 to the buffer die 202. The buffer die 202 is shown coupled to the substrate 204 using one or more solder interconnects 203, such as an array of solder balls. Several substrate solder interconnects 206 are further shown on the bottom side of the substrate 204 to further transmit signals and data from the buffer die into the substrate 102 and ultimately to the processor 106, as shown in FIG. Figure 1BAs shown in .

[0046] Figure 3 Show and from Figure 2 202. A host device interface 312 and a DRAM interface 314 are shown. Additional circuitry components of the buffer die 300 may include controller and switching logic 316; reliability, availability, and serviceability (RAS) logic 317; and built-in self-test (BIST) logic 318. Communication from the buffer die 300 to the DRAM die stack is indicated by arrow 320. Communication from the buffer die 300 to the host device is indicated by arrows 322 and 324. Figure 3 , arrow 324 represents communication from the command / address (CA) pin, and arrow 322 represents communication from the data (DQ) pin 322. The example numbers of CA pins and DQ pins are provided as examples only, as the host device interface may have substantially more or less of either or both CA and DQ pins. The number of pins of either desired type may vary depending on the width of the interface channel, the provision of additional bits (e.g., ECC bits), and many other variables. In many examples, the host device interface will be an industry standard memory interface (either clearly defined by a standards setting organization, or a de facto standard adopted by the industry).

[0047] In one example, all CA pins 324 act as a single channel and all data pins 322 act as a single channel. In one example, all CA pins serve all data pins 322. In another example, CA pins 324 are subdivided into multiple sub-channels. In another example, data pins 322 are subdivided into multiple sub-channels. A configuration may include a portion of CA pins 324 serving a portion of data pins 322. In a specific example, 8 CA pins serve 9 data (DQ) pins as a sub-combination of CA pins and data (DQ) pins. Multiple sub-combinations such as the 8CA pin / 9 data pin example may be included in a memory device.

[0048] It is common in computing devices to couple DRAM memory to a substrate (e.g., a motherboard) using jacks, such as dual in-line memory (DIMM) jacks. However, for some applications, the physical layout of the DRAM chips and jack connectors on a DIMM device can take up a lot of space. It may be desirable to reduce the amount of space used for DRAM memory. In addition, communication through the jack interface is slower and less reliable than connecting directly to the motherboard using solder connectors. The additional components of the jack interface increase the cost of the computing device.

[0049] Using some of the example memory device examples in the present disclosure, the physical size of the memory device can be reduced for a given DRAM memory capacity. Speed ​​is improved due to direct connection to the substrate, and cost is reduced by eliminating the jack component.

[0050] In operation, the possible data speed from the host device may be higher than the speed that the interconnect components to the DRAM die, such as traces, TSVs, wire bonds, etc., can handle. The addition of the buffer die 300 (or other form of buffer assembly) allows for buffering of fast data exchanges from the host device. Figure 3 In an example, the host interface 312 is configured to operate at a first data speed. In one example, the first data speed can match the speed that the host device is capable of delivering.

[0051] In one example, the DRAM interface 314 is configured to operate at a second data speed that is slower than the first data speed. In one example, the DRAM interface 314 is configured to be slower and wider than the host interface 312. In operation, the buffer die can convert the high-speed data interaction on the host interface 312 side into a slower and wider data interaction on the DRAM interface 314 side. In addition, as further described below, in order to maintain a data throughput that is at least approximate to the data throughput of the host interface, in some examples, the buffer assembly can reallocate the connectors of the host interface to multiple memory sub-channels associated with the corresponding DRAM interface. The slower and wider DRAM interface 314 can be configured to substantially match the capacity of the narrower, higher-speed host interface 312. In this way, more limited interconnect components to the DRAM die, such as traces, TSVs, wire bonding, etc., are able to handle the capacity of the interaction supplied from the faster host device. Although one example host interface to the buffer die 300 is shown (having both CA pins and DQ pins), the buffer die 300 may include multiple host interfaces that are each mapped by the buffer die 300 to separate data paths of multiple DRAM interfaces in a similar manner.

[0052] In one example, host device interface 312 includes a first number of data paths, and DRAM interface 314 includes a second number of data paths that is greater than the first number of data paths. In one example, circuitry in buffer die 300 maps data and commands from the first number of data paths to the second number of data paths. In this configuration, the second number of data paths provides a slower and wider interface, as described above.

[0053] In one example, the command / address pins 324 of the host device interface 312 include a first number of command / address paths, and on the corresponding DRAM interface 314 side of the buffer die 300, the DRAM interface 314 includes a second number of command / address paths that is larger than the first number of command / address paths. In one example, the second number of command / address paths is twice the first number of command / address paths. In one example, the second number of command / address paths is more than twice the first number of command / address paths. In one example, the second number of command / address paths is four times the first number of command / address paths. In one example, the second number of command / address paths is eight times the first number of command / address paths.

[0054] In one example, a given command / address path on the DRAM interface 314 side of the buffer die 300 communicates with only a single DRAM die. In one example, a given command / address path on the DRAM interface 314 side of the buffer die 300 communicates with multiple DRAM dies. In one example, a given command / address path on the DRAM interface 314 side of the buffer die 300 communicates with 4 DRAM dies. In one example, a given command / address path on the DRAM interface 314 side of the buffer die 300 communicates with 16 DRAM dies.

[0055] In one example, the data pins 322 of the host device interface 312 include a first number of data paths, and on the corresponding DRAM interface 314 side of the buffer die 300, the DRAM interface 314 includes a second number of data paths that is greater than the first number of data paths. In one example, the second number of data paths is twice the first number of data paths. In one example, the second number of data paths is more than twice the first number of data paths. In one example, the second number of data paths is four times the first number of data paths. In one example, the second number of data paths is eight times the first number of data paths.

[0056] In one example, a data path on the DRAM interface 314 side of the buffer die 300 communicates with only a single DRAM die. In one example, a given data path on the DRAM interface 314 side of the buffer die 300 communicates with multiple DRAM dies. In one example, a given data path on the DRAM interface 314 side of the buffer die 300 communicates with 4 DRAM dies. In one example, a given data path on the DRAM interface 314 side of the buffer die 300 communicates with 16 DRAM dies.

[0057] In one example, the host interface 312 includes command / address pins 324 and data pins 322 of different speeds. In one example, the data pins 322 of the host interface are configured to operate at 6.4 Gb / s. In one example, the command / address pins 324 of the host interface are configured to operate at 3.2 Gb / s.

[0058] In one example, the DRAM interface 314 of the buffer die 300 slows down and widens communications from the host interface 312 side of the buffer die 300. In one example where a given command / address path from the host interface 312 maps to two command / address paths on the DRAM interface 314, the speed at the host interface is 3.2 Gb / s and the speed at the DRAM interface 314 is 1.6 Gb / s.

[0059] In one example where a given data path from the host interface 312 is mapped to two data paths on the DRAM interface 314, the speed at the host interface is 6.4 Gb / s and the speed at the DRAM interface 314 is 3.2 Gb / s, where each data path communicates with a single DRAM die in the DRAM die stack. In one example where a given data path from the host interface 312 is mapped to four data paths on the DRAM interface 314, the speed at the host interface is 6.4 Gb / s and the speed at the DRAM interface 314 is 1.6 Gb / s, where each data path communicates with four DRAM dies in the DRAM die stack. In one example where a given data path from the host interface 312 is mapped to eight data paths on the DRAM interface 314, the speed at the host interface is 6.4 Gb / s and the speed at the DRAM interface 314 is 0.8 Gb / s, where each data path communicates with 16 DRAM dies in the DRAM die stack.

[0060] In one example, a pulse amplitude modulation (PAM) protocol is used to communicate on the DRAM interface 314 side of the buffer die 300. In one example, the PAM protocol includes PAM-4, although other PAM protocols are within the scope of the present invention. In one example, the PAM protocol increases data bandwidth. In one example where a given data path from the host interface 312 is mapped to four data paths on the DRAM interface 314, the PAM protocol is used, the speed at the host interface is 6.4Gb / s, and the speed at the DRAM interface 314 is 0.8Gb / s, where each data path communicates with four DRAM dies in the DRAM die stack. In one example where a given data path from the host interface 312 is mapped to eight data paths on the DRAM interface 314, the PAM protocol is used, the speed at the host interface is 6.4Gb / s, and the speed at the DRAM interface 314 is 0.4Gb / s, where each data path communicates with 16 DRAM dies in the DRAM die stack.

[0061] The number of pins required to communicate between the buffer die 300 and the example 16 DRAM dies varies depending on the number of command / address paths on the DRAM interface 314 side of the buffer die 300 and the number of DRAM dies coupled to each data path. The following table shows several non-limiting examples of pin counts and corresponding command / address path configurations.

[0062]

[0063]

[0064] The number of pins required to communicate between the buffer die 300 and the example 16 DRAM dies varies depending on the number of data paths on the DRAM interface 314 side of the buffer die 300 and the number of DRAM dies coupled to each data path. The following table shows several non-limiting examples of pin counts and corresponding data path configurations.

[0065]

[0066] As described below in selected examples, the number of pins in the above table can be coupled to the DRAM die in the DRAM die stack in several different ways. In one example, wire bonding is used to couple from the pins to several DRAM die. In one example, TSVs are used to couple from the pins to several DRAM die. Although wire bonding and TSVs are used as examples, other communication pathways other than wire bonding and TSVs are also within the scope of the present disclosure.

[0067] Figure 4Another example of a memory device 400 is shown. The memory device 400 includes a buffer die 402 coupled to a substrate 404. The memory device 400 also includes a DRAM die stack 410 coupled to the substrate 404. Figure 4 In the example of FIG. 4 , DRAM die stacks 410 are staggered in at least one staircase configuration. Figure 4 The example of FIG. 4 shows two different staggered orientations in a stepped stack 410 of DRAM dies. Figure 2 Similar to the configuration of , in the illustrated step configuration, the exposed surface portion 412 is used for several wire bonding interconnects.

[0068] A plurality of wire bond interconnects 414, 416 are shown from the dies in the DRAM die stack 410 to the substrate 404. Additional conductors (not shown) on or within the substrate 404 further couple the wire bond interconnects 414, 416 to the buffer die 402. The buffer die 402 is shown coupled to the substrate 404 using one or more solder interconnects, such as an array of solder balls. Several substrate solder interconnects 406 are further shown on the bottom side of the substrate 404 to further transfer signals and data from the buffer die into the motherboard and ultimately to the host device.

[0069] exist Figure 4 In the example of FIG. 4 , multiple wire bond interconnects 414, 416 are connected in series on multiple stacked DRAM dies. In selected examples, a single wire bond can drive loads in more than one DRAM die. In this example, the wire bond interconnects can be as shown in FIG. Figure 4 . In one example, a single wire bond may be connected in series to four DRAM dies. In one example, a single wire bond may be connected in series to eight DRAM dies. In one example, a single wire bond may be connected in series to sixteen DRAM dies. Other numbers of serially connected DRAM dies are also within the scope of the present invention. Additionally, the DRAM interface may be CA connected to a first number of DRAM dies, and the DRAM interface may be DQ connected to a second number of DRAM dies that is different from the first number.

[0070] Figure 5A Another example of a memory device 500 is shown. The memory device 500 includes a buffer die 502 coupled to a substrate 504. The memory device 500 also includes a DRAM die stack 510 coupled to the substrate 504. Figure 5A In the example of FIG. 5 , the DRAM die stack 510 is staggered in at least one staircase configuration. The example of FIG. 5 shows two different staggering directions in the DRAM die staircase stack 510. In the illustrated staircase configuration, the exposed surface portion 512 is used for several wire bonding interconnects.

[0071] A plurality of wire bond interconnects 514, 516 are shown from the dies in the DRAM die stack 510 to the substrate 504. Additional conductors (not shown) on or within the substrate 504 further couple the wire bond interconnects 514, 516 to the buffer die 502. The buffer die 502 is shown coupled to the substrate 504 using one or more solder interconnects, such as an array of solder balls. Several substrate solder interconnects 506 are further shown on the bottom side of the substrate 504 to further transmit signals and data from the buffer die into the motherboard and ultimately to the host device.

[0072] exist Figure 5A In one example, the buffer die 502 is at least partially located below the DRAM die stack 510. In one example, the encapsulant 503 at least partially surrounds the buffer die 502. Figure 5A The example of further reduces the area footprint of the memory device 500. In addition, the interconnect distance between the DRAM die stack 510 and the buffer die 502 is reduced.

[0073] Figure 5B Another example of a memory device 520 is shown. The memory device 520 includes a buffer die 522 coupled to a substrate 524. The memory device 520 also includes a DRAM die stack 530 coupled to the substrate 524. A plurality of wire bond interconnects 534, 536 are shown from the die in the DRAM die stack 530 to the substrate 524. Figure 5B In an example, multiple wire bonding interconnects 534, 536 are connected in series on multiple stacked DRAM dies. In an example, a single wire bonding can be connected in series to four DRAM dies. In an example, a single wire bonding can be connected in series to eight DRAM dies. In an example, a single wire bonding can be connected in series to sixteen DRAM dies. Other numbers of series DRAM dies are also within the scope of the present invention.

[0074] Figure 5C A top view of a memory device 540 is shown that is similar to memory devices 500 and 520. Figure 5C In the example of , the buffer die 542 is shown coupled to the substrate 544 and completely underneath the DRAM die stack 550. Figure 5D A top view of a memory device 560 similar to memory devices 500 and 520 is shown. Figure 5D560 . Buffer die 562 is coupled to substrate 564 and partially located below a portion of first DRAM die stack 570 and second DRAM die stack 572. In one example, shorter DRAM die stacks provide shorter interconnect paths and higher manufacturing yields. In selected examples, for these reasons, it may be desirable to use multiple shorter DRAM die stacks. One tradeoff of multiple shorter DRAM die stacks is a larger area footprint of memory device 560.

[0075] Figure 6 Another example of a memory device 600 is shown. The memory device 600 includes a buffer die 602 coupled to a substrate 604. The memory device 600 also includes a DRAM die stack 610 coupled to the substrate 604. Figure 6 In the example of FIG. 6 , DRAM die stacks 610 are staggered in at least one staircase configuration. Figure 6 The example of FIG. 6 shows four staggers in two different staggered directions in a DRAM die staircase stack 610 . Figure 6 The DRAM die stack 610 in FIG. 1 includes 16 DRAM dies, although the present invention is not limited thereto. Similar to the other ladder configurations shown, in FIG. Figure 6 In FIG. 6 , the exposed surface portion 612 is used for a number of wire bonding interconnects.

[0076] A plurality of wire bond interconnects 614, 616 are shown from the dies in the DRAM die stack 610 to the substrate 604. Additional conductors (not shown) on or within the substrate 604 further couple the wire bond interconnects 614, 616 to the buffer die 602. The buffer die 602 is shown coupled to the substrate 604 using one or more solder interconnects, such as an array of solder balls. Several substrate solder interconnects 606 are further shown on the bottom side of the substrate 604 to further transfer signals and data from the buffer die into the motherboard and ultimately to the host device.

[0077] Figure 7 Another example of a memory device 700 is shown. The memory device 700 includes a buffer die 702 coupled to a substrate 704. The memory device 700 also includes a DRAM die stack 710 coupled to the substrate 704. Figure 7 In the example of FIG. 7 , the DRAM die stacks 710 are staggered in at least one staircase configuration. Figure 7 The example of FIG. 7 shows four staggers in two different staggered directions in a DRAM die stepped stack 710 . Figure 7 The DRAM die stack 710 in FIG. 7 includes 16 DRAM dies, although the present invention is not limited thereto. Similar to the other ladder configurations shown, in FIG. Figure 7 In FIG. 7 , the exposed surface portion 712 is used for a number of wire bonding interconnects.

[0078] A plurality of wire bond interconnects 714, 716 are shown from the dies in the DRAM die stack 710 to the substrate 704. Additional conductors (not shown) on or within the substrate 704 further couple the wire bond interconnects 714, 716 to the buffer die 702. The buffer die 702 is shown coupled to the substrate 704 using one or more solder interconnects, such as an array of solder balls. Several substrate solder interconnects 706 are further shown on the bottom side of the substrate 704 to further transfer signals and data from the buffer die into the motherboard and ultimately to the host device.

[0079] exist Figure 7 In one example, the buffer die 702 is at least partially located below the DRAM die stack 710. In one example, the encapsulant 703 at least partially surrounds the buffer die 702. Figure 7 The example of further reduces the area footprint of the memory device 700. In addition, the interconnect distance between the DRAM die stack 710 and the buffer die 702 is reduced.

[0080] Fig. 8A Another example of a memory device 800 is shown. The memory device 800 includes a buffer die 802 coupled to a substrate 804. The memory device 800 also includes a DRAM die stack 810 coupled to the substrate 804. Fig. 8A In the example of FIG. 8 , the DRAM die stack 810 is vertically aligned. Fig. 8A The DRAM die stack 810 in FIG. 8 includes 8 DRAM dies, although the present invention is not limited thereto.

[0081] A plurality of TSV interconnects 812 are shown passing through and communicating with one or more dies in the DRAM die stack 810 to the substrate 804. Additional conductors (not shown) on or within the substrate 804 further couple the TSVs 812 to the buffer die 802. The buffer die 802 is shown coupled to the substrate 804 using one or more solder interconnects, such as an array of solder balls. Several substrate solder interconnects 806 are further shown on the bottom side of the substrate 804 to further transmit signals and data from the buffer die into the motherboard and ultimately to the host device.

[0082] Figure 8B Another example of a memory device 820 is shown. The memory device 820 includes a buffer die 822 coupled to a substrate 824. The memory device 820 also includes a DRAM die stack 830 coupled to the substrate 824. Figure 8B In the example of , the DRAM die stack 830 is vertically aligned. Figure 8BThe DRAM die stack 830 in FIG. 8 includes 16 DRAM dies, although the present invention is not limited thereto.

[0083] A plurality of TSV interconnects 832 are shown passing through and communicating with one or more dies in the DRAM die stack 830 to the substrate 824. Additional conductors (not shown) on or within the substrate 824 further couple the TSVs 832 to the buffer die 822. The buffer die 822 is shown coupled to the substrate 824 using one or more solder interconnects, such as an array of solder balls. Several substrate solder interconnects 826 are further shown on the bottom side of the substrate 824 to further transmit signals and data from the buffer die into the motherboard and ultimately to the host device.

[0084] Fig. 9A A block diagram is shown of a single DRAM die 900 that may be included in a DRAM die stack according to any of the examples in the present disclosure. Fig. 9A 9, a DRAM die 900 includes a storage area 902 containing an array of memory cells. A first data I / O stripe 904 is shown as passing from a first side 901 to a second side 903 of the DRAM die 900. In one example, contacts may be formed at the edge of the first data I / O stripe 904 on one or both sides 901, 903 of the first data I / O stripe 904. The contacts may be connected to wire bonds as described in the above examples. In other examples, TSVs may be coupled to the first data I / O stripe 904 at sides 901, 903, or other locations along the first data I / O stripe 904.

[0085] Fig. 9A 906. In one example, the second data I / O stripe 906 is substantially the same as the first data I / O stripe 904. Fig. 9A In the example of , each data I / O stripe includes 36 contacts for connecting to wire bonds on either side. In the case of two data I / O stripes, each with two sides, DRAM die 900 includes connections for 144 wire bonds or TSVs.

[0086] Fig. 9A Further shown in FIG. 1 is a command / address strip 910. In the example shown, the command / address strip 910 includes 30 contacts for connecting to wire bonds or TSVs. In one example, one or more of the DRAM dies may include a redistribution layer that redistributes the connections of one or more of the data I / O strips 904, 906, 910 to a second location for wire bonding, such as to one or more rows of wire bond pads along the edge of the die (as depicted with respect to the example wire bonded stacked configuration discussed earlier herein). Fig. 9AIn the data stripes 904 and 906 (and in Figures 9B to 9C The instance number of DQ contacts in a data stripe of an instance of FIG. 1 and the instance number of command / address contacts in such an instance are relative examples only, and different numbers of contacts of either or both signal types may be used in any of the described instances.

[0087] Fig. 9B A block diagram showing a stack 920 of four DRAM dies that may be included in a DRAM die stack according to any of the examples in the present disclosure. Fig. 9B 920. In the embodiment of the present invention, each die in the stack 920 includes a storage area 922 containing an array of memory cells. A first data I / O stripe 924 is shown as passing from a first side 921 to a second side 923 of the stack 920. In one example, contacts can be formed on the edge of the first data I / O stripe 924 on one or both sides 921, 923 of the first data I / O stripe 924. The contacts can be connected to wire bonds as described in the above examples. In other examples, TSVs can be coupled to the first data I / O stripe 924 at sides 921, 923 or other locations along the first data I / O stripe 924.

[0088] Fig. 9B 926. In one example, the second data I / O stripe 926 is substantially the same as the first data I / O stripe 924. Fig. 9B In the example of , each data I / O stripe includes 9 contacts for connecting to wire bonds on either side. With two data I / O stripes and two sides, each DRAM die in stack 920 includes connections for 36 wire bonds or TSVs. In one example, all four dies in stack 920 are driven by a single data path as described in the above example.

[0089] Fig. 9B 1. Further shown in FIG. 1 is a command / address strip 930. In the example shown, the command / address strip 930 includes 30 contacts for connecting to wire bonds or TSVs.

[0090] Fig. 9C A block diagram showing a stack 940 of four DRAM dies that may be included in a DRAM die stack according to any of the examples in the present disclosure. Fig. 9C940. In the embodiment of the present invention, each die in the stack 940 includes a storage area 942 containing an array of memory cells. A single data I / O stripe 944 is shown as passing from a first side 941 to a second side 943 of the stack 940. In one example, contacts can be formed on the edge of the data I / O stripe 944 on one or both sides 941, 943 of the data I / O stripe 944. The contacts can be connected to wire bonds as described in the above examples. In other examples, TSVs can be coupled to the data I / O stripe 944 at sides 941, 943 or other locations along the first data I / O stripe 944.

[0091] exist Fig. 9C In the example of , a single data I / O stripe 944 includes 18 contacts for connecting to wire bonds on either side. In the two-sided case, each DRAM die in stack 940 includes connections for 36 wire bonds or TSVs. In one example, all four dies in stack 940 are driven by a single data path as described in the above example.

[0092] Fig. 9C 1. Further shown in FIG. 1 is a command / address strip 950. In the example shown, the command / address strip 950 includes 30 contacts for connecting to wire bonds or TSVs.

[0093] Fig. 10A A block diagram of an operating method according to an embodiment of the present invention is shown. In operation 1002, data is exchanged between a processor and a buffer die at a first data speed. In operation 1004, data is exchanged between the buffer die and a stack of DRAM dies at a second speed that is slower than the first speed. Operation 1006 explains that exchanging data between the buffer die and the stack of DRAM dies includes exchanging data through a plurality of wire bonds. Fig. 10B A block diagram of another method of operation according to an embodiment of the present invention is shown. In operation 1010, data is exchanged between a processor and a buffer die at a first data speed. In operation 1012, data is exchanged between the buffer die and a vertically aligned DRAM die stack at a second speed that is slower than the first speed. Operation 1014 explains that exchanging data between the buffer die and the vertically aligned DRAM die stack includes exchanging data through a plurality of through silicon vias (TSVs) in the vertically aligned DRAM die stack.

[0094] Fig.11A An example memory system 1100 is depicted that includes a buffer as may be implemented, for example, in a buffer die. For ease of describing the example embodiments, the buffer will be described in an example configuration of a buffer die 1102. However, the described buffer functionality may be implemented in another structure, such as as part of another device, such as a memory device or an interposer.

[0095] The memory system 1100 may include a series of configurations of a memory structure 1104. In some examples, the memory structure 1104 may be a single memory device; but in many examples, multiple memory devices will be included. Where multiple memory devices are used, the memory devices may be stacked on top of each other, and / or may each be placed directly on a supporting substrate, in some cases a printed circuit board (PCB) such as, for example, a system motherboard or a memory module such as a dual in-line memory module (DIMM). In some examples, the buffer die 1102 and the individual memory devices of the memory structure 1104 may be configured so that one or more of the memory devices may be mounted directly to the buffer die 1102 (or other buffer structure); and in some examples, a stack of memory dies may be mounted on (or above) the buffer die. As an example configuration, a system according to the present description may be implemented as a dual-rank DDR5 RDIMM having, for example, 32-40 individual DRAM dies, forming two channels.

[0096] The buffer die 1102 is configured in conjunction with the memory structure 1104 to avoid data loss in the event of a failure of a portion of the memory array or a control and / or data path associated with a corresponding portion of the array. To implement this functionality, the first interface 1106, referred to in this description as the "host interface," will include additional DQ connections for ECC / parity bits, as described above. For example, Figure 3 The host interface of the buffer die is depicted as having 36 DQs: 32 DQs carrying data and 4 DQs carrying ECC / parity bits. Fig.11A In the example of , this host interface is extended, for example, by 4 additional DQs carrying ECC / parity bits.

[0097] Fig.11A An alternative embodiment of the CA interface is also depicted (which, as discussed earlier herein, may include one or more chip select "CS" paths). In some example systems, the CA path may be single-clocked (compared to DQ, which is typically dual-clocked), and thus Figure 3 The number of CA paths may be increased compared to an example of a DDR5 device. For example, in some systems, the system host may interface with an intermediate device to drive and buffer the interface connection (such as, for example, a registered clock driver (RCD) used with some DDR5 devices). In selected embodiments, a buffer die 1102 as described herein may be placed between this intermediate buffer device and the memory structure; but in other examples, the buffer die 1102 may be implemented in place of this intermediate driving and buffering device (such as, for example, an RCD).

[0098] The number of CA paths required for the memory physical interface may vary depending on the addressing method of the memory (and, for example, the use of chip select pins (if any) when operating the memory structure). Therefore, the example number of CA paths (including any CS pins) is illustrative only, and the number of CA paths on the host physical interface or the memory physical interface may be different from the example number identified herein. In some example configurations, just as the DQ connections are mapped from four DQs to 16 DQs (in the depicted example), the CA paths may be mapped to an increased number of CA paths. Because there are paths for CS, clock, etc., not all control / address paths need to be doubled. In one example, the CA paths at the host interface may be mapped to (for example only) from 30 CA paths to 120 CA paths, which are arranged into 4 DRAM CA PHY interfaces, each with 30 CA paths. And in the example configuration, each DRAM CA PHY may be configured to drive four DRAM loads; so that the described configuration will therefore be able to serve 16 DRAM dies.

[0099] exist Fig.11A In the example of the embodiment of the present invention, the buffer die 1102 is configured to reallocate the example 40 DQ data paths of the host PHY 1106 to a plurality of DRAM DQ PHYs, each DRAM DQ PHY being configured to communicate with at least one corresponding region of the memory structure 1104, wherein each DRAM DQ PHY is wider than a corresponding portion of the host interface and is configured in accordance with the embodiment of the present invention. Figure 3 The host PHY 1106 may be configured to operate at a slower data transfer speed than the corresponding portion of the host interface in a manner similar to that described. The description of multiple DRAM PHYs is not intended to represent a specific physical structure, but rather a reallocation of pin groups from the host interface to a larger number of pins at the memory interface. In order to maintain the ability to recover from errors affecting multiple pins at the host PHY 1106, in some instances it will be desirable to maintain substantially separate sub-channels through the buffer die 1102 and to the memory interface, and then to substantially independent operable logical regions (or "slices") of the memory structure, as described below with respect to Fig.12 Therefore, the pin connections used to communicate data signals (DQ) with the memory structure of each such sub-channel are discussed herein as DRAM PHY.

[0100] In some cases, the host PHY 1106 may represent a channel or sub-channel of a memory bus. For example, in some embodiments, the host PHY 1106 may be configured according to the DDR5 specification promulgated by JEDEC; and by way of example only, an instance of the host PHY 1106 may represent an independent memory channel according to that standard.

[0101] In the depicted example, the buffer die 1102 reallocates the 40 DQ pins of the host interface to multiple memory physical interfaces, such as Figure 3 Discussed. Fig.11A The various functionalities present in the buffer die are not depicted. However, the buffer die 1102 should be understood to include controller and switching logic structures; reliability, availability, and serviceability (RAS) structures; and built-in self-test (BIST) structures; all as described with respect to Figure 3 1. As discussed above with respect to the buffer die 300 of FIG. 110 (although it will be apparent to one skilled in the art having the benefit of this disclosure that the structure may be adapted to accomplish different data path reallocations of the depicted embodiment). In the depicted example, the host PHY 1106 may, for example, operate at a data transfer rate of approximately 6.4 Gb / s at the DQ; while the DRAM DQ PHY may include 160 pins that (collectively) operate at a data transfer rate of approximately 1.6 Gb / s. Similar transfer rates would apply to the CA pins.

[0102] In addition, the pins of the memory physical interface will be allocated to at least 10 or multiples of 10 sub-arrays of the memory structure 1104. In one example, every 4 sequential DQs of the host physical interface 1106 will be mapped to a corresponding DRAM DQ PHY functionally indicated by 16 DQs, identified by example at 1108 (as indicated by arrows 1122A-J), which extends to multiple sub-arrays. In other examples, DQs may be remapped in addition to groups of four sequential DQs. In some examples, alternative DQs may be remapped in place of four sequential DQs (i.e., for example, a selected number of "even" DQs may be remapped separately from a selected number of "odd" DQs). In other examples, as discussed later herein, the pins of the memory physical interface may be allocated to different numbers of sub-arrays (and / or different numbers of memory structure slices). For example, as discussed with respect to Fig.15 As discussed, the DQs of the memory physical interface can be distributed to nine sub-arrays (slices) of the memory structure.

[0103] As previously discussed, in many examples, each respective DRAM DQ PHY (and data path 1108) will operate at a slower data transfer rate than the data transfer rate of the host physical interface 1106. For example, each DQ data path 1108 of the respective memory physical interface may operate at one-quarter the data transfer rate of the host physical interface 1106 (1.6 Gb / s in the example discussed above). In other examples, every 4 sequential DQ data paths of the host physical interface 1106 may be mapped to a DRAM DQ PHY having 8 DQs (instead of 16, as depicted) and operating at, for example, one-half the data transfer rate of the host PHY instead of one-quarter, as in Fig.11A Examples of various potential implementations of host interface pin reallocation include the following (the example pin rates are merely illustrative and provided as examples for purposes of illustration; as actual pin rates in various implementations may be substantially slower or faster than the examples provided):

[0104]

[0105]

[0106] Each DRAM DQ PHY will be coupled to multiple sub-arrays (as indicated by example at 1110A-D, 1112A-D) through respective data paths 1108. In general, a DRAM bank may include thousands of rows of memory cells, and will include multiple sub-arrays. Each sub-array will include some subset of the bank rows; and will include row buffers and sense amplifiers for the subset of rows. The allocation of the host physical interface 40 DQ pins across groups of at least 10 sub-channels, and the allocation of each sequential group of 4 host physical interface DQs to a separate sub-channel (as indicated by arrows 1122A-J), will allow for the successful allocation of the host physical interface DQ pins to a single sub-channel, even in the case of a failed sub-channel or sub-array (e.g. Fig. 11B 1) (or a failed "slice" of a memory device, as discussed below), also allows for data to be recovered by using eight ECC / parity bits at the host interface, in a manner that will be apparent to those skilled in the art having the benefit of this disclosure. These data recovery mechanisms are common in systems utilizing ChipKill or SDDC, as discussed earlier herein. This recovery from a failed slice (or other memory region) may be performed under the control of the host. In some examples, individual memory dies and / or buffers 1102 may also include internal ECC functionality to recover from local single-bit or double-bit errors, as known to those skilled in the art.

[0107] Each DRAM DQ PHY 1108 may be coupled to multiple memory device columns and / or sub-arrays in multiple memory device banks (and / or across multiple memory devices and / or memory device banks). Fig.11A , as generally indicated by 1114, 1116, 1118, 1120, each of the depicted overlapping levels of identified sub-memory bank arrays (i.e., sub-arrays) may be located in a different memory device, or in a different memory device column and / or memory bank within the memory structure 1104.

[0108] Fig.12 An example memory system 1200 is depicted, which is depicted in a block diagram representation, showing the Figures 11A-11B 1200. The depicted example structure of memory system 1200 is a logical representation rather than a physical representation.

[0109] For purposes of this description, the term "slice" will be used to refer to a portion of ten (or other number) logical regions of a memory array (in this example, a sub-array) coupled to corresponding DRAM DQ PHYs having corresponding data paths 1108, combined CA paths, and read / write data paths (DQ) coupled to I / O circuits for that portion of the array. Fig.12 Ten memory slices 1202A-J are depicted, each formed by a respective group of memory cells (in this example, subarrays) as indicated at 1204A-J, with associated data paths 1206A-J. Figure 3 Although not discussed in the embodiments of Fig.12 1108, but at least the relevant portion of the DRAM CA PHY interface will be allocated to each sub-array to provide addressing for each of the sub-arrays. In various embodiments, the depicted memory slices 1202A-J may be formed on one memory die, or may be distributed across multiple memory dies. In selected examples, individual host PHY DQs will be distributed (through respective sub-array data paths 1108) to each memory cell (die, column, or bank) within the respective slice.

[0110] Each subarray includes a plurality of array pads, as indicated by way of example in slice 1202A at 1202A-1 through 1202A-4. The number of memory cells in each array pad, and the associated number of word lines and data lines, is a matter of design choice. Thus, the configuration of each array pad may be based on design considerations such as, for example, process node (with respect to feature size), the associated size and configuration of each memory cell, and the desired dimensions of the local word lines within the array pad, etc. In many examples, the array pads will extend between rows of sense amplifiers on opposite sides of the array pad (in the column direction) and will have sub-word line decoders on at least one, if not both, remaining sides of the array pad (in the row direction). In some examples, physically adjacent array pads (separated in some cases by sub-word line decoders) may form a bank.

[0111] One example configuration includes the depicted 10 memory slices 1202A-J formed on a single memory die; and according to that configuration, a representative global word line 1208 (of multiple global word lines) is depicted as extending across the depicted slices and to multiple array pads within each slice. It will be apparent to those skilled in the art having the benefit of this disclosure that the global word line 1208 will carry higher order terms across the associated sub-arrays and pads. In many examples, the sub-word line decoders will use additional terms to drive local word lines within each array pad or array pad pair (or other memory cell grouping) along the global word line.

[0112] In the depicted example, each subarray includes a large number of individually addressable pads. As depicted, each subarray includes a matrix array of pads, including four pads along the row direction (i.e., in the direction of the global word line 1208), and 16 array pads along the column direction (perpendicular to the direction of the global word line 1208). The memory structure can be configured so that each memory page includes a multiple of 10 array pads. The array pads of a page are not necessarily physically aligned with each other, as in Fig.12 1204A-J. In this example configuration, each of the 10 depicted subarrays 1204A-J includes 4 array pads configured such that each subarray can be configured to provide a corresponding 8-byte 80-byte prefetch (64 bytes of data, 8 bytes of parity bits, and 8 bytes of ECC bits). In, for example, regarding Fig. 11BIn the example of the described example, where each slice is distributed across four tiers, each tier will provide one quarter of the prefetch. For example, where each tier in a slice includes a portion of a respective memory device, each memory device will provide 2B of the 8B prefetch per slice. Other examples may have different configurations and be adapted to prefetch different numbers of bytes (examples 60 bytes or 100 bytes). In many desired examples, the bytes prefetched will be a multiple of 10.

[0113] The ability to configure the memory system 1200 to provide, for example, approximately 4kB page sizes in a DIMM is believed to facilitate having a significantly smaller power envelope than that required, for example, for conventional DRAM DIMM configurations. According to the present description, 4kB pages may be allocated across one, two, or four (or more) memory dies. In conventional DRAM DIMM configurations, 20-40kB page sizes would be common, which would require substantially more power than that required to access smaller pages according to the described configuration. Current thinking is that a 40 DRAM die DIMM configured with approximately 4kB pages may use 40% to 60% less power than a conventional configuration using 20-40kB pages.

[0114] One consideration in implementing the techniques described and implemented herein is to configure slices (or other memory cell groupings and associated circuitry) to minimize shared failure points. For example, in a conventional DRAM memory device, a sub-wordline driver may extend between a pair of array pads and drive a local wordline within each adjacent pad. However, in the example system 1200 as described above, including 4 parity bits and 4 ECC / parity bits associated with 32 data bits (at the host physical interface), only failures associated with 4 such data bits can be recovered. In the example memory system, if physically adjacent pads are driven by a shared sub-wordline driver, then a failure of the shared sub-wordline driver may affect multiple array pads and thus cause unrecoverable errors. Therefore, in this structure, it would be advantageous to have a separate sub-wordline driver for each array pad in order to minimize shared failure points. Similarly, common control circuits within a subarray (or similar memory cell grouping), such as those that control addressing and timing, may be provided independently for each array pad. For example, sub-word line drivers across sub-array boundaries do not present the same problem, since the column decoder circuits for the individual sub-arrays (ie, in the respective slices) will prevent selection of data from adjacent array pads across those boundaries.

[0115] In other examples, slices of pages may be distributed across different devices or banks within a device. However, needing to activate more devices / banks to read or write a page of data will typically require activating multiple global word lines and thus may require power beyond the desired level.

[0116] Fig.13 Flowchart illustrating an example method of operation of a memory system. In method 1300, data and control / address signals are received at a first interface of a buffer structure at a first data rate, as indicated at 1302. In some examples, the data pins will include a plurality of data pins coupled to carry data bits, a plurality of data pins coupled to carry ECC / parity bits, and a plurality of data pins coupled to carry parity bits for use in ECC operations. The data pins of the first interface are mapped to a plurality of memory sub-channel interfaces that can operate at a second data rate that is slower than the first data rate of the first interface, as indicated at 1304. Reference Figures 11A-11B Examples of such reallocation of data pins in the buffer structure are discussed. In some desirable examples, the first interface will be mapped to at least 10 subchannel interfaces. Additionally, in some examples, each data pin of the first interface will be mapped to at least two data pins of the memory subchannel interface. In various examples, the reallocation may be performed at least in part by firmware including instructions stored in a machine-readable storage device, such as one or more non-volatile memory devices.

[0117] As a result of the reallocation, as indicated at 1306, a signal may then be communicated from each subchannel interface to a corresponding slice of the memory device (also as described with reference to FIG. Figures 11A-11B In some examples, each slice of a memory device may include multiple array pads.

[0118] Fig.14 Flowchart illustrating an alternative example method 1400 of operation of a memory system. In method 1400, as indicated at 1402, a signal is received at a host physical interface including command / address (CA) pins and data pins (DQ), wherein the DQ includes a plurality of ECC / parity pins.

[0119] As indicated at 1404, at least a DQ of the host physical interface is mapped to at least two sub-channel memory interfaces, wherein each sub-channel memory interface includes a CA pin and a DQ, wherein the DQ includes a plurality of ECC pins and a plurality of parity pins. As discussed with respect to method 1300, at least some portion of the reallocation may be performed by firmware, including instructions stored in a machine-readable storage device forming part of the controller and switching logic 316, as described with reference to Figure 3 Discussed.

[0120] Then, as indicated at 1406, a signal may be communicated from the sub-channel memory interface to a corresponding region located in one or more memory dies, where the received signal is divisible by 10. In some examples, each region may be a sub-array of a memory die (although the number of regions may be distributed across multiple memory dies). And in some examples, each region will include multiple array pads.

[0121] Fig.15 Alternative configurations and functionality of the memory system 1500 are disclosed. As an example, the memory system 1500 includes Figure 3 11 . Thus, except for the description herein of the host interface PHY 1502 and buffer device 1504 implementations similar to those described in connection with the interface 322 and buffer die 300 of FIG. 11 , the memory system 1500 further incorporates a memory structure 1506 having some of the features discussed generally with reference to the memory structure 1104 of FIG. 11 . Fig.15 Aside from the differences discussed, the discussion of the structure and operation of memory system 1100 with reference to FIGS. 11-13 applies to memory system 1500 and will not be repeated here.

[0122] As in Fig.15 As can be seen in FIG. 11 , host PHY 1502 includes (as an example) 36 DQ pins, thereby providing a data interface of approximately 6.4 Gb / s. The 36 DQ pins may include, for example, 32 DQ pins allocated to data and four DQ pins allocated to ECC / parity bits for associated data. Thus, example host PHY 1502 differs from host PHY 1104 of FIG. 11 in that only four DQs are included for ECC / parity bits (eight DQs are allocated for them in host PHY 1104). As described below, these 36 DQs will be remapped to nine slices (or more, such as multiples of nine) within the memory structure.

[0123] In other examples, the host PHY may include only CA pins and data DQ pins (i.e., no ECC / parity DQs). For example, 32 data DQs may be used, such as in a system consistent with the previously identified JEDEC's DDR5 standard. In some cases, those 32 host PHY DQs may then each be remapped to multiple DQs at the DRAM DQ PHY (as discussed in detail above) and applied to eight slices (or more, such as multiples of eight) within the memory structure.

[0124] In the depicted example, each group of four DQ bits is reallocated to 16 DQs at the DRAM DQ PHY interface, generally indicated at 1508 and by arrows 1510A-I; which in turn are connected to respective slices 1512A-I of the memory structure 1506. In some examples, each consecutive four DQ bits will be reallocated to the 16 DQs communicated to the respective slices. In other examples, other allocations are possible; for example, a certain number of even bits / pins at the host PHY 1502 may be reallocated to the first slice 1510A-I of the memory structure, while the adjacent odd bits / pins may be reallocated to the second slice. In other examples, a greater or lesser number of bits of the host PHY 1502 may be reallocated to the respective slices 1510A-I. In the depicted example, the data DQs would be remapped to multiple pins in eight slices (1510A-I), while the ECC / parity bits DQs would be remapped to the ninth slice.

[0125] As with memory system 1100, memory system 1500 may be implemented with a smaller page size, such as a 4K page size, allocated across one or more memory dies. For example, in the depicted embodiment, the 4K page size may be allocated across 36 array pads. Additionally, as discussed with respect to memory system 1100, in some examples, each subarray may include four array pads for a page, such that each subarray provides 8 bytes of data for a 72-byte prefetch (64 bytes of data and 8 bytes of ECC / parity bits). However, as described with respect to memory system 1100, a memory system similar to memory system 1500 may be configured to implement other page sizes and / or prefetch sizes.

[0126] In an example system, a memory slice (whether or not containing one or more memory devices) may have a selected granularity. For example, an example configuration of memory system 1500 includes nine slices 1512-1512J, wherein each slice includes four array pads 1514 in the row direction (the direction of global word lines 1516); and 4 DQs of the host interface are mapped (1 to 4) to each slice. As an alternative, the memory system may be configured to allocate a 4kB page size across, for example, 18 slices, wherein each slice has a row direction size with two array pads. In this configuration, each slice may be configured for 4B prefetch (which is in a four-sub memory bank data array, as described with respect to Fig. 11B In one example configuration, instead of Fig.15Instead of mapping 4 host interface DQs to each slice as in , 2 host interface DQs may be mapped to each slice. Unlike the number of host DQs mapped to the corresponding slice; each host DQ may be mapped to a selected number of memory interface DQs depending on the array configuration and the desired load, as discussed with respect to the table of paragraph

[0098] .

[0127] As with memory system 1100, memory system 1500 can be implemented in a variety of configurations, including using one or more memory devices in a variety of contexts. In some examples, memory system 1500 can be implemented using multiple memory devices supported directly or indirectly on a substrate or buffer 1504; while in other examples, memory system 1500 can be implemented in an assembly having multiple memory devices arranged (individually or stacked) on a memory module, such as a DIMM module.

[0128] In some examples, any of the embodiments described herein may be implemented according to a selected standard. For example, as previously mentioned, the host interface of the buffer may be configured according to the DDR 5 standard developed by the JC-42 Solid State Memory Committee or a future iteration thereof. In other examples, the interface and memory system functionality may be configured according to other industry standards for interoperability.

[0129] The memory system 1500 may be based on reference Fig.13 The example method 1300 discussed in the flowchart of FIG. 1 is operated. Therefore, the description of that method is not repeated here.

[0130] Fig.16 The illustration may include a block diagram of an example machine (e.g., a host system) 1600 of one or more memory devices and / or memory systems as described above. As discussed above, the machine 1600 may benefit from enhanced memory performance resulting from use of the described memory devices and / or memory systems, thereby facilitating improved performance of the machine 1600 (with respect to many such machines or systems, efficient reading and writing of memory may facilitate improved performance of a processor or other component of the machine, as further described below).

[0131] In alternative embodiments, the machine 1600 may operate as a standalone device or may be connected (e.g., via a network) to other machines. In a networked deployment, the machine 1600 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 1600 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network facility, an IoT device, an automotive system, or any machine capable of executing instructions (sequentially or otherwise) that specify actions to be taken by that machine. In addition, although only a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform the methods discussed herein, such as cloud computing, software as a service (SaaS), any one or more of other computer cluster configurations.

[0132] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by them. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The membership of the circuit system may become flexible over time and with the underlying hardware variability. The circuit system includes members that can perform specific tasks alone or in combination when in operation. In an example, the hardware of the circuit system may be designed invariably to perform specific operations (e.g., hardwired). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including physically modified computer-readable media (e.g., magnetically, electrically, removably placed particles of constant mass, etc.) to encode instructions for specific operations. When connecting physical components, the basic electrical properties of the hardware components change, for example, from insulators to conductors or vice versa. The instructions enable the participating hardware (e.g., execution units or loading mechanisms) to create members of the circuit system in hardware via variable connections to perform parts of specific tasks when in operation. Thus, when the device is operating, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any one of the physical components can be used in more than one member of more than one circuit system. For example, under operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and can be reused by a second circuit in the first circuit system or by a third circuit in the second circuit system at a different time.

[0133] The machine (e.g., computer system, host system, etc.) 1600 may include a processing device 1602 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory 1604 (e.g., a read-only memory (ROM), a dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1606 (e.g., a static random access memory (SRAM), etc.), and a storage system 1618, some or all of which may communicate with each other via a communication interface (e.g., a bus) 1630. In one example, the main memory 1604 includes one or more memory devices as described in the above examples.

[0134] The processing device 1602 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 1602 may be configured to execute instructions 1626 to perform the operations and steps discussed herein. The computer system 1600 may further include a network interface device 1608 for communicating over a network 1620.

[0135] The storage system 1618 may include a machine-readable storage medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 1626 or software embodying any one or more of the methodologies or functions described herein. The instructions 1626 may also reside, completely or at least partially, within the main memory 1604 or within the processing device 1602 during execution by the computer system 1600, the main memory 1604 and the processing device 1602 also constituting machine-readable storage media.

[0136] The term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions, or any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present invention. Thus, the term "machine-readable storage medium" should be understood to include, but not limited to, solid-state memory, optical media, and magnetic media. In an example, a collective machine-readable medium includes a machine-readable medium with multiple particles having a constant (e.g., stationary) mass. Thus, a collective machine-readable medium is not a transient propagating signal. Specific examples of collective machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0137] The machine 1600 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touch screen display. The machine is a signal generating device (e.g., a speaker) or one or more sensors, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors. The machine 1600 may include an output controller, such as a serial (e.g., universal serial bus (USB), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating with or controlling one or more peripheral devices (e.g., printers, card readers, etc.).

[0138] Instructions 1626 (e.g., software, programs, operating system (OS), etc.) or other data stored on storage system 1618 may be accessed by main memory 1604 for use by processing device 1602. Main memory 1604 (e.g., DRAM) is typically fast but volatile, and thus a different type of storage than storage system 1618 (e.g., SSD), which is suitable for long-term storage, including when in an "off" state. Instructions 1626 or data in use by a user or machine 1600 are typically loaded in main memory 1604 for use by processing device 1602. When main memory 1604 is full, virtual space from storage system 1618 may be allocated to supplement main memory 1604; however, because storage system 1618 is typically slower than main memory 1604, and write speeds are typically at least 1 / 2 of the read speed, the use of virtual memory greatly degrades the user experience due to memory system latency (compared to main memory 1604, such as DRAM). Furthermore, using storage system 1618 for virtual storage may significantly reduce the useful life of storage system 1618 .

[0139] The instructions 1626 may further utilize any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.) to be transmitted or received over the network 1620 via the network interface device 1608 using a transmission medium. Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.15 series of standards, known as The IEEE 802.16 family of standards, known as IEEE 802.15.4 family of standards), peer-to-peer (P2P) networks, and the like. In an example, network interface device 1608 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to network 1620. In an example, network interface device 1608 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be understood to include any intangible media capable of storing, encoding, or carrying instructions executed by machine 1600, and includes digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0140] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show by way of illustration specific embodiments in which the present invention can be practiced. These embodiments are also referred to as "examples" herein. Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples using any combination or arrangement of those elements (or one or more aspects thereof) shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0141] All publications, patents, and patent documents mentioned in this document are incorporated herein by reference in their entirety as if individually incorporated by reference. In the event of inconsistencies between the usages of this document and those incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0142] In this document, as is common in patent documents, independent of any other examples or usages of "at least one" or "one or more", the term "one" or "an" is used to include one or more than one. In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, so that "A or B" includes "A but not B", "B but not A" and "A and B". In the appended claims, the terms "include" and "in which" are used as the plain English equivalents of the corresponding terms "include" and "wherein". Moreover, in the appended claims, the terms "include" and "include" are open. That is, this term including elements other than those listed after the system, device, object or process in the claim is still considered to fall within the scope of that claim. In addition, in the appended claims, the terms "first", "second" and "third" etc. are used only as labels and are not intended to impose numerical requirements on their objects.

[0143] In various examples, the components, controllers, processors, units, engines, or tables described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including groups of processors or multi-core devices.

[0144] The term "horizontal" as used in this document is defined as a plane parallel to a conventional plane or surface of a substrate, such as that underlying a wafer or die, regardless of the actual orientation of the substrate at any point in time. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions such as "on", "above", and "below" are defined relative to a conventional plane or surface, on the top or exposed surface of a substrate, regardless of the orientation of the substrate; while "on" is intended to imply direct contact of one structure relative to another structure "located on" the structure (in the absence of an explicit indication to the contrary); the terms "above" and "below" are explicitly intended to identify relative placement of structures (or layers, features, etc.), which explicitly include (but are not limited to) direct contact between identified structures unless specifically indicated as such. Similarly, the terms "above" and "below" are not limited to a horizontal orientation, as a structure may be "above" a referenced structure if it is the outermost portion of the construction being discussed at a certain point in time, even if that structure extends vertically rather than in a horizontal orientation relative to the referenced structure.

[0145] The term "wafer" is used herein to refer generally to any structure on which an integrated circuit is formed, and also to such structures during the various stages of integrated circuit fabrication. The term "substrate" is used to refer to a wafer or other structure that supports or is connected to other components, such as a memory die or portion thereof. Thus, the term "substrate" encompasses, for example, circuit or "PC" boards, interposers, and other organic or non-organic support structures (which may also contain active or passive components in some cases). Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the various embodiments is defined solely by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0146] It will be understood that when an element is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, connected to, or coupled to another element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements or layers. If two elements are shown in a drawing with a line connecting them, the two elements may be coupled, or directly coupled, unless otherwise indicated.

[0147] The method examples described herein may be at least partially machine or computer implemented. Some examples may include computer-readable media or machine-readable media encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. This code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. In addition, the code may be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical disks (e.g., optical disks and digital video disks), cassettes, memory cards or sticks, random access memories (RAMs), read-only memories (ROMs), etc.

[0148] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of examples is provided here:

[0149] Example 1 is a memory device comprising: a buffer device coupled to a substrate, the buffer device including a host device interface and a DRAM interface; one or more DRAM dies supported by the substrate; a plurality of wire bonding interconnects between the DRAM interface of the buffer device and the one or more DRAM dies; and a circuit system in the buffer device configured to operate the host device interface at a first data speed and to operate the DRAM interface at a second data speed that is slower than the first data speed.

[0150] In Example 2, the memory device of Example 1 optionally includes 8 dies.

[0151] In Example 3, the memory device of Example 2 optionally includes 16 dies.

[0152] In Example 4, the memory device of any one or more of Examples 2-3, wherein the DRAM die stack comprises a ladder-type stacked DRAM die.

[0153] In Example 5, the memory device of Example 4, wherein the stack of DRAM dies includes more than one stepping direction within a single stack.

[0154] In Example 6, the memory device of any one or more of Examples 1-5, wherein two stacks of DRAM dies are coupled to the substrate.

[0155] In Example 7, the memory device of any one or more of Examples 1-6, wherein the buffer device is at least partially located below the one or more DRAM dies.

[0156] In Example 8, the memory device of any one or more of Examples 6-7, wherein the buffer device is at least partially located below a portion of each of the two DRAM die stacks.

[0157] In Example 9, the memory device of any one or more of Examples 1-8 optionally includes solder balls on a back side of the substrate.

[0158] In Example 10, the memory device of any one or more of Examples 1-9, wherein the one or more DRAM dies include multiple DRAM dies in a DRAM die stack coupled to a single buffer device pin.

[0159] In Example 11, the memory device of any one or more of Examples 1-10, wherein the circuitry in the buffer device is configured to operate using a pulse amplitude modulation (PAM) protocol at the host device interface or the DRAM interface, or both.

[0160] Example 12 is a memory device comprising: a buffer device coupled to a substrate, the buffer device including a host interface and a DRAM interface; a vertically aligned DRAM die stack supported by the substrate; a plurality of through-silicon via (TSV) interconnects coupling a plurality of dies in the vertically aligned DRAM die stack with the buffer device; and a circuit system in the buffer device configured to operate the host interface at a first data speed and to operate the DRAM interface at a second data speed that is slower than the first data speed.

[0161] In Example 13, the memory device of Example 12 optionally includes 8 dies.

[0162] In Example 14, the memory device of Example 13 optionally includes 16 dies.

[0163] In Example 15, the memory device of any one or more of Examples 13-14, wherein the buffer device is at least partially located below the vertically aligned DRAM die stack.

[0164] In Example 16, the memory device of any one or more of Examples 13-15, wherein two vertically aligned DRAM die stacks are coupled to the substrate.

[0165] In Example 17, the memory device of Example 16, wherein the buffer die is at least partially located below a portion of each of the two vertically aligned DRAM die stacks.

[0166] Example 18 is a system comprising: a processor coupled to a first substrate; a memory device coupled to the first substrate adjacent to the processor, the memory device comprising: a buffer device coupled to a second substrate, the buffer device comprising a host interface and a DRAM interface; a stack of multiple DRAM dies coupled to the second substrate; a plurality of wire bonding interconnects between the DRAM interface of the buffer device and the stack of DRAM dies; and a circuit system in the buffer device configured to operate the host interface at a first data speed and to operate the DRAM interface at a second data speed that is slower than the first data speed.

[0167] In Example 19, the system of Example 18, wherein the first substrate is a motherboard, and both the memory device and the processor are soldered to the motherboard by a ball grid array.

[0168] In Example 20, according to the system of Example 19, the memory device is one or more memory devices soldered to the motherboard adjacent to the processor.

[0169] In Example 21, the system of any one or more of Examples 18-20, wherein the plurality of wirebond interconnects includes both command / address interconnects and data interconnects.

[0170] In Example 22, the system of any one or more of Examples 18-21, wherein the host interface includes a first number of data paths, and wherein the DRAM interface includes a second number of data paths; and wherein the second number of data paths is at least twice the first number of data paths.

[0171] In Example 23, the system of any one or more of Examples 18-22, wherein the host interface includes a third number of command / address paths; and wherein the DRAM interface includes a fourth number of command / address paths that is at least twice the number of the third command / address paths.

[0172] In Example 24, the system of any one or more of Examples 22-23, wherein at least some data paths of the DRAM interface communicate only with a single DRAM die.

[0173] In Example 25, the system of any one or more of Examples 22-24, wherein at least some data paths of the DRAM interface communicate with more than one DRAM die of the plurality of stacked DRAM dies.

[0174] In Example 26, the system of any one or more of Examples 23-25, wherein at least some command / address paths of the DRAM interface communicate with a single bank of a single DRAM die.

[0175] In Example 27, the system of any one or more of Examples 23-26, wherein at least some command / address paths of the DRAM interface communicate with multiple memory banks of the multiple stacked DRAM dies.

[0176] In Example 28, the system of any one or more of Examples 18-27, wherein each DRAM die includes a plurality of IO data stripes.

[0177] In Example 29, the system of Example 28, wherein each data stripe terminates on two opposing sides of the DRAM die.

[0178] In Example 30, the system of Example 29, wherein wire bonds from the second substrate extend from the two opposing sides to the plurality of stacked DRAM dies.

[0179] In Example 31, the system of Example 30, wherein at least some of the wire bonds are connected in series on the plurality of stacked DRAM dies.

[0180] Example 32 is a method of operating a memory device, comprising: exchanging data between a processor and a buffer device at a first data speed; exchanging data between the buffer device and one or more DRAM dies at a second data speed that is slower than the first data speed; wherein exchanging data between the buffer device and the one or more DRAM dies includes exchanging data through multiple wire bonds.

[0181] In Example 33, the method of Example 32, wherein exchanging data between the buffer device and the one or more DRAM dies includes exchanging using a pulse amplitude modulation (PAM) protocol.

[0182] In Example 34, a method according to any one or more of Examples 32-33, wherein exchanging data between a processor and a buffer device includes exchanging data through a first number of data paths; and wherein exchanging data between the buffer device and the one or more DRAM dies includes exchanging data through a second number of data paths that is greater than the first number of data paths.

[0183] Example 35 is a method of operating a memory device, comprising: exchanging data between a processor and a buffer device at a first data speed; exchanging data between the buffer device and a vertically aligned DRAM die stack at a second speed slower than the first speed; wherein exchanging data between the buffer device and the vertically aligned DRAM die stack includes exchanging data through a plurality of through-silicon vias (TSVs) in the vertically aligned DRAM die stack.

[0184] In Example 36, the method of Example 35, wherein exchanging data between the buffer device and a stack of DRAM dies includes exchanging using a pulse amplitude modulation (PAM) protocol.

[0185] In Example 37, a method is described according to any one or more of Examples 35-36, wherein exchanging data between a processor and a buffer device includes exchanging data through a first number of data paths; and wherein exchanging data between the buffer device and a vertically aligned DRAM die stack includes exchanging data through a second number of data paths that is greater than the first number of data paths.

[0186] Example 38 is a memory system comprising: a plurality of memory dies stacked on top of one another above a substrate; a buffer assembly comprising: a host physical interface comprising connections for at least one memory channel, the connections for the memory channel comprising command / address connections and data connections; control logic mapping the connections for the at least one memory channel to at least two sub-channels; and a DRAM physical interface for each sub-channel, each sub-channel physical interface comprising command / address connections and data connections; and an interconnect between the DRAM physical interface for each sub-channel and one or more memory dies of the plurality of DRAM dies.

[0187] In Example 39, a memory system according to Example 38, wherein the stacked plurality of memory dies are each laterally offset relative to at least one vertically adjacent memory die; and wherein individual memory dies in the stacked plurality of memory dies are wire-bonded to corresponding connectors of the DRAM physical interface.

[0188] Example 40 is a method of operating a memory system, comprising: receiving command / address (CA) signals and corresponding data (DQ) signals for a first memory channel at a first memory interface; mapping the received CA signals and the corresponding DQ signals to at least first and second sub-channels; wherein each sub-channel DRAM interface carries a greater number of DQ signals than the first memory interface and clocks the DQ signals at a slower speed than the first memory interface; and communicating the CA signals and DQ signals of each sub-channel DRAM interface to one or more dies in a stack of multiple memory dies through wire bonding connections.

[0189] In Example 41, the method of Example 40, wherein the mapping is performed by a buffer assembly supported by a substrate, and wherein a stack of the plurality of memory dies is supported by the substrate.

[0190] Example 42 is a memory system comprising: a plurality of DRAM memory dies stacked on top of one another above a substrate, wherein vertically adjacent memory dies are laterally offset from at least one vertically adjacent die; a buffer assembly comprising: a host physical interface comprising connections for a plurality of memory channels, the connections for each memory channel comprising command / address (CA) connections and data (DQ) connections; control logic that maps the connections for the at least one memory channel to at least two sub-channels; and a DRAM physical interface for each sub-channel, each sub-channel DRAM physical interface comprising command / address connections and data connections, wherein the host physical interface comprises a first number of DQ connections for the memory channel, and wherein the DRAM physical interface for the respective sub-channel comprises a second number of DQ connections that is at least a multiple of the first number of DQ connections, and wherein the DQ connections of the sub-channel DRAM clock data at a speed that is less than a speed at which the host physical interface receives data; and wire bonding interconnects between the DRAM physical interface for each sub-channel and one or more memory dies of the plurality of DRAM memory dies.

[0191] In Example 43, the memory system of Example 42, wherein the DQ connections of the sub-channel DRAM interface clock data at an even fraction of the speed at which the host physical interface receives data.

[0192] In Example 44, the memory system of Example 43, wherein the sub-channel DRAM interface clocks data at half the speed at which the host physical interface receives data.

[0193] In Example 45, the memory system of any one or more of Examples 43-44, wherein the sub-channel DRAM interface clocks data at one quarter of the speed at which the host physical interface receives data.

[0194] In Example 46, the memory system of any one or more of Examples 42-45, wherein the CA connection of at least one sub-channel DRAM interface is coupled to multiple banks of DRAM memory in the stacked multiple DRAM memory dies.

[0195] In Example 47, the memory system of Example 46, wherein the CA connection of the at least one sub-channel DRAM interface is coupled to memory banks in different DRAM memory dies.

[0196] In Example 48, the memory system of any one or more of Examples 42-47, wherein at least one of the DRAM memory dies includes a redistribution layer (RDL) including wire bonding pads.

[0197] In Example 49, a memory system according to Example 48, wherein the wire bonding pad is positioned adjacent to an edge of the at least first DRAM memory die, and wherein the wire bonding pad of the first DRAM memory die is accessible due to a lateral offset of at least one vertically adjacent DRAM memory die relative to the first DRAM memory die.

[0198] Example 50 is a memory system comprising: at least one memory die; a buffer coupled to the at least one memory die, the buffer comprising a host physical interface, the host physical interface comprising pins for a memory channel, the pins comprising command / address pins and data pins, and wherein the data pins comprise multiple ECC pins and multiple parity pins; control logic that maps the data pins of the at least one memory channel at the host physical interface to at least two memory physical interfaces, each memory physical interface comprising multiple data pins, including multiple ECC pins and multiple parity pins; and an interconnect between the memory physical interface and one or more memory dies in the at least one memory die, wherein the memory physical interface data pins are mapped between multiple regions of the at least one memory die, and wherein the number of the multiple regions is divisible by 10.

[0199] In Example 51, the memory system of Example 50, wherein the host physical interface and the memory physical interface each include a plurality of pins for parity bits.

[0200] In Example 52, a memory system according to any one or more of Examples 50-51, wherein the host physical interface includes a first number of data pins; and wherein each sub-channel physical connection includes a second number of data pins that is at least twice the first number of data pins.

[0201] In Example 53, the memory system of Example 52, wherein the second number of data pins is four times the first number of data pins.

[0202] In Example 54, the memory system of any one or more of Examples 50-53, wherein each memory physical interface is a greater number of command / address pins than the host physical interface.

[0203] In Example 55, the memory system of any one or more of Examples 50-54, wherein the at least one memory device comprises a DRAM memory device; and wherein each memory physical interface is a DRAM physical interface.

[0204] In Example 56, the memory system of any one or more of Examples 50-55 optionally includes regions of the at least one memory device each including a sub-array.

[0205] In Example 57, the memory system of Example 56, wherein each sub-array includes a plurality of array pads.

[0206] In Example 58, the memory system of any one or more of Examples 56-57 optionally includes a region distributed across at least two memory devices.

[0207] In Example 59, the memory system of any one or more of Examples 56-58 optionally includes a region distributed across multiple banks of the memory device.

[0208] Example 60 is a memory system comprising: at least one memory die; a buffer coupled to the at least one memory die, the buffer configured to reallocate data pins of a first interface that can operate at a first data rate to a plurality of memory interfaces that can operate at a second data rate that is slower than the first data rate, the buffer further configured to reallocate groups of the data pins of the first interface to at least 10 slices of the at least one memory die.

[0209] In Example 61, the memory system of Example 60, wherein the buffer is further configured to reallocate each data pin of the first interface to at least two data pins of the plurality of memory interfaces.

[0210] In Example 62, the memory system of any one or more of Examples 60-61, wherein the buffer is further configured to reallocate control / address pins of the first interface to the plurality of memory interfaces.

[0211] In Example 63, a memory system according to Example 62, wherein the buffer is further configured to reallocate each control / address pin of the first interface to multiple pins of the multiple memory interfaces; and wherein the control / address pins of the first interface can operate at a third data rate, and the control / address pins of the multiple memory interfaces can operate at a fourth data rate.

[0212] In Example 64, the memory system of Example 63, wherein the first data rate is the same as the third data rate; and wherein the second data rate is the same as the fourth data rate.

[0213] In Example 65, a memory system according to any one or more of Examples 60-64, wherein the multiple data pins of the first interface include multiple data pins coupled to carry data, multiple data pins coupled to carry ECC bits, and multiple data pins coupled to carry parity bits.

[0214] In Example 66, the memory system of Example 65 optionally includes a slice of the at least one memory die comprising a plurality of array pads.

[0215] In Example 67, the memory system of any one or more of Examples 60-66 optionally includes slices coupled to a common global word line.

[0216] In Example 68, the memory system of any one or more of Examples 66-67 optionally includes a slice containing local word lines operable independently of word lines in physically adjacent array pads.

[0217] In Example 69, the memory system of Example 68, wherein the local word lines of the array pad are operable by using corresponding global word lines.

[0218] In Example 70, the memory system of any one or more of Examples 62-69 optionally includes sub-channel interfaces, and wherein each sub-channel interface is connected to a respective slice of the at least one memory die.

[0219] In Example 71, the memory system of any one or more of Examples 60-70 optionally includes slices located in at least two memory devices.

[0220] In Example 72, the memory system of any one or more of Examples 60-71 optionally includes slices located in at least two columns of memory dies.

[0221] In Example 73, the memory system of any one or more of Examples 60-72 optionally includes slices located in a plurality of banks of the memory die.

[0222] In Example 74, the memory system of any one or more of Examples 60-73, wherein the at least one memory die comprises a stack of at least two memory dies.

[0223] In Example 75, the memory system of any one or more of Examples 60-74, wherein the at least one memory die comprises a DRAM memory die.

[0224] In Example 76, the memory system of any one or more of Examples 70-75, wherein the at least one memory die comprises a plurality of DRAM memory dies.

[0225] In Example 77, the memory system of any one or more of Examples 70-76, wherein each subchannel interface is coupled to at least two slices of the at least one memory die.

[0226] In Example 78, the memory system of Example 77, wherein the at least two slices coupled to each subchannel interface are located in different banks of the memory die.

[0227] In Example 79, the memory system of any one or more of Examples 60-78, wherein the buffer includes a controller and switching logic operable to reallocate the pins of the first interface.

[0228] In Example 80, the memory system of Example 79, wherein the buffer further comprises row address select (RAS) logic.

[0229] In Example 81, the memory system of Example 80, wherein the buffer further comprises a built-in self-test (BIST) engine.

[0230] Example 82 is a method of operating a memory system, comprising: receiving data and control / address signals at a first interface of a buffer structure and at a first data rate; mapping data pins of the first interface to a plurality of memory sub-channel interfaces, the memory sub-channel interfaces being operable at a second data rate that is slower than the first data rate; and communicating signals from each sub-channel interface to at least one slice of a memory device.

[0231] In Example 83, the method according to Example 82 optionally includes a subchannel interface.

[0232] In Example 84, the method of any one or more of Examples 82-83, wherein mapping data pins of the first interface to multiple memory sub-channel interfaces comprises mapping each data pin of the first interface to at least two data pins of the memory sub-channel interface.

[0233] In Example 85, a method according to any one or more of Examples 82-84, wherein the first interface includes a plurality of data pins coupled to carry data, a plurality of data pins coupled to carry ECC bits, and a plurality of data pins coupled to carry parity bits.

[0234] In Example 86, the method of any one or more of Examples 83-85 optionally includes slicing of a memory system and including a plurality of array pads in each slice of the memory system.

[0235] In Example 87, the method of any one or more of Examples 83-86 optionally includes coupling the slices to a common global word line.

[0236] In Example 88, the method of any one or more of Examples 86-87 optionally includes a slice including local word lines operable independently of word lines in physically adjacent array pads.

[0237] Example 89 is a method of operating a memory system, comprising: receiving a signal at a host physical interface, the host physical interface including command / address pins and data pins (DQ), and wherein the DQ includes multiple ECC pins and multiple parity pins; mapping the DQ of the host physical interface to at least two sub-channel memory interfaces, each sub-channel memory interface including command / address pins and DQ, including multiple ECC pins and multiple parity pins; and communicating the signal from the sub-channel memory interface to corresponding regions located in one or more memory dies, wherein the number of the regions receiving the signal is divisible by 10.

[0238] In Example 90, the method of Example 89, wherein each of the respective regions located in one or more memory dies is a sub-array of a memory die.

[0239] In Example 91, the method of Example 90, wherein each subarray includes a plurality of array pads.

[0240] In Example 92, the method of Example 91, wherein communicating signals from the sub-channel memory interface to respective regions comprises communicating signals to a plurality of array pads within each sub-array, and wherein the signals are communicated to a number of array pads that is a multiple of ten.

[0241] Example 93 is a memory system comprising: at least one memory die; a buffer coupled to the at least one memory die, the buffer configured to reallocate data pins of a first interface that can operate at a first data rate to a plurality of memory interfaces that can operate at a second data rate that is slower than the first data rate, the buffer further configured to reallocate groups of the data pins of the first interface to at least nine slices of the at least one memory die.

[0242] In Example 94, the memory system of Example 93, wherein the buffer is further configured to reallocate each data pin of the first interface to at least two data pins of the plurality of memory interfaces.

[0243] In Example 95, the memory system of any one or more of Examples 93-94, wherein the buffer is further configured to reallocate control / address pins of the first interface to the plurality of memory interfaces.

[0244] In Example 96, a memory system according to Example 95, wherein the buffer is further configured to reallocate each control / address pin of the first interface to multiple pins of the multiple memory interfaces; and wherein the control / address pins of the first interface can operate at a third data rate, and the control / address pins of the multiple memory interfaces can operate at a fourth data rate.

[0245] In Example 97, the memory system of Example 96, wherein the first data rate and the third data rate are the same; and wherein the second data rate and the fourth data rate are the same.

[0246] In Example 98, a memory system according to any one or more of Examples 93-97, wherein the multiple data pins of the first interface include multiple data pins coupled to carry data, multiple data pins coupled to carry ECC bits, and multiple data pins coupled to carry parity bits.

[0247] In Example 99, the memory system of Example 98, wherein each slice of the at least nine slices of the at least one memory die includes a plurality of array pads.

[0248] In Example 100, the memory system of any one or more of Examples 98-99, wherein the plurality of array pads of the at least nine slices are coupled to a common global word line.

[0249] In Example 101, the memory system of any one or more of Examples 99-100, wherein each array pad within the at least nine slices includes a local word line operable independently of word lines in physically adjacent array pads.

[0250] In Example 102, the memory system of Example 101, wherein the local word lines of the array pad are operable by using corresponding global word lines.

[0251] In Example 103, the memory system of any one or more of Examples 95-102, wherein the plurality of memory interfaces includes at least nine sub-channel interfaces, and wherein each sub-channel interface is connected to a respective slice of the at least one memory die.

[0252] In Example 104, the memory system of any one or more of Examples 93-103, wherein the at least nine slices are located in at least two memory devices.

[0253] In Example 105, the memory system of any one or more of Examples 93-104, wherein the at least nine slices are located in at least two columns of the memory device.

[0254] In Example 106, the memory system of any one or more of Examples 93-105, wherein the at least nine slices are located in at least two banks of the memory device.

[0255] In Example 107, the memory system of any one or more of Examples 93-106, wherein the at least one memory die comprises a stack of at least two memory dies.

[0256] In Example 108, the memory system of any one or more of Examples 93-107, wherein the at least one memory die comprises a DRAM memory die.

[0257] In Example 109, the memory system of any one or more of Examples 93-108, wherein the at least one memory die comprises a plurality of DRAM memory dies.

[0258] In Example 110, the memory system of any one or more of Examples 103-109, wherein each subchannel interface is coupled to at least two slices of the at least one memory die.

[0259] In Example 111, the memory system of Example 110, wherein the at least two slices coupled to each subchannel interface are located in different banks of the memory device.

[0260] In Example 112, the memory system of any one or more of Examples 93-111, wherein the buffer includes a controller and switching logic operable to reallocate the pins of the first interface.

[0261] In Example 113, the memory system of Example 112, wherein the buffer further comprises row address select (RAS) logic.

[0262] In Example 114, the memory system of any one or more of Examples 112-113, wherein the buffer further comprises a built-in self-test (BIST) engine.

[0263] Example 115 is a method of operating a memory system, comprising: receiving data and control / address signals at a first interface of a buffer structure and at a first data rate; mapping data pins of the first interface to a plurality of memory sub-channel interfaces, the memory sub-channel interfaces being operable at a second data rate that is slower than the first data rate; and communicating signals from each sub-channel interface to at least one slice of a memory device.

[0264] In Example 116, the method of Example 115, wherein mapping data pins of the first interface to a plurality of memory sub-channel interfaces comprises mapping groups of the data pins of the first interface to at least nine sub-channel interfaces.

[0265] In Example 117, the method of any one or more of Examples 115-116, wherein mapping data pins of the first interface to multiple memory sub-channel interfaces includes mapping each data pin of the first interface to at least two data pins of the memory sub-channel interface.

[0266] In Example 118, the method of any one or more of Examples 115-117, wherein the first interface includes a plurality of data pins coupled to carry data and a plurality of data pins coupled to carry parity bits.

[0267] In Example 119, the method of any one or more of Examples 115-118, wherein each of the memory subchannel interfaces extends to a respective slice of at least nine slices of a memory array, and wherein each slice of the memory array includes a plurality of array pads.

[0268] In Example 120, the method of any one or more of Examples 116-119, wherein a plurality of slices of the at least nine slices are coupled to a common global word line.

[0269] In Example 121, the method of any one or more of Examples 119-120, wherein each array pad within the at least nine slices includes a local word line operable independently of word lines in physically adjacent array pads.

[0270] Example 122 is a method of operating a memory system, comprising: receiving a signal at a host physical interface, the host physical interface including command / address pins and data pins (DQ); mapping the DQs of the host physical interface to at least two sub-channel memory interfaces, each sub-channel memory interface including command / address pins and DQs; and communicating the signal from the sub-channel memory interfaces to corresponding regions located in one or more memory dies, wherein the number of the multiple regions receiving the signal is divisible by nine.

[0271] In Example 123, the method of Example 122, wherein each of the respective regions located in one or more memory dies is a sub-array of a memory die.

[0272] In Example 124, according to the method of Example 123, each sub-array includes a plurality of array pads.

[0273] In Example 125, the method of Example 124, wherein communicating signals from the sub-channel memory interface to respective regions comprises communicating signals to a plurality of array pads within each sub-array, and wherein the signals are communicated to a number of array pads that is a multiple of nine.

[0274] Example 126 is a memory system comprising: a plurality of memory dies supported by a substrate; a buffer assembly electrically coupled to the plurality of memory dies, the plurality of memory dies comprising: a host memory channel interface comprising command / address connections and data connections; control logic mapping the data connections of the at least one memory channel to at least two memory sub-channel interfaces coupled to the memory device, comprising mapping each host data connection to at least two data connections at the memory sub-channel interface; wherein the memory sub-channel data connections are operable to transfer data at a slower rate than data connections of the host memory channel interface.

[0275] In Example 127, the system of Example 126, wherein the buffer assembly includes a buffer die stacked with at least one memory device.

[0276] In Example 128, the system of Example 127, wherein a plurality of memory devices are stacked with the buffer die.

[0277] In Example 129, the system of any one or more of Examples 126-128, wherein the memory system forms part of a memory module.

[0278] In Example 130, the system of Example 129, wherein the memory module is a dual in-line memory module (DIMM).

[0279] In Example 131, the system of any one or more of Examples 126-130, wherein the plurality of memory devices comprises a plurality of DRAM memory devices.

[0280] In Example 132, the system of any one or more of Examples 126-131, wherein the data connection includes an ECC / parity connection.

[0281] In Example 133, the memory device or system described in any of Examples 1-39 and 93-114 can be modified with the structure and functionality of other of such examples.

[0282] In Example 134, the memory device or system of any of Examples 1-39 and 93-114 may be configured or adapted to perform the method of any of Examples 32-37, 40-41, 82-92, 42-81, or 115-125.

[0283] In Example 135, the method described in accordance with any of Examples 32-37, 40-41, 82-92, 42-81, or 115-125 can be modified to include the operations of others of such examples.

[0284] In Example 136, the method described in any of Examples 32-37, 40-41, 82-92, 42-81, or 115-125 may be implemented by one or more of the devices described in any of Examples 1-39 and 93-114.

[0285] The above description is intended to be illustrative and non-restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, for example, a person of ordinary skill in the art may use other embodiments. An abstract is provided to comply with 37C.FR§1.72(b) to allow readers to quickly confirm the nature of the technical disclosure. It should be understood when submitting that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features may be grouped together to simplify the present disclosure. This should not be interpreted as unclaimed disclosure features intended to be essential to any claim. Instead, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the specific embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached claims together with the full range of equivalents given by this claim.

Claims

1. A memory system, comprising: a memory array comprising a plurality of memory dies; a buffer coupled to at least one memory die of the plurality of memory die, the buffer being configured to reallocate data pins of a first interface operating at a first data rate to data pins of a plurality of memory sub-channel interfaces, the data pins of the plurality of memory sub-channel interfaces operating at a second data rate slower than the first data rate, each memory sub-channel interface being coupled to a respective region of the memory array, each region extending across a plurality of memory dies, each region comprising a plurality of sub-arrays; wherein the sub-arrays respectively include matrix array pads, each array pad including a plurality of rows and a plurality of columns of memory cells; and The memory array comprises a plurality of global word lines extending across the plurality of sub-arrays, and a plurality of sub-wordline decoders driving local wordlines extending across one or more array pads, wherein each array pad is accessible by the plurality of local wordlines; The buffer is further configured to reallocate groups of the data pins of the first interface to at least eight corresponding regions of the memory array.

2. The memory system of claim 1 , wherein the buffer is further configured to reallocate each data pin of the first interface to at least two data pins of the plurality of memory sub-channel interfaces; and Wherein memory cells in an array pad are coupled to a plurality of local word lines that are operated independently from a local word line in at least one physically adjacent array pad.

3. The memory system of claim 1, wherein the buffer is configured to reallocate groups of the data pins of the first interface to at least nine regions of the memory array.

4. The memory system of claim 1, wherein the buffer is configured to reallocate groups of the data pins of the first interface to at least ten regions of the memory array.

5. The memory system of claim 1, wherein the buffer is further configured to reallocate control / address pins of the first interface to the plurality of memory sub-channel interfaces.

6. The memory system of claim 1, wherein the plurality of data pins of the first interface comprises a plurality of data pins coupled to carry data, a plurality of data pins coupled to carry ECC bits, and a plurality of data pins coupled to carry parity bits.

7. The memory system of claim 1, wherein the plurality of data pins of the first interface comprises at least 36 data pins.

8. The memory system of claim 7, wherein the plurality of data pins of the first interface comprises at least 40 data pins.

9. The memory system of claim 1, wherein the buffer comprises a controller and switching logic operated to reallocate the pins of the first interface.

10. The memory system of claim 9, wherein the buffer further comprises reliability, availability, and serviceability (RAS) logic.

11. The memory system of claim 9, wherein the buffer further comprises a built-in self-test (BIST) engine.

12. The memory system of claim 1, wherein the memory array comprises a stack of a plurality of memory devices.

13. A method of operating a memory system, comprising: receiving data and control / address signals from an external device at a first interface of the buffer structure at a first data rate; mapping data pins of the first interface to data pins of a plurality of memory sub-channel interfaces, the data pins of the memory sub-channel interfaces operating at a second data rate that is slower than the first data rate; and communicating signals from each sub-channel interface to a corresponding region of a plurality of regions of a memory array of the memory system, each region comprising a plurality of rows and a plurality of columns of memory cells, and wherein each region comprises a plurality of sub-arrays and extends across a plurality of memory dies; wherein each sub-array comprises a matrix array pad; and The memory array comprises a plurality of global word lines extending across the plurality of sub-arrays, and A plurality of sub-wordline decoders drive local wordlines extending across one or more array pads, wherein each array pad is accessible by the plurality of local wordlines.

14. The method of claim 13 wherein the plurality of regions comprises at least 8 regions of the memory array.

15. The method of claim 13, wherein at least two of the respective ones of the plurality of regions of a memory array share a common global word line.

16. The method of claim 13, wherein the memory array comprises a plurality of memory banks including memory devices.

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