A multi-chip structure including a memory die stacked on a die having a programmable integrated circuit

Abstract

Some examples described herein provide a multi-chip structure that includes one or more memory dies stacked on a die having a programmable integrated circuit (IC). In one example, the multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes a memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

Description

Technical Field

[0001] This disclosure relates to a multi-chip structure and a method of forming such a structure, and more particularly to a multi-chip structure comprising one or more memory dies stacked on a die having a programmable integrated circuit, and a method of forming such a structure. Background Technology

[0002] A programmable integrated circuit (IC) is a type of IC that includes a programmable circuit system. An example of a programmable IC is a field-programmable gate array (FPGA). An FPGA is characterized by including programmable circuit blocks. Circuit designs can be physically implemented within the programmable circuit system of a programmable IC by loading configuration data (sometimes called a configuration bitstream) into the device. The configuration data can be loaded into the device's internal configuration memory cells. The collective state of the individual configuration memory cells determines the functionality of the programmable IC. For example, the specific operations performed by various programmable circuit blocks and the connectivity between the programmable circuit blocks of a programmable IC are defined by the collective state of the configuration memory cells once the configuration data is loaded. Summary of the Invention

[0003] Some examples described herein provide a multi-chip architecture comprising one or more memory dies stacked on a die having a programmable integrated circuit (IC). Some examples described herein can avoid the use of an interposer and / or physical layer (PHY) interface, which can reduce processing costs, power consumption, and / or die area usage.

[0004] One example is a multi-chip architecture. The multi-chip architecture includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit, and the programmable integrated circuit includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0005] Another example is a method of forming a multi-chip structure. A first die is stacked on a second die. The first die includes a memory. The second die includes a programmable integrated circuit, and the programmable integrated circuit includes a memory controller. The memory controller is communicatively coupled to the memory via the first die stacked on the second die. The first die is attached to a package substrate.

[0006] Another example is a multi-chip architecture. The multi-chip architecture includes a package substrate, a first die, and a second die. The first die includes a field-programmable gate array (FPGA) and a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the side of the first die opposite the package substrate. Memory communication is coupled to the memory controller.

[0007] These and other aspects can be understood by referring to the following detailed description. Attached Figure Description

[0008] To gain a more detailed understanding of the features described above, a more specific description of the points briefly summarized above can be obtained by referring to the example implementations, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only show typical example implementations and should not be considered as limiting the scope of the examples.

[0009] Figure 1 It is a block diagram depicting a programmable integrated circuit (IC) connected to external memory, based on some examples.

[0010] Figure 2 Field-Programmable Gate Arrays (FPGAs) based on some examples of programmable ICs are depicted.

[0011] Figure 3 , 4 Figures 5 and 6 are circuit diagrams of corresponding multi-chip structures based on some examples.

[0012] Figure 6 , 7 8 is based on the configuration of a multi-chip structure on a printed circuit board (PCB) in some examples.

[0013] Figure 9 This is a flowchart illustrating methods for forming multi-chip structures, based on some examples.

[0014] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It can be expected that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0015] Some examples described in this document provide a multi-chip architecture comprising one or more memory dies stacked on a die having a programmable integrated circuit (IC). In some examples, the memory die may implement memory for high-bandwidth memory (HBM). In some examples, the programmable IC includes programmable logic regions, such as the structure of a field-programmable gate array (FPGA). The programmable IC allows a user-configurable front-end process to read or write data from or to the memory of any memory die.

[0016] Some examples described in this article can avoid the use of an interposer. By stacking memory dies on a base die that includes a programmable IC, an interposer is not implemented (the base die and memory die stack would otherwise be individually attached to that interposer). Eliminating the interposer also avoids the costs associated with processing and including an interposer in a multi-die stack. Furthermore, without an interposer, fewer processes are required to form a multi-die stack, which, in addition to reducing costs, also reduces processing cycle time. Eliminating the interposer and stacking memory dies on a base die also allows for a smaller package footprint and a smaller vertical profile.

[0017] Some examples described in this article can avoid the use of physical layer (PHY) interfaces, such as HBM interfaces, in multi-chip architectures. PHY interfaces consume power and chip area. By avoiding the use of PHY interfaces, such as HBM interfaces, it is possible to avoid PHY interfaces on two dies (e.g., one on each side of the HBM physical layer connection), which can reduce power consumption and reduce the area usage of both dies. Furthermore, reducing die area usage can reduce the costs associated with the processing used to form the dies.

[0018] Several examples offer additional benefits. For instance, composite devices formed from multi-chip structures are easier to test and place within multi-chip modules, such as those with additional packages and / or dies. Furthermore, multi-chip structures with programmable ICs, as described herein, allow for customization of logic and functionality adjacent to one or more memory dies (e.g., adjacent to one or more HBM dies). Such multi-chip structures allow users to create deployable, customizable devices with, for example, high memory bandwidth and low power consumption within a single package. Moreover, such multi-chip structures maintain the programmability and flexibility of programmable logic regions and boundary circuitry (e.g., input / output circuitry, transceiver circuitry, and / or other circuitry).

[0019] Various features will be described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by the same reference numerals throughout the drawings. It should be noted that these drawings are merely for the purpose of facilitating the description of features. They are not intended as an exhaustive description of the claimed invention or a limitation on the scope of the claimed invention. Furthermore, the examples shown do not need to possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not so stated or explicitly described. Moreover, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented using more or fewer operations in various other orders (e.g., including different sequential or parallel executions of various operations).

[0020] Figure 1 This is a block diagram depicting a programmable integrated circuit (IC) 102 connected to external memory according to some examples. The programmable IC 102 may be a system-on-a-chip (SoC) and may include or be an IC as a programmable logic device, such as a field-programmable gate array (FPGA). The programmable IC 102 includes a processing system 104, a network-on-chip (NoC) 106, a configuration interconnect 108, one or more programmable logic regions 110a to 110n (generally, individually, or collectively referred to as "(a plurality of) programmable logic regions 110"), a memory controller 112, a multi-gigabit transceiver (MGT) 114, input / output blocks (IO) 116, and other IP circuitry 118. NoC 106 includes a routing network 120 and NoC peripheral interconnects (NPI) 122.

[0021] Typically, processing system 104 is connected to programmable logic regions (PLRs) 110 via configuration interconnect 108. Processing system 104, PRLs 110, memory controller 112, MGT 114, I / O 116, and other IP circuitry 118 are also connected to NoC 106 (e.g., routing network 120) and are therefore communicatively coupled to each other via NoC 106 (e.g., routing network 120). Processing system 104, memory controller 112, MGT 114, I / O 116, and other IP circuitry 118 are also connected to corresponding subsets of PRLs 110. For example, each of processing system 104, I / O 116, and other IP circuitry 118 is connected to programmable logic region 110a, and each of memory controller 112 and MGT 114 is connected to programmable logic region 110n. Various circuits can be connected to any subset of the programmable logic regions 110, and circuits can be connected to a given subset of the programmable logic regions 110 in any combination with any other circuits. Additionally, in some examples, the memory controller 112 can be connected to at least one of the I / O 116.

[0022] The processing system 104 may include one or more processor cores. For example, the processing system 104 may include multiple ARM-based embedded processor cores.

[0023] The multiple programmable logic regions 110 may include any number of configurable logic blocks, lookup tables (LUTs), digital signal processing blocks, random access memory blocks, and programmable interconnect elements, as described below. The multiple programmable logic regions 110 can be programmed or configured using the processing system 104 via configuration interconnect 108. For example, configuring interconnect 108 can enable frame-based programming of the structure of the multiple programmable logic regions 110, for example, by a processor core of the processing system 104 (e.g., a platform management controller (PMC)).

[0024] The routing network 120 of NoC 106 provides routing for NoC packets between different systems or circuits. The routing network 120 includes NoC packet switches interconnected via line segments between NoC Master Units (NMUs) and NoC Slave Units (NSUs). Each NMU is an ingress circuit connecting a master circuit to the NoC 106. Each NSU is an egress circuit connecting the NoC 106 to a slave endpoint circuit. Each NoC packet switch performs the switching of NoC packets. Therefore, the NMUs, NoC packet switches, and NSUs can be configured to provide a channel for communication between master endpoint circuits and slave endpoint circuits via the NMUs, the line-interconnected NoC packet switches, and the NSUs. The NMUs, NoC packet switches, and NSUs also include register blocks that are written to configure the respective NMUs, NoC packet switches, and NSUs. These register blocks can be written via NPI 122. For example, the PMC of processing system 104 can transmit memory-mapped write requests to the NMU, NoC packet switch, and NSU via NPI 122 to write register blocks to configure the NMU, NoC packet switch, and NSU. NPI 122 may include interconnected NPI switches that can route memory-mapped write requests to the appropriate register blocks.

[0025] IO 116 can be any input / output circuit used to couple the programmable IC 102 to communicate with other circuitry and / or the system. In some examples, IO 116 may include high-bandwidth memory (HBM) interface circuitry, high-density input / output (HDIO) circuitry, peripheral component interconnect fast (PCIe) circuitry, extreme performance input / output (XPIO) circuitry, etc. Other IP circuitry 118 can be, for example, a digital clock manager, an analog-to-digital converter, system monitoring logic, and / or any circuitry for a given implementation. In some examples, at least some of the memory controller 112, MGT 114, IO 116, and / or other IP circuitry 118 are configurable. For example, the memory controller 112, MGT 114, IO 116, and / or other IP circuitry 118 may be configurable via NPI 122 of NoC106.

[0026] In some examples, the programmable IC 102 includes interface and control logic 124. In other examples, the interface and control logic 124 is on a separate IC from the programmable IC 102 (e.g., as shown by dashed lines). The interface and control logic 124 is connected to external memory 126. For example, external memory 126 may be memory in a single die or multiple dies. In some examples, external memory 126 is random access memory (RAM), such as dynamic RAM (DRAM) that can be implemented as high-bandwidth memory (HBM).

[0027] In some examples, the interface and control logic 124 is directly connected to the memory controller 112, while in other examples, the interface and control logic 124 is connected via IO 116 of programmable IC 102 and IO 128 of another IC (e.g., as shown in the image). Figure 1 (As shown by the dashed arrow in the diagram) Communication is coupled to memory controller 112. In some examples where programmable IC 102 includes interface and control logic circuitry 124, memory controller 112 is directly connected to interface and control logic circuitry 124 (e.g., without intervening in the physical layer (PHY) interface), which in turn is connected to external memory 126. In some examples where interface and control logic circuitry 124 is in an IC separate from programmable IC 102, memory controller 112 is directly connected to interface and control logic circuitry 124 (e.g., without intervening in the physical layer (PHY) interface), which in turn is connected to external memory 126. In some examples where interface and control logic circuitry 124 is in an IC separate from programmable IC 102, memory controller 112 is directly connected to IO 116 (e.g., HBM interface), and IO 116 is connected to IO 128 of a separate IC (e.g., HBM interface), which is connected to interface and control logic circuitry 124. Interface and control logic circuitry 124 is also connected to external memory 126. Therefore, in these examples, the memory controller 112 is communicatively coupled to the external memory 126.

[0028] In some examples, and detailed below, programmable IC 102, interface and control logic circuitry 124 (if on a separate IC), and external memory 126 can be included in a die stacked to form a multi-chip structure. This multi-chip structure can have a smaller package size and can be manufactured using reduced processing, which can increase yield and reduce the time required to manufacture the multi-chip structure.

[0029] Figure 2 The following examples illustrate what can be implemented as Figure 1The programmable IC 102 is a field-programmable gate array (FPGA) of the programmable IC 200. The programmable IC 200 includes a large number of different programmable blocks, including configurable logic blocks (CLBs) 202, random access memory blocks (BRAMs) 204, signal processing blocks (DSPs) 206, input / output blocks (IOBs) 208, configuration and clock logic (CONFIG / CLOCKS) 210, dedicated input / output blocks (I / O) 212 (e.g., configuration ports and clock ports), and other programmable logic 214, such as digital clock managers, system monitoring logic, etc. The programmable IC 200 may also include boundary circuitry, such as an MGT 216, a memory controller (MC) 218, interface and control logic circuitry (INT / CNTL) 220, and other IP circuitry 222, such as PCIe interfaces, analog-to-digital converters (ADCs), etc. The boundary circuitry can also be programmable.

[0030] In some FPGAs, each programmable block may include at least one programmable interconnect element (INT) 230, which has connections to input and output terminals 232 of programmable logic elements within the same block, such as... Figure 2 The example included is shown. Each programmable interconnect element 230 may also include a connection to interconnect segments 234 of adjacent programmable interconnect elements in the same block or other blocks. Each programmable interconnect element 230 may also include a connection to interconnect segments 236 of a general routing resource between logic blocks (not shown). The general routing resource may include a routing path between a logic block (not shown) that includes an interconnect segment (e.g., interconnect segment 236) and a switch block (not shown) for connecting the interconnect segments. The interconnect segment of the general routing resource (e.g., interconnect segment 236) may span one or more logic blocks. The programmable interconnect elements 230, together with the general routing resources, implement a programmable interconnect structure for the FPGA shown.

[0031] In the example implementation, CLB 202 may include configurable logic elements (CLEs) 240 that can be programmed to implement user logic, plus a single programmable interconnect element 230. In addition to one or more programmable interconnect elements 230, BRAM 204 may also include BRAM logic elements (BRLs) 242. Typically, the number of programmable interconnect elements 230 included in a block depends on the height of the block. In the depicted example, BRAM 204 has the same height as five CLBs 202, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements 230, signal processing block 206 may also include DSP logic elements (DSPLs) 244. In addition to one instance of programmable interconnect elements 230, IOB 208 may also include, for example, two instances of input / output logic elements (IOLs) 246. Those skilled in the art will appreciate that the actual I / O pads connected to, for example, the input / output logic elements 246 are typically not limited to the area of ​​the input / output logic elements 246.

[0032] In the illustrated example, the horizontal region near the center of the die is used for configuration and clock logic (CONFIG / CLOCKS) 210, and may be used for other control logic. The vertical column 248 extending from this horizontal region or column is used to distribute clock and configuration signals across the width of the FPGA.

[0033] use Figure 2 Some FPGAs in the illustrated architecture may include additional logic blocks that disrupt the conventional columnar structure that makes up most of the FPGA. These additional logic blocks can be programmable blocks and / or dedicated logic.

[0034] Notice, Figure 2 This is intended to illustrate only example FPGA architectures. For example, in Figure 2 The number of logic blocks in a row at the top, the relative width of the row, the number and order of rows, the types of logic blocks included in the row, the relative size of the logic blocks, and the interconnect / logic implementation are just examples. For instance, in a real FPGA, more than one adjacent CLB row is typically included wherever a CLB appears to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

[0035] Figure 3 These are circuit diagrams based on some examples of multi-chip structures. Figure 3 The multi-chip structure includes a programmable IC 102 and a memory 302, wherein the memory 302 can be located in multiple dies stacked on a die including the programmable IC 102. Figure 3In a simplified version, the programmable IC 102 includes a programmable logic region 110, a bus 304, a memory controller 112, and interface and control logic circuitry 124. For example, the programmable logic region 110 (or other subsystems, such as processing system 104 and / or NoC 106) is connected to the memory controller 112 via bus 304, which may be an Advanced Scalable Interface (AXI) bus. The memory controller 112 is connected to the interface and control logic circuitry 124.

[0036] Each of the memories 302 includes multiple memory slices 306. In some examples, each memory slice 306 may be a 2 gigabyte (Gb) memory or other sizes. Each of the memories 302 may implement DRAM and may further implement HBM. In some examples, each of the memories 302 may implement 32Gb HBM DRAM. Interface and control logic 124 is connected to the memory slices 306 of the memories 302. The interface and control logic 124 can decode read and write requests from the memory controller 112 and responsively transmit native signals to the memories 302 to read from or write to the memories 302. There is no standardized physical layer interface circuitry between the memory controller 112 and the memory slices 306 of the memories 302 to encapsulate and decapsulate read and write requests having and from standardized forms. For example, if the memories 302 implement HBM, there is no HBM interface between the memory controller 112 and the memory slices 306.

[0037] Figure 4 This is a circuit diagram of another multi-chip structure based on some examples. Figure 4 The multi-chip structure is similar to Figure 3 The multi-chip architecture differs in that two die stacks, including memory 302, are stacked on a die including programmable IC 102. Programmable IC 102 also includes an additional bus 304, a memory controller 112, and interface and control logic circuitry 124 to accommodate the additional die stack including memory 302.

[0038] exist Figure 3 and 4 In one example, the interface and control logic circuitry 124 is included within a corresponding die including the programmable IC 102. In other examples, another control die (separate from the die including the programmable IC 102) may include multiple interface and control logic circuitry 124 and may be situated between the die including the programmable IC 102 and a stack of dies including the memory 302. The circuit diagram of such an example will be similar to... Figure 3 and 4 They are the same, except that they indicate separate control dies.

[0039] Figure 5 This is a circuit diagram of yet another multi-chip structure based on some examples. Figure 5 The multi-chip architecture implements the HBM interface (e.g., as a PHY interface) between the memory controller 112 and the memory slice 306. Figure 5 The multi-chip structure includes a programmable IC 102, a control IC 502, and a memory 302, wherein the control IC 502 is stacked on a die including the programmable IC 102 and is separate from the die including the programmable IC 102, and the memory 302 can be located in multiple dies stacked on the die including the control IC 502. Figure 5 In a simplified version, the programmable IC 102 includes a programmable logic region 110, a bus 304, a memory controller 112, and an HBM interface (HBM PHY) 504. The programmable logic region 110 (or other subsystems, such as processing system 104 and / or NoC 106) is connected to the memory controller 112 via the bus 304, and the memory controller 112 is connected to the HBM interface 504. The HBM interface 504 is configured to encapsulate read and write requests from the memory controller 112 into, for example, a normalized HBM format, and to unpack responses from the memory 302 from the normalized HBM format into a format usable by the memory controller 112.

[0040] The control IC 502 includes an HBM interface (HBM PHY) 506 and interface and control logic 124. The HBM interface 506 of the control IC 502 is connected to the HBM interface 504 of the programmable IC 102. The HBM interface 506 is configured to unpack read and write requests from the HBM interface 504 from, for example, a standardized HBM format into a native format usable by the interface and control logic 124, and to package responses from the memory 302 into a standardized HBM format for transmission to the HBM interface 504 of the programmable IC 102. The interface and control logic 124 can decode read and write requests from the HBM interface 506 and responsively transmit native signals to the memory 302 to read from or write to the memory 302 on various memory dies. Figure 5 The circuit diagram can be modified to achieve the same Figure 3 and Figure 4 The differences between them are similar to those between individual memory die stacks.

[0041] Figure 6This is a configuration of a multi-chip structure on a printed circuit board (PCB) 602, based on some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, and a memory die 608 stacked on the base die 606. The base die 606 includes a programmable IC 102, for example... Figure 3 In and / or 4, and each of the memory dies 608 includes a memory 302, for example in Figure 3 And / or 4.

[0042] The multi-chip architecture includes a stack of four memory dies 608, but other examples can implement any number of memory dies 608 in any number of stacks. Each memory die 608 has an external connector 610, such as a microbump, attached to the active side of the memory die 608 and to the back side of the underlying die. Each memory die 608 may include a substrate via (TSV) through a semiconductor substrate on which the memory 302 of the corresponding memory die 608 is formed. The TSV may be implemented to electrically connect the memory 302 of the overlying memory die 608 to the corresponding memory die 608 and / or the underlying die.

[0043] The programmable IC 102 based on the 606 base die includes, for example: Figure 3 The interface and control logic circuitry 124 shown in Figure 4. The bottom memory die 608 of the stacked memory dies 608 has an external connector 610 attached to the active side of the bottom memory die 608 and the back side of the base die 606. The base die 606 may include a TSV through a semiconductor substrate on which, for example, a programmable IC 102 is formed. The TSV may be implemented to electrically connect the memory 302 overlying the memory die 608 to the programmable IC 102. The base die 606 also has an external connector 612, such as a controlled collapse chip connection (C4) bump, attached to a first side of the package substrate 604 and opposite to the first side. An external connector 614, such as a ball grid array (BGA) ball, is attached to a second side of the package substrate 604 opposite to the first side, and the external connector 614 is further attached to the PCB 602.

[0044] Figure 7 This is another configuration of a multi-chip structure on a PCB 602, based on some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 702 on the base die 606, and a memory die 608 stacked on the control die 702. The base die 606 includes a programmable IC 102 without interfaces and control logic circuitry 124, such as in... Figure 3 And / or 4. The control die 702 includes a control IC with an interface and control logic circuitry 124, such as in Figure 3And / or 4. Each memory die 608 includes a memory 302, such as in Figure 3 And / or 4.

[0045] Just like in Figure 6 middle, Figure 7 The multi-chip architecture includes a stack of four stacked memory dies 608, but other examples can implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the stack has an external connector 610 attached to the active side of the bottom memory die 608 and the back side of the control die 702. The control die 702 may include a TSV through a semiconductor substrate, on which, for example, the logic structure (e.g., transistors) of the control die 702 is formed. The TSV may be implemented as a control IC (e.g., interface and control logic circuitry 124) electrically connecting the memory 302 overlying the memory die 608 to the control die 702 and / or the programmable IC 102. The active side of the control die 702 is attached to the back side of the base die 606. For example, the active side of the control die 702 may be bonded to the back side of the base die 606 via wafer bonding or other bonding techniques, such as oxide-to-oxide and / or metal-to-metal bonding. The base die 606 has an external connector 612 attached to the active side of the base die 606 and to a first side of the package substrate 604. An external connector 614 is attached to a second side of the package substrate 604 opposite to the first side, and the external connector 614 is further attached to the PCB 602.

[0046] Figure 8 This is another configuration of a multi-chip structure on PCB 602, based on some examples. The multi-chip structure includes a package substrate 604, a base die 606 on the package substrate 604, a control die 802 on the base die 606, and a memory die 608 stacked on the control die 802. The base die 606 includes a programmable IC 102, such as... Figure 5 More specifically, the programmable IC 102 also includes, for example, Figure 5 The HBM interface 504 is shown. The control die 802 includes a control IC 502, such as in... Figure 5 More specifically, the control IC 502 of the control die 802 includes interface and control logic circuitry 124 and HBM interface 506, such as... Figure 5 As shown. Each memory die 608 includes a memory 302, such as in Figure 5 middle.

[0047] Just like in Figure 6 middle, Figure 8The multi-chip architecture includes a stack of four stacked memory dies 608, but other examples can implement any number of memory dies 608 in any number of stacks. The bottom memory die 608 of the stack has an external connector 610 attached to the active side of the bottom memory die 608 and the back side of the control die 802. The control die 802 may include a TSV through a semiconductor substrate, on which, for example, a logic structure (e.g., transistors) of a control IC 502 is formed. The TSV may be implemented as electrically connecting the memory 302 overlying the memory die 608 to the control die 802 and / or the control IC 502 of the programmable IC 102. The control die 802 has an external connector 804, such as a microbump, attached to the active side of the control die 802 and to the back side of the base die 606. The base die 606 has an external connector 612 attached to the active side of the base die 606 and to a first side of the package substrate 604. An external connector 614 is attached to the second side of the packaging substrate 604 opposite to the first side, and the external connector 614 is further attached to the PCB 602.

[0048] Although various dies with specified orientations (e.g., certain active sides of dies attached to the back of other dies) have been described, regarding Figures 6 to 8 Various multi-chip structures are described, but these orientations are provided as examples. Any die (e.g., any base die 606, memory die 608, control die 702 and / or control die 802) may be flipped relative to the description provided above or may have any other orientation.

[0049] The multi-chip architecture described above can be a programmable, dense memory device. Programmable devices with dense memory utilizing HBM logic and stacking technology can be implemented using this architecture. The performance advantages associated with programmable ICs (e.g., FPGAs) can be maintained while achieving faster and simpler manufacturing, lower manufacturing costs, and lower power consumption.

[0050] Some examples can be implemented using any kind of programmable IC. For example, a programmable IC can be a Application Standard Part (ASSP) IC with, for example, configurable input / output circuitry and interfaces. Some examples can be implemented using multi-port memory with a host interface, such as n×PCIe Genx, n×100GE, n×40G, n×10GE, 112G PAM4, etc.

[0051] Figure 9 This is a flowchart of a method 900 for forming a multi-chip structure, based on some examples. In block 902, a base die is formed. For example, the base die could be... Figures 6 to 8The base die is 606, and it can be formed through front and back semiconductor processes to realize programmable ICs and TSVs in the base die.

[0052] Optionally, a control die is formed in block 904. For example, the control die could be... Figure 7 Control dies 702 and / or 802, and similarly, can be formed using front and back semiconductor processes to implement the control IC and TSV within the control die. Optionally, in block 906, the control die is attached to the base die. For example, the control die can be bonded to the base die via wafer-to-wafer bonding during the processing of both the control die and the base die (e.g., prior to monolithic die formation). As another example, the control die can be attached to the base die using an external connector (e.g., microbumps), which may include a return flow external connector for attaching the control die to the base die. In some examples, no control die is implemented, for example, to form Figure 6 The multi-chip structure eliminates the need to form a control die in block 904 and attach the control die to the base die in block 906.

[0053] In box 908, a memory die stack is formed. For example, the memory die stack could be... Figures 6 to 8 The memory die 608, and each memory die can be formed by front and back semiconductor processes to realize memory and TSV in the memory die, except that the back semiconductor process and TSV can be omitted for the top memory die. The memory dies can be attached to each other in a stack, for example by using external connectors such as microbumps, which may include return external connectors to attach the memory dies together.

[0054] In box 910, the memory die stack is attached to a base die or control die (if implemented). An external connector (e.g., microbumps) can be used to attach the memory die stack to the base die (e.g., as shown in Figure 910). Figure 6 (in the middle) or control die (e.g., such as Figure 7 (Or 8), this may include a return-to-external connector to attach the memory die stack to the base die or control die. As mentioned above, the order of operations can vary. For example, when implementing a control die, such as in Figure 8 In this process, memory dies can be stacked and attached to the control die before the control die is attached to the base die.

[0055] In box 912, the base die is attached to the packaging substrate. For example, the packaging substrate could be... Figures 6 to 8 The packaging substrate 604 can be attached to the base die using an external connector (e.g., a C4 bump), which may include a return external connector to attach the base die to the packaging substrate.

[0056] In box 914, the package substrate is attached to the PCB. For example, the PCB substrate could be... Figures 6 to 8 The PCB 602 can be attached to the package substrate using an external connector (e.g., a BGA ball), which may include a reflow external connector to attach the package substrate to the PCB.

[0057] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

[0058] In some examples of the multi-chip architecture described above, the first die may include a semiconductor substrate. A through-substrate via (TSV) may pass through the semiconductor substrate. The memory controller may be coupled to the memory via TSV communication.

[0059] In some examples of the multi-chip structure described above, the second die can be attached to the side of the first die opposite to the packaging substrate via an external electrical connector.

[0060] In some examples of the multi-chip architecture described above, there may be no communication setup or electrical physical layer interface between the memory controller and the memory.

[0061] In some examples of the multi-chip architecture described above, the first die may include control logic circuitry, and the control logic circuitry may be communicatively disposed between the memory controller and the memory.

[0062] In some examples, the multi-chip architecture described above may further include a third die, which includes control logic circuitry. The third die may be stacked on and attached to the side of the first die opposite to the package substrate. A second die may be stacked on and attached to the side of the third die opposite to the first die. The control logic circuitry may be communicatively disposed between the memory controller and the memory. The third die may be bonded to the first die. The third die may be attached to the side of the first die opposite to the package substrate via an external electrical connector. The second die may be attached to the side of the third die opposite to the first die via an external electrical connector. There may be no communication and electrical physical layer interface between the memory controller and the memory. The first die may include a first physical layer interface communicatively coupled to the memory controller. The third die may include a second physical layer interface communicatively coupled to the first physical layer interface and the control logic circuitry, and between them.

[0063] In some examples of the multi-chip architectures described above, programmable integrated circuits include field-programmable gate arrays (FPGAs).

[0064] According to some examples, a method of forming a multi-chip structure includes: stacking a first die on a second die, and attaching the first die to a package substrate. The first die includes a memory. The second die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The memory controller is communicatively coupled to the memory via the first die stacked on the second die.

[0065] In some examples of the above methods, stacking the first die on the second die may include attaching the first die to the second die via an external electrical connector; the second die may include control logic circuitry, with the control logic circuitry communicating between the memory controller and the memory. Furthermore, there may be no communication setup or electrical physical layer interface between the memory controller and the memory.

[0066] In some examples, the method described above may further include attaching a third die to a second die. A first die may be attached to a third die. The third die may include control logic circuitry. The control logic circuitry may be communicatively disposed between the memory controller and the memory.

[0067] According to some examples, a multi-chip architecture includes a package substrate, a first die, and a second die. The first die includes a field-programmable gate array (FPGA) and a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the side of the first die opposite to the package substrate. The memory is communicatively coupled to the memory controller.

[0068] In some examples of the multi-chip architecture described above, there may be no communication setup or electrical physical layer interface between the memory controller and the memory.

[0069] In some examples of the multi-chip architecture described above, the first die may include control logic circuitry. This control logic circuitry may be communicatively positioned between the memory controller and the memory.

[0070] In some examples, the multi-chip architecture described above may further include a third die, which includes control logic circuitry. The third die may be stacked on and attached to the side of the first die opposite to the package substrate. A second die may be stacked on and attached to the side of the third die opposite to the first die. The control logic circuitry may be communicatively disposed between the memory controller and the memory. The first die may include a first physical layer interface communicatively coupled to the memory controller. The third die may include a second physical layer interface communicatively coupled to the first physical layer interface and the control logic circuitry, and between them.

[0071] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from its basic scope, the scope of which is determined by the appended claims.

Claims

1. A multi-chip structure comprising: a package substrate; a first die comprising a programmable integrated circuit, the programmable integrated circuit comprising a memory controller, the first die being directly attached to the package substrate without an intervening layer, wherein the first die comprises a control logic circuit; and a second die comprising a memory, the second die being stacked on the first die, the memory being communicatively coupled to the memory controller, the memory controller being coupled to the package substrate through the programmable integrated circuit; wherein the control logic circuit is communicatively disposed between the memory controller and the memory and is configured to decode read and write requests from the memory controller and responsively transmit native signals to the memory to read from or write to the memory.

2. The multi-chip structure of claim 1, wherein the first die comprises a semiconductor substrate, a through-substrate via (TSV) passing through the semiconductor substrate, the memory controller being communicatively coupled to the memory via the TSV.

3. The multi-chip structure of claim 1, wherein the second die is attached to a side of the first die opposite the package substrate by an external electrical connector.

4. The multi-chip structure of claim 1, wherein there is no communicative and electrical setup physical layer interface between the memory controller and the memory.

5. The multi-chip structure of claim 1, wherein the programmable integrated circuit comprises a field programmable gate array (FPGA).

6. A method of forming a multi-chip structure, the method comprising: stacking a second die on a first die, the second die comprising a memory, the first die comprising a programmable integrated circuit, the programmable integrated circuit comprising a memory controller, the memory controller being communicatively coupled to the memory through the second die stacked on the first die, wherein the first die comprises a control logic circuit, the control logic circuit being communicatively disposed between the memory controller and the memory and being configured to decode read and write requests from the memory controller and responsively transmit native signals to the memory to read from or write to the memory; and directly attaching the first die to a package substrate without an intervening layer, wherein the memory controller is coupled to the package substrate through the programmable integrated circuit.

7. The method of claim 6, wherein: stacking the second die on the first die comprises attaching the second die to the first die by an external electrical connector; there is no communicative and electrical setup physical layer interface between the memory controller and the memory. ​

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