Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate including a body donor; and a first buffer zone of a first conductivity type, which is provided on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate, wherein the doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer zone is less than 50 times the body donor concentration of the semiconductor substrate. The doping concentration of the shallowest concentration peak may be lower than a reference carrier concentration when a current of 1 / 10 of the rated current flows between the upper surface and the lower surface of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, in semiconductor devices such as diodes, there is known a structure in which an N+ type buffer area is provided on the lower surface side of a semiconductor substrate (for example, refer to Patent Documents 1 and 2).

[0003] Patent Document 1: International Publication No. 2011-052787

[0004] Patent Document 2: U.S. Patent Application Publication No. 2015 / 0214347 Summary of the invention

[0005] Technical issues

[0006] It is preferable for a semiconductor device to suppress oscillation during a reverse recovery operation or the like.

[0007] General disclosure

[0008] In order to solve the above-mentioned problems, a semiconductor device is provided in one embodiment of the present invention. The semiconductor device may include a semiconductor substrate including a body donor. The semiconductor device may include a first buffer zone of a first conductivity type provided on the lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate. The doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer zone may be less than 50 times the body donor concentration of the semiconductor substrate.

[0009] The doping concentration of all doping concentration peaks in the first buffer region may be less than 50 times the bulk donor concentration.

[0010] The first buffer region may have more than two doping concentration peaks, and a doping concentration of at least one of the doping concentration peaks may be higher than 50 times of a bulk donor concentration.

[0011] The first buffer region may have more than two doping concentration peaks, and the doping concentration of at least one doping concentration peak may be higher than the doping concentration of the shallowest concentration peak.

[0012] The doping concentration of the shallowest concentration peak may be lower than the doping concentration of the doping concentration peak closest to the shallowest concentration peak.

[0013] The doping concentration of the shallowest concentration peak may be lower than a reference carrier concentration when a current of 1 / 10 of a rated current flows between the upper surface and the lower surface of the semiconductor substrate.

[0014] The semiconductor device may include a groove portion disposed on the upper surface of the semiconductor substrate. When the concentration obtained by integrating the doping concentration of the semiconductor substrate from the lower end of the groove portion toward the lower surface of the semiconductor substrate is set as the integrated concentration, and the position where the integrated concentration reaches the critical integrated concentration of the semiconductor substrate is set as the critical position, the critical position overlaps with the shallowest concentration peak, or the critical position is disposed at a position closer to the groove portion than the shallowest concentration peak.

[0015] The semiconductor device may include a cathode region of the first conductivity type disposed between the shallowest concentration peak and the lower surface of the semiconductor substrate and having a peak value of doping concentration higher than the shallowest concentration peak.

[0016] The semiconductor device may include a lower surface side region of a second conductivity type disposed between the shallowest concentration peak and the lower surface of the semiconductor substrate. The minimum value of the valley portion of the donor concentration between the shallowest concentration peak and the cathode region is smaller than the second concentration peak, and the second concentration peak is adjacent to the shallowest concentration peak at a position closer to the upper surface side of the semiconductor substrate than the shallowest concentration peak.

[0017] The semiconductor device may include a collector region of the second conductivity type provided between the shallowest concentration peak and the lower surface of the semiconductor substrate.

[0018] The semiconductor device may include a transistor portion and a diode portion. The diode portion may include a first buffer portion. The diode portion may include a cathode region of a first conductivity type disposed between the first buffer portion and the lower surface of the semiconductor substrate. The transistor portion may include a second buffer region of a first conductivity type disposed on the lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate. The transistor portion may include a collector region of a second conductivity type disposed between the second buffer portion and the lower surface of the semiconductor substrate.

[0019] The doping concentration of each doping concentration peak in the second buffer zone may be the same as the doping concentration of the doping concentration peak disposed at the same depth position in the first buffer zone.

[0020] The doping concentration of the doping concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the second buffer region may be higher than the doping concentration of the shallowest concentration peak of the first buffer region. The minimum value of the valley of the donor concentration between the shallowest concentration peak and the cathode region may be smaller than the donor concentration at the boundary between the shallowest concentration peak of the second buffer region and the collector region.

[0021] In a second aspect of the present invention, a method for manufacturing a semiconductor device having a transistor portion and a diode portion is provided. The manufacturing method may include an active region forming step of forming an emitter region of the transistor portion and an anode region of the diode portion on the upper surface of a semiconductor substrate containing a body donor. The manufacturing method may include an ion implantation step of implanting a first dopant of a first conductivity type into the transistor portion and the diode portion from the lower surface of the semiconductor substrate by ion implantation, and implanting a second dopant of a first conductivity type into the transistor portion by ion implantation from the lower surface of the semiconductor substrate.

[0022] The depth position at which the first dopant is implanted may be the same as the depth position at which the second dopant is implanted.

[0023] The first dopant may be hydrogen.

[0024] The second dopant may be any one of hydrogen, phosphorus, and arsenic.

[0025] It should be noted that the above summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0027] Figure 2 Yes means Figure 1 A diagram showing an example of the doping concentration distribution and the hydrogen chemical concentration distribution at the kk line.

[0028] Figure 3 1 is a diagram showing an example of a voltage waveform and a current waveform of the semiconductor device 100 during reverse recovery.

[0029] Figure 4 This is a diagram showing an example of the relationship between the current flowing through the semiconductor device 100 and the oscillation threshold voltage.

[0030] Figure 5A 1 is a diagram showing an example of the relationship between the ratio D1 / Db of the doping concentration D1 of the doping concentration peak 25 - 1 and the body donor concentration Db and the oscillation threshold voltage.

[0031] Figure 5B This is an example of the carrier concentration distribution in each region when the current density is 0.1×Jr.

[0032] Figure 6 1 is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer region 20 .

[0033] Figure 71 is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer region 20 .

[0034] Figure 8 1 is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer region 20 .

[0035] Fig. 9 1 is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer region 20 .

[0036] Fig.10 is a cross-sectional view showing another configuration example of the semiconductor device 100 .

[0037] Fig.11 is a cross-sectional view showing another configuration example of the semiconductor device 100 .

[0038] Fig.12 is a plan view showing another example of the semiconductor device 100 .

[0039] Fig.13 yes Fig.12 Magnified view of area A in FIG.

[0040] Fig.14 Yes means Fig.13 A diagram showing an example of the bb cross section in FIG.

[0041] Fig.15 1 is a diagram showing an example of doping concentration distribution in the first buffer region 20 - 1 and the second buffer region 20 - 2 .

[0042] Fig.16 1 is a flowchart showing a part of the steps of a method for manufacturing the semiconductor device 100 .

[0043] Fig.17 This is a diagram showing an example of integrated concentration obtained by integrating the doping concentration of the semiconductor substrate 10 in the depth direction.

[0044] Explanation of symbols

[0045] 10: semiconductor substrate; 11: well region; 12: emitter region; 14: base region; 15: contact region; 16: reservoir region; 18: drift region; 20: buffer region; 21: upper surface; 22: collector region; 23: lower surface; 24: collector electrode; 25: doping concentration peak; 26: first valley; 27: second valley; 28: third valley; 29: straight line portion; 30: dummy groove portion; 31: front end portion; 32: dummy insulating film; 34: dummy conductive portion; 38: interlayer insulating film; 39: straight line portion 40: gate groove; 41: front end; 42: gate insulating film; 44: gate conductive portion; 52: emitter electrode; 54: contact hole; 60, 61: mesa portion; 70: transistor portion; 80: diode portion; 81: extension region; 82: cathode region; 83: lower surface side region; 90: edge terminal structure portion; 100: semiconductor device; 102: end edge; 112: gate pad; 125: hydrogen concentration peak; 130: peripheral gate wiring; 131: active side gate wiring; 160: active portion DETAILED DESCRIPTION

[0046] The present invention will be described below by way of the embodiments of the invention, but the following embodiments are not intended to limit the invention of the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0047] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0048] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to the height direction relative to the ground. It should be noted that the +Z axis direction and the -Z axis direction are opposite directions to each other. When the Z axis direction is recorded without recording the positive and negative, it refers to the direction parallel to the +Z axis and the -Z axis.

[0049] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the Z-axis direction is sometimes referred to as the depth direction. In addition, in this specification, the direction parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, is sometimes referred to as the horizontal direction.

[0050] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0051] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, the so-called impurity sometimes refers to a specific N-type donor or a P-type acceptor, and sometimes is described as a dopant. In this specification, the so-called doping refers to introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0052] In this specification, the so-called doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the so-called net doping concentration refers to the net concentration obtained by setting the donor concentration to the concentration of positive ions and the acceptor concentration to the concentration of negative ions, including the polarity of the charge. As an example, if the donor concentration is N D And the acceptor concentration is set to N A , then the net doping concentration at any position becomes N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0053] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of accepting electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect formed by a combination of vacancies (V), oxygen (O), and hydrogen (H) present in a semiconductor functions as a donor for supplying electrons. In this specification, a VOH defect is sometimes referred to as a hydrogen donor.

[0054] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. In addition, when it is described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0055] In this specification, the so-called chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation. The chemical concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance determination (CV method). In addition, the carrier concentration measured by the extended resistance determination method (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be set to a value in thermal equilibrium. In addition, since the donor concentration in the N-type region is much greater than the acceptor concentration, the carrier concentration in the region can also be set to the donor concentration. Similarly, in the P-type region, the carrier concentration in the region can also be set to the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0056] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor or net doping in the region. When the concentration of the donor, acceptor or net doping is approximately uniform, the average value of the concentration of the donor, acceptor or net doping in the region can be used as the concentration of the donor, acceptor or net doping.

[0057] The carrier concentration measured by the SR method can be lower than the concentration of the donor or acceptor. In the range of current flow when measuring the spreading resistance, the carrier mobility of the semiconductor substrate is sometimes lower than the value in the crystal state. The reduction in carrier mobility is caused by the disorder (disorder) of the crystal structure caused by lattice defects, etc., which causes the carriers to scatter.

[0058] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic that serves as a donor in a silicon semiconductor, or the acceptor concentration of boron that serves as an acceptor, is about 99% of their chemical concentrations. On the other hand, the donor concentration of hydrogen that serves as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is used. In this specification, the units of distance and length are sometimes expressed in cm (centimeter). In this case, each calculation can be converted to m (meter) for calculation.

[0059] Figure 1 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes at least one of a transistor element such as an insulated gate bipolar transistor (IGBT) and a diode element such as a freewheeling diode (FWD). Figure 1 2 shows a semiconductor device 100 provided with a diode element.

[0060] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 of this example has a first conductivity type (N type) body donor distributed throughout. The body donor is a donor formed by a dopant contained in the ingot substantially uniformly when manufacturing an ingot that is a raw material of the semiconductor substrate 10. The body donor of this example is an element other than hydrogen. The dopant of the body donor is, for example, phosphorus, antimony, arsenic, selenium, and sulfur, but is not limited thereto. The body donor of this example is phosphorus. In this case, the body donor concentration can be the minimum value of the phosphorus concentration in the semiconductor substrate 10. The body donor is also contained in the P-type region. The semiconductor substrate 10 can be a wafer cut from a semiconductor ingot, or a chip formed by singulating a wafer. The semiconductor ingot can be manufactured by any one of the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), and the floating zone melting method (FZ method). The ingot of this example is manufactured by the MCZ method. The bulk donor concentration Db may use the chemical concentration of donors distributed throughout the semiconductor substrate 10 , or may be a value between 90% and 100% of the chemical concentration.

[0061] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are two main surfaces of the semiconductor substrate 10. In this specification, the axes orthogonal to the planes parallel to the upper surface 21 and the lower surface 23 are set as the X axis and the Y axis, and the axis perpendicular to the upper surface 21 and the lower surface 23 is set as the Z axis.

[0062] The semiconductor substrate 10 of this example has a base region 14, a drift region 18, and a buffer region 20. The drift region 18 of this example is an N-type region. The buffer region 20 is arranged on the lower surface 23 side of the semiconductor substrate 10. The buffer region 20 is an N-type region with a doping concentration higher than that of the drift region 18. The so-called lower surface 23 side is a region within a distance of T / 2 in the depth direction from the lower surface 23 when the thickness in the depth direction (Z-axis direction) of the semiconductor substrate 10 is set to T. The buffer region 20 can be set in a region within T / 4 from the lower surface 23.

[0063] The buffer region 20 has a doping concentration peak 25 having a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the doping concentration peak 25 refers to the doping concentration at the top of the doping concentration peak 25. In addition, the doping concentration of the drift region 18 can use the average value of the doping concentration in the region where the doping concentration distribution is roughly flat. The so-called region where the doping concentration distribution is roughly flat can be a region where the variation of the doping concentration is within ±10% and has a width of more than 10μm in the depth direction. The buffer region 20 of this example has multiple doping concentration peaks 25 in the depth direction (Z-axis direction) of the semiconductor substrate 10.

[0064] The buffer region 20 of this example is formed by implanting hydrogen ions such as protons into the semiconductor substrate 10 and performing a heat treatment. The hydrogen ions may be implanted from the lower surface 23 of the semiconductor substrate 10 or from the upper surface 21 .

[0065] The base region 14 is a P-type region disposed between the drift region 18 and the upper surface 21 of the semiconductor substrate 10. When the semiconductor device 100 is a diode, the base region 14 functions as an anode region of the diode. When the semiconductor device 100 is a transistor, a channel is formed in the base region 14 facing the gate electrode. Figure 1 The base region 14 is in contact with the drift region 18. In other examples, other regions may be provided between the base region 14 and the drift region 18. The base region 14 may be in contact with the upper surface 21 of the semiconductor substrate 10.

[0066] The semiconductor substrate 10 of this example has an N+ type cathode region 82 disposed between the buffer region 20 and the lower surface 23. The cathode region 82 is disposed in contact with the lower surface 23. In the case where the semiconductor device 100 is a transistor, the semiconductor substrate 10 has a P+ type collector region disposed between the buffer region 20 and the lower surface 23. The collector region 22 is disposed in contact with the lower surface 23. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region or the N+ type cathode region 82.

[0067] Electrodes are provided on the upper surface 21 and the lower surface 23 of the semiconductor substrate 10, respectively. Figure 1 Each electrode may be formed of a metal material including aluminum or the like. In this example, the electrode disposed on the upper surface 21 is in contact with the base region 14 , and the electrode disposed on the lower surface 23 is in contact with the cathode region 82 .

[0068] Figure 2 Yes means Figure 1 FIG. 1 is a diagram showing an example of doping concentration distribution and hydrogen chemical concentration distribution at the kk line of FIG. The kk line is a line that crosses the buffer zone 20 and is parallel to the Z axis. The buffer zone 20 of this example is formed by implanting hydrogen ions from the lower surface 23 to a predetermined depth position.

[0069] In the area through which the hydrogen ions injected from the lower surface 23 pass, lattice defects are formed, which are mainly composed of vacancies such as single atomic vacancies (V) and polyatomic vacancies (VV). The atoms adjacent to the vacancies have dangling bonds. Lattice defects also include lattice interstitial atoms, dislocations, etc., and in a broad sense, can also include donors and acceptors, but in this specification, lattice defects mainly composed of vacancies are sometimes referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In addition, since more lattice defects are formed by injecting hydrogen ions into the semiconductor substrate 10, the crystallinity of the semiconductor substrate 10 is sometimes strongly disordered. In this specification, the disorder of the crystallinity is sometimes referred to as disorder. In addition, hydrogen (H), vacancies (V) and oxygen (O) injected into the buffer zone 20 combine and form VOH defects. Furthermore, hydrogen is diffused by thermal annealing, thereby promoting the formation of VOH defects. VOH defects function as donors that supply electrons. In this specification, VOH defects are sometimes referred to as hydrogen donors. The buffer zone 20 in this example includes hydrogen donors. The hydrogen donors may also be included in the region between the two doping concentration peaks 25. The doping concentration of the hydrogen donors is lower than the chemical concentration of hydrogen. If the ratio of the doping concentration of the hydrogen donors to the chemical concentration of hydrogen is set as the activation rate, the activation rate may be a value of 0.1% to 30%. In this example, the activation rate is 1% to 5%.

[0070] The hydrogen chemical concentration distribution of the buffer zone 20 has one or more hydrogen concentration peaks 125 at the depth position where hydrogen ions are injected. The hydrogen chemical concentration distribution of this example has multiple hydrogen concentration peaks 125-1, 125-2, 125-3, and 125-4. The higher the hydrogen chemical concentration, the easier it is for the above-mentioned VOH defects to form. Therefore, the doping concentration distribution of the buffer zone 20 has one or more doping concentration peaks 25 at the depth position corresponding to each hydrogen concentration peak 125. The doping concentration peak 25 of the buffer zone 20 can be a concentration peak of a hydrogen donor. The doping concentration distribution of this example has multiple doping concentration peaks 25-1, 25-2, 25-3, and 25-4.

[0071] The number of doping concentration peaks 25 may be consistent with the number of hydrogen concentration peaks 125. In addition, the doping concentration peaks 25 and the hydrogen concentration peaks 125 may be arranged at the same depth position. The peaks being arranged at the same depth position may mean that the apex of one peak is arranged within the half-maximum full width of another peak.

[0072] In addition, since VOH defects are also formed in the hydrogen diffusion region, the doping concentration in the region between the two doping concentration peaks 25 is likely to increase. Therefore, the region between the doping concentration peaks 25 is likely to have a higher concentration than the drift region 18 .

[0073] In this example, hydrogen ions are implanted from the lower surface 23 side of the semiconductor substrate 10. Therefore, in the hydrogen chemical concentration distribution, the hem Sh1 extending from the apex of the hydrogen concentration peak 125 to the lower surface 23 side is more gentle than the hem Sh2 extending from the apex of each hydrogen concentration peak 125 to the upper surface 21 side. That is, the inclination of the hem Sh1 is smaller than the inclination of the hem Sh2. Similarly, in the doping concentration distribution, the hem Sd1 extending from the apex of the doping concentration peak 25 to the lower surface 23 side can also be more gentle than the hem Sd2 extending from the apex of each doping concentration peak 25 to the upper surface 21 side. That is, the inclination of the hem Sd1 can be smaller than the inclination of the hem Sd2.

[0074] The peak closest to the lower surface 23 of the semiconductor substrate 10 among the doping concentration peaks 25 of the buffer region 20 is set as the shallowest concentration peak. In this example, the doping concentration peak 25-1 is the shallowest concentration peak. The doping concentration D1 of the doping concentration peak 25-1 is below a predetermined threshold concentration Dth. The threshold concentration Dth may be 50 times the body donor concentration Db of the semiconductor substrate 10. The threshold concentration Dth may be 30 times, 20 times, or 10 times the body donor concentration Db.

[0075] By setting the doping concentration of the doping concentration peak 25 - 1 , which is the shallowest concentration peak, to be lower than the threshold concentration Dth, depletion of carriers in the semiconductor device 100 during reverse recovery or the like can be suppressed, and oscillation of voltage or current waveforms can be suppressed.

[0076] In this example, the doping concentrations D1, D2, D3, and D4 of all the doping concentration peaks 25-1, 25-2, 25-3, and 25-4 of the buffer zone 20 are below the threshold concentration Dth. Thus, the oscillation of the voltage or current waveform can be further suppressed. The farther away from the lower surface 23, the smaller the doping concentration of the doping concentration peak 25 can be. However, the doping concentration D4 of the doping concentration peak 25-4 configured farthest from the lower surface 23 can be greater than the doping concentration D3 of the adjacent doping concentration peak 25-3. The doping concentration between the doping concentration peak 25-1 and the cathode region 82 can have a valley-shaped concentration distribution, namely the first valley 26. The minimum value Dv1 of the doping concentration of the first valley 26 can be the minimum value of the donor concentration. The minimum value Dv1 of the doping concentration or the donor concentration can be less than the doping concentration D2 of the doping concentration peak 25-2. Thus, the depletion of carriers during reverse recovery and the like can be further suppressed, and the oscillation of the voltage or current waveform can be suppressed. The minimum value Dv1 of the doping concentration or the donor concentration may be equal to or lower than a predetermined threshold concentration Dth.

[0077] In addition, the peak value of the doping concentration of the cathode region 82 is higher than the doping concentration of the doping concentration peak 25 - 1 . The peak value of the doping concentration of the cathode region 82 may be higher than the doping concentration of any doping concentration peak 25 in the buffer region 20 .

[0078] Figure 3 1 is a diagram showing an example of a voltage waveform and a current waveform of the semiconductor device 100 during reverse recovery. The voltage waveform is a waveform of a voltage applied between the electrode on the upper surface 21 and the electrode on the lower surface 23. In addition, the current waveform is a waveform of a current flowing between the electrode on the upper surface 21 and the electrode on the lower surface 23. Figure 3 In FIG. 1 , the waveform of the comparative example is indicated by a dotted line, and the waveform of the semiconductor device 100 is indicated by a solid line. Figure 3 In the example of FIG. 1 , the ambient temperature is set to 25° C., and the current in the on-state of the semiconductor device 100 is set to 1 / 10 of the rated current. In addition, in the comparative example, the doping concentration of the shallowest concentration peak 25-1 is approximately 100 times the body donor concentration Db. The doping concentrations of the other doping concentration peaks 25 are the same in both the comparative example and the semiconductor device 100.

[0079] If the doping concentration of the doping concentration peak 25 of the buffer region 20 is high, the number of holes near the doping concentration peak 25 decreases. Therefore, during the reverse recovery of the semiconductor device 100, carriers are easily depleted near the doping concentration peak 25. If carriers are locally depleted before the reverse recovery operation is completed, oscillations may occur in the voltage and current waveforms during the reverse recovery. In particular, if carriers are depleted near the lower surface 23 of the semiconductor substrate 10, oscillations may occur in the voltage and current waveforms during the reverse recovery.

[0080] In the comparative example, the doping concentration of the doping concentration peak 25-1 arranged near the lower surface 23 is high. Therefore, large swings are generated in the voltage waveform and the current waveform of the comparative example. On the other hand, in the semiconductor device 100, the doping concentration of the doping concentration peak 25-1 arranged near the lower surface 23 is set to be 50 times or less of the body donor concentration Db. Therefore, the swings are suppressed in the voltage waveform and the current waveform of the semiconductor device 100.

[0081] Figure 4 This is a diagram showing an example of the relationship between the current flowing through the semiconductor device 100 and the oscillation threshold voltage. Figure 4 The horizontal axis of represents the current density of the current flowing between the electrode on the upper surface 21 and the electrode on the lower surface 23 of the semiconductor device 100. The current density when the rated current flows through the semiconductor device 100 is Jr. The current density when the current of 1 / 10 of the rated current flows is 0.1×Jr. Figure 3As shown in the comparative example, the so-called oscillation threshold voltage is the voltage between the anode and the cathode when an oscillation with an amplitude greater than a predetermined amplitude begins to occur in the voltage waveform and the current waveform. As an example, the so-called predetermined amplitude is set to the amplitude during the time when the absolute value of the voltage between the anode and the cathode is greater than the power supply voltage. In addition, as an example, the so-called oscillation with an amplitude greater than a predetermined amplitude means that the absolute value of the voltage between the anode and the cathode increases sharply over time relative to the predetermined amplitude, and the sharp increase becomes a trigger, and the subsequent voltage waveform fluctuates. Since the smaller the current density of the current flowing through the semiconductor device 100, the fewer the accumulated carriers, carrier depletion is likely to occur. Therefore, as Figure 4 As shown, the smaller the current density of the current flowing through the semiconductor device 100 is, the smaller the oscillation threshold voltage is, and oscillation is more likely to occur.

[0082] exist Figure 4 Two examples are shown in the figure, one is an example in which the doping concentration peak 25-1, which is the shallowest concentration peak, has a relatively high doping concentration, and the other is an example in which the doping concentration is relatively low. The lower the doping concentration of the doping concentration peak 25-1, the larger the oscillation threshold voltage is, and the oscillation is suppressed. For example, when the current density is 0.1×Jr, the oscillation threshold voltage of the example in which the doping concentration peak 25-1 has a high doping concentration is Vth1, and the oscillation threshold voltage of the example in which the doping concentration peak 25-1 has a low doping concentration is Vth2. Vth2 is higher than Vth1. It should be noted that the oscillation start voltage may also be the power supply voltage applied to the diode when a waveform with a predetermined amplitude or above is generated in the voltage waveform or the current waveform. Even in this case, the oscillation start voltage is shown to be different from Figure 4 Same trend.

[0083] Figure 5A This is a diagram showing an example of the relationship between the ratio D1 / Db of the doping concentration D1 of the doping concentration peak 25-1 and the body donor concentration Db and the oscillation threshold voltage. By setting D1 / Db to be less than 50, the oscillation threshold voltage can be increased and the oscillation can be suppressed. D1 / Db can also be less than 20, or less than 10.

[0084] in addition, Figure 2 The threshold concentration Dth shown may be smaller than the reference carrier concentration when a current of 1 / 10 of the rated current flows between the upper surface 21 and the lower surface 23 of the semiconductor substrate 10. The rated current of the semiconductor device 100 may be a specification value in a catalog of the semiconductor device 100 or the like. The rated current density Jr can be calculated by dividing the rated current by the area of ​​the active portion of the semiconductor device 100. The doping concentration of each region of the semiconductor device 100 can be measured by a SIMS method, a CV method, an SR method, or the like.

[0085] Figure 5B This is an example of the carrier concentration distribution in each region when the current density is 0.1×Jr. Figure 5B The horizontal axis represents the distance from the lower surface 23 of the semiconductor substrate 10, and the vertical axis represents the concentration of electrons or holes. In this example, the thickness of the semiconductor substrate 10 in the Z-axis direction is set to W0. In addition, the position of the lower end of the groove portion in the Z-axis direction is set to Zt. The groove portion is a gate groove portion or a dummy groove portion described later. The carrier concentration of each region can be calculated by simulation using the doping concentration of each region. In this example, each region is the drift region 18 and the buffer region 20. The position of the end on the upper surface 21 side of the drift region 18 can be the position of the lower end of the base region 14 (functioning as the anode region of the diode) or the position Zt of the lower end of the groove portion. The carrier concentration at the center 0.5W0 of the semiconductor substrate 10 in the depth direction (or the center of the drift region 18 in the depth direction) can be set as the reference carrier concentration p c The threshold concentration Dth can be the reference carrier concentration p c less than half of the reference carrier concentration p c This makes it possible to suppress oscillations in the voltage waveform and the current waveform.

[0086] Figure 6 1 is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer region 20. The buffer region 20 of this example has two or more doping concentration peaks 25.

[0087] In this example, the doping concentration of at least one doping concentration peak 25 is higher than the doping concentration D1 of the doping concentration peak 25-1. Figure 6 In the example shown, the doping concentration D1 of the doping concentration peak 25 - 1 is lower than the doping concentration D2 of the doping concentration peak 25 - 2 closest to the doping concentration peak 25 - 1 . This makes it possible to suppress oscillation.

[0088] In addition, the doping concentration of at least one doping concentration peak 25 may be higher than the threshold concentration Dth. By making the doping concentration of any doping concentration peak 25 higher than the threshold concentration Dth, it is possible to suppress the depletion layer extending from the lower end of the base region 14 from reaching the cathode region 82. In addition, even if the doping concentration of the doping concentration peaks 25 other than the doping concentration peak 25-1 is increased, the effect on the oscillation threshold voltage is relatively small. That is, since the distance between the lower surface 23 of the semiconductor substrate 10 and the high-concentration doping concentration peak 25 is relatively large, carriers are likely to remain between the lower surface 23 and the high-concentration doping concentration peak 25. As a result, oscillation is suppressed.

[0089] exist Figure 6In the example, the doping concentrations of all doping concentration peaks 25 except for the doping concentration peak 25-1 are higher than the threshold concentration Dth. Thus, it is possible to suppress the depletion layer extending from the lower end of the base region 14 from reaching the cathode region 82. The doping concentration of the doping concentration peak 25 can become higher as it is farther from the lower surface 23. In Figure 6 the example, D1 < D2 < D3 < D4. Thus, it is possible to suppress the oscillation threshold voltage from becoming smaller and suppress the depletion layer from reaching the cathode region 82.

[0090] Figure 7 FIG. is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer layer 20. In this example, the doping concentration D2 of the doping concentration peak 25-2 disposed second closest to the lower surface 23 is higher than the threshold concentration Dth. The doping concentration of the doping concentration peak 25 disposed farther from the lower surface 23 than the doping concentration peak 25-2 may be higher than the threshold concentration Dth or may be lower than the threshold concentration Dth. In Figure 7 the example, the doping concentrations of all doping concentration peaks 25 disposed farther from the lower surface 23 than the doping concentration peak 25-2 are lower than the threshold concentration Dth. With such a configuration, it is also possible to suppress the depletion layer extending from the lower end of the base region 14 from reaching the cathode region 82 and suppress oscillation.

[0091] Figure 8 FIG. is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer layer 20. In this example, the doping concentration D4 of the doping concentration peak 25-4 disposed farthest from the lower surface 23 is higher than the threshold concentration Dth. The doping concentration of the doping concentration peak 25 between the doping concentration peak 25-1 and the doping concentration peak 25-4 may be higher than the threshold concentration Dth or may be lower than the threshold concentration Dth. In Figure 8 the example, the doping concentration of the doping concentration peak 25-2 is higher than the threshold concentration Dth. In addition, a doping concentration peak 25-3 having a doping concentration lower than the threshold concentration Dth is disposed between the doping concentration peak 25-2 and the doping concentration peak 25-4. With such a configuration, it is also possible to suppress the depletion layer extending from the lower end of the base region 14 from reaching the cathode region 82 and suppress oscillation.

[0092] Fig. 9 FIG. is a diagram showing another example of the doping concentration distribution and the hydrogen chemical concentration distribution in the buffer layer 20. In this example, the doping concentrations of all doping concentration peaks 25 except for the doping concentration peak 25-1 are higher than the threshold concentration Dth. However, the doping concentrations of the doping concentration peaks 25 except for the doping concentration peak 25-1 become lower as they are farther from the lower surface 23. With such a configuration, it is also possible to suppress the depletion layer extending from the lower end of the base region 14 from reaching the cathode region 82 and suppress oscillation.

[0093] Fig.101 is a cross-sectional view showing another example of the structure of the semiconductor device 100. The semiconductor device 100 of this example includes a P+ type lower surface side region 83. The structure other than the lower surface side region 83 is the same as that in Figures 1 to 9 The lower surface side region 83 is selectively arranged in the region in contact with the lower surface 23. That is, the cathode region 82 and the lower surface side region 83 are provided in the region in contact with the lower surface 23. By providing the lower surface side region 83, the amount of electron injection from the lower surface 23 side can be adjusted. In addition, holes can be supplied from the lower surface 23 side during reverse recovery, etc. Thus, oscillation can be suppressed.

[0094] Fig.11 1 is a cross-sectional view showing another example of the structure of the semiconductor device 100. The semiconductor device 100 of this example includes a P+ type lower surface side region 83. The structure other than the lower surface side region 83 is the same as that in Figures 1 to 9 The lower surface side region 83 is configured between the cathode region 82 and the doping concentration peak 25-1. The lower surface side region 83 is a floating region that is not in contact with the lower surface 23. The lower surface side region 83 is selectively configured on the upper surface of the cathode region 82. That is, a portion of the upper surface of the cathode region 82 is not covered by the lower surface side region 83. By providing the lower surface side region 83, the amount of electron injection from the lower surface 23 side can be adjusted. In addition, during reverse recovery, etc., holes can be supplied from the lower surface 23 side. Thereby, oscillation can be suppressed.

[0095] Fig.12 FIG. 1 is a top view showing another example of the semiconductor device 100. Fig.12 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Fig.12 Only some components of the semiconductor device 100 are shown, and some components are omitted.

[0096] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has an edge 102 when viewed from above. In this specification, the term "viewed from above" means viewing from the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edges 102 facing each other when viewed from above. Fig.12 In the embodiment, the X-axis and the Y-axis are parallel to any one of the end sides 102. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0097] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but Fig.12 Omitted in .

[0098] The active portion 160 includes at least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Fig.12 In the example of FIG. 1 , the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) of the upper surface of the semiconductor substrate 10. In other examples, only one of the transistor portion 70 and the diode portion 80 may be provided in the active portion 160.

[0099] exist Fig.12 In the figure, the region where the transistor portion 70 is arranged is marked with the symbol "I", and the region where the diode portion 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in Fig.12 The transistor portion 70 and the diode portion 80 may each have a long side in the extension direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each groove portion described later.

[0100] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is a region overlapping with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a P+ type collector region may be provided in a region other than the cathode region. In this specification, an extension region 81 formed by extending the diode section 80 along the Y-axis direction to the gate wiring described later is sometimes also included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0101] The transistor portion 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor portion 70 has a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0102] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged near the end 102. The so-called vicinity of the end 102 refers to the area between the end 102 and the emitter electrode when viewed from above. When the semiconductor device 100 is installed, each pad can be connected to an external circuit via wiring such as a wire.

[0103] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 to the gate trench portion. Fig.12 The gate wiring is shaded with diagonal lines.

[0104] The gate wiring of this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is arranged between the active portion 160 and the edge 102 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above may also be set as the active portion 160. In addition, the peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0105] The active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, it is possible to reduce the variation in wiring length from the gate pad 112 in each region of the semiconductor substrate 10.

[0106] The active-side gate wiring 131 is connected to the gate trench portion of the active portion 160. The active-side gate wiring 131 is disposed above the semiconductor substrate 10. The active-side gate wiring 131 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0107] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. The active-side gate wiring 131 of this example is provided to extend in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 at the approximate center in the Y-axis direction, across the active portion 160. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 may be alternately arranged in the X-axis direction in each divided region.

[0108] The semiconductor device 100 may also include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) which simulates the operation of a transistor portion provided in the active portion 160 .

[0109] The semiconductor device 100 of this example includes an edge termination structure portion 90 between the active portion 160 and the edge 102. The edge termination structure portion 90 of this example is arranged between the peripheral gate wiring 130 and the edge 102. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may further include at least one of a guard ring, a field plate, and a surface electric field reduction structure that surrounds the active portion 160 and is provided in an annular shape.

[0110] Fig.13 yes Fig.12 1 is an enlarged view of region A in FIG. Region A is a region including a transistor portion 70, a diode portion 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate groove portion 40, a dummy groove portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are provided inside the upper surface side of the semiconductor substrate 10. The gate groove portion 40 and the dummy groove portion 30 are each an example of a groove portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131, which are provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0111] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but Fig.13 In the interlayer insulating film of this example, a contact hole 54 is provided so as to penetrate the interlayer insulating film. Fig.13 In FIG. 1 , each contact hole 54 is hatched with oblique lines.

[0112] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole provided in the interlayer insulating film. The emitter electrode 52 can be connected to the dummy conductive portion of the dummy trench portion 30 at the front end of the dummy trench portion 30 in the Y-axis direction.

[0113] The active side gate wiring 131 is connected to the gate groove portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 can be connected to the gate conductive portion of the gate groove portion 40 at the front end portion 41 of the gate groove portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy groove portion 30.

[0114] The emitter electrode 52 is formed of a material including metal. Fig.13, the emitter electrode 52 is shown in the figure. For example, at least a part of the emitter electrode 52 is formed of aluminum (Al), or aluminum-silicon alloy, aluminum-silicon-copper alloy, such as AlSi, AlSiCu and other metal alloys. The emitter electrode 52 may have a barrier metal formed of titanium, titanium compound, etc. in the lower layer of the region formed of aluminum or the like. Furthermore, the contact hole may also have a plug formed by filling tungsten or the like in a manner that contacts the barrier metal and aluminum or the like.

[0115] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend with a predetermined width in a range not overlapping with the active side gate wiring 131. The well region 11 of this example is provided so as to be away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131 side. The well region 11 is a region of the second conductivity type having a higher doping concentration than the doping concentration of the base region 14. The base region 14 of this example is of P- type, and the well region 11 is of P+ type.

[0116] The transistor section 70 and the diode section 80 each have a plurality of groove sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate groove sections 40 and one or more dummy groove sections 30 are alternately arranged along the arrangement direction. In the diode section 80 of this example, a plurality of dummy groove sections 30 are arranged along the arrangement direction. In the diode section 80 of this example, no gate groove section 40 is provided.

[0117] The gate trench portion 40 of this example may include two straight line portions 39 extending in an extending direction perpendicular to the arrangement direction (a portion of the trench that is straight along the extending direction) and a front end portion 41 connecting the two straight line portions 39 . Fig.13 The extension direction is the Y-axis direction.

[0118] Preferably, at least a portion of the tip portion 41 is curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39 .

[0119] In the transistor portion 70, the dummy trench portion 30 is provided between the respective straight line portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the respective straight line portions 39, or a plurality of dummy trench portions 30 may be provided. The dummy trench portion 30 may have a straight line shape extending in the extending direction, or may have a straight line portion 29 and a front end portion 31 similarly to the gate trench portion 40. Fig.13 The semiconductor device 100 shown includes both a linear dummy trench portion 30 having no front end portion 31 and a dummy trench portion 30 having a front end portion 31 .

[0120] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 in a plan view. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. Thus, the electric field concentration at the bottom of each trench portion can be alleviated.

[0121] A mesa portion is provided between each groove portion in the arrangement direction. The mesa portion refers to an area sandwiched by the groove portion inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the groove portion. The mesa portion of this example is provided on the upper surface of the semiconductor substrate 10 in a manner extending along the groove in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when only the mesa portion is referred to, it refers to each of the mesa portion 60 and the mesa portion 61.

[0122] A base region 14 is provided in each mesa portion. A region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion and disposed closest to the active-side gate wiring 131 is referred to as a base region 14-e. Fig.13 The base region 14-e is shown as being arranged at one end of each mesa portion in the extension direction, but the base region 14-e is also arranged at the other end of each mesa portion. In each mesa portion, at least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type can be arranged in the region sandwiched by the base region 14-e when viewed from above. In this example, the emitter region 12 is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 can be arranged between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0123] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0124] The contact regions 15 and emitter regions 12 of the mesa portion 60 are provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the extending direction of the trench portion (Y-axis direction).

[0125] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be arranged in stripes along the extending direction of the groove portion (Y-axis direction). For example, the emitter region 12 is arranged in the region connected to the groove portion, and the contact region 15 is arranged in the region sandwiched by the emitter region 12.

[0126] The emitter region 12 is not provided in the mesa portion 61 of the diode portion 80. The base region 14 and the contact region 15 may be provided on the upper surface of the mesa portion 61. The contact region 15 may be provided in the region sandwiched by the base regions 14-e on the upper surface of the mesa portion 61 so as to be in contact with each base region 14-e. The base region 14 may be provided in the region sandwiched by the contact regions 15 on the upper surface of the mesa portion 61. The base region 14 may be arranged in the entire region sandwiched by the contact regions 15.

[0127] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched by the base region 14-e. The contact hole 54 of this example is provided above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact hole 54 can be arranged at the center of the mesa portion 60 in the arrangement direction (X-axis direction).

[0128] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. Fig.13 The boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0129] The cathode region 82 is arranged to be separated from the well region 11 in the Y-axis direction. Thus, the distance between the P-type region (well region 11) with a relatively high doping concentration and formed to a deep position and the cathode region 82 can be ensured to improve the withstand voltage. The end of the cathode region 82 in the Y-axis direction of this example is arranged to be farther away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction can be arranged between the well region 11 and the contact hole 54.

[0130] Fig.14 Yes means Fig.13FIG. bb section is an example of a cross section in FIG. bb section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52 and a collector electrode 24 in this cross section. The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film and other insulating films. The interlayer insulating film 38 is provided with Fig.13 The contact hole 54 described in FIG.

[0131] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0132] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in the transistor portion 70 and the diode portion 80, respectively.

[0133] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially provided from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is arranged between the base region 14 and the drift region 18. The conductivity type of the dopant in the accumulation region 16 is the same as the conductivity type of the dopant in the drift region 18. The accumulation region 16 is a region having a higher doping concentration than the drift region 18. In this example, the accumulation region 16 is a region having a higher donor concentration than the drift region 18.

[0134] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0135] The base region 14 is provided below the emitter region 12. The base region 14 of this example is provided so as to be in contact with the emitter region 12. The base region 14 may be in contact with the groove portions on both sides of the mesa portion 60.

[0136] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region having a higher doping concentration than the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved and the on-voltage can be reduced. The accumulation region 16 can be provided in a manner covering the entire lower surface of the base region 14 in each mesa portion 60.

[0137] In the mesa portion 61 of the diode portion 80, a P-type base region 14 is provided so as to be in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. In the mesa portion 61, an accumulation region 16 may be provided below the base region 14.

[0138] In each of the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided under the drift region 18. The buffer section 20 of this example includes a first buffer section 20-1 provided in the diode section 80 and a second buffer section 20-2 provided in the transistor section 70. Figures 1 to 11 The second buffer 20-2 may be the same as the buffer 20 described in Figures 1 to 11 The buffer zone 20 described in is the same.

[0139] In the transistor portion 70, a P+ type collector region 22 is provided below the second buffer region 20-2. The collector region 22 is provided between the doping concentration peak 25-1, which is the shallowest concentration peak of the second buffer region 20-2, and the lower surface 23. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain an acceptor different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0140] In the diode portion 80, an N+ type cathode region 82 is provided below the first buffer region 20-1. The cathode region 82 is provided between the shallowest concentration peak of the first buffer region 20-1, namely the doping concentration peak 25-1, and the lower surface 23. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that become the donors and acceptors of each region are not limited to the above examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can be connected to the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0141] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least any one of the emitter region 12, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these doped regions and reaches the drift region 18. The so-called groove portion penetrating the doped region is not limited to a structure manufactured in the order of forming the groove portion after forming the doped region. A structure in which a doped region is formed between the groove portions after the groove portions are formed is also included in a structure in which the groove portion penetrates the doped region.

[0142] As described above, the transistor portion 70 is provided with the gate trench portion 40 and the dummy trench portion 30. The diode portion 80 is provided with the dummy trench portion 30, and the gate trench portion 40 is not provided. In this example, the boundary between the diode portion 80 and the transistor portion 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22. Figures 1 to 11 The semiconductor device 100 described in the embodiment of the present invention does not have a groove portion, but Figures 1 to 11 The semiconductor device 100 described in the foregoing may also be provided with a trench portion.

[0143] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position closer to the inner side than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0144] The gate conductive portion 44 can be set longer than the base region 14 in the depth direction. The gate groove portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel generated by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is connected to the gate groove portion 40.

[0145] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32 and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0146] The gate trench 40 and the dummy trench 30 of this example are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces convex downward (curved in cross section).

[0147] Fig.15 2 is a diagram showing an example of doping concentration distribution in the first buffer region 20-1 and the cathode region 82, and in the second buffer region 20-2 and the collector region 22. Figures 1 to 11 The doping concentration distribution of any buffer region 20 described in the above is the same. Thus, it is possible to suppress the oscillation of the diode portion 80 during reverse recovery.

[0148] The second buffer region 20-2 has one or more doping concentration peaks 25. The doping concentration peaks 25 of the second buffer region 20-2 are disposed at the same depth position as the doping concentration peaks 25 in the first buffer region 20-1.

[0149] The doping concentration of each doping concentration peak 25 in the second buffer region 20-2 may be the same as the doping concentration of the doping concentration peak 25 set at the same depth position in the first buffer region 20-1. That is, the second buffer region 20-2 may have the same doping concentration distribution as the first buffer region 20-1. In this case, the hydrogen chemical concentration distribution of the second buffer region 20-2 may be the same as the hydrogen chemical concentration distribution of the first buffer region 20-1. Alternatively, the depth position of the doping concentration peak 25-1b of the second buffer region 20-2 may be closer to the lower surface 23 than the depth position of the doping concentration peak 25-1a of the first buffer region 20-1. Thus, the depletion layer of the transistor portion 70 can be stopped at a position close to the collector region 22, and the injection of holes from the collector region 22 can be maintained high.

[0150] In addition, if Fig.15As shown, the doping concentration of the doping concentration peak 25-1b, which is the shallowest concentration peak of the second buffer region 20-2, can be higher than the doping concentration of the doping concentration peak 25-1a, which is the shallowest concentration peak of the first buffer region 20-1. Thus, oscillation can be suppressed in the diode portion 80, and the depletion layer can be suppressed from reaching the collector region 22 in the transistor portion 70. The doping concentration D1b of the doping concentration peak 25-1b can be more than 5 times, more than 10 times, or more than 20 times the doping concentration D1a of the doping concentration peak 25-1a.

[0151] The doping concentration D1b of the doping concentration peak 25-1b may be higher than the threshold concentration Dth. The doping concentration D1b of the doping concentration peak 25-1b may be more than 2 times, more than 5 times, or more than 10 times the threshold concentration Dth. Thus, in the transistor portion 70, the depletion layer can be further suppressed from reaching the collector region 22. The doping concentration between the doping concentration peak 25-1b and the collector region 22 may have a valley-shaped concentration distribution close to the doping concentration peak 25-1b, i.e., a second valley 27 and a third valley 28 close to the collector region 22. The third valley 28 may be a boundary having a pn junction between the second buffer region 20-2 and the collector region 22. The doping concentration at the third valley 28 is the donor concentration at the third valley 28 (N D ) and acceptor concentration (N A ) net concentration (N D -N A). Since the third valley 28 is a pn junction, the donor concentration and the acceptor concentration are the same concentration. Therefore, the doping concentration of the third valley 28 is theoretically 0. The donor concentration at the third valley 28 may have a finite value that is not 0. The donor concentration Dv2 at the second valley 27 is set to the donor concentration at the boundary between the doping concentration peak 25-1b and the collector region 22. The donor concentration Dv2 is the donor concentration Dv2 of the region connected to the pn junction of the third valley 28 from the upper surface 21 of the semiconductor substrate 10. The donor concentration Dv2 of the second valley 27 may be the doping concentration of a portion where the differential value is initially lower than 0.5, or the doping concentration of a portion where the differential value is initially lower than 0.25, or the doping concentration of a portion where the differential value initially becomes 0, the differential value being the value obtained by differentiating the doping concentration at a depth position in the direction from the third valley 28 toward the second buffer region 20-2. The donor concentration Dv2 at the second valley 27 may be higher than the minimum value Dv1 of the doping concentration of the first valley 26 of the first buffer zone 20-1. Thus, in the transistor portion 70, the depletion layer can be further suppressed from reaching the collector region 22, and the reverse recovery oscillation of the diode portion 80 can be suppressed. The donor concentration Dv2 at the second valley 27 may be greater than or less than a predetermined threshold value Dth. In this example, the donor concentration Dv2 at the second valley 27 is less than the predetermined threshold value Dth. The donor concentration Dv2 at the second valley 27 may be greater than or less than the doping concentration peak 25-2. In this example, the donor concentration Dv2 at the second valley 27 is greater than the doping concentration peak 25-2. Thus, in the transistor portion 70, the depletion layer can be further suppressed from reaching the collector region 22.

[0152] Fig.16 1 is a flowchart showing a part of the steps of the method for manufacturing the semiconductor device 100. Fig.16 An example of the process of forming the first buffer region 20-1 and the second buffer region 20-2 is shown in FIG. The doping concentration peak 25-1b, which is the shallowest concentration peak of the second buffer region 20-2, can be formed as follows.

[0153] The structure on the upper surface 21 side of the semiconductor substrate 10 in the active portion 160 provided with the transistor portion 70 and the diode portion 80 is formed on the semiconductor substrate 10 (active region forming step S0). The structure on the upper surface 21 side refers to, for example, Fig.14 In the structure shown, the structure is provided at a position closer to the upper surface 21 than the center in the depth direction of the semiconductor substrate 10. For example, the structure on the upper surface 21 side includes the emitter region 12 of the transistor section 70 and the base region 14 of the diode section 80. The base region 14 of the diode section 80 functions as an anode region of the diode. A groove portion may be included on the upper surface 21 side of one or both of the transistor section 70 and the diode section 80.

[0154] Next, N-type dopant ions are implanted from the lower surface 23 of the semiconductor substrate 10 into both the transistor portion 70 and the diode portion 80 to form a doping concentration peak 25-1a as the shallowest concentration peak of the first buffer portion 20-1 (first ion implantation step S1). That is, in the first ion implantation step S1, a doping concentration peak 25-1a of the same concentration is formed in both the transistor portion 70 and the diode portion 80. The dopant in the first ion implantation step S1 of this example is hydrogen. After the first ion implantation step S1, the semiconductor substrate 10 may be thermally annealed (first annealing step S2). The first annealing step S2 may also be omitted. In the first ion implantation step S1, concentration peaks other than the shallowest concentration peak may also be formed in both the transistor portion 70 and the diode portion 80. Each concentration peak can be formed by injecting dopants multiple times from the lower surface 23 of the semiconductor substrate 10 by changing the range of the dopant.

[0155] Next, ion implantation of an N-type dopant is additionally performed from the lower surface 23 of the semiconductor substrate 10 only to the transistor portion 70 (second ion implantation process S3). In the second ion implantation process S3, ion implantation is additionally performed at a depth position where the doping concentration peak 25-1b should be formed. In this example, the depth position at which the dopant is implanted in the second ion implantation process S3 is the same as the depth position at which the dopant is implanted in the first ion implantation process S1. That is, in the second ion implantation process S3, the dopant is implanted in a manner overlapping with the doping concentration peak 25-1a formed in the transistor portion 70. Thus, a doping concentration peak 25-1b is formed as the shallowest concentration peak of the second buffer region 20-2. The doping concentration of the doping concentration peak 25-1b is higher than the doping concentration of the doping concentration peak 25-1a by the amount of the dopant additionally implanted in the second ion implantation process S3. After the second ion implantation process S3, the semiconductor substrate 10 may be thermally annealed (second annealing process S4).

[0156] The dopant in the second ion implantation step S3 may be the same as or different from the dopant in the first ion implantation step S1. The dopant of the doping concentration peak 25-1b, which is the shallowest concentration peak of the second buffer zone 20-2, may be hydrogen, and may also contain phosphorus or arsenic. Alternatively, the dopant of the doping concentration peak 25-1b may also be phosphorus or arsenic without hydrogen. The concentration of hydrogen donors contained in the doping concentration peak 25-1b may be higher than the concentration of donors other than hydrogen contained in the doping concentration peak 25-1b, or may be lower than the concentration of donors other than hydrogen contained in the doping concentration peak 25-1b.

[0157] exist Fig.16In the example, the second ion implantation step S3 is performed after the first ion implantation step S1, but the second ion implantation step S3 may be performed before the first ion implantation step S1. In addition, each time the first ion implantation step S1 and the second ion implantation step S3 are performed, the semiconductor substrate 10 is thermally annealed, but a common thermal annealing step may be performed after performing the two ion implantation steps.

[0158] In addition, the cathode region 82 and the collector region 22 may be formed after the buffer region 20 or may be formed before the buffer region 20. Through such steps, various regions can be formed inside the semiconductor substrate 10.

[0159] Fig.17 1 is a diagram showing an example of an integrated concentration obtained by integrating the doping concentration in the semiconductor substrate 10 in the depth direction. The depth position of the lower end of the groove portion such as the gate groove portion 40 is set as Zt. In this example, the concentration obtained by integrating the doping concentration of the semiconductor substrate 10 from the position Zt toward the lower surface 23 of the semiconductor substrate 10 is set as the integrated concentration. As for the starting point in the depth direction for integrating the doping concentration, the depth position of the lower end of the drift region 18 closest to the base region 14 may be used instead of the position Zt.

[0160] Since drift region 18 has a substantially uniform doping concentration, the integrated concentration increases linearly toward lower surface 23. In buffer region 20 and collector region 22 (or cathode region 82), the integrated concentration increases toward lower surface 23 according to their respective doping concentration distributions.

[0161] The integrated concentration is set to be greater than the critical integrated concentration n of the semiconductor substrate 10. c The maximum depth position is defined as the critical position Znc. It should be noted that when the forward bias voltage applied between the upper surface 21 and the lower surface 23 of the semiconductor substrate 10 is increased and the maximum value of the electric field intensity reaches the critical electric field intensity E c When avalanche breakdown occurs, the integrated concentration at the depth of the depletion layer extending from the bottom end of the drift region 18 closest to the base region 14 to the bottom surface 23 is the critical integrated concentration n c . Critical electric field strength E c The value can be 1×10 5 (V / cm) or more and 3×10 5 (V / cm) or less. As an example, the critical electric field strength E c The value is 2×10 5 (V / cm). If the critical electric field strength is set to E c , set q to the elementary charge (1.602×10 -19[C]), and let ε0 be the dielectric constant of vacuum (8.854×10 -14 [F / cm]), ε r Assuming the relative dielectric constant of the substance, the critical integral concentration n c For E c (ε r ε0 / q)=n c The relative dielectric constant of silicon is 11.9. The critical integral concentration n c It can be 8.0×10 11 ( / cm 2 ) or more. In addition, the critical integral concentration n c It can be 2.0×10 12 ( / cm 2 ) or less. In this example, the critical integral concentration n c 1.2×10 12 ( / cm 2 ).

[0162] The critical position Znc preferably overlaps with the doping concentration peak 25-1, which is the shallowest concentration peak, or is arranged at a position closer to the groove portion than the doping concentration peak 25-1. The so-called overlap of the critical position Znc and the doping concentration peak 25-1 may mean that the critical position Znc is arranged within the half-maximum full width of the doping concentration peak 25-1. In this way, it is possible to suppress the depletion layer extending from the lower end of the base region 14 to the lower surface 23 from reaching the collector region 22 or the cathode region 82. The critical position Znc can be arranged in the buffer region 20.

[0163] Although the present invention is described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such changes or improvements can also be included in the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate including a body donor; and a first conductive type first buffer region, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate, The doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer region is less than 50 times the bulk donor concentration of the semiconductor substrate. The doping concentration of the shallowest concentration peak is lower than a reference carrier concentration when a current of 1 / 10 of a rated current flows between the upper surface and the lower surface of the semiconductor substrate.

2. A semiconductor device, characterized in that: have: a semiconductor substrate including a body donor; and a first conductive type first buffer region, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate, The doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer region is less than 50 times the bulk donor concentration of the semiconductor substrate. The semiconductor device includes a transistor portion and a diode portion. The diode unit includes: the first buffer zone; and a cathode region of a first conductivity type, which is disposed between the first buffer region and the lower surface of the semiconductor substrate, The transistor unit includes: A second buffer region of the first conductivity type, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate; and a collector region of a second conductivity type, which is disposed between the second buffer region and the lower surface of the semiconductor substrate, The doping concentration of the doping concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the second buffer region is higher than the doping concentration of the shallowest concentration peak of the first buffer region.

3. A semiconductor device, characterized in that: have: a semiconductor substrate including a body donor; and a first conductive type first buffer region, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate, The doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer region is less than 50 times the bulk donor concentration of the semiconductor substrate. The semiconductor device includes a transistor portion and a diode portion. The diode unit includes: the first buffer zone; and a cathode region of a first conductivity type, which is disposed between the first buffer region and the lower surface of the semiconductor substrate, The transistor unit includes: A second buffer region of the first conductivity type, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate; and a collector region of a second conductivity type, which is disposed between the second buffer region and the lower surface of the semiconductor substrate, A minimum value of a valley portion of donor concentration between the shallowest concentration peak and the cathode region is smaller than a donor concentration at a boundary between the shallowest concentration peak of the second buffer region and the collector region.

4. A semiconductor device, characterized in that: have: a semiconductor substrate including a body donor; and a first conductive type first buffer region, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate, The doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer region is less than 50 times the bulk donor concentration of the semiconductor substrate. Among the doping concentration peaks of the first buffer region, the doping concentration of the shallowest concentration peak is lower than the doping concentration of the doping concentration peak farthest from the lower surface of the semiconductor substrate.

5. The semiconductor device according to claim 4, wherein: Among the doping concentration peaks in the first buffer zone, the doping concentration of the shallowest concentration peak is lower than the doping concentration of any of the other doping concentration peaks.

6. A semiconductor device, characterized in that: have: a semiconductor substrate including a body donor; and a first conductive type first buffer region, which is disposed on the lower surface side of the semiconductor substrate and has one or more doping concentration peaks and one or more hydrogen concentration peaks in the depth direction of the semiconductor substrate, The doping concentration of the shallowest concentration peak closest to the lower surface of the semiconductor substrate among the doping concentration peaks of the first buffer region is 10 times or less of the bulk donor concentration.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The doping concentration of all the doping concentration peaks in the first buffer region is less than 50 times the concentration of the bulk donor.

8. The semiconductor device according to any one of claims 1 to 6, wherein: The first buffer region has more than two doping concentration peaks, and a doping concentration of at least one of the doping concentration peaks is higher than 50 times the concentration of the bulk donor.

9. The semiconductor device according to any one of claims 1 to 6, wherein: The first buffer region has more than two doping concentration peaks, and a doping concentration of at least one of the doping concentration peaks is higher than a doping concentration of the shallowest concentration peak.

10. The semiconductor device according to claim 9, wherein: The doping concentration of the shallowest concentration peak is lower than the doping concentration of the doping concentration peak closest to the shallowest concentration peak.

11. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device further includes a groove portion arranged on the upper surface of the semiconductor substrate. When the concentration obtained by integrating the doping concentration of the semiconductor substrate from the lower end of the groove portion toward the lower surface of the semiconductor substrate is set as the integrated concentration, and the position where the integrated concentration reaches the critical integrated concentration of the semiconductor substrate is set as the critical position, the critical position overlaps with the shallowest concentration peak, or the critical position is arranged at a position closer to the groove portion side than the shallowest concentration peak.

12. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device further includes a cathode region of the first conductivity type, the cathode region being disposed between the shallowest concentration peak and the lower surface of the semiconductor substrate, and having a peak value of doping concentration of the cathode region higher than the shallowest concentration peak.

13. The semiconductor device according to claim 12, wherein: The semiconductor device further includes a lower surface side region of the second conductivity type provided between the shallowest concentration peak and the lower surface of the semiconductor substrate.

14. The semiconductor device according to claim 12, wherein: The minimum value of the valley portion of the donor concentration between the shallowest concentration peak and the cathode region is smaller than a second concentration peak, and the second concentration peak is adjacent to the shallowest concentration peak at a position closer to the upper surface of the semiconductor substrate than the shallowest concentration peak.

15. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device includes a collector region of a second conductivity type provided between the shallowest concentration peak and the lower surface of the semiconductor substrate.

16. A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device includes a transistor portion and a diode portion, the method comprising: an active region forming step of forming an emitter region of the transistor portion and an anode region of the diode portion on an upper surface of a semiconductor substrate including a body donor; and The ion implantation step implants a first dopant of a first conductivity type into the transistor portion and the diode portion from the lower surface of the semiconductor substrate by ion implantation, and implants a second dopant of a first conductivity type into the transistor portion by ion implantation from the lower surface of the semiconductor substrate by ion implantation.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The depth position at which the first dopant is implanted is the same as the depth position at which the second dopant is implanted.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: The first dopant is hydrogen.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: The first dopant is hydrogen.

20. The method for manufacturing a semiconductor device according to any one of claims 16 to 19, characterized in that: The second dopant is any one of hydrogen, phosphorus and arsenic.

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