Power converter including active non-dissipative clamping circuit and corresponding controller

Abstract

A controller for a power converter (100). The controller includes a control circuit coupled to receive an input line voltage sense signal (149) representing an input voltage (VIN) of the power converter. The control circuit is configured to generate a control signal in response to a request signal (135) representing an output of the power converter. In response to the input line voltage sense signal (149), the control signal indicates a delay time for turning on a power switch (SI) after turning on a clamp switch (108). The control circuit may also generate a clamp drive signal to control a clamp driver, and the drive circuit is configured to generate a drive signal to control the power switch to transfer energy from the input of the power converter to the output of the power converter.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 838,227, filed on April 24, 2019, the contents of which are incorporated herein by reference in their entirety.

[0003] Background Information

[0004] Areas of public content

[0005] The present invention relates generally to power converters, and more particularly to zero voltage switching (ZVS) for a variable frequency flyback power converter.

[0006] background

[0007] Electronic devices (such as cell phones, tablet computers, laptop computers, etc.) run on electricity. Switched mode power supplies are commonly used to power many of today's electronic devices because of their high efficiency, small size, and light weight. Conventional wall outlets provide high voltage alternating current. In a switching power supply, a high voltage alternating current (AC) input is converted with a switched mode power converter to provide a well-regulated direct current (DC) output to a load through an energy transfer element. In operation, the switch is turned on and off to provide the desired output by changing the duty cycle (usually the ratio of the on time of the switch to the total switching period), changing the switching frequency, or changing the number of on / off pulses per unit time of the switch in the switched mode power converter.

[0008] In a power converter such as a flyback converter, when the primary power switch is turned off, the path for the current on the primary side is suddenly interrupted. The energy stored in the form of magnetizing energy of the energy transfer element can be transferred to the output, but the energy in the leakage inductance cannot be transferred to the output. The stored energy is transferred to the drain to source capacitance of the main power switch. This can have a catastrophic effect on the device because the voltage developed across the drain to source may exceed the device rating. Conventional flyback converters use a passive clamp, such as an RCD clamp, where the leakage energy is captured in the clamp capacitor and the energy is dissipated in the resistor. This wasted energy reduces the overall efficiency of the system.

[0009] Active clamp strategies have been proposed that recycle leakage energy to achieve zero voltage switching on the primary switch. This increases the efficiency of the overall system. The most commonly used ZVS technique today uses an active clamp located on the primary side and a resonant LC secondary output winding structure. While this approach has excellent efficiency and reliable ZVS operation, it requires operating the controller in burst mode. Burst mode is a complex control strategy that requires careful optimization of the loop speed and stability of the system. This can be particularly challenging for adapters whose output voltage can vary over a wide range, such as USB PD. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0011] Figure 1 One example of a power converter having a primary controller, a secondary controller, and a clamp driver according to an embodiment of the present disclosure is illustrated.

[0012] Figure 2 The embodiment according to the present disclosure is illustrated. Figure 1 An embodiment of a timing diagram of a current of a power switch used in a power converter.

[0013] Figure 3 The embodiments according to the present disclosure are illustrated Figure 1 An embodiment of a control circuit used in.

[0014] Figure 4A Another example of a timing diagram illustrating signals of a power converter, such as drain voltage, clamp current, drain current, secondary current, enable signal, and drive signal, is illustrated according to an embodiment of the present disclosure.

[0015] Figure 4B Another example of a timing diagram illustrating signals of a power converter, such as a drain-source voltage, a clamp current, a drain current, a secondary current, an enable signal, and a drive signal, according to an embodiment of the present disclosure is illustrated.

[0016] Figure 4CTiming diagrams illustrating drain-source voltage, clamp current, switch current of a power switch, secondary current, clamp enable signal, and drive signal according to an embodiment of the present disclosure are illustrated.

[0017] Figure 5A An example of a timing diagram illustrating signals of a power converter, such as a drain voltage, an enable signal, and a drive signal, according to an embodiment of the present disclosure is illustrated.

[0018] Figure 5B An example of a timing diagram illustrating signals of a power converter, such as a drain voltage, an enable signal, and a drive signal, according to an embodiment of the present disclosure is illustrated.

[0019] Fig. 6A An example timing diagram of the drain voltage of a power switch according to an embodiment of the present disclosure is illustrated.

[0020] Figure 6B Another example timing of the drain voltage of a power switch according to an embodiment of the present disclosure is illustrated.

[0021] Figure 6C Another example of a timing diagram of a drain voltage of a power switch according to an embodiment of the present disclosure is illustrated.

[0022] Figure 7 A timing diagram of a drain voltage of a power switch according to an embodiment of the present disclosure is illustrated.

[0023] Figure 8 A timing diagram of a drain voltage of a synchronous rectifier switch and a drain voltage of a power switch according to an embodiment of the present disclosure is illustrated.

[0024] In all several views of the accompanying drawings, corresponding reference characters indicate corresponding parts. It will be appreciated by the skilled person that the elements in the accompanying drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the sizes of some elements in the accompanying drawings may be exaggerated relative to other elements to help improve the understanding of the various embodiments of the invention. In addition, common but easily understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted so as to less hinder the viewing of these various embodiments of the invention. DETAILED DESCRIPTION

[0025] Embodiments of power converters that can transition from a discontinuous conduction mode of operation to a continuous conduction mode of operation in response to a line input voltage are described herein. In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that specific details are not required to practice the invention. In other cases, well-known materials or methods are not described in detail to avoid obscuring the present invention.

[0026] Reference throughout this specification to "one embodiment", "anembodiment", "one example" or "an example" means that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "one example" or "an example" appearing in various places throughout this specification do not necessarily all refer to the same embodiment or example. In addition, specific features, structures or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Specific features, structures or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functions. In addition, it should be understood that the drawings provided herewith are used for the purpose of explanation to those of ordinary skill in the art, and the drawings are not necessarily drawn to scale.

[0027] Power converters such as flyback converters can provide low output current at low component cost and are relatively simple compared to other converter topologies. Flyback converters can also utilize active clamping circuits to prevent overvoltage from damaging components within the flyback converter.

[0028] Conduction losses and switching losses occur due to resistance in the circuit and parasitic capacitance switched by the power converter, especially when the power switch is a transistor. When the power switch conducts current, the resistance of the circuit, together with the current passing through the circuit, generates conduction losses. Switching losses are generally associated with losses that occur when the power switch of the power converter is transitioning between the on (ON) state and the off (OFF) state (or vice versa). In one embodiment, a switch that is on (or closed) can conduct current, while a switch that is off (or disconnected) cannot conduct current. When the power switch is disconnected, the voltage across the switch stores energy in the parasitic capacitance. When the power switch is closed, the parasitic capacitance discharges, dissipating the energy stored in the parasitic capacitance in the resistance of the power switch to generate switching losses. In addition, switching losses may be caused by having a non-zero voltage across the power switch when the power switch is turned on or by having a non-zero current through the power switch when the power switch is turned off. By using zero voltage switching technology, active clamping circuits can be used to reduce switching losses.

[0029] To maintain high efficiency of the power converter under light load or no load conditions, the power converter controller can implement a burst operation mode by turning the power switch on and off in a time interval (also referred to as a burst interval), followed by an interval without switching. For a flyback converter with an active clamp, it may be difficult to optimize loop speed and stability and ripple for a wide output voltage range or a design that requires stable constant current (CC) operation. To avoid the complexity of the burst mode, the present disclosure shows a power converter controller that controls an active clamp and a flyback converter that provides a continuously variable frequency for zero voltage switching (ZVS) without the complexity of a burst mode or an LC output winding network. The variable frequency can be easily controlled to achieve an optimal loop response for output response and line rejection. In addition, the power converter controller can determine whether to operate in a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM) in response to a line sensing input voltage representing an input line voltage. In one embodiment, when operating in CCM at lower input voltages, the root mean square (RMS) current of the power switch is reduced, which improves the efficiency of the power converter.

[0030] For illustration, Figure 1 1 shows a block diagram of an example power converter 100 including a clamp driver 106, a primary controller 133, and a secondary controller 137 in accordance with the teachings of the present disclosure. The illustrated embodiment of the power converter 100 includes an input capacitor C IN 102, energy transfer element 116, primary winding 118 of energy transfer element 116, secondary winding 120 of energy transfer element 116, power switch S1 145, clamping capacitor C CL 104 , diodes 107 and 115 , clamp switch 108 , output capacitor Co 122 , input return line 126 , output return line 125 , synchronous rectifier 128 , and sensing circuit 131 .

[0031] The clamp driver 106 is shown to include a low-side driver 150 and a high-side driver 151. The low-side driver 150 is configured to control the high-side driver via a communication link 152. The high-side driver is configured to generate a clamp enable signal U CE 168 is used to control the clamp switch 108.

[0032] The secondary controller 137 is configured to generate the secondary drive signal 134 to control the synchronous rectifier 128 and generate a request signal U REQ 135. Request signal U REQ135 is communicated to the primary controller to enable the power switch S1 145. In addition, the secondary controller 137 is coupled to receive a feedback signal U representing the output of the power converter 100. FB 132.

[0033] The primary controller 133 is shown to include a control circuit 139 and a drive circuit 141. The control circuit 139 is coupled to receive a request signal U from the secondary controller 137. REQ 135 and represents the switching current I of the power switch D The control circuit 139 is configured to respond to the input line voltage sensing signal U LS 149 and generate a control signal U CTRL 142. Control signal U CTRL 142 represents the delay time of turning on the power switch S1 145 after the transition of the clamp switch 108. LS 149 represents the input voltage V of the power converter 100 IN 101. As will be further explained, in response to the input line voltage sensing signal U LS 149 and select control signal U CTRL The driving circuit 141 is coupled to receive the control signal U CTRL 142 and generates a driving signal U D 144 to control the power switch 145. The drive circuit 141 is also coupled to receive a switching current I representing the power switch 145. D The drive circuit 141 is coupled to turn on the power switch S1 145 and is coupled to respond to the switch current I D 143 reaches the current limit (not shown) and turns off the power switch S1 145.

[0034] The magnetizing inductance L is also shown. MAG 112, leakage inductance LLK 114, which may represent the magnetizing inductance and leakage inductance associated with the energy transfer element 116 or discrete inductor. The parasitic capacitance C is shown in dashed lines. P 146 represents all capacitance coupled to the power switch S1 145 and may include the natural capacitance within the energy transfer element 116, the natural internal capacitance of the power switch S1 145, and / or discrete capacitors. Figure 1 The secondary current I S 121. Output voltage V O 123. Output current I O 127. Output U O 136. Feedback signal UFB 132. Clamping voltage V CL 109. Clamping current I CL 110 and leakage voltage V L 111. In the illustrated embodiment, power converter 100 is shown as having a flyback topology. It should be understood that other known topologies and configurations of power converters may also benefit from the teachings of the present disclosure.

[0035] The power converter 100 is operated from an unregulated input voltage V IN 101 provides output power to load 124. In one embodiment, the input voltage V IN 101 is the rectified and filtered ac line voltage. In another embodiment, the input voltage V IN 101 is a dc input voltage. The energy transfer element 116 is coupled to receive the input voltage V IN 102. In some embodiments, the energy transfer element 116 may be a coupled inductor, a transformer, or an inductor. The example energy transfer element 116 is shown as including two windings - a primary winding 118 (having a number of turns N) and a secondary winding 118 (having a number of turns N). P ) and the secondary winding 120 (having N turns S ). However, the energy transfer element 116 may have more than two windings. The voltage across the primary winding 118 is illustrated as a primary voltage having a positive polarity at a point end of the primary winding 118. When the power switch S1 145 is turned on, the primary voltage is substantially equal to the input voltage V IN 102 and leakage voltage V L The negative sum of 1135, or mathematically: V P =-(V IN +V L ). When the power switch S1 145 is turned off, the primary voltage is substantially equal to the reflected output voltage of the secondary winding 120. The primary winding 118 of the energy transfer element is also coupled to the power switch S1 145 and the power switch S1 145 is also coupled to the input return line 126.

[0036] In operation, the primary controller 133 responds to the input line voltage sensing signal U LS 149 determines the first operation mode. When the input line voltage sensing signal U LS 149 is less than the CCM threshold, the first mode of operation occurs. In one embodiment, the CCM threshold can be in the range of 130 volts. When the power switch S1 145 is turned off, after being turned on, the drain-source voltage rises at a rate determined by the peak current when the power switch is turned off and the capacitance CP 146. The drain-source voltage will continue to rise until it is clamped to the clamp capacitor C through the diode 115.CL 106 clamping voltage V CL 109. Before the power switch S1 145 is turned on, the clamp switch 108 is turned on by the clamp driver 106. Leakage inductance L LK 114 and the primary winding 118 are in the on state through the clamp switch 108 by C CL When the clamp switch 108 is turned on, the voltage is applied to the leakage inductor L LK 114, which causes the current to rise in the opposite direction to when the power switch S1 145 is turned on. After a specified time, the clamp switch 108 is turned off. The turning off of the clamp switch 108 causes the drain-source voltage of the power switch S1 145 to drop substantially to zero. During this time, the leakage and energy that has been charged by the clamp switch 108 turning on is discharged. After the drain voltage has reached substantially zero volts, the power switch S1 145 can be turned on.

[0037] In addition, the primary controller 133 can respond to the input line voltage sensing signal U LS 149 determines the second operation mode. LS When 149 is greater than the DCM threshold, the second mode of operation occurs. In one embodiment, the DCM threshold is in the range of 150 volts.

[0038] When the power switch S1 145 is turned off, after being turned on, the drain-source voltage rises at a rate determined by the peak current when the power switch is turned off and the capacitance C P 146. The drain-source voltage will continue to rise until it is clamped to the clamping voltage V by diode 115. CL 109. Before the power switch S1 145 is turned on, the clamp switch 108 is turned on by the clamp driver 106. When the clamp switch 108 is turned on, a voltage is applied to the leakage inductance L LK 114 and magnetizing inductance L MAG 112, which causes the current to rise in the opposite direction compared to when the power switch S1 145 is turned on. After a specified time, the clamp switch 108 is turned off. The turning off of the clamp switch 108 causes the drain-source voltage of the power switch S1 145 to drop substantially to zero. During this time, the leakage and magnetizing energy that has been charged by the clamp switch 108 turning on is discharged. This causes the voltage across the drain-source of the power switch S1 145 to decrease and eventually reach zero. This mode generally takes longer to reach zero volts on the drain of the power switch S1 145, which is accommodated by the second operating mode by increasing the delay between the clamp switch 108 turning off and the power switch S1 145 turning on. After the drain voltage has substantially reached zero volts, the main switch is turned on.

[0039] As shown, the leakage inductance L LK 114 can be coupled between the power switch S1 145 and the primary winding 118. The leakage inductance L LK 114 may represent the leakage inductance associated with the energy transfer element 116 or a discrete inductor. Uncoupled leakage inductance L LK The voltage across 114 can be expressed as the leakage voltage V L 111.

[0040] The primary winding 118 and the leakage inductance L are coupled LK Across 114 is the clamp switch 108. The clamp driver 106 is coupled to the clamp capacitor C CL 104. The voltage across the clamping capacitor CCL 104 is represented as the clamping voltage V CL 109, and the current in the clamp circuit is expressed as the clamp current I CL 110. The clamp switch 108 limits the maximum voltage on the power switch S1 145, and the control of the clamp switch 108 (generated by the clamp driver 106) facilitates zero voltage switching of the power switch S1 145. In addition, the clamp driver 106 in combination with the clamp switch 108 can reduce the RMS current in the power converter 100. Specifically, the clamp drive signal U is received at the high-side driver 151 driving the clamp switch 108 (illustrated as a transistor). CD 147. The clamp switch 108 is controlled to be turned on to inject current into the primary winding 118. The clamp switch 108 is turned on for a first duration before the power switch S1 145 is turned on. In other words, the clamp switch 108 is not turned on for the entire duration that the power switch S1 145 is turned off. At or near the beginning of the off time of the power switch S1 145, the clamp switch 108 conducts the leakage inductance L of the power converter 100. LK 114 is associated with the charge from the uncoupled leakage inductance L LK This charge of 114 is transferred to the clamping capacitor C through the diode 115. CL 104 and is stored. LK After the net charge associated with 114 has been transferred, diode 115 substantially stops conducting. Clamp switch 108 remains off until near the end of the off time of power switch S1 145. Once it is determined that the power switch should be turned on, clamp switch 108 is turned on for a first duration. The transistor of clamp switch 108 is turned on, causing the previously transferred charge to clamp capacitor C CL 104 and the leakage inductance L LKThe net charge associated with 114 is transferred to the primary winding 118. Thus, the leakage inductance L LK The energy associated with 114 is returned to the system rather than being dissipated. In one embodiment, the leakage inductance L LK 114 represents the leakage inductance of the energy transfer element 116. The clamp switch 108 is controlled so that the leakage energy is reset and returned to the power converter instead of being dissipated.

[0041] The secondary winding 120 is coupled to a synchronous rectifier 128. The current output from the secondary winding 120 is illustrated as a secondary current I S 121. Output capacitor C O 122 is shown coupled to a synchronous rectifier 128 and an output return 125. The power converter 100 also includes circuitry to regulate the output, which is illustrated as an output quantity U O 136. Usually, the output U O 136 can be the output voltage V O 123, and the output current I O 127, or a combination of the two. The sensing circuit 131 is coupled to sense the output quantity U O 136 and provide feedback signal U FB 132, the feedback signal U FB 132 represents the output quantity U O 136.

[0042] As shown, the secondary controller 137 is coupled to receive a feedback signal U FB 132 and in the feedback signal U FB 132 Generate request signal U below regulation threshold REQ 135. Request signal U REQ 135 is transmitted to the primary controller 133 via a communication link to enable the power switch S1 145. In one embodiment, the primary controller 133 and the secondary controller 137 are galvanically isolated from each other. The communication link may be magnetic coupling or optical coupling.

[0043] The primary controller 133 is coupled to receive the current sensing signal 167 and generate a drive signal U D 144 and clamp enable signal U CE 147. The current sensing signal 167 may represent the switching current I received by the power switch S1 145. D 143 and can be a voltage signal or a current signal. In addition, the primary controller 133 provides a drive signal U 145 to the power switch S1. D144 to control various switching parameters to control the transfer of energy from the input of the power converter 100 through the energy transfer element 116 to the output of the power converter 100. Examples of such parameters may include the switching frequency (or period), duty cycle, on-time and off-time of the power switch S1 145, or changing the number of pulses per unit time of the power switch S1 145. In addition, the power switch S1 145 may be controlled so that it has a fixed switching frequency or a variable switching frequency. In one embodiment of the variable switching frequency control, the switching frequency may be reduced for light load conditions or no load conditions. Previously, it was difficult to achieve zero voltage switching (ZVS) of a flyback converter at a lower switching frequency using conventional active clamping techniques, in which the clamping circuit is turned on during the entire off-time of the power switch.

[0044] The power switch S1 145 responds to the drive signal U D 144 is opened and closed. In operation, the switching of the power switch S1145 generates a pulsating secondary current Is 121. The pulsating secondary current I S 121 through the output capacitor C O 122 filtering to produce a substantially constant output voltage V O 123. Output current I O 127 or a combination of the two. In one embodiment, the power switch S1 145 can be a transistor such as a metal oxide semiconductor field effect transistor (MOSFET). In another embodiment, the power switch S1 145 can include a cascode configuration so that the low voltage transistor is coupled to the high voltage junction field effect transistor (JFET). In one embodiment, the JFET can include gallium nitride (GaN) or silicon carbide (SiC) material. The primary controller 133, the secondary controller 137 and the power switch 145 can be implemented as a monolithic integrated circuit or can be implemented with discrete electrical components or a combination of discrete components and integrated components.

[0045] Figure 2 This example shows the various control modes. Figure 1 A diagram of the current of the power switch S1 145, the diagram including the switch on time t ON 269. Switch off time t OFF 270. Switching cycle T S 271 , a trapezoidal shape 272 and a triangular shape 273 . Figure 2 The general waveform of the current through the power switch S1 145 over time in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is illustrated.

[0046] In any switching cycle T SDuring 271, the power switch S1 145 may respond to the drive signal U from the primary controller 133. D 144 and conduction to adjust the output U O 136. Switching cycle T S 271 can be divided into two time sections: switch on time t ON 269. Switch off time t OFF 270. Switch on time t ON 269 ​​represents the switching period T S 271, the portion of the power switch S1 145 conducting. The switch off time t OFF 270 represents the switching period T S 271 when the power switch S1 110 is not conducting. Figure 2 The current waveforms of FIG. 27 show two basic operating modes. The trapezoidal shape 272 is characteristic of CCM, while the triangular shape 273 is characteristic of DCM. During CCM, during the switch on time t ON 269 ​​The current through the power switch S1 145 is substantially non-zero immediately after the start of the switch, and is constant throughout the switch on time t ON 269 ​​increases steadily. During DCM, during the switch on time t ON 269 ​​The current through the power switch S1 145 is substantially zero at the beginning and remains constant throughout the switch on time t ON 269 ​​has increased steadily from zero.

[0047] Figure 3 The embodiments according to the present disclosure are illustrated Figure 1 It should be understood that Figure 3 The control circuit 339 may be Figure 1 The present invention is an embodiment of a control circuit 139 of the present invention, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0048] The control circuit 339 includes an enable circuit 305, flip-flops 315 and 375, a set-reset (SR) latch 338, comparators 317 and 319, a delay circuit 360, and a monostable multivibrator 307. The delay circuit 360 includes a first switch 358, a second switch 359, a first delay circuit 361, and a second delay circuit 362.

[0049] The control circuit 339 can select the control signal U CTRL 342, the control signal U CTRL342 represents the delay time of turning on the power switch. The delay time depends on the operation mode of the power converter, which responds to the input line voltage sensing signal U LS 349, the input line voltage sense signal represents the line input voltage. The comparator 317 is coupled to receive the input line voltage sense signal U at the inverting input. LS 349 and receives the CCM threshold V at the non-inverting input CCM 365. The comparator 317 is configured to receive the line voltage sensing signal U LS 349 is less than the CCM threshold V CCM 365 generates an output having a first state, and when the input line voltage sensing signal U LS 349 is not less than the CCM threshold V CCM The second state is further generated at 365. The output of the comparator 317 is coupled to the set input of the SR latch 338. The SR latch 338 is configured to output the first operation mode signal U of the first state in response to the set input. M1 363. Figure 3 In the embodiment of the present invention, the first operation mode signal U of the first state M1 363 may be logic high. The first operating mode represents CCM operation of the power converter. The SR latch 338 is also configured to output a second operating mode signal U at the inverting output of the SR latch 338. M2 364. Figure 3 In the embodiment of the present invention, the second operation mode signal U of the first state M2 364 can be logic low.

[0050] The comparator 319 is coupled to receive the input line voltage sense signal U at the inverting input. LS 349 and receives the DCM threshold V at the non-inverting input DCM 366. The comparator 319 is configured to receive the line voltage sensing signal U LS 349 is greater than the DCM threshold V DCM 366 generates a first output, and when the input line voltage sensing signal U LS 349 is not greater than the DCM threshold V DCM The second state is further generated when 366. The output of the comparator 319 is coupled to the reset input of the SR latch 338. The SR latch 338 is configured to output the first operation mode signal U in response to the reset input. M1 The second state of 364. Figure 3 In the embodiment of the present invention, the first operation mode signal U M1The second state of 363 may be logic low. The SR latch 338 is also configured to output a second operating mode signal U at the inverting output of the SR latch 338. M2 364. Figure 3 In the embodiment of the present invention, the second operation mode signal U M2 The second state of the second of 364 may be logic high. The second operating mode represents DCM operation of the power converter.

[0051] Before the power switch is turned on, the control circuit 339 turns on the clamp switch to discharge the clamp capacitor. The enabling circuit 305 is coupled to receive the request signal U REQ 135 and is configured to generate an enable signal U EN 374. Request signal U REQ 337 indicates that the power switch is turned on. The monostable multivibrator 307 is coupled to the enabling circuit 305. The monostable multivibrator 307 is configured to output a pulse in a first duration, wherein the monostable multivibrator 307 is configured to output a pulse in a first duration in response to the request signal U REQ 337 determines to turn on the power switch, and the first duration starts near the end of the off time of the power switch. CD 347 indicates that after the duration of the pulse ends, the trigger 315 is configured to respond to the clamping drive signal U CD 347 generates a first logic state. The output of the flip-flop 315 is coupled to the switch 358 and the switch 359. The switch 359 is controlled by the first operation mode signal U M1 359 is closed, and the flip-flop 375 is clocked by the output of the first delay circuit 361. The first delay circuit 361 outputs a first delay, which is the control signal U CTRL 342. The switch 358 is controlled by the second operation mode signal U M2 364 is closed, and the flip-flop 375 is clocked by the output of the second delay circuit 362. The second delay circuit 362 outputs a second delay, which is the control signal U CTRL 342. The second delay time is greater than the first delay time. In one embodiment, the first delay time may be in the range of 50 ns and the second delay time may be in the range of 200 ns. In the first operating mode, the first delay time accounts for the time when the leakage inductance causes the drain-source voltage of the power switch to be substantially zero. In the second operating mode, the second delay time accounts for the time when the leakage inductance and the magnetizing inductance cause the drain-source voltage of the power switch to be substantially zero.

[0052] Figure 4A 1 shows a timing diagram illustrating drain-source voltage, clamp current, switch current of the power switch, secondary current, enable signal and drive signal. It should be understood that Figure 4AThe mentioned signals can be Figure 1 The present invention is an embodiment of a signal of the present invention, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0053] The first timing diagram illustrates the drain-source voltage V DS 453. The second timing diagram illustrates the clamping current I CL 410. The third timing diagram illustrates the switching current I D 443. The fourth timing diagram illustrates the secondary current I S 421. The fifth timing diagram illustrates the clamp enable signal U CE 468. The sixth timing diagram illustrates the driving signal U D 444.

[0054] exist Figure 4A In the embodiment of the present invention, the operation mode for the power converter is a critical conduction mode (CRM), which is determined by the switching current I D The triangle shape of 443 indicates that CRM can occur when the line sense input voltage is above the CCM threshold but below the DCM threshold. In some designs, CRM can be used by Figure 3 The control signal generated by the first delay circuit or the second delay circuit discussed in the above. Before t1, the power switch is turned on, so that the drain-source voltage V DS 453 is zero. Clamping current I CL 410 is zero. The switch current I D 443 is rising. The secondary current I S 421 is zero. Clamp enable signal U CE 468 is zero. The driving signal U D 444 is logic high.

[0055] At time t1, the power switch is turned off, as indicated by the drive signal U D 444 is represented by a logic low. As a result, the drain-source voltage V DS 453 rises to the input voltage plus the clamp voltage. The clamp capacitor is being charged, as indicated by the clamp current I CL 410. The energy stored in the energy transfer element is transferred from the primary winding to the secondary winding, as indicated by the secondary current I S 421. After t1 and before t2, the drain-source voltage V DS 453 rises and becomes equal to the input voltage plus the clamp voltage. The clamp capacitor continues to charge, as indicated by the clamp current I CL 410 decays to zero. D444 is logic low, so the switch current I D 443 is also zero.

[0056] At time t2, the drain-source voltage V DS 453 is reduced to the input voltage plus the reflected output voltage of the secondary winding. The clamping current I CL 410 is zero, indicating that the clamp capacitor is no longer charged. When energy is transferred from the primary winding to the secondary winding, the switch current I D 443 is zero. Secondary current I S 421 is a non-zero value and decreases in a linear manner. CE 468 is logic low. The drive signal U D 444 is logic low. During the time between t2 and t3, the drain-source voltage V DS 453 is non-zero and has a slope of zero indicating that the synchronous rectifier is conducting. CL 410 is zero. The secondary current I S 421 is decreasing linearly. Clamp enable signal U CE 468 is logic low. The drive signal U D 444 is logic low.

[0057] At time t3, the clamp driver generates a clamp enable signal U CE 468 to turn on the clamp switch before the power switch is turned on. DS 453 rises to the clamp voltage plus the input voltage. As energy is transferred to the secondary winding of the energy transfer element, the clamp capacitor discharges, as indicated by the clamp current I CL The negative polarity of 410 indicates the switching current I D 443 is zero. Due to the on-state of the clamp switch, the secondary current I S 421 starts to increase. When the power switch is turned off, the drive signal U D 444 is logic low.

[0058] At time t4, the clamp enable signal U CE 468 transitions to logic low. The clamping current I CL 410 drops to zero. The switch current I D 443 is zero. Drain-source voltage V DS 453 decreases towards the input voltage. D 444 is logic low.

[0059] The time between t4 and time t5 is represented as in Figure 2 The second delay time discussed in the previous section is given by t DEL2 As shown. Figure 2 , the second delay time is denoted as T B The magnetizing inductance and leakage inductance will increase the drain-source voltage V DS 453 is reduced to zero to provide zero voltage switching. In other embodiments for CRM, the leakage inductance can reduce the drain-source voltage V DS 453 is reduced to zero to provide ZVS of the power switch. CL 410 is zero. The switch current I D 443 is zero. Secondary current I S 421 is zero. Clamp enable signal U CE 468 is logic low. The drive signal U D 444 is logic low.

[0060] At time t5, there is a delay time t DEL2 The drain-source voltage V DS 453 is zero, and the power switch is turned on, as indicated by the drive signal U D 444 transitions to logic high. The clamping current I CL 410 is zero. The switch current I D 443 begins to increase linearly. The secondary current I S 421 is zero. Clamp enable signal U CE 468 is logic low.

[0061] After t5 and before t6, the power switch is turned on, as indicated by the drive signal U D 444 is represented by a logic high. The drain-source voltage V DS 453 is zero. The switch current I D 443 increases linearly. In one embodiment, the switch current I D 443 continues to rise until it reaches the current limit (not shown). The secondary current I S 421 is zero. Clamp enable signal U CE 468 is zero.

[0062] At time t6, the power switch is turned off, as indicated by the drive signal U D 444 is represented by a logic low. As a result, the drain-source voltage V DS 453 rises to the input voltage plus the clamp voltage. The clamp capacitor is being charged, as indicated by the clamp current I CL 410. The energy stored in the energy transfer element is transferred from the primary winding to the secondary winding, as indicated by the secondary current I SAfter t1 and before t2, the drain-source voltage is equal to the input voltage plus the clamp voltage. The clamp capacitor is still charging, as indicated by the clamp current I CL 410 decays to zero. D 444 is logic low, so the switch current I D 443 is also zero.

[0063] Figure 4B 1 shows a timing diagram illustrating drain-source voltage, clamp current, switch current of the power switch, secondary current, clamp enable signal and drive signal. It should be understood that Figure 4B The mentioned signals can be Figure 1 The present invention is an embodiment of a signal of the present invention, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0064] The first timing diagram illustrates the drain-source voltage V DS 453. The second timing diagram illustrates the clamping current I CL 410. The third timing diagram illustrates the switching current I D 443. The fourth timing diagram illustrates the secondary current I S 421. The fifth timing diagram illustrates the clamp enable signal U CE 468. The sixth timing diagram illustrates the driving signal U DR 444.

[0065] exist Figure 4B In the embodiment, the operation mode for the power converter is CCM, and the switching current I D The trapezoidal shape of 443 indicates that before t1, the power switch is turned on, so that the drain-source voltage V DS 453 is zero. Clamping current I CL 410 is zero. The switch current I D 443 is rising. The secondary current I S 421 is zero. Clamp enable signal U CE 468 is zero. The driving signal U D 444 is logic high.

[0066] At time t1, the power switch is turned off, as indicated by the drive signal U D 444 transitions to a logic low. As a result, the drain-source voltage V DS 453 rises to the input voltage plus the clamp voltage. The clamp capacitor is being charged, as indicated by the clamp current I CL 410. The energy stored in the energy transfer element is transferred from the primary winding to the secondary winding, as indicated by the secondary current I S421. After t1 and before t2, the drain-source voltage V DS 453 is equal to the input voltage plus the clamp voltage. The clamp capacitor continues to charge, as indicated by the clamp current I CL 410 decays to zero. Because energy is transferred from the primary winding to the secondary winding, the secondary current I S 421 rises. Drive signal U D 444 is logic low, so the switch current I D 443 is also zero.

[0067] At time t2, the drain-source voltage V DS 453 is reduced to the input voltage plus the reflected output voltage of the secondary winding. The clamping current I CL 410 is zero, indicating that the clamp capacitor is no longer charged. When energy is transferred from the primary winding to the secondary winding, the switch current I D 443 is zero. Secondary current I S 421 is a non-zero value and decreases in a linear manner. CE 468 is logic low. The drive signal U DR 444 is logic low. During the time between t2 and t3, the drain-source voltage V DS 453 is non-zero and has a slope of zero indicating that the synchronous rectifier is conducting. CL 410 is zero. The secondary current I S 421 linearly decreases. Clamp enable signal U CE 468 is logic low. The drive signal U D 444 is logic low.

[0068] At time t3, the clamp driver generates a clamp enable signal U CE 468 to turn on the clamp switch before the power switch is turned on. DS 453 rises to the clamp voltage plus the input voltage. As energy is transferred from the primary winding of the energy transfer element to the secondary winding, the clamp capacitor discharges, as indicated by the clamp current I CL The negative polarity of 410 indicates the secondary current I S 421 is non-zero and rises slightly because the energy stored in the clamp capacitor is being transferred to the secondary. The switch current I D 443 is zero. When the power switch is turned off, the drive signal U D 444 is logic low.

[0069] At time t4, the clamp enable signal U CE 468 transitions to logic low. The drain-source voltage V DS453 is rapidly decaying to zero. The clamping current I CL 410 is zero. The switch current I D 443 is zero. The driving signal U DR 444 is logic low.

[0070] The time between t4 and time t5 is represented as in Figure 2 The time T is shown in the discussion A The first delay time is Figure 3 is exemplified as T DEL1 The discharge of the leakage inductance will increase the drain-source voltage V DS 453 is reduced to zero to provide ZVS of the power switch. CL 410 is zero. The switch current I D 443 is zero. Secondary current I S 421 is falling towards zero. The clamp enable signal U CE 468 is logic low. The drive signal U D 444 is logic low.

[0071] At time t5, the drain-source voltage V DS 453 is zero, and the power switch is turned on, as indicated by the drive signal U D 444 transitions to logic high. The clamping current I CL 410 is zero. The switch current I D 443 begins to increase linearly. The secondary current I S 421 is zero. Clamp enable signal U CE 468 is logic low.

[0072] After t5 and before t6, the power switch is turned on, as indicated by the drive signal U D 444 is represented by a logic high. The drain-source voltage V DS 453 is zero. The switch current I D 443 continues to rise linearly. In one embodiment, the switch current I D 443 continues to rise until it reaches the current limit (not shown). The secondary current I S 421 is zero. Clamp enable signal U CE 468 is zero.

[0073] At time t6, the power switch is turned off, as indicated by the drive signal U D 444 transitions to a logic low. As a result, the drain-source voltage V DS 453 rises to the input voltage. The clamp capacitor is being charged, as indicated by the clamp current I CL410. The energy stored in the energy transfer element is transferred from the primary winding to the secondary winding, as indicated by the secondary current I S 421. After t6, the drain-source voltage V DS 453 rises to the input voltage plus the clamp voltage. The clamp capacitor continues to charge, as indicated by the clamp current I CL 410 decays to zero. D 444 is logic low, so the switch current I D 443 is also zero.

[0074] Figure 4C 1 shows a timing diagram illustrating drain-source voltage, clamp current, switch current of the power switch, secondary current, clamp enable signal and drive signal. It should be understood that Figure 4C The mentioned signals can be Figure 1 The present invention is an embodiment of a signal of the present invention, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0075] The first timing diagram illustrates the drain-source voltage V DS 453. The second timing diagram illustrates the clamping current I CL 410. The third timing diagram illustrates the switching current I D 443. The fourth timing diagram illustrates the secondary current I S 421. The fifth timing diagram illustrates the clamp enable signal U CE 468. The sixth timing diagram illustrates the driving signal U D 444.

[0076] exist Figure 4C In the embodiment, the operation mode for the power converter is DCM, and the switching current I D The triangle shape of 443 indicates that before t1, the power switch is turned on, so that the drain-source voltage V DS 453 is zero. Clamping current I CL 410 is zero. The switch current I D 443 is rising. The secondary current I S 421 is zero. Clamp enable signal U CE 468 is zero. The driving signal U D 444 is logic high.

[0077] At time t1, the power switch is turned off, as indicated by the drive signal U D 444 is represented by a logic low. As a result, the drain-source voltage V DS 453 rises to the input voltage. The clamp capacitor is charged, as indicated by the clamp current I CL410. The energy stored in the energy transfer element is transferred from the primary winding to the secondary winding, as indicated by the secondary current I S 421. After t1 and before t2, the drain-source voltage V DS 453 rises to the input voltage plus the clamp voltage. The clamp capacitor continues to charge, as indicated by the clamp current I CL 410 decays to zero. D 444 is logic low, so the switch current I D 443 is also zero.

[0078] At time t2, the drain-source voltage V DS 453 is reduced to the input voltage plus the reflected output voltage of the secondary winding. The clamping current I CL 410 is zero, indicating that the clamp capacitor is no longer charged. When energy is transferred from the primary winding to the secondary winding, the switch current I D 443 is zero. Secondary current I S 421 is a non-zero value and decreases in a linear manner. CE 468 is logic low. The drive signal U D 444 is logic low. During the time between t2 and t3, the drain-source voltage V DS 453 is non-zero and has a slope of zero indicating that the synchronous rectifier is conducting. CL 410 is zero. The secondary current I S 421 linearly decreases. Clamp enable signal U CE 468 is logic low. The drive signal U D 444 is logic low.

[0079] At time t3, the drain-source voltage V DS 343 begins to oscillate - caused by the completion of the energy transfer from the primary winding to the secondary winding, making the secondary current Is 421 zero. The oscillation is caused by the resonant tank formed by the leakage inductance and the magnetizing inductance and the resonant capacitance of the power switch. At time t4, the drain-source voltage V DS 453 is at the peak, and the clamp driver generates a clamp enable signal U CE 468 to turn on the clamp switch before the power switch is turned on, which causes the drain-source voltage V DS 453 rises again to the input voltage plus the clamp voltage. As energy is transferred from the clamp capacitor through the primary winding of the energy transfer element to the secondary winding, the clamp capacitor discharges, as indicated by the clamp current I CL The negative polarity of 410 indicates the switching current I D443 is zero. Due to the on-state of the clamp switch, the secondary current I S 421 starts to increase, indicating that the energy stored in the clamp capacitor is transferred to the secondary winding through the primary winding. Because the power switch is turned off, the drive signal U D 444 is logic low.

[0080] At time t5, the clamp enable signal U CE 468 transitions to logic low. The clamping current I CL 410 drops to zero. The switch current I D 443 is zero. Drain-source voltage V DS 453 decreases towards zero. The drive signal U DR 444 is logic low.

[0081] The time between t5 and time t6 is represented as in Figure 2 The delay time discussed in the previous section is given by t DEL1 As shown. Although the drain-source voltage V DS 453 is falling towards zero, but the leakage inductance causes a brief slight increase. For DCM operation, the leakage inductance and magnetizing inductance can increase the drain-source voltage V DS 453 is reduced to zero to provide zero voltage switching. CL 410 is zero. The switch current I D 443 is zero. Secondary current I S 421 is zero. Clamp enable signal U CE 468 is logic low. The drive signal U D 444 is logic low.

[0082] At time t6, the drain-source voltage V DS 453 is zero, and the power switch is turned on, as indicated by the drive signal U D 444 transitions to logic high. The clamping current I CL 410 is zero. The switch current I D 443 begins to increase linearly. The secondary current I S 421 is zero. Clamp enable signal U CE 468 is logic low.

[0083] After t6 and before t7, the power switch is turned on, as indicated by the drive signal U D 444 is represented by a logic high. The drain-source voltage V DS 453 is zero. The switch current I D 443 rises linearly. In one embodiment, the switch current continues to rise until it reaches the current limit (not shown). The secondary current I S421 is zero. Clamp enable signal U CE 468 is zero.

[0084] At time t7 , the power switch is turned off and the behavior is the same as described previously after time t1 .

[0085] Figure 5A An example of a timing diagram illustrating signals of a power converter, such as drain voltage, enable signal, and drive signal, according to an embodiment of the present disclosure is illustrated. It should be understood that Figure 5A The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0086] The first timing diagram is the drain-source voltage V DS 553. The second timing diagram is the clamp enable signal U CE 568. The third timing diagram is the driving signal U D 544. The operation of the power converter is CRM, but may also be CCM. As previously mentioned, CRM may occur when the line sense input voltage is above the CCM threshold but below the DCM threshold. In some designs, CRM can use a control signal generated by the first delay circuit or the second delay circuit.

[0087] Before t1, the driving signal U D 544 is logic high, which means the power switch is turned on. DS 553 is zero. Clamp enable signal U CE 568 is logic low. At time t1, the drive signal U D 544 transitions to logic low, which indicates that the power switch is turned off. DS 553 rises to the input voltage. After time t1 and before t2, the drain-source voltage V DS 553 rises to the clamping voltage plus the input voltage. At time t2, the drain-source voltage V DS 553 is reduced to the input voltage plus the reflected output voltage of the secondary winding. At time t3, the clamp enable signal U CE 568 transitions to logic high. Because the clamp switch is turned on, the drain-source voltage V DS 553 rises to the clamping voltage. At the time after t3 and before t4, the drain-source voltage V DS 553 starts to decrease. Clamp enable signal U CE 568 is logic high. The drive signal U D 544 is logic low.

[0088] At time t4, the clamp enable signal U CE 568 transitions to logic low. The drain-source voltage V DS 553 decreases toward zero. After time t4 and before t5 represents the first delay time t generated as a control signal before the power switch is turned on. DEL1 At time t5, the drain-source voltage V DS 553 is at zero. The drive signal U D 544 transitions to logic high. At a time after t5 and before t6, the drain-source voltage V DS 553 is zero. Clamp enable signal U CE 568 is zero. The driving signal U D 544 is logic high. At time t6, the drive signal U DR 544 transitions to logic low, which indicates that the power switch is turned off. DS 553 rises to the input voltage. After time t6 and before t7, the drain-source voltage V DS 553 rises to the clamping voltage plus the input voltage. At time t7, the drain-source voltage V DS The 553 steps down to the input voltage plus the reflected output voltage from the secondary winding.

[0089] Figure 5B An example of a timing diagram illustrating signals of a power converter, such as drain voltage, enable signal, and drive signal, according to an embodiment of the present disclosure is illustrated. It should be understood that Figure 5B The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0090] The power converter operates in DCM. The first timing diagram is the drain-source voltage V DS 553. The second timing diagram is the clamp enable signal U CE 568. The third timing diagram is the driving signal U D 544.

[0091] Before t5, the power switch is turned on, causing the drain-source voltage V DS 553 is zero. The driving signal U D 544 is logic high. Clamp enable signal U CE 568 is logic low.

[0092] At time t5, the power switch is turned off, as indicated by the drive signal U DR 544 is represented by a logic low. As a result, the drain-source voltage V DS553 rises to the input voltage. Clamp enable signal U CE 568 is logic low. After t5 and before t6, the drain-source voltage V DS 553 rises to the input voltage plus the clamping voltage. After that, the drain-source voltage V DS 553 starts to oscillate, which is caused by the completion of energy transfer from the primary winding to the secondary winding. The oscillation is caused by the resonant circuit formed by the leakage inductance and magnetizing inductance and the resonant capacitance of the power switch. The drive signal U D 444 is logic low. Clamp enable signal U CE 568 is logic low.

[0093] At time t6, the clamp enable signal U CE 568 becomes logic high. Drain-source voltage V DS 553 is clamped by the clamp capacitor and the input voltage. At time t7, the clamp enable signal U CE 568 becomes logic low. The drain-source voltage V DS 553 decreases towards zero. After time t7 and before t8 represents the delay t generated as the control signal before the power switch is turned on. DEL2 At time t8, the drain-source voltage V DS 553 is zero. The driving signal U D 544 turns to logic high. At time t8, the power switch is turned on, causing the drain-source voltage V DS 553 is zero. The driving signal U DR 544 is logic high until time t9. The clamp enable signal U CE 568 is logic low until time t9. At time t9, the drive signal U DR 544 becomes logic low, and the power switch is turned off, and the drain-source voltage V DS 553 started to rise.

[0094] Fig. 6A An example timing diagram of the drain voltage of a power switch according to an embodiment of the present disclosure is illustrated. It should be understood that Fig. 6A The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0095] exist Fig. 6A In the drain-source voltage V DS 653 indicates that the power converter operates in CCM. The delay time t represented by time t1 to time t2 DEL1is the delay between the clamp switch turning off and the power switch turning on. As mentioned earlier, only the energy from the leakage inductance can be used to make the drain-source voltage V DS 653 to zero. After time t2, if the power switch is not turned on, the drain-source voltage V DS The dotted line increases sharply, which is caused by the resonant tank of the leakage inductance and the resonant capacitance of the power switch.

[0096] Figure 6B Another example timing diagram of the drain voltage of a power switch according to an embodiment of the present disclosure is illustrated. It should be understood that Figure 6B The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0097] Drain-source voltage V DS 653 indicates that the power converter operates in DCM. The delay time t represented by time t1 to time t2 DEL2 Represents the delay between the clamp switch turning off and the power switch turning on. The second delay time t DEL2 Longer than Fig. 6A The first delay time t DEL1 , the energy from the leakage inductance and magnetizing inductance can be used to increase the drain-source voltage V DS 653 to zero. After time t2, if the power switch is not turned on, the dotted line of the drain-source voltage increases sharply, which is caused by the resonant tank composed of the leakage inductance and the magnetizing inductance and the resonant capacitance of the power switch.

[0098] Figure 6C Another example of a timing diagram of the drain voltage of a power switch according to an embodiment of the present disclosure is illustrated. It should be understood that Figure 6C The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0099] Drain-source voltage V DS 653 indicates that the power converter operates in DCM. The delay time t represented by time t1 to time t2 DEL2 represents the delay between the clamp switch turning off and the power switch turning on. Before t1, the drain-source voltage V DS The oscillation of 653 indicates the end of secondary conduction caused by the resonant tank of leakage inductance and output capacitance. DEL3 represents the time before the power switch is turned on. The energy from the leakage inductance and magnetizing inductance can be used to make the drain-source voltage V DS 653 to zero. Use the magnetizing inductance to reduce the drain-source voltage VDS The benefit of 653 allows for minimal overshoot of the drain-source voltage of the synchronous rectifier.

[0100] Figure 7 1 illustrates a timing diagram of the drain voltage of a power switch according to an embodiment of the present disclosure. It should be understood that Figure 7 The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0101] This timing diagram illustrates the rise to voltage V CL1 710 drain-source voltage V DS 753, when the power switch is turned off, the voltage V CL1 710 is equal to the clamping voltage V CL 709 plus input voltage V IN 701, and the voltage V CL1 710 reaches zero at t2. At time t1, when the clamp switch is turned off, the energy stored in the leakage inductance is proportional to V CL YesL LK I^2. Turning off the clamp switch causes current to enter the resonant capacitor and begin to charge negatively relative to the clamp voltage. Depending on the application, the peak current of the power switch is defined. When the peak current of the power switch has been defined and the amount of energy that will charge the clamp capacitor can be determined, the leakage inductance to achieve ZVS can be calculated by L LK =(C RES *VC L1 2 ) / (0.65*I LIMPK ) 2 Definition. Capacitor C RES is the capacitance of the power switch, and I LIMPK is the peak current of the switch. The time from t1 to t2 represents the time when ZVS occurs, a function of the resonant period formed by the leakage inductance and the resonant capacitance, and the theoretical unclamped voltage amplitude V of the ring TOTAL It can be defined by the following formula

[0102]

[0103] At time t3 , if the power switch is not turned on, the resonant tank formed by the leakage inductance and the output capacitance of the power switch may cause the drain-source voltage to rise rapidly.

[0104] Figure 8 1 illustrates a timing diagram of the drain voltage of a synchronous rectifier switch and the drain voltage of a power switch according to an embodiment of the present disclosure. It should be understood that Figure 8The signals mentioned may be one embodiment of signals from previous figures, and similarly named and numbered elements mentioned below may be coupled and function similarly to those described above.

[0105] The first timing diagram illustrates the drain-source voltage V SR 855. The second timing diagram illustrates the drain-source voltage V DS 853. Synchronous rectifier drain-source voltage V SR 855 and the drain-source voltage of the power switch V DS 853 can be a reflection of each other. In other words, when the drain-source voltage V DS When 853 is zero, the drain-source voltage V SR 855 is positive. When the drain-source voltage V DS When 853 is positive, the drain-source voltage V SR 855 is zero.

[0106] exist Figure 8 In the case of a power converter, the operation is DCM. At time t1, when the synchronous rectifier switch is turned on, the drain-source voltage V SR 855 is zero, and when the power switch is turned off, the drain-source voltage V DS 853 at the input voltage plus the clamp voltage. Before the transition of the power switch, the clamp switch is enabled to make the drain-source voltage V DS 853 to zero. Thus, energy is stored in the leakage inductance and magnetizing inductance. When the clamp switch is turned off, the leakage inductance will reduce the drain-source voltage V DS 853 drops from the input voltage plus the clamp voltage to a lower value clamped by the magnetizing inductance, which is indicated by a small oscillation in the voltage. The discharge of the magnetizing inductance continues to drive the drain-source voltage V DS 853 decreases to zero. The drain-source voltage V DS The dotted line 853 indicates that if the power switch is not turned on, the resonant circuit will cause the drain-source voltage V DS 853 oscillation.

[0107] At time t2, when the drain-source voltage V DS When 953 is zero, the power switch is turned on, which provides minimum overshoot of the synchronous rectifier.

[0108] The above description of the illustrated embodiments of the present invention, including the content described in the summary, is not intended to be exhaustive or to limit the exact form disclosed. Although specific embodiments and embodiments of the present invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. In fact, it should be understood that providing specific example voltages, currents, frequencies, power range values, times, etc. is for the purpose of explanation, and other values ​​may also be adopted in other embodiments and embodiments according to the teachings of the present invention.

[0109] Although the invention is defined in the claims, it will be appreciated that the invention may alternatively be defined according to the following embodiments:

[0110] Embodiment 1: A controller configured for use in a power converter, the controller comprising: a control circuit coupled to receive an input line voltage sensing signal representing an input voltage of the power converter, the control circuit configured to generate a control signal in response to a request signal representing an output of the power converter, wherein in response to the input line voltage sensing signal, the control signal represents a delay time for turning on a power switch after turning on a clamp switch, the control circuit further configured to generate a clamp drive signal to control a clamp driver; and a drive circuit configured to generate a drive signal to control the power switch to transfer energy from the input of the power converter to the output of the power converter.

[0111] Embodiment 2: According to the controller described in Embodiment 1, the control circuit includes: an enable circuit, which is configured to generate an enable signal in response to the request signal; and a monostable multivibrator, which is configured to generate the clamp drive signal in response to the enable signal to turn on the clamp switch, and the monostable multivibrator is configured to output a pulse within a first duration, wherein in response to determining to turn on the power switch, the first duration starts near the end of the off time of the power switch.

[0112] Embodiment 3: According to the controller of any one of the preceding embodiments, the control circuit further comprises a trigger coupled to the monostable multivibrator, the trigger being configured to generate a first logic state in response to the clamp drive signal.

[0113] Embodiment 4: The controller according to any one of the preceding embodiments, wherein the control circuit is further configured to control the clamp driver to inject the charge stored in the clamp capacitor into the energy transfer element to discharge the parasitic capacitance of the power switch into the energy transfer element before turning on the power switch.

[0114] Embodiment 5: A controller according to any one of the preceding embodiments, wherein the control circuit further comprises a delay circuit, wherein the delay circuit is configured to delay the turning-on of the power switch to provide sufficient time for the parasitic capacitance of the power switch to discharge into the energy transfer element before turning on the power switch.

[0115] Embodiment 6: According to the controller described in any one of the preceding embodiments, the delay circuit includes: a first switch, the first switch is controlled by a first operating mode signal; a first delay circuit, the first delay circuit is coupled to the first switch, and the first delay circuit is configured to output the control signal after a first delay time; a second switch, the second switch is controlled by a second operating mode signal; and a second delay circuit, the second delay circuit is coupled to the second switch, and the second delay circuit is configured to output the control signal after a second delay time, wherein the second delay time is greater than the first delay time.

[0116] Embodiment 7: A controller according to any one of the preceding embodiments, wherein the control circuit further comprises: a first comparator, the first comparator being configured to determine whether the input line voltage sensing signal is less than a continuous conduction mode (CCM) threshold; a second comparator, the second comparator being configured to determine whether the input line voltage sensing signal is greater than a discontinuous conduction mode (DCM) threshold; and a set-reset (SR) latch, the set-reset (SR) latch having a set input coupled to the output of the first comparator, the SR latch also being coupled to a reset input coupled to the output of the second comparator, the SR latch being configured to output a first operating mode signal, and the SR latch being further configured to output a second operating mode signal.

[0117] Embodiment 8: The controller according to any one of the preceding embodiments, wherein the first operation mode signal indicates DCM operation of the power converter.

[0118] Embodiment 9: The controller according to any one of the preceding embodiments, wherein the second operation mode signal indicates CCM operation of the power converter.

[0119] Embodiment 10: A power converter, comprising: an energy transfer element, the energy transfer element coupled between the input of the power converter and the output of the power converter; a power switch, the power switch coupled to the energy transfer element; a clamp driver, the clamp driver coupled to the energy transfer element and the power switch; and a primary controller, the primary controller coupled to the clamp driver and the power switch, the primary controller comprising: a control circuit, the control circuit being configured to generate a control signal in response to a request signal representing the output of the power converter, wherein the control signal selects one of a plurality of operating modes in response to an input line voltage sensing signal to turn on the power switch after the clamp switch is turned on, the control circuit being further configured to generate a clamp drive signal to control the clamp driver; and a drive circuit, the drive circuit being configured to generate a drive signal to control the power switch to transfer energy from the input of the power converter to the output of the power converter.

[0120] Embodiment 11: The power converter of Embodiment 10, the clamp driver comprising a clamp capacitor coupled to the clamp switch, wherein the clamp capacitor is coupled to store charge injected into the primary winding of the energy transfer element through the clamp switch in response to the clamp drive signal.

[0121] Embodiment 12: The power converter according to any one of the preceding embodiments, wherein the energy transfer element further comprises a magnetizing inductance and a leakage inductance between the clamp driver and the primary winding.

[0122] Embodiment 13: A power converter according to any one of the preceding embodiments, wherein the plurality of operating modes comprises a first operating mode and a second operating mode, wherein the first operating mode is a continuous conduction mode (CCM), and wherein the second operating mode is a discontinuous conduction mode (DCM).

[0123] Embodiment 14: The power converter of any of the preceding embodiments, wherein in response to the clamp switch being turned on, the leakage inductance of the energy transfer element reduces a drain-source voltage of the power switch to substantially zero.

[0124] Embodiment 15: The power converter of any of the preceding embodiments, wherein in response to the clamp switch being turned on, the leakage inductance and the magnetizing inductance of the energy transfer element reduce the drain-source voltage of the power switch to substantially zero.

[0125] Embodiment 16: According to the power converter described in any one of the preceding embodiments, the clamp driver includes: a low-side driver, the low-side driver is coupled to receive the clamp drive signal, the low-side driver is configured to communicate the turning on of the clamp switch; a high-side driver, the high-side driver is coupled to the clamp switch, the high-side driver is configured to generate a clamp enable signal to control the clamp switch; and a communication link, the communication link is coupled to the low-side driver and the high-side driver.

[0126] Embodiment 17: According to any one of the preceding embodiments, the power converter further comprises a secondary controller configured to generate the request signal in response to a feedback signal representing the output of the power converter.

[0127] Embodiment 18: The power converter according to any one of the preceding embodiments, wherein the secondary controller is galvanically isolated from the primary controller.

[0128] Embodiment 19: According to the power converter described in any one of the preceding embodiments, the enable circuit is configured to generate an enable signal in response to the request signal; and a monostable multivibrator is configured to generate the clamp drive signal in response to the enable signal to turn on the clamp switch, and the monostable multivibrator is also configured to output a pulse within a first duration, wherein in response to determining to turn on the power switch, the first duration starts near the end of the off time of the power switch.

[0129] Embodiment 20: According to the power converter of any one of the preceding embodiments, the control circuit further comprises a flip-flop coupled to the monostable multivibrator, the flip-flop being configured to generate a first logic state in response to the clamp drive signal.

[0130] Embodiment 21: A power converter according to any one of the preceding embodiments, wherein the control circuit further comprises a delay circuit configured to delay turning on the power switch to provide sufficient time for the parasitic capacitance of the power switch to discharge into the energy transfer element before turning on the power switch.

[0131] Embodiment 22: A power converter according to any one of the preceding embodiments, wherein the delay circuit comprises: a first switch, the first switch being configured to be controlled by a first operating mode signal; a first delay circuit, the first delay circuit being configured to output the control signal after a first delay time; a second switch, the second switch being coupled to be controlled by a second operating mode signal; and a second delay circuit, the second delay circuit being configured to output the control signal after a second delay time, wherein the second delay time is greater than the first delay time.

[0132] Embodiment 23: According to the power converter described in any one of the preceding embodiments, the control circuit further includes: a first comparator, the first comparator is configured to determine whether the input line voltage sensing signal is less than a continuous conduction mode (CCM) threshold; a second comparator, the second comparator is configured to determine whether the input line voltage sensing signal is greater than a discontinuous conduction mode (DCM) threshold; and a set-reset (SR) latch, the set-reset (SR) latch having a set input coupled to the output of the first comparator, the SR latch also coupled to a reset input coupled to the output of the second comparator, the SR latch being configured to output a first operating mode signal, and the SR latch being further configured to output a second operating mode signal.

Claims

1. A primary controller configured for use in a power converter, the power converter comprising an active clamp circuit and a power switch, the primary controller comprising: a control circuit configured to be coupled to receive an input line voltage sense signal representative of an input voltage of the power converter, wherein the control circuit is configured to: a) generating a control signal in response to a request signal communicated to the primary controller to enable the power switch, wherein the request signal is generated by a secondary controller coupled to receive a feedback signal representative of an output of the power converter and represents a determination to turn on the power switch, wherein the control signal represents a delay time for turning on the power switch after turning off of a clamp switch, wherein the delay time of the control signal is selected in response to the input line voltage sensing signal, and b) generating a clamp drive signal to control a clamp driver to turn on the clamp switch for a specified, fixed duration; as well as A drive circuit is coupled to receive the control signal and is configured to generate a drive signal to control the power switch to transfer energy from the input of the power converter to the output of the power converter.

2. The primary controller according to claim 1, wherein the control circuit comprises: an enable circuit configured to generate an enable signal in response to the request signal; as well as a monostable multivibrator configured to generate the clamp drive signal to turn on the clamp switch in response to the enable signal, the monostable multivibrator configured to output a pulse for a first duration, wherein the power switch is turned on in response to a determination represented by the request signal, the first duration starting near the end of an off time of the power switch.

3. The primary controller of claim 2, the control circuit further comprising a flip-flop coupled to the monostable multivibrator, the flip-flop configured to generate a first logic state in response to the clamp drive signal.

4. The primary controller of claim 1 , wherein the control circuit is further configured to control the clamp driver to inject the charge stored in the clamp capacitor into the energy transfer element to discharge the parasitic capacitance of the power switch into the energy transfer element within a specified time before turning on the power switch.

5. The primary controller of claim 4, wherein the control circuit further comprises a delay circuit configured to delay turning on of the power switch to provide sufficient time for a parasitic capacitance of the power switch to discharge into an energy transfer element before turning on the power switch.

6. The primary controller of claim 5, wherein the delay circuit comprises: a first switch controlled by a first operation mode signal; a first delay circuit, the first delay circuit being coupled to the first switch, the first delay circuit being configured to output the control signal after a first delay time; a second switch controlled by a second operation mode signal; as well as A second delay circuit is coupled to the second switch, and the second delay circuit is configured to output the control signal after a second delay time, wherein the second delay time is greater than the first delay time.

7. The primary controller of claim 6, wherein the control circuit further comprises: a first comparator configured to determine whether the input line voltage sense signal is less than a continuous conduction mode (CCM) threshold; a second comparator configured to determine whether the input line voltage sense signal is greater than a discontinuous conduction mode (DCM) threshold; and The set-reset latch is an SR latch, which has a set input coupled to the output of the first comparator, and the SR latch also has a reset input coupled to the output of the second comparator. The SR latch is configured to output the first operating mode signal, and the SR latch is also configured to output the second operating mode signal. 8 . The primary controller of claim 7 , wherein the first operating mode signal indicates DCM operation of the power converter and the second operating mode signal indicates CCM operation of the power converter.

9. The primary controller of any one of claims 4 to 8, wherein the control circuit is configured to control the clamp driver to inject the charge within a specified time.

10. A power converter comprising: an energy transfer element coupled between an input of the power converter and an output of the power converter; a power switch coupled to the energy transfer element; a clamp driver coupled to drive an active clamp circuit coupled in parallel to the energy transfer element; a secondary controller configured to generate a request signal in response to a feedback signal representative of the output of the power converter; as well as a primary controller coupled to the clamp driver and the power switch, the primary controller comprising: A control circuit, the control circuit being configured to: a) generating a control signal in response to a request signal communicated to the primary controller to enable the power switch, wherein the request signal is generated by the secondary controller and indicates a determination to turn on the power switch, wherein the control signal selects one of a plurality of operation modes to turn on the power switch after turning off of a clamp switch, wherein a delay time of the control signal is selected in response to an input line voltage sensing signal; as well as b) generating a clamp drive signal to control the clamp driver to turn on the clamp switch for a specified, fixed duration, and A drive circuit is coupled to receive the control signal and is configured to generate a drive signal to control the power switch to transfer energy from the input of the power converter to the output of the power converter.

11. The power converter of claim 10, the clamp driver comprising a clamp capacitor coupled to the clamp switch, wherein the clamp capacitor is coupled to store charge injected into the primary winding of the energy transfer element through the clamp switch in response to the clamp drive signal.

12. The power converter of claim 11, wherein the energy transfer element further comprises a magnetizing inductance and a leakage inductance between the clamp driver and the primary winding.

13. The power converter of claim 12, wherein the plurality of operating modes include a first operating mode and a second operating mode, wherein the first operating mode is a continuous conduction mode (CCM), and wherein the second operating mode is a discontinuous conduction mode (DCM). 14 . The power converter of claim 12 , wherein the leakage inductance of the energy transfer element reduces a drain-source voltage of the power switch to zero in response to the clamp switch being turned on. 15 . The power converter of claim 12 , wherein in response to the clamp switch being turned on, the leakage inductance and the magnetizing inductance of the energy transfer element reduce a drain-source voltage of the power switch to zero.

16. The power converter of claim 11, wherein the clamp driver comprises: a low-side driver coupled to receive the clamp drive signal, the low-side driver configured to communicate the turning on of the clamp switch; a high-side driver coupled to the clamp switch, the high-side driver configured to generate a clamp enable signal to control the clamp switch; as well as A communication link is coupled to the low-side driver and the high-side driver.

17. The power converter according to any one of claims 11-16, wherein the control circuit is configured to control the clamp driver to inject the charge within a specified time.

18. The power converter of claim 11 wherein the secondary controller is galvanically isolated from the primary controller.

19. The power converter according to claim 10, wherein the control circuit comprises: an enable circuit configured to generate an enable signal in response to the request signal; as well as a monostable multivibrator configured to generate the clamp drive signal to turn on the clamp switch in response to the enable signal, the monostable multivibrator further configured to output a pulse for a first duration, wherein the power switch is turned on in response to a determination represented by the request signal, the first duration beginning near the end of an off time of the power switch.

20. The power converter of claim 19, the control circuit further comprising a flip-flop coupled to the monostable multivibrator, the flip-flop configured to generate a first logic state in response to the clamp drive signal.

21. The power converter of claim 20, wherein the control circuit further comprises a delay circuit configured to delay turning on the power switch to provide sufficient time for a parasitic capacitance of the power switch to discharge into the energy transfer element before turning on the power switch.

22. The power converter of claim 21 , wherein the delay circuit comprises: a first switch configured to be controlled by a first operation mode signal; a first delay circuit, the first delay circuit being configured to output the control signal after a first delay time; a second switch coupled to be controlled by a second operating mode signal; as well as A second delay circuit is configured to output the control signal after a second delay time, wherein the second delay time is greater than the first delay time.

23. The power converter according to claim 22, wherein the control circuit further comprises: a first comparator configured to determine whether the input line voltage sense signal is less than a continuous conduction mode (CCM) threshold; a second comparator configured to determine whether the input line voltage sense signal is greater than a discontinuous conduction mode (DCM) threshold; and The set-reset latch is an SR latch, which has a set input coupled to the output of the first comparator, and the SR latch also has a reset input coupled to the output of the second comparator. The SR latch is configured to output a first operating mode signal, and the SR latch is also configured to output a second operating mode signal.

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