A decoder, an encoder and methods for decoding and encoding wireless communications signals

Abstract

An electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors. An electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically 5 interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101). A first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a 10 respective output for each column of memristors.

Description

[0001] A DECODER, AN ENCODER AND METHODS FOR DECODING AND ENCODING WIRELESS COMMUNICATIONS SIGNALS

[0002] TECHNICAL FIELD

[0003] The embodiments herein relate to a channel encoder or decoder and a method for encoding or decoding communications signals. A corresponding computer program and a computer program carrier are also disclosed.

[0004] BACKGROUND

[0005] In communication systems, data transmission involves processing and transmitting signals from a transmitter through either a wired or wireless link. At the receiver end, the received signal is processed to extract the original transmitted data. Noise, interference, and device non-idealities cause errors in data transmission. On the other hand, there are many applications like remote surgery and autonomous vehicles, which require a very low probability of error since any noticeable error may result in catastrophic outcomes. Thus, achieving a very high-performance and low error rate is a critical demand in for example wireless communication systems.

[0006] In a typical wireless communication system 10 schematically illustrated in Figure 1 , communication is performed between multiple user equipments (UE) 12, 14, 16 such as cell phones, Internet of Things (loT) devices, etc. and a base station (BS) 11 via a respective wireless channel 22, 24, 26.

[0007] In order to improve reliability and performance, a technique called channel coding is employed in many systems to ensure that the received data is most likely the same as the transmitted data. This is achieved at the expense of reduced throughput and increased implementation complexity.

[0008] Channel coding is a two-step process known as channel encoding and channel decoding, which are performed in transmitter and receiver, respectively. Channel encoding may be seen as adding redundancy to the transmitted information bits in a controlled way. More specifically, every K information bits of the original message are mapped to N bits of encoded data, which are called code words. Under this definition, the code rate is determined as R = K / N and the structured redundancy added in the coding is called parity, which has N-K bits. The channel decoder uses the parity bits to correct a limited number of errors and eventually recovers the original information sequence without retransmission.

[0009] Figure 2 is a schematic illustration of data transmission over the wireless channel and processing of wireless signals in a transmitter chain 210 and in a receiver chain 220.

[0010] At a transmitter (TX) side, i.e. , in the transmitter chain 210, information bits are encoded with a channel encoder 211 , and the encoded bits are mapped to constellation symbols by a symbol mapper 213. Before mapping the bits to constellation symbols the bits may be interleaved in an interleaver 212. The symbols may be precoded in a precoder 214. The symbols are then modulated by a modulator 215, such as by an Orthogonal Frequency Division Multiplexing (OFDM) modulator, and then converted to analog signals to be transmitted over the wireless channel in the uplink or downlink path using one or more antennas. The OFDM modulator may use an Inverse Discrete Fourier Transform (IDFT) for the modulation.

[0011] The modulated symbols are then passed through a digital front end 216. The digital front end 216 may include digital signal conditioning to convert the baseband signal to a conditioned signal that compensates for inaccuracies in the analog transmit chain. Functions of the digital front end 216 may include Digital Upconversion (DUO), also known as channelization.

[0012] The symbols are then passed through an analog front end 218. The TX / RX analog and digital front-end chains may include several modules such as low noise amplifiers (LNAs), mixers, analog to digital converters, and filters. These blocks perform several operations such as amplifying, filtering, predistortion, and down / up conversion of the transmitted / received signals. The calibration and compensation for hardware imperfections may be done either in the analog chains and / or in the digital front-end. Moreover, one of the tasks in the digital front-end block is to perform symbol synchronization to determine the exact timing of the incoming OFDM symbols.

[0013] The analog signals are propagated from one or more antennas 219 through the atmosphere in the form of electromagnetic waves, and they are received by one or more antennas at the receiver (RX) side. The receiver chain 220 performs inverse transformations (demodulation) on the received signals in a demodulator 223 and corrects errors introduced by the propagation channel and TX / RX chains to extract the transmitted information, e.g., from a certain UE. To this end, the received signal goes through the analogue front-end and is eventually filtered and demodulated. Then, the received symbols are detected in a detector 224, demapped by a symbol demapper 226, and decoded by a channel decoder 228 to obtain an estimate of the transmitted bits.

[0014] In the detection process, the receiver chain 220 may need to know the channel state. This may be done by, for example, sending known pilots used to estimate the effects of the propagation channel on the transmitted signal. The receiver chain 220 may comprise a channel estimator 225.

[0015] Furthermore, the receiver chain may also comprise a de-interleaver 227.

[0016] Channel coding is considered as a key technology in Fifth Generation (5G) networks, as well as in 4G and 6G networks, complying with third generation partnership program (3GPP). In such systems, the data transmission is done through uplink and downlink paths as described further below.

[0017] Channel coding schemes have been widely used in:

[0018] • wireless communication systems to improve the communication performance and reliability of the system. For example, Turbo, Low-Density Parity-Check (LDPC), and Polar codes have been used in 4G and 5G systems.

[0019] • ultra-reliable applications such as remote surgery, robotics, smart factories, etc.

[0020] • storage applications, to protect the data to be written to or read from memories.

[0021] Performance (i.e., bit error rate) of the channel coding schemes is usually improved by increasing the code length. However, a large code length results in a long latency and limited throughput.

[0022] Traditional designs of the channel coding schemes are not flexible and reconfigurable in terms of coding algorithm and code length. In other words, for any specific coding algorithm or code length, the corresponding hardware should be designed from scratch. This is due to the fact that the internal components of the coding hardware like the interleaver / de-interleaver are designed for a certain coding algorithm and code length. So, the traditional hardware implementations of coding schemes cannot support multiple coding algorithms and variable coding lengths with the same hardware.

[0023] Another way to improve the performance is to employ more sophisticated codes. However, such schemes suffer from a very high computational complexity, especially in case of large code lengths. This makes the hardware implementation of such coding schemes very challenging and costly.

[0024] Hardware implementation of non-binary coding is also challenging due to their hardware complexity, especially in a high-order Galois field (GF).

[0025] SUMMARY

[0026] Embodiments herein disclose an electronic device that may operate as a channel encoder or a channel decoder. The electronic device comprises an analog crossbar array.

[0027] An analog crossbar ARRAY is a 2-dimensional array that consists of M*N memristive devices, each of which can be programmed to represent an m-bit binary value.

[0028] According to a first aspect, the object is achieved by an electronic decoder for decoding of block coded wireless communications signals. The electronic decoder comprises at least two electrically interconnected analogue crossbar arrays of memristors. An electrical interconnection between a column of an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays and a row of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays comprises a current-to-voltage converter. A first analogue crossbar array of the at least two analogue crossbar arrays comprises at least a first row of memristors with a single input and a respective output for each column of memristors.

[0029] According to a second aspect, the object is achieved by a receiver for wireless communications signals. The receiver comprises the electronic decoder according to the first aspect.

[0030] According to a third aspect, the object is achieved by an electronic encoder for nonbinary block encoding of wireless communications signals. The electronic encoder comprises an analogue crossbar array of memristors. Each memristor of the analogue crossbar array is configured to be programmed with a respective matrix element of a nonbinary generator matrix for non-binary block code generation. According to a fourth aspect, the object is achieved by a transmitter for wireless communications signals. The transmitter comprises the electronic encoder according to the second aspect.

[0031] According to a fifth aspect, the object is achieved by a network node for a wireless communications network. The network node comprises the receiver according to the second aspect or the transmitter according to the fourth aspect or both.

[0032] According to a sixth aspect, the object is achieved by a wireless communications device comprising the receiver according to the second aspect or the transmitter according to the fourth aspect or both.

[0033] According to a sixth aspect, the object is achieved by a method for decoding of block coded wireless communications signals with an electronic decoder comprising at least two electrically interconnected analogue crossbar arrays of memristors. An electrical interconnection between a column of an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays and a row of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays comprises a current-to-voltage converter. A first analogue crossbar array of the at least two analogue crossbar arrays comprises at least a first row of memristors with a single input and a respective output for each column of memristors. The method comprises iteratively updating, by the at least two electrically interconnected analogue crossbar arrays, probability distributions of bits in an obtained codeword until convergence.

[0034] According to a seventh aspect, the object is achieved by a method for encoding of non-binary block coded wireless communications signals with an electronic encoder comprising an analogue crossbar array of memristors.

[0035] The method comprises programming each memristor of the analogue crossbar array with a respective matrix element of a non-binary generator matrix for non-binary block code generation.

[0036] The method further comprises providing a message vector based on wireless communications signals as input to crossbar rows of the analogue crossbar array.

[0037] The method further obtaining non-binary block coded wireless communications signals at outputs of crossbar columns of the analogue crossbar array. According to a further aspect, the object is achieved by a computer program comprising instructions, which when executed by a processor of a receiving device, causes the receiving device to perform actions according to the sixth aspect, wherein the receiving device comprises the decoder according to the first aspect.

[0038] According to a further aspect, the object is achieved by a computer program comprising instructions, which when executed by a processor of a transmitting device, causes the transmitting device to perform actions according to the seventh aspect, wherein the transmitting device comprises the encoder according to the third aspect.

[0039] According to a further aspect, the object is achieved by a carrier comprising the computer program of the aspect above, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0040] Since the electronic decoder and the electronic encoder each comprise at least an analogue crossbar arrays of memristors a fully parallel implementation of channel decoding and encoding schemes is enabled. The fully parallel implementation may achieve a low latency and ultra-high throughput.

[0041] Embodiments disclosed herein are scalable and independent of the code length. Thus, they may be used for short, medium, and long code lengths.

[0042] Embodiments disclosed herein enable flexibility and reconfigurability in terms of the coding algorithm, which enables achieving a very good decoding performance and low bit error rate. Embodiments disclosed herein may realize any coding scheme in a parallel manner, which is not possible with prior art. As a result, sophisticated coding algorithms may be implemented using embodiments disclosed herein to improve the performance as well as the throughput.

[0043] Since most code designs use binary codes, there is no need for very advanced and high-cost memristive devices to realize the decoder according to embodiments disclosed herein. Thus, cheap and simple memristive devices may be used for this purpose.

[0044] The embodiments disclosed herein support serial, partial parallel, and fully parallel implementation of coding schemes.

[0045] The latency of the embodiments disclosed herein is only limited by the read cycle of crossbar array, and it is not limited by the coding algorithms. Embodiments disclosed herein may reduce the power / energy consumption, which in turn leads to increased battery life at the user equipment (UE) side. This is because embodiments disclosed herein enable to employ a complicated channel coding algorithm, which is not possible using prior art approaches, and therefore achieve better performance, e.g., higher coding gain. Consequently, an additional coding gain may be translated directly to a lower requirement on the signal to noise ratio (SNR) of a link budget and thus lowering the power / energy consumption at the UE. Moreover, the memristive devices consume much lower power compared to traditional digital modules e.g., multipliers, which result in a reduced power / energy consumption for embodiments disclosed herein. This is a critical demand in many use cases, e.g., loT devices.

[0046] Computational complexity is reduced considerably compared to the traditional coding schemes.

[0047] BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the figures, features that appear in some embodiments are indicated by dashed lines.

[0049] The various aspects of embodiments disclosed herein, including particular features and advantages thereof, will be readily understood from the following detailed description and the accompanying drawings, in which:

[0050] Figure 1 is a block diagram schematically illustrating a wireless communication system,

[0051] Figure 2 is a block diagram schematically illustrating a transmitter chain and a receiver chain according to prior art,

[0052] Figure 3 is a block diagram schematically illustrating an electronic device comprising a memristive crossbar array,

[0053] Figure 4a is a block diagram schematically illustrating a transmitter according to some embodiments herein,

[0054] Figure 4b is a block diagram schematically illustrating a receiver according to some embodiments herein,

[0055] Figure 5a is an example ofa generator matrix for a non-binary LDPC code, Figure 5b is an example of a generator matrix for a binary LDPC code, Figure 6a is a block diagram schematically illustrating a parity check matrix, Figure 6b is a block diagram schematically illustrating a Tanner Graph, Figure 7a is a flowchart illustrating embodiments of a method for encoding nonbinary block coded wireless communications signals, Figure 7b is a further flowchart illustrating embodiments of a further method for encoding non-binary block coded wireless communications signals,

[0056] Figure 8 is a block diagram schematically illustrating some embodiments of an encoder,

[0057] Figure 9 is a flowchart illustrating embodiments of a method for decoding block coded wireless communications signals according to some embodiments herein,

[0058] Figure 10a is a block diagram schematically illustrating a decoder according to some embodiments herein,

[0059] Figure 10b is a further block diagram schematically illustrating details of a decoder according to some embodiments herein,

[0060] Figure 10c is a further block diagram schematically illustrating further details of a decoder according to some embodiments herein;

[0061] Figure 10d is a further block diagram schematically illustrating further details of a decoder according to some embodiments herein;

[0062] Figure 10e is a further block diagram schematically illustrating further details of a decoder according to some embodiments herein;

[0063] Figure 10f is a further block diagram schematically illustrating further details of a decoder according to some embodiments herein;

[0064] Figure 10g is a further block diagram schematically illustrating further details of a decoder according to some embodiments herein;

[0065] Figure 10h is a further block diagram schematically illustrating further details of a decoder according to some embodiments herein;

[0066] Figure 11 is a block diagram schematically illustrating a decoder according to some further embodiments herein,

[0067] Figure 12 is a block diagram illustrating embodiments of a crossbar array of memristors,

[0068] Figure 13 is a schematic block diagram illustrating further embodiments of a crossbar array of memristors,

[0069] Figure 14 is a block diagram schematically illustrating a network node.

[0070] Figure 15 is a block diagram schematically illustrating a wireless communications device.

[0071] Figure 16 is a block diagram schematically illustrating a wireless communication system. DETAILED DESCRIPTION

[0072] Embodiments herein relate to decoder, an encoder, a receiver, a transmitter, a network node and a wireless communications device and methods for encoding and decoding wireless communications signals using analogue crossbar arrays of memristors.

[0073] A memristor may also be referred to as a memristive device. Analog memristive devices have emerged as a new technology for storing and processing information in analog domain. These devices make it possible to perform computations in a place where data is stored. This concept is called in-memory computing (or processing in memory), which eliminates the need for moving data from a memory to a processing unit. There are different types of memristive devices, which are differentiated with respect to the used materials, switching principles, device endurance, retention, etc. The main types of memristive devices include phase change memory (PCM), resistive random-access memory (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM), ferroelectric memristive devices (FeRAM). Memristive devices may support a limited bit precision, attributed to the limited number of conductance levels that may be reliably programmed in the device. For example, a PCM device may support around 50 conductance levels, meaning that it may represent around 6 bits.

[0074] A number of memristor devices may be organized to form an analog crossbar array. Figure 3 illustrates an electronic device 301, such as a baseband signal processor, comprising a memristor crossbar array 310 which computes MVM by calculating a dotproduct of the input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines). The memristor crossbar array 310 is a two-dimensional array that comprises an M*N array of memristors 311, 312, 321, 322, each of which may be programmed to represent an m-bit binary value. A memristor is a tunable and programmable. The memristor may comprise a dielectric layer sandwiched by two electrodes. A unique feature of memristors is that the conductance depends on historical electrical signals, making them capable of working as nonvolatile memory. In addition, memristors may store multibit information with continuously tunable conductance, in contrast to binary states “0” and “1” in traditional digital storage systems, equipping them with higher bit density. Thus, the m-bit binary value of the memristor may be set or programmed by applying a current to the memristor. The binary value may depend on the amplitude of the current. Thus, an M x M matrix of binary words, G, may be represented by the memristor crossbar array 310 comprising M x M memristors. The input to the memristor crossbar array 310 is an electronic input signal of multiple samples, such as a vector of M analog voltages, e.g., V, which correspond to M binary values.

[0075] Analog crossbar arrays comprise parallel conductors, such as metal lines, termed word lines and bit lines, respectively, as electrodes of the memristors. The word lines and bit lines may be perpendicular to each other. The memristors are formed at the intersections of word and bit lines. In embodiments herein input conductors 331 of the analog crossbar array 310 corresponds to the word lines and output conductors 332 of the analog crossbar array 310 corresponds to the bit lines.

[0076] The analog crossbar array 310 computes MVM by calculating the dot-product of the input vector applied to crossbar rows (i.e., word lines) and every column of the crossbar (i.e., bit lines), all performed in analog domain using Ohm’s law for multiplication and Kirchhoff’s law for accumulation.

[0077] In Figure 3 the entries of a matrix G (an MxM matrix) are programmed to the memristive devices 311, 312, 321, 322 of the MxM crossbar array 310 while the input vector V (an Mxl vector) is applied to the crossbar rows. Note that, the vector V corresponds to the actual input vector (Input 1, ... , Input M), which may be converted to analog voltages using one or more DAC modules 304 illustrated in Figure 3. As a result, the following MVM may be realized using the illustrated crossbar array 310, j = 1, ..., M (1) where an output vector I is the output current of crossbar columns, which is equal to the result of matrix-vector multiplication, i.e., I = G- V. The output vector I may be converted to the corresponding binary words using one or more ADC modules 305 as shown in Figure 3. This conversion may be done either separately for each crossbar column (i.e., one ADC for each binary word) or in a time-multiplexed fashion and hence reduce ADC overhead (i.e., multiple bit lines may share one ADC 305).

[0078] In this disclosure vectors and matrices are represented using capital boldface letters while their entries are shown using normal letters. Thus, when the electronic input signal is digital then the electronic device 301 further comprises the one or more DACs 304 adapted to convert the input signal of multiple samples to corresponding analogue voltages Vi, V2, ... VN.

[0079] In other words, when the input signal of the multiple samples is digital, the electronic device 301 may further comprise the DACs 304 configured to convert the digital input signal of the multiple samples to the analogue voltages.

[0080] There may be one DAC 304 per input sample. In some other embodiments there may be less than one DAC 304 per input sample as one DAC 304 may be shared among several input samples by multiplexing. For example, two input samples may share the same DAC 304.

[0081] Output signals will be extracted from the bit lines (columns in Figure 3) of the crossbar array 310. If digital output values of the crossbar array 310 are needed then the outputs of the crossbar array 310 may be converted to digital values. Thus, the electronic device 301 may further comprise the one or more ADCs 305 adapted to convert the output samples, comprising analog output current, to corresponding digital output values. In other words, the electronic device 301 may further comprise ADCs 305 configured to convert the output from the respective output conductor to a digital signal.

[0082] If analogue signals are needed in a next block in the processing chain then the ADCs 305 in the electronic device 301 may not be needed.

[0083] Further, if the analogue outputs are sent to another crossbar array then they may be converted to voltage signals, which may be done by a resistor.

[0084] Figure 4a schematically illustrates an embodiment of a transmitter 410 for wireless communications signals comprising an electronic encoder 411. The electronic encoder 411 may be part of a baseband signal processor 400a. In Figure 4a the baseband signal processor 400a further comprises an interleaver 412, a MIMO precoder 413 and an OFDM modulator 414 as well as a filter 401a. The transmitter 410 may further comprise an RF circuit 403a for wireless transmission of the wireless communications signals.

[0085] Figure 4b schematically illustrates an embodiment of a receiver 420 for wireless communications signals comprising a decoder 421. The decoder 421 may be part of a second baseband signal processor 400b. In Figure 4b the second baseband signal processor 400b further comprises a de-interleaver 422, a MIMO detector 423, an OFDM de-modulator 424 and a channel estimator 425 as well as a second filter 401 b. The receiver 420 may further comprise a second RF circuit 403b for wireless reception of the wireless communications signals.

[0086] Channel encoding

[0087] A code may be described with C K,N), where K is a length of an original message and ? is a number of bits per codeword. In such a code, each message which is represented by K bits, is mapped to a certain codeword. This mapping may be described using a Generator matrix, G, which has the dimension of K x N. Thus, the functionality of a linear coding algorithm may be mathematically expressed as v = uG, (1) where u is a vector of message signal, which includes K bits, and v is a vector of codeword, which has N bits. As mentioned, the content and structure of the generator matrix is specified based on the coding algorithm. Depending on the code type, i.e. , binary or non-binary code, the entries of G will be binary or non-binary numbers, respectively.

[0088] Figure 5a illustrates a generator matrix for a non-binary LDPC code in GF(64) with 0(8,16) and a code rate of1

[0089] In case of binary codes, the entries of the generator matrix are single bit, 0 or 1. Figure 5b illustrates a binary LDPC code with 0(5,20) and a code rate of 1 / 4.

[0090] Graph Representations of Codes

[0091] In the context of channel coding, graph representations play an important role in visualizing and understanding the structure of error-correcting codes. These graphical models illustrate the relationships between code bits and parity-check equations, providing insights into the decoding process. There are various graph representations including Tanner Graphs, Trellis Diagrams, Factor Graphs, Checksum Graphs, and Bipartite Graphs. Tanner Graph is commonly used in the area of LDPC codes, as described in the next section.

[0092] Tanner Graph

[0093] Tanner graphs represent LDPC codes, where nodes correspond to code bits and parity checks, and edges represent their connections. These representations are essential for efficient decoding algorithms, like belief propagation, as they help identify and correct errors introduced during data transmission over noisy channels. More specifically, the Tanner Graph represents the parity check matrix, H, of an error correcting code. H is an (N-K)*N matrix. The Tanner graph has N bit nodes (or variable nodes), represented by circles and N-K check nodes, represented by squares. There is an edge between variable node / and check node j if there is a one in row / and column j of H. An example of a parity check matrix where the code has N=7 bits, and K=Q parity checks while the code rate is 6 / 7 is shown in Figure 6a. A corresponding Tanner graph is shown in Figure 6b.

[0094] Method for block coding

[0095] Figure 7a illustrates a high-level flow chart for a method for encoding non-binary block coded wireless communications signals with the electronic encoder 411 comprising the analogue crossbar array 310 of memristors 311 , 312. Each memristor (311 , 312) of the analogue crossbar array is configured to be programmed with a respective matrix element of a non-binary generator matrix for non-binary block code generation.

[0096] The method actions may be performed in any suitable order.

[0097] Action 701

[0098] Each memristor 311 , 312 of the analogue crossbar array 310 is programmed with a respective matrix element of a non-binary generator matrix for non-binary block code generation.

[0099] Action 702

[0100] A message vector, based on wireless communications signals, is provided as input to crossbar rows of the analogue crossbar array 310.

[0101] Action 703

[0102] Non-binary block coded wireless communications signals are obtained at outputs of crossbar columns of the analogue crossbar array 310.

[0103] Figure 7b illustrates a more detailed flow chart for the method for encoding non- binary block coded wireless communications signals with the electronic encoder 411 comprising the analogue crossbar array 310 of memristors 311 , 312. In case of a code with C K,N), a crossbar with K rows and N columns is used. First, the generator matrix is constructed according to the target code and corresponding code parameters. Then, the memristors of the analogue crossbar array 310 will be programmed by the generator matrix such that j-th memristor in the j-th row of the crossbar is programmed by g^. Next, the K entries of the message vector, u, are sent to the the one or more DACs 304 and the output voltage of the DACs will be applied to the K crossbar rows. The analog signals, which are generated at the crossbar columns will be converted to binary values using the one or more ADCs 305.

[0104] Finally, after a read cycle of the analogue crossbar array 310, the generated binary words at the crossbar columns will be extracted, which correspond to the N entries of codeword vector, v. Thus, the generated codeword in the j-th column of the analogue crossbar array 310 is calculated as

[0105] This procedure will be repeated for the next sequence of messages. As long as the size and type of the code remain fixed, there is no need for reprogramming the crossbar array 310. However, it is clear that if the generator matrix is changed because of any reason such as changing the coding scheme, etc., then the crossbar array 310 should be programmed with the new generator matrix.

[0106] Figure 8 illustrates the required hardware components to realize the proposed coding scheme. This example is shown for C(8,12) (K = 8 and N = 12), in which three crossbar arrays are used to implement this coding scheme. Note that it is possible to implement such a small code using only one crossbar, but here (in Figure 8) the purpose is to show how multiple crossbars may be used to realize a code. This concept will be explained in more detail further below.

[0107] In Figure 8, only 1 -bit DACs, which have relatively low hardware cost, are used to generate the voltage signals corresponding to the message bits.

[0108] Channel Decoding Matrix-based and vector-based computations are commonly used in soft-decision decoding, iterative decoding techniques like Turbo decoding and LDPC decoding, decoding of convolutional codes like Turbo decoder and Reed Solomon decoders. These methods leverage the principles of linear algebra to efficiently process large sets of data and perform computations on vectors and matrices representing the received signals and decoding algorithms.

[0109] Soft-decision decoding, which considers the reliability of received symbols based on probabilities, often involves matrix operations such as multiplication, addition, and inversion. This approach is well-suited for problems where the received signal can be represented as a matrix, such as in the case of channel codes like LDPC codes.

[0110] Iterative decoding algorithms like Turbo decoding and LDPC decoding also rely heavily on matrix-based computations. In Turbo decoding, for example, the decoding process involves passing messages between different components of the decoder, which may be represented and manipulated using matrices. Similarly, LDPC decoding employs belief propagation algorithms that update probabilities associated with bits based on messages passed along the edges of a corresponding graph representation of the code, which may be formulated using matrices and vectors.

[0111] Overall, matrix-based and vector-based computations are powerful tools for implementing various decoding algorithms, allowing for efficient processing of large-scale data and enabling the use of advanced decoding techniques in modern communication systems. On the other hand, as discussed before, the memristor-based crossbar arrays enable massive parallelism of MAC operations and consequently matrix-based and vector-based computations, e.g., vector-vector and vector-matrix multiplications and additions. Embodiments for different decoding algorithms using memristor-based crossbar arrays will now be disclosed. Even though the concept of channel decoding using memristor-based crossbar arrays is presented for only two cases of decoding types below, the same concept may be similarly applied to other coding schemes like Viterbi decoding and Reed Solomon decoding as well.

[0112] Block decoding

[0113] Figure 9 illustrates a high-level flow chart of a method for decoding of block coded wireless communications signals with the electronic decoder 421. Figures 10a-1 Oh illustrate some first embodiments of the electronic decoder 421 which may be used for LDPC decoding. Figure 11 illustrates some second embodiments of the electronic decoder 421 which may be used for Polar decoding. The electronic decoder 421 comprises multiple calculation circuits, for example depicted in Figure 10a and Figure 11. Each calculation circuit comprises an analogue crossbar array.

[0114] In general, the electronic decoder 421 comprises at least two electrically interconnected analogue crossbar arrays 1010, 1020, 1110, 1120 of memristors. An electrical interconnection 1115 between a column of an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays 1010, 1020, 1110, 1120 and a row of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays 1010, 1020, 1110, 1120 comprises a current- to-voltage converter 1101. A first analogue crossbar array 1010, 1110 of the at least two analogue crossbar arrays comprises at least a first row 1112a of memristors with a single input and a respective output for each column of memristors.

[0115] A number of memristors of the first row 1112a of memristors of the first analogue crossbar array 1010 may equal a bit length of a coded wireless signal to be received by the electronic decoder 421.

[0116] In some embodiments disclosed herein the first analogue crossbar array 1110 is configured to provide a respective output which is linearly dependent on a Log-Likelihood Ratio (LLR) of a symbol value of a noisy coded wireless communications signal.

[0117] Each memristor of the first row 1112a of memristors may be configured to be programmed with the respective symbol value of the received noisy coded wireless communications signal to calculate the LLR of the symbol value.

[0118] In some embodiments disclosed herein the electronic decoder 421 is configured for non-binary decoding. Each memristor of the first row 1112a of memristors may be configured to be programmed with non-binary values.

[0119] Action 901

[0120] The method for decoding of block coded wireless communications signals with the electronic decoder 421 comprises iteratively updating, by the at least two electrically interconnected analogue crossbar arrays 1010, 1020, probability distributions of bits in an obtained codeword until convergence. For example, a convergence criterion may be that the variable-to-check node messages do not change significantly or a maximum number of iterations is reached.

[0121] LDPC decoding LDPC decoding involves iteratively updating probability distributions of the bits in a codeword until convergence. Embodiments disclosed herein may implement LDPC decoding using belief propagation by using matrix multiplication and addition operations with analogue crossbar arrays to update variable node and check node messages iteratively until convergence. Similar to the encoding process presented above, the computations of the decoding process will be mapped to the corresponding crossbar array as well. As a result, the decoding process may be implemented using memristor-based crossbars, which enables parallel processing and reducing the decoding latency significantly. Moreover, this idea provides a flexible and reconfigurable hardware platform to realize variable code length, large code lengths, and desired coding algorithms.

[0122] As mentioned above, the electronic decoder 421 comprises multiple calculation circuits. According to the first embodiments for LDPC decoding there may be seven calculation circuits as depicted in Figure 10a. For example, the electronic decoder 421 may comprise a first calculation circuit 1001 for calculating a Log-Likelihood Ratio (LLR).

[0123] In some embodiments herein the electronic decoder 421 for LDPC decoding comprises a second calculation circuit 1002 for initialization. The electronic decoder 421 for LDPC decoding may further comprise a third calculation circuit 1003 for a check-to-variable node update calculation, e.g. for updating check-to-variable node decoding messages.

[0124] In some embodiments herein the electronic decoder 421 for LDPC decoding comprises a fourth calculation circuit 1004 for calculating P and R matrices.

[0125] The electronic decoder 421 for LDPC decoding may further comprise a fifth calculation circuit 1005 for variable-to-check node update calculations, e.g. for updating variable-to-check node decoding messages.

[0126] In some embodiments herein the electronic decoder 421 for LDPC decoding comprises a sixth calculation circuit 1006 for variable-to-check node update calculations, e.g. for updating variable-to-check node decoding messages.

[0127] The electronic decoder 421 for LDPC decoding may further comprise a seventh calculation circuit 1007 for variable-to-check node update calculations, e.g. for updating variable-to-check node decoding messages.

[0128] Since output of a crossbar is a current signal, it may be converted to a corresponding voltage signal before being applied to a subsequent crossbar. This conversion may be performed using current to voltage converters. An uncomplicated strategy for implementing current-to-voltage converters involves utilizing resistors. However, alternative methods include the utilization of operational amplifiers (Op-Amps), transimpedance amplifiers, and passive resistor networks. The selection among these methods depends on factors like the desired gain, input impedance, and the availability of components. Note that some of the current-to-voltage converters have been omitted in the figures to simplify the figures.

[0129] Definitions:

[0130] Let y be the received vector of code words of length N.

[0131] - H is the parity-check matrix of the LDPC code of size (N-K) *N.

[0132] Let R be the message matrix from check nodes to variable nodes of size (N- K)*N.

[0133] Let Q be the message matrix from variable nodes to check nodes of size (N- K)*N.

[0134] In the following, the notation M = N-K is used for the matrix dimensions to simplify the description.

[0135] Initialization:

[0136] - A first step is to calculate the LLR. LLR is used in belief propagation algorithms to update and pass messages between nodes in a Tanner graph during the decoding process. The LLR value for each bit represents the logarithm of the ratio between the probabilities that a given bit is a 0 or a 1, given the received noisy signal.

[0137] Let Lchbe the vector of LLRs of size N, which are initially obtained from the channel as follows: ich = y ) (4) i is the index of the LLRs since it is calculated for all bits.

[0138] In some embodiments, the vector Lchis initialized as Lch= y.

[0139] The process of generating LLR values in equation (4) may be done by memristor- based architecture in Figure 10b, where all the memristors of the first analogue crossbar array 1010 are programmed by the entries of the received vector, y, and the constant 2 value of — is applied to the crossbar row. As a result, the LLR values are generated along the crossbar columns.

[0140] Then the message matrix Q is initialized (Variable nodes to check nodes messages) as follows:

[0141] Q = H O (lMLchT) (5) where 1Mis a column vector of ones with size M, and © represents element-wise multiplication. As a result, Q is initialized with the LLRs replicated according to the structure of H.

[0142] The element-wise multiplication, ©, is used in different steps of the PIM-based LDPC decoder. Element-wise multiplication of a row / column of two matrices may be implemented using an array of memristors with the same size of the matrix row / column. The proposed PIM-based circuit to perform the elementwise multiplication is illustrated in Figure 10c, which realizes A © B. As an example, in this figure the size of matrices is MxN, where the entries of / -th row of matrix A and B are represented as A^ and B^.

[0143] The computation in equation (5) may be performed in an efficient way using the PIM-based circuit shown in Figure 10c. The memristors may be programmed with the entries of each row in H while the input to the memristors are the entries of the vector Lch. In other words, the following assignment may be considered in Figure 10c: A^ = Lch. and Btj = Htj. As a result, there is no need to perform the internal multiplication of lMLchTin equation (5). This is due to the fact that, the result of equation (5) is to replicate the LLRs according to the structure of H. The term iw^d / in eq. 5 creates a matrix of LLR values which are repeated in a regular structure since is just a column of ones. Next, when this term is multiplied by H in eq. 5, the pattern of LLRs will be changed, i.e. , permuted, according to the structure of H and 0 / 1 entries in H. So, the result is a replicated version of LLRs according to the structure of H.

[0144] Note that, the computation in eq. (5) may be done either in a row-wise manner, as described, or in a matrix-wise manner by employing M samples of the proposed circuit in Figure 10c. This is a kind of speed-cost trade off, which may be decided by the designer of the circuit by considering the application requirements and design constraints. However, here the row-wise computation is demonstrated to simplify the description and figures to understand the main idea. It is worth to mention that since all the element-wise multiplications in the proposed scheme involve multiplication by matrix H, it is possible to reuse the proposed PIM-based circuit in Figure 10c for multiple steps of the decoding procedure.

[0145] Thus, the at least two electrically interconnected analogue crossbar arrays 1010, 1020 may comprise a second analogue crossbar array 1020 of memristors. The first analogue crossbar array 1010 may be configured to provide an LLR of a respective symbol value of a noisy coded wireless communications signal as output from a respective crossbar column 1011 , 1012, 1013. An output of a respective crossbar column 1011, 1012, 1013 of the first analogue crossbar array 1010 may be electrically interconnected to a corresponding memristor 1021, 1022, 1023 of the second analogue crossbar array 1020.

[0146] In some embodiments herein the second analogue crossbar array 1020 comprises memristors 1021, 1022, 1023 configured to be programmed with elements of a matrix representing connections between variable nodes and check nodes of a Tanner graph. The second analogue crossbar array 1020 may be configured to calculate an initial variable-to-check node message matrix based on input from the first analogue crossbar array 1010.

[0147] In some embodiments herein the at least two electrically interconnected analogue crossbar arrays further comprises one or more further electrically interconnected analogue crossbar arrays 10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090 of memristors which as an ensemble are configured to iteratively calculate an updated variable-to-check node message matrix based on a previous variable-to-check node message matrix as input. Initially, the previous variable-to-check node message matrix may be the initial variable-to-check node message matrix.

[0148] The further electrically interconnected analogue crossbar arrays 10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090 are depicted in Figures 10d-10h.

[0149] Check to Variable Node Update:

[0150] To update the check nodes to variable nodes matrix R, the following values may be calculated using the message matrix Q

[0151] T = H tanh Figure 10d presents a set of analogue crossbar arrays to implement the computations in eq. (6). First, the values are multiplied by constant value of 0.5, which is programmed to all the memristors in the first crossbar in Figure 10d. The size of matrix Q is (N-K) *N. However, the embodiment illustrated in Figure 10d shows a single row / column. It is possible to parallelize this architecture to do all multiplications using multiple crossbars similar to the one shown in Figure 10d.

[0152] Then, the tanh function is applied to the result of the first crossbar in Figure 10d. Note that, it is possible to realize this function using memristors following the disclosure of Z. Zhang, J. Jiang, Y. Zhu, Q. Wang, Z. Mao and N. Jing, "A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 7, pp. 2094- 2106, July 2022, doi: 10.1109 / TCAD.2021.3107252.

[0153] Next, the result of tanh may be multiplied by the corresponding row of matrix H using the second crossbar in Figure 10d. As a result, the entries of matrix T may be calculated and sent to the next step of the decoding process.

[0154] Thus, the one or more further electrically interconnected analogue crossbar arrays 10030, 10040, 10050, 10060, 10070, 10080, 10090 may comprise a further first analogue crossbar array 10010 of memristors for which all memristors are configured with a value of 1 / 2, a further second analogue crossbar array 10020 of memristors for calculating a tanh-function of an output from the further first analogue crossbar array 10010, a further third analogue crossbar array 10030 of memristors comprising memristors 10031 , 10032, 10033 configured to be programmed with elements of a parity check matrix.

[0155] Each memristor of the further second analogue crossbar array 10020 may be connected to a corresponding memristor of the further first analogue crossbar array 10010 through a current-to-voltage converter 10015. Each memristor of the further third analogue crossbar array 10030 may be connected to a corresponding output of the further second analogue crossbar array 10020 through a current-to-voltage converter 10025. The further third analogue crossbar array 10030 may be configured to calculate element-wise multiplication of the outputs from the further second analogue crossbar array 10020 with the parity check matrix.

[0156] Next, an intermediate matrix P of size M*N may be created such that each of its entries is obtained as follows: where n T denotes the product along the rows of T, and N(i) represents the set of variable nodes connected to the check node i,

[0157] N(t) = {j\Hij = 1}. (8)

[0158] This means multiplying all the elements in the row of T except for the one being updated. Finally, the check nodes to variable nodes are updated as,

[0159] R = 2tanh“1(P) . (9)

[0160] Figure 10e illustrates embodiments to implement the computations in eq. (7). The entries of / -th row of matrix T which are specified by N(i), may be programmed on the memristors of the top crossbar in Figure 10e. The generated value, P^, may be sent to an inv-tanh function, which may be realized as presented in Z. Zhang, J. Jiang, Y. Zhu, Q. Wang, Z. Mao and N. Jing, "A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator," in IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 41, no. 7, pp. 2094-2106, July 2022, doi: 10.1109 / TCAD.2021.3107252.

[0161] The output may be multiplied by the constant value of 2, using a single memristor as depicted in Figure 10e to generate the corresponding entry of matrix R, following the computation in eq. (9).

[0162] Thus, in some embodiments the one or more further electrically interconnected analogue crossbar arrays comprises a further fourth analogue crossbar array 10040 of memristors configured to calculate an output as a product of the outputs from the further third analogue crossbar array 10030. Thus, the further fourth analogue crossbar array 10040 is configured to calculate a product of the outputs from the further third analogue crossbar array 10030.

[0163] A respective memristor 10041, 10042, 10043 of the further fourth analogue crossbar array 10040 may be configured to be programmed with a corresponding output from the further third analogue crossbar array 10030. The programming of the memristors of the further fourth analogue crossbar array 10040 may be performed when the decoding is performed. Each memristor 10041, 10042, 10043 of the further fourth analogue crossbar array 10040 may be interconnected to a further memristor of the further fourth analogue crossbar array 10040 via a current-to-voltage converter 100412, 100423. in some embodiments the one or more further electrically interconnected analogue crossbar arrays comprises a further fifth analogue crossbar array 10050 of memristors and a further sixth analogue crossbar array 10060 of memristors. The further fifth analogue crossbar array 10050 may be configured to calculate an output as an inverse tanh value of the output from the further fourth analogue crossbar array 10040. The further sixth analogue crossbar array 10060 may be configured to calculate an element of a check-to-variable node message matrix by comprising a memristor 10061 connected to the output of the fifth analogue crossbar array 10050 and configured with a value of two.

[0164] Variable to Check Node Update:

[0165] To update the variable node to check node matrix Q, the first step is to compute element-wise multiplication of the updated check node to variable node matrix R by the parity check matrix H as,

[0166] S = H Q R (10) where H is the parity-check matrix of the LDPC code. This computation may be simply realized by the proposed PIM-based circuit in Figure 10f as described above. This means that the following assignment may be considered in Figure 10f: = Rtj and

[0167] Next, the sum of messages for each variable node (i.e., column-wise sum) may be computed which is given by:

[0168] This implies that Ssumis a vector of size N where each element is the sum of the messages for the corresponding variable node. Figure 10g illustrates the proposed PIM- based summation, which is used to realize eq. (11). All the memristors may be programmed by ones and the entries of y-th column of S are applied to the crossbar rows in Figure 10g.

[0169] Thus, in some embodiments herein the one or more further electrically interconnected analogue crossbar arrays comprises a further seventh analogue crossbar array 10070 of memristors and a further eighth analogue crossbar array 10080 of memristors. The further seventh analogue crossbar array 10070 may comprise memristors 10071 , 10072, 10073 configured to be programmed with elements of the matrix representing connections between variable nodes and check nodes of the Tanner graph. The further seventh analogue crossbar array 10070 may be configured to perform multiplication of the element of the variable-to-check node message matrix with a corresponding element of the matrix representing the connections between the variable nodes and the check nodes of the Tanner graph.

[0170] The further eighth analogue crossbar array 10080 may be configured to calculate a sum of messages for each variable node by being configured to calculate a sum of outputs from the further seventh analogue crossbar array 10070 by comprising a column of memristors of which each memristor is configured with a value of one and connected to a corresponding output of the further seventh analogue crossbar array 10070.

[0171] Q is updated as,

[0172] The computation in eq. (12) may be rewritten and simplified to be mapped efficiently on the crossbars. Having considered the computation of eq. (12), each row of Q may be computed as

[0173] Qt = Hi © (LchT+ STsum- Rt). (13)

[0174] Figure 10h depicts embodiments to perform the computation in eq. (12). First, the computation of LchT+ STsum- R, may be done by the first crossbar in Figure 10h, which consists of cascaded adders and subtractors. The addition is carried out by the memristors which are programmed by 1 while the subtraction is performed using the memristors which are programmed by the value of -1. Next, the outputs of this computation may be multiplied by the entries of corresponding row in the parity check matrix using the proposed element-wise multiplication scheme, as shown in the lower part of Figure 10h.

[0175] The complicated computation in (12), is mapped efficiently onto the crossbars using the proposed architecture in Figure 10h. Thus, in some embodiments herein the one or more further electrically interconnected analogue crossbar arrays comprises a further ninth analogue crossbar array 10090 of memristors. The further ninth analogue crossbar array 10090 may comprise multiple columns 10091, 10092 of memristors. Each column of the further ninth analogue crossbar array 10090 may comprise three memristors 10091a, 10091b, 10091c of which a first and a second memristor 10091a, 10091b are each configured with a value of one and a third memristor 10091c is configured with a value of minus one. Each memristor of each column may be connected to a separate input such that a respective output from each column is calculated by adding inputs to the first and the second memristor 10091a, 10091b and subtracting input to the third memristor 10091c. Thus, ninth analogue crossbar array 10090 is configured to subtract the third input from the first and the second input.

[0176] In some embodiments herein an input to a respective first memristor 10091a of the further ninth analogue crossbar array 10090 is connected to a corresponding output of a column of the further eighth analogue crossbar array 10080. An input to a respective second memristors 100091b of the further ninth analogue crossbar array 10090 may be connected to a corresponding output of a column of the first analogue crossbar array 1010. An input to a respective third memristor of the further ninth analogue crossbar array 10090 may be connected to a corresponding output of a column of the sixth analogue crossbar array 10060.

[0177] In some embodiments herein the one or more further electrically interconnected analogue crossbar arrays comprises a further tenth analogue crossbar array 100100 of memristors comprising memristors configured to be programmed with a row of elements of the matrix representing the connections between the variable nodes and the check nodes of the Tanner graph. The further tenth analogue crossbar array 100100 may be configured to multiply the output from each column of the ninth analogue crossbar array 10090 with a memristor value of a corresponding column of the tenth analogue crossbar array 100100.

[0178] It is worth to mention that, in most of the above-presented architectures, the memristors are programmed by the values of 0 or 1. As a result, low-cost memristors may be employed in embodiments disclosed herein since a high number of conductance levels of memristors (high precision) is not needed. Iterations: Repeat the message passing Step 3 to Step 5 iteratively until a convergence criterion is met. Each iteration involves updating R and Q using matrix and vector-based computations as described above.

[0179] This process may be performed iteratively until a certain threshold like the number of iterations is satisfied, which may be decided by a controller.

[0180] It is possible to reformulate the message passing algorithm for LDPC decoding to avoid the hyperbolic tangent function. This alternative approach may use a Min-Sum Algorithm, which approximates the Belief Propagation (Sum-Product) algorithm by replacing the tanh and tanh inverse operations with simpler operations.

[0181] Polar Decoding

[0182] Polar decoding includes iteratively updating the probability distributions of the bits in a codeword until convergence. The step-by-step procedure of Polar decoding is presented below, which involves matrix / vector-computations as follows. Also, the proposed memristor-based architecture to perform the polar decoding is illustrated in Figure 11.

[0183] Initialization:

[0184] - y is the received vector of noisy symbols, which includes N symbols. Note that, the initial LLRs for the / -th bit is calculated in advance using the received vector y and the channel information, i.e., LLRt= y be calculated as

[0185] LLRi = yi^ where a2is the noise variance in the communication channel. Then, the vector ! is created using the LLR values of all symbols, i.e., L = [LLR1,LLR2, ...,LLRN].

[0186] Initialize the variable node messages v and check node messages c to zeros.

[0187] This step is done using the first row of the first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120 in Figure 11. To this end, the symbols of the received vector, y, are programmed to N memristors of the first row of first

[0188] 2 analogue crossbar array (1110. Next, the constant value of — is applied to this crossbar row. As a result the LLRs will be calculated in parallel following the operation in eq. (7). The generated values will be converted to the corresponding voltage signals by using the current to voltage converters as shown in Figure 11. Variable to Check Node Update (VN):

[0189] Update the variable node messages v based on the received LLRs, y, and the previous check node messages c. This update may be represented as: v = HVN. L + (I — HVN). c (15)

[0190] Here, HVNis the matrix representing the connections between variable nodes and check nodes for the variable node update and I is the identity matrix.

[0191] For embodiments disclosed herein the operations in eq. (8) are rewritten as follows: v = HVN. L — C^ + I. C (16) which may be realized using the proposed architecture in Figure 11 as follows. First, the subtraction of (1 - c) is calculated using the first analogue crossbar array 1110. As shown in Figure 11 , the memristors of the first row are programmed with the entries of vector y while the memristors of the second row of the first analogue crossbar array 1110 are programed with the entries of vector c. Thus, in some embodiments, such as for polar decoding, the first analogue crossbar array 1110 comprises a second row 1112b of memristors with a single input and a respective output for each column of memristors.

[0192] 2

[0193] The input of first and second row of first analogue crossbar array (1110 are — and - 1 , respectively. The generated results of (1 - c) may be converted to the corresponding voltage signals by using the current to voltage converters as shown in Figure 11 , which are then applied to the rows of a second analogue crossbar array 1120. Since the memristors of the second analogue crossbar array 1120 are programmed by the entries of HVN, the output of columns of the second analogue crossbar array 1120 will be equal to HVN- ( ~c)-

[0194] Thus, in some embodiments disclosed herein the at least two electrically interconnected analogue crossbar arrays 1110, 1120 comprise the second analogue crossbar array 1120. A respective crossbar column of the first analogue crossbar array 1110 is electrically interconnected to a corresponding crossbar row of the second analogue crossbar array 1120. Thus the first crossbar column of the first analogue crossbar array 1110 is electrically interconnected to the first crossbar row of the second analogue crossbar array 1120, while the second crossbar column of the first analogue crossbar array 1110 is electrically interconnected to a second crossbar row of the second analogue crossbar array 1120, etc.

[0195] The second analogue crossbar array 1120 may comprise memristors configured to be programmed with elements of a parity check matrix. The at least two electrically interconnected analogue crossbar arrays 1110, 1120, 1130 may comprise a third analogue crossbar array 1130. Then a respective crossbar column of the third analogue crossbar array 1130 is directly electrically interconnected to a corresponding crossbar column of the second crossbar array 1120. Thus, it is not necessary to arrange a current-to-voltage converter between the second analogue crossbar array 1120 and the third analogue crossbar array 1130.

[0196] The third analogue crossbar array 1130 may comprise memristors configured to be programmed with elements of an identity matrix.

[0197] Thus, the memristors of the third analogue crossbar array 1130 may be programmed by values of the identity matrix, I, and the vector c is applied to the crossbar rows of the third analogue crossbar array 1130. Due to the fact that the second analogue crossbar array 1120 and the third analogue crossbar array 1130 are connected together, the final output of them v = HVN. (L — c) + 1, c. Note that the second analogue crossbar array 1120 and the third analogue crossbar array 1130 may be considered as a single crossbar, as shown in Figure 11 , or they may be realized using two separate crossbar arrays.

[0198] Update the LLRs

[0199] The vector of LLRs may be updated using the current status of v

[0200] Lj = v (17)

[0201] The generated values by the third analogue crossbar array 1130 are converted to corresponding voltage signals by using current to voltage converters as shown in Figure 11, which are then applied to the rows of a fourth analogue crossbar array 1140.

[0202] Check to Variable Node Update (CN)

[0203] Update the check node messages c based on the updated LLRs, Lj. This update can be represented as:

[0204] Cj = HTVNLj (18)

[0205] This computation is realized using the fourth analogue crossbar array 1140, in which the memristors are programmed with the entries of matrix HyN. As a result, the check node messages c are generated along the columns of the fourth analogue crossbar array 1140.

[0206] Thus, in some embodiments herein the at least two electrically interconnected analogue crossbar arrays (1110, 1120, 1130, 1140) comprise the fourth analogue crossbar array 1140 of memristors. A respective crossbar column of the third analogue crossbar array 1130 may be electrically interconnected to a corresponding crossbar row of the fourth crossbar array 1140. For example, the first crossbar column of the third analogue crossbar array 1130 may be electrically interconnected to the first crossbar row of the fourth analogue crossbar array 1140, while the second crossbar column of the third analogue crossbar array 1130 may be electrically interconnected to a second crossbar row of the fourth analogue crossbar array 1140, etc.

[0207] The fourth analogue crossbar array (1140) of memristors may comprise memristors configured to be programmed with elements of a transpose of the parity check matrix.

[0208] Iterative Process

[0209] The method may continue iterating between the Variable-to-Check Node Update and Check-to-Variable Node Update until convergence, e.g., the messages do not change significantly or a maximum number of iterations is reached. Each iteration involves updating the variable node messages v and check node messages c using the matrix and vector-based computations described above. The decision making is done by a controller module 1150 in Figure 11 , which for example may check the number of decoding iterations.

[0210] Throughout the aforementioned steps, the variable node messages v, check node messages c, and received LLRs, y, are represented as vectors, while the decoding updates are computed using matrix-based operations defined by the polar code construction matrix (i.e. the parity check matrix) and the specific decoding algorithm chosen. Therefore, similar to the case of LDPC decoding, the computations of Polar decoding may be mapped to the corresponding crossbar array as well. As a result, the decoding process may be implemented using memristor-based crossbars, which enables fully parallel processing and reducing the decoding latency significantly. Moreover, embodiments disclosed herein provide a flexible and reconfigurable hardware platform to realize any code length and desired coding algorithm.

[0211] For Polar codes, especially in the context of simplified iterative belief propagation, the structure of the Tanner graph may sometimes be reduced where every variable node participates in defining a parity check.

[0212] In this case, the matrix HVN may be simplified to an N*N matrix if the connections within a single Tanner graph are defined such that variable nodes and check nodes are implicitly coupled. The decoding process for this case follows equations (14)-(18).

[0213] However, another alternative is to consider a KxN matrix as the corresponding HVN. In this case, a similar approach may be used for Polar decoding but a difference is that dimensions of the crossbars are different. In this case the computations of iterative belief propagation for Polar decoding may be expressed as follows.

[0214] L = y(2 / o2) v = HVN. L Cj = HTVNV

[0215] L = c

[0216] In this case the crossbar sizes are as follows: the first analogue crossbar array 1110 may be of size 1xN, the second analogue crossbar array 1120 may be of size NxK, the third analogue crossbar array 1130 may not be used, and the fourth analogue crossbar array 1140 may be of size KxN.

[0217] Further details of methods for decoding

[0218] The LDPC embodiments will be described first.

[0219] In some embodiments herein updating the probability distributions of the bits in the obtained codeword comprises calculating message matrices by the at least two electrically interconnected analogue crossbar arrays. The message matrices may comprise the Q and R matrices described above.

[0220] Updating the probability distributions of the bits in the obtained codeword may further comprise programming each memristor of the first row of memristors with a respective first symbol value of a received noisy coded wireless communications signal to calculate the LLR. Calculating the LLR may be performed in a parallel manner. For example, the LLR may be calculated by inputting a value of 2 divided by a noise variance of the wireless communications channel to the row of memristors of the first crossbar array.

[0221] The method may further comprise programming an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays 1010, 1020 with elements of a parity check matrix.

[0222] In some embodiments the method further comprises programming memristors of the third analogue crossbar array 1130 of the at least two electrically interconnected analogue crossbar arrays 1120, 1120, 1010 with elements of the identity matrix. The method may further comprise providing check node messages as input to crossbar rows of the third crossbar array 1130 of the at least two electrically interconnected analogue crossbar arrays 1120, 1120, 1130.

[0223] In some embodiments when the at least two electrically interconnected analogue crossbar arrays comprise the fourth analogue crossbar array 1140 of memristors, and a respective crossbar column of the third analogue crossbar array 1130 is electrically interconnected to the corresponding crossbar row of the fourth crossbar array 1140, then the method may further comprise programming memristors of the fourth analogue crossbar array 1140 with elements of a transpose of the parity check matrix.

[0224] In some embodiments updating the probability distributions of the bits in the obtained codeword further comprises programming the second analogue crossbar array 1020 of the at least two electrically interconnected analogue crossbar arrays 1010, 1020 with elements of the parity check matrix, and calculating by the second analogue crossbar array 1020, an initial variable-to-check node message matrix based on input from the first analogue crossbar array 1010.

[0225] In some embodiments wherein the at least two electrically interconnected analogue crossbar arrays 1010, 1020 further comprise one or more further electrically interconnected analogue crossbar arrays 10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090, 100100 of memristors, updating 901 the probability distributions of the bits in the obtained codeword further comprises calculating, by the one or more further electrically interconnected analogue crossbar arrays 10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090, 100100, the updated variable-to-check node message matrix based on the previous variable-to-check node message matrix as input.

[0226] As mentioned above, the one or more further electrically interconnected analogue crossbar arrays 10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090, 100100 may comprise the further first analogue crossbar array 10010 of memristors for which all memristors are configured with a value of 1 / 2, the further second analogue crossbar array 10020 of memristors for calculating the tanh-function of the output from the further first analogue crossbar array 10010, the further third analogue crossbar array 10030 of memristors. Then updating the probability distributions of the bits in the obtained codeword may further comprise programming memristors of the further third analogue crossbar array 10030 with elements of the parity check matrix, and calculating, by the further third analogue crossbar array 10030, element-wise multiplication of the outputs from the further second analogue crossbar array 10020 with the parity check matrix.

[0227] In some embodiments wherein the one or more further electrically interconnected analogue crossbar arrays comprises the further fourth analogue crossbar array 10040 of memristors then wherein updating the probability distributions of the bits in the obtained codeword may further comprise programming the respective memristor of the further fourth analogue crossbar array with the corresponding output from the further third analogue crossbar array, and calculating the product of the outputs from the further third analogue crossbar array.

[0228] As mentioned above, the one or more further electrically interconnected analogue crossbar arrays may comprise the further fifth analogue crossbar array 10050 of memristors and the further sixth analogue crossbar array 10060 of memristors comprising the memristor 10061 connected to the output of the fifth analogue crossbar array 10050 and configured with the value of two. Then updating the probability distributions of the bits in the obtained codeword may further comprise calculating, by the further fifth analogue crossbar array 10050, the inverse tanh value of the output from the further fourth analogue crossbar array 10040, and calculating, by the further sixth analogue crossbar array 10060, the element of the check-to-variable node message matrix.

[0229] In some embodiments updating the probability distributions of the bits in the obtained codeword further comprises re-programming each memristor of the first row of memristors with a respective second symbol value of a received noisy coded second wireless communications signal. A second code length of the second symbol value differs from a first code length of the symbol value of the wireless communications signal.

[0230] The methods described by embodiments disclosed herein may be for non-binary decoding.

[0231] Hardware Sharing in the Implementation of Coding Schemes

[0232] In the above description it is assumed that encoding and decoding are performed in two separate crossbars. However, the same crossbar hardware may be used for both procedures. To this end, the crossbar array may be programmed with the corresponding matrix. Moreover, another point that may be considered is that for the encoding step, the message to be coded is applied to the crossbar rows and the codewords are generated along the crossbar columns while in the decoding step the codewords are applied to the columns and the decoded message is obtained from the rows (using a crossbar array with bidirectional rows and columns).

[0233] Moreover, in order to reduce the hardware cost, the ADCs may be shared between multiple columns. For example, in case of N crossbar columns, one, two, N / 4, N / 2, N, and any other number of ADCs may be used, which means that it takes one, two, N / 4, N / 2, and N read cycles to generate all the codewords. An example of this concept is shown in Figure 12, where four ADCs are used in a time multiplex manner between 12 crossbar columns. Thus, the same algorithm may be realized with the hardware of Figure 12 and Figure 8. The only difference is that in the embodiment depicted in Figure 8, all the outputs are generated in one read cycle while in the embodiment in Figure 12, it takes three read cycles to generate all the outputs.

[0234] Supported Coding Algorithms

[0235] An advantage of embodiments herein is that any block code, including binary and non / binary codes, may be realized using the disclosed crossbar arrays. Some of the well- known coding schemes, which are supported by the disclosed embodiments, are listed below:

[0236] • LDPC codes

[0237] • Turbo codes

[0238] • Hamming codes

[0239] • Reed-Solomon codes

[0240] • Reed-Muller codes

[0241] • Hadamard codes

[0242] • Expander codes

[0243] • Golay codes

[0244] Sparsity of Parity Check Matrix

[0245] The parity check matrix is typically large but comprises mostly zeros, with only a small number of ones in each row and column. This sparse structure reduces the complexity of both encoding and decoding processes, particularly in the iterative belief propagation algorithm. The sparsity allows for faster computations, less memory usage, and enables the handling of large block lengths, making LDPC codes highly effective for modern communication systems.

[0246] In the proposed scheme, this sparsity leads to: (i) higher tolerance to the noise and thus achieving better accuracy since many of the memristors are programmed with zeros and the remaining with ones. The reason is that due to the sparsity the memristors are programmed either with the lowest or highest conductance levels, which provides a large gap and prevents unwanted changes in the programmed values of the memristors. (ii) Less hardware cost, since most entries of the parity check matrix are zero and the rest are one, low-cost memristor devices may be used. This is due to the fact that in such a case the memristors behave like switches.

[0247] Realization of Non-Binary Codes

[0248] Non-binary codes extend the concept of error-correcting codes beyond the binary alphabet, using symbols from larger finite fields, typically GF(q) where q is greater than 2 and the corresponding elements are 0, 1, ... , q-1. These codes offer enhanced error correction capabilities, particularly in channels where errors are more likely to affect multiple bits or occur in bursts. Non-binary codes may achieve better performance with shorter code lengths compared to binary codes, as they may correct more complex error patterns. They are particularly useful in applications like data storage and high-speed communication systems, where robustness against diverse types of noise is critical.

[0249] Implementing non-binary codes (e.g., non-binary LDPC) poses significant challenges due to their increased computational complexity and memory requirements. Unlike binary codes, which operate over simple binary arithmetic, non-binary codes involve operations in larger finite fields, which are more computationally intensive. The decoding process, particularly for iterative algorithms like belief propagation, becomes more complex as it requires managing a larger number of possible symbol states and their associated probabilities. Additionally, the need for specialized hardware or software to efficiently perform finite field arithmetic may further complicate implementation, making non-binary codes less practical in resource-constrained environments.

[0250] Embodiments disclosed herein may be employed in case of non-binary codes as well. To this end, the non-binary elements of the generator matrix may be programmed to the corresponding memristive elements in the crossbar array. As a result, all the above- mentioned advantages may be achieved in case of non-binary codes as well.

[0251] Large number of bits per element of the generator matrix may reduce the performance of the proposed channel coding scheme, which depends on the type of memristive devices. In order to solve this issue and improve the performance of the proposed channel coding scheme, it is possible to assign more than one memristor to every element of the generator matrix. In other words, each element of generator matrix may be divided into multiple parts, which may be programmed to multiple devices in a crossbar row.

[0252] For example, let’s consider a channel code, which is defined in GF(64). Thus, each element of the corresponding generator matrix is represented by 6 bits, i.e., gt= g- 9i 9i 9i 9i 9i ■ As explained above, each element of generator matrix gtmay be programmed into one memristor. However, to improve the performance, each element of generator matrix gtmay be programmed into more than one memristors. Assuming two memristors per element, g g gf is programmed to one memristor and g g gt is programmed to the second one. In this scenario, a “Shift & Add” circuit may be employed to calculate the output samples of the channel coding scheme. This may be done by combining the outputs of the corresponding crossbar columns.

[0253] Slicing each element of the generator matrix into multiple parts may be used to reduce the hardware cost. This is due to the fact that simpler and cheaper memristive devices may be used when the number of bits per device is reduced.

[0254] Realization of Large Code Lengths

[0255] Sometimes the size of the generator matrix, G, is large such that it cannot be programmed to a single crossbar array. In such cases, the generator matrix may be divided into multiple smaller matrices, which may be programmed to multiple crossbar arrays. An example of this concept is shown in Figure 12 for C(S, 12), in which the generator matrix is divided into three parts and then it is programmed into three smaller crossbar arrays.

[0256] It is also possible to map the generator matrix into multiple crossbars of different sizes to improve the hardware utilization.

[0257] Bit-Serial Inputs

[0258] Sometimes the input words to the coding scheme have more than one bit. For example, in case of decoding, the inputs to the decoder may be the LLR of the noisy codewords, which are represented by multiple bits. In these cases, high-resolution ADCs and DACs may be needed. The supported bit resolution of ADCs determines the quantization error; the higher supported bit resolution the lower the quantization error and hence the better performance. Therefore, in case that either the ADCs do not support the required resolution or in order to improve the performance of the encoder / decoder, each input sample, which is a binary word, may be sent to the DACs in a bit-serial manner.

[0259] Figure 13 shows a crossbar array which performs the same operation as the one in Figure 3 while the bit-serial scheme is employed for the input vector. At each time instance, which corresponds to the read cycle of the crossbar array, one bit of all input binary-words is applied to the corresponding DAC.

[0260] In Figure 13, the i-th bit of j-th input and output words are shown by V- and I- , respectively. After each read cycle, the output signals of crossbar columns may be converted to the corresponding digital values by using ADCs. These binary values may be sent to a “Shift & Add” circuit, which calculates the output samples of encoder / decoder. As a result, after every W read cycles, the encoding / decoding operation will be completed for all the input samples where W is the number of bits per input sample. As shown in Figure 13, in this scheme 1 -bit DACs are used since the inputs are received in a bit-serial manner. As a result, the hardware cost of this scheme is reduced compared to the one in Figure 3.

[0261] Figure 14 schematically illustrates a network node 511 for a wireless communications network 170 illustrated in Figure 16. The network node 511 comprises the receiver 420 or the transmitter 410 described above or both.

[0262] Figure 15 schematically illustrates a wireless communications device 513 comprising the receiver 420 or the transmitter 410 described above or both.

[0263] Figure 14 illustrates further optional details of the network node 511. Figure 15 illustrates further optional details of the wireless communications device 513. The network node 511 and the wireless communications device 513 may both be configured to perform the method actions of Figure 7a and Figure 9 above.

[0264] The embodiments herein may be implemented through a processor or one or more processors, such as the processor 1404, 1504 of a processing circuitry in the network node 511 and the wireless communications device 513 respectively, and depicted in Figure 14 and 15 together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product, for instance in the form of a data carrier carrying computer program code for performing the embodiments herein when being loaded into the network node 511 and the wireless communications device 513 respectively. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server and downloaded to the network node 511 and the wireless communications device 513 respectively.

[0265] The network node 511 and the wireless communications device 513 respectively may further comprise a memory 1402, 1502 comprising one or more memory units. The memory comprises instructions executable by the processor in the network node 511 and the wireless communications device 513 respectively.

[0266] The respective memory 1402, 1502 is arranged to be used to store e.g. information, data, configurations, and applications to perform the methods herein when being executed in the network node 511 and the wireless communications device 513 respectively.

[0267] In some embodiments, a computer program 1403, 1503 comprises instructions, which when executed by the at least one processor, cause the at least one processor of the network node 511 and the wireless communications device 513 respectively to perform the actions above.

[0268] In some embodiments, a carrier 1405, 1505 comprises the computer program, wherein the carrier is one of an electronic signal, an optical signal, an electromagnetic signal, a magnetic signal, an electric signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0269] The network node 511 and the wireless communications device 513 respectively may further comprise an input and output interface, I / O, 1406, 1506 configured to communicate with other devices. The input and output interface 1406, 1506 may comprise a receiver, such as a wireless receiver, (not shown) and a transmitter, such as a wireless transmitter, (not shown).

[0270] Those skilled in the art will also appreciate that the units described above may refer to a combination of analog and digital circuits, and / or one or more processors configured with software and / or firmware, e.g. stored in the network node 511 and the wireless communications device 513 respectively, that when executed by the respective one or more processors such as the processors described above. One or more of these processors, as well as the other digital hardware, may be included in a single Application- Specific Integrated Circuitry (ASIC), or several processors and various digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).

[0271] Figure 16 illustrates a wireless communications network 170 in which embodiments herein may be implemented.

[0272] The wireless communications network 170 may use a number of different technologies, such as Wi-Fi, Long Term Evolution (LTE), LTE-Advanced, 5G, New Radio (NR), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile communications / enhanced Data rate for GSM Evolution (GSM / EDGE), Worldwide Interoperability for Microwave Access (WiMax), or Ultra Mobile Broadband (UMB), just to mention a few possible implementations. Embodiments herein relate to recent technology trends that are of particular interest in a 5G context. However, embodiments are also applicable in further development of other existing wireless communication systems such as e.g. WCDMA and LTE and in future wireless communication systems, such as 6G systems.

[0273] Network nodes operate in the wireless communications network 170 such as the network node 511. The network node 511 provides radio coverage over a geographical area, a service area referred to as a cell 15, which may also be referred to as a beam or a beam group of a first radio access technology (RAT), such as 5G, LTE, Wi-Fi or similar. There may be more than one cell. For example, there may be a second cell 16 as well. The network node 511 may be a NR-RAN node, transmission and reception point e.g. a base station, a radio access node such as a Wireless Local Area Network (WLAN) access point or an Access Point Station (AP STA), an access controller, a base station, e.g. a radio base station such as a NodeB, an evolved Node B (eNB, eNode B), a gNB, a base transceiver station, a radio remote unit, an Access Point Base Station, a base station router, a transmission arrangement of a radio base station, a stand-alone access point or any other network unit capable of communicating with a wireless communications device within the service area depending e.g. on the radio access technology and terminology used. The respective network node 511 may be referred to as a serving radio access node and communicates with a UE with Downlink (DL) transmissions to the UE and Uplink (UL) transmissions from the UE.

[0274] A number of wireless communications devices operate in the wireless communication network 10, such as the wireless communications device 513.

[0275] The wireless communications device 12 may be a mobile station, a non-access point (non-AP) STA, a STA, a user equipment and / or a wireless terminal, that communicate via one or more Access Networks (AN), e.g. RAN, e.g. via the network node 511 to one or more core networks (CN) e.g. comprising a CN node 13, for example comprising an Access Management Function (AMF). It should be understood by the skilled in the art that “UE” is a non-limiting term which means any terminal, wireless communication terminal, user equipment, Machine Type Communication (MTC) device, Device to Device (D2D) terminal, or node e.g. smart phone, laptop, mobile phone, sensor, relay, mobile tablets or even a small base station communicating within a cell.

[0276] When using the word "comprise" or “comprising” it shall be interpreted as nonlimiting, i.e. meaning "consist at least of".

[0277] The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used.

Claims

CLAIMS1. An electronic decoder (421) for decoding of block coded wireless communications signals, the electronic decoder (421) comprising at least two electrically interconnected analogue crossbar arrays (1110, 1120) of memristors, wherein an electrical interconnection (1115) between a column (1111) of an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) and a row (1121) of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprises a current-to-voltage converter (1101), and wherein a first analogue crossbar array (1110) of the at least two analogue crossbar arrays (1110, 1120) comprises at least a first row of memristors (1112a) with a single input and a respective output for each column of memristors.

2. The electronic decoder (421) according to claim 1 , wherein the at least two electrically interconnected analogue crossbar arrays (1110, 1120) comprise a second analogue crossbar array (1120), and wherein a respective crossbar column of the first analogue crossbar array (1110) is electrically interconnected to a corresponding crossbar row of the second analogue crossbar array (1120).

3. The electronic decoder (421) according to claim 2, wherein the second analogue crossbar array (1120) comprises memristors configured to be programmed with elements of a parity check matrix.

4. The electronic decoder (421) according to claim 2 or 3, wherein the at least two electrically interconnected analogue crossbar arrays (1110, 1120, 1130) comprise a third analogue crossbar array (1130), and wherein a respective crossbar column of the third analogue crossbar array (1130) is directly electrically interconnected to a corresponding crossbar column of the second crossbar array (1120).

5. The electronic decoder (421) according to claim 4, wherein the third analogue crossbar array (1130) comprises memristors configured to be programmed with elements of an identity matrix.

6. The electronic decoder (421) according to claim 4 or 5, wherein the at least two electrically interconnected analogue crossbar arrays (1110, 1120, 1130, 1140)comprise a fourth analogue crossbar array (1140) of memristors, and wherein a respective crossbar column of the third analogue crossbar array (1130) is electrically interconnected to a corresponding crossbar row of the fourth crossbar array (1140).

7. The electronic decoder (421) according to claim 6, wherein the fourth analogue crossbar array (1140) of memristors comprises memristors configured to be programmed with elements of a transpose of the parity check matrix.

8. The electronic decoder (421) according to any of the claims 1-7, wherein the first analogue crossbar array (1110) comprises a second row (1112b) of memristors with a single input and a respective output for each column of memristors.

9. The electronic decoder (421) according to claim 1 , wherein the at least two electrically interconnected analogue crossbar arrays (1010, 1020) comprise a second analogue crossbar array (1020) of memristors, and wherein the first analogue crossbar array (1010) is configured to provide a Log Likelihood Ratio, LLR, of a respective symbol value of a noisy coded wireless communications signal as output from a respective crossbar column (1011 , 1012, 1013), and wherein an output of a respective crossbar column (1011 , 1012, 1013) of the first analogue crossbar array (1010) is electrically interconnected to a corresponding memristor (1021 , 1022, 1023) of the second analogue crossbar array (1020).

10. The electronic decoder (421) according to claim 9, wherein the second analogue crossbar array (1020) comprises memristors (1021 , 1022, 1023) configured to be programmed with elements of a matrix representing connections between variable nodes and check nodes of a Tanner graph, and wherein the second analogue crossbar array (1020) is configured to calculate an initial variable-to-check node message matrix based on input from the first analogue crossbar array (1010).

11. The electronic decoder (421) according to claim 9 or 10, wherein the at least two electrically interconnected analogue crossbar arrays further comprises one or more further electrically interconnected analogue crossbar arrays (10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090) of memristors which as an ensemble are configured to iteratively calculate an updated variable-to-check node message matrix based on a previous variable-to-check node message matrix as input.

12. The electronic decoder (421) according to claim 11 , wherein the one or more further electrically interconnected analogue crossbar arrays (10030, 10040, 10050, 10060, 10070, 10080, 10090) comprises a further first analogue crossbar array (10010) of memristors for which all memristors are configured with a value of 1 / 2, a further second analogue crossbar array (10020) of memristors for calculating a tanh-function of an output from the further first analogue crossbar array (10010), a further third analogue crossbar array (10030) of memristors comprising memristors (10031, 10032, 10033) configured to be programmed with elements of a parity check matrix, each memristor of the further second analogue crossbar array (10020) being connected to a corresponding memristor of the further first analogue crossbar array (10010) through a current-to-voltage converter (10015), each memristor of the further third analogue crossbar array (10030) being connected to a corresponding output of the further second analogue crossbar array (10020) through a current-to-voltage converter (10025), and wherein the further third analogue crossbar array (10030) is configured to calculate element-wise multiplication of the outputs from the further second analogue crossbar array (10020) with the parity check matrix.

13. The electronic decoder (421) according to claim 12, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further fourth analogue crossbar array (10040) of memristors configured to calculate an output as a product of the outputs from the further third analogue crossbar array (10030), wherein a respective memristor (10041 , 10042, 10043) of the further fourth analogue crossbar array (10040) is configured to be programmed with a corresponding output from the further third analogue crossbar array (10030), and each memristor (10041 , 10042, 10043) of the further fourth analogue crossbar array (10040) is interconnected to a further memristor of the further fourth analogue crossbar array (10040) via a current-to-voltage converter (100412, 100423).

14. The electronic decoder (421) according to claim 13, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further fifth analogue crossbar array (10050) of memristors and a further sixth analogue crossbar array (10060) of memristors, wherein the further fifth analogue crossbar array (10050) is configured to calculate an output as an inverse tanh value of the output from the further fourth analogue crossbar array (10040) and wherein the further sixth analogue crossbar array (10060) is configured to calculate an element of a check-to-variablenode message matrix by comprising a memristor (10061) connected to the output of the fifth analogue crossbar array (10050) and configured with a value of two.

15. The electronic decoder (421) according to claim 14, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further seventh analogue crossbar array (10070) of memristors and a further eighth analogue crossbar array (10080) of memristors, and wherein the further seventh analogue crossbar array (10070) comprises memristors (10071 , 10072, 10073) configured to be programmed with elements of the matrix representing connections between variable nodes and check nodes of the Tanner graph, and wherein the further seventh analogue crossbar array (10070) is configured to perform multiplication of the element of the variable-to-check node message matrix with a corresponding element of the matrix representing the connections between the variable nodes and the check nodes of the Tanner graph, and wherein the further eighth analogue crossbar array (10080) is configured to calculate a sum of messages for each variable node by being configured to calculate a sum of outputs from the further seventh analogue crossbar array (10070) by comprising a column of memristors of which each memristor is configured with a value of one and connected to a corresponding output of the further seventh analogue crossbar array (10070).

16. The electronic decoder (421) according to claim 15, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further ninth analogue crossbar array (10090) of memristors, and wherein the further ninth analogue crossbar array (10090) comprises multiple columns (10091, 10092) of memristors, each column comprising three memristors (10091a, 10091b, 10091c) of which a first and a second memristor (10091a, 10091b) are each configured with a value of one and a third memristor (10091c) is configured with a value of minus one and wherein each memristor of each column is connected to a separate input such that a respective output from each column is calculated by adding inputs to the first and the second memristor (10091a, 10091b) and subtracting input to the third memristor (10091c).

17. The electronic decoder (421) according to claim 16, wherein an input to a respective first memristor (10091a) of the further ninth analogue crossbar array (10090) is connected to a corresponding output of a column of the further eighth analogue crossbar array (10080), and wherein an input to a respective second memristors(100091b) of the further ninth analogue crossbar array (10090) is connected to a corresponding output of a column of the first analogue crossbar array (1010), and wherein an input to a respective third memristor of the further ninth analogue crossbar array (10090) is connected to a corresponding output of a column of the sixth analogue crossbar array (10060).

18. The electronic decoder (421) according to claim 16 or 17, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further tenth analogue crossbar array (100100) of memristors comprising memristors configured to be programmed with a row of elements of the matrix representing the connections between the variable nodes and the check nodes of the Tanner graph, and wherein the further tenth analogue crossbar array (100100) is configured to multiply the output from each column of the ninth analogue crossbar array (10090) with a memristor value of a corresponding column of the tenth analogue crossbar array (100100).

19. The electronic decoder (421) according to any of the claims 1-18, wherein a number of memristors of the first row (1112a) of memristors of the first analogue crossbar array (1010) equals a bit length of a coded wireless signal to be received by the electronic decoder (421).

20. The electronic decoder (421) according to any of the claims 1-19, wherein the first analogue crossbar array (1110) is configured to provide a respective output which is linearly dependent on a Log Likelihood Ratio, LLR, of a symbol value of a noisy coded wireless communications signal.

21. The electronic decoder (421) according to claim 20, wherein each memristor of the first row (1112a) of memristors is configured to be programmed with the respective symbol value of the received noisy coded wireless communications signal to calculate the LLR of the symbol value.

22. The electronic decoder (421) according to any of the claims 1-21, wherein the electronic decoder (421) is configured for non-binary decoding.

23. The electronic decoder (421) according to claim 22, wherein each memristor of the first row (1112a) of memristors is configured to be programmed with non-binary values.

24. A receiver (420) for wireless communications signals, the receiver (420) comprising the electronic decoder (421) of any of the claims 1-23.

25. An electronic encoder (411) for non-binary block encoding of wireless communications signals, the electronic encoder (411) comprising: an analogue crossbar array (310) of memristors (311, 312) wherein each memristor (311 , 312) of the analogue crossbar array is configured to be programmed with a respective matrix element of a non-binary generator matrix for non-binary block code generation.

26. A transmitter (410) for wireless communications signals, the transmitter (410) comprising the electronic encoder (411) according to claim 25.

27. A network node (511) for a wireless communications network (170), the network node (511) comprising the receiver (420) according to claim 24 or the transmitter (410) according to claim 26 or both.

28. A wireless communications device (513), comprising the receiver (420) according to claim 24 or the transmitter (410) according to claim 26 or both.

29. A method for decoding of block coded wireless communications signals with an electronic decoder (421) comprising at least two electrically interconnected analogue crossbar arrays (1010, 1020) of memristors, wherein an electrical interconnection (1115) between a column of an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1010, 1020) and a row of a following analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1010, 1020) comprises a current-to-voltage converter (1101), and wherein a first analogue crossbar array (1010) of the at least two analogue crossbar arrays comprises at least a first row (1112a) of memristors with a single input and a respective output for each column of memristors, and wherein the method comprises: iteratively updating (901), by the at least two electrically interconnected analogue crossbar arrays (1010, 1020), probability distributions of bits in an obtained codeword until convergence.

30. The method according to claim 29, wherein updating (901) the probability distributions of the bits in the obtained codeword comprises: calculating message matrices by the at least two electrically interconnected analogue crossbar arrays.

31. The method according to any of the claims 29-30, wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises: programming each memristor of the first row of memristors with a respective first symbol value of a received noisy coded wireless communications signal to calculate a Log Likelihood Ratio, LLR.

32. The method according to claim 31, wherein calculating the LLR is performed in a parallel manner by inputting a value of 2 divided by a noise variance of the wireless communications channel to the row of memristors of the first crossbar array.

33. The method according to any of the claims 29-32, further comprising programming an analogue crossbar array of the at least two electrically interconnected analogue crossbar arrays (1010, 1020) with elements of a parity check matrix.

34. The method according to any of the claims 29-33, further comprising: programming memristors of a third analogue crossbar array (1130) of the at least two electrically interconnected analogue crossbar arrays (1120, 1120, 1010) with elements of an identity matrix; and providing check node messages as input to crossbar rows of the third crossbar array (1130) of the at least two electrically interconnected analogue crossbar arrays (1120, 1120, 1130).

35. The method according to any of the claims 29-34, wherein the at least two electrically interconnected analogue crossbar arrays comprise a fourth analogue crossbar array (1140) of memristors, and wherein a respective crossbar column of the third analogue crossbar array (1130) is electrically interconnected to a corresponding crossbar row of the fourth crossbar array (1140), and wherein the method further comprises: programming () memristors of the fourth analogue crossbar array (1140) with elements of a transpose of the parity check matrix.

36. The method according to any of the claims 29-33, wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises: programming a second analogue crossbar array (1020) of the at least two electrically interconnected analogue crossbar arrays (1010, 1020) with elements of the parity check matrix, and calculating by the second analogue crossbar array (1020), an initial variable-to-check node message matrix based on input from the first analogue crossbar array (1010).

37. The method according to any of the claims 29-33 or 36, wherein the at least two electrically interconnected analogue crossbar arrays (1010, 1020) further comprise one or more further electrically interconnected analogue crossbar arrays (10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090, 100100) of memristors, and wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises: calculating, by the one or more further electrically interconnected analogue crossbar arrays (10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090, 100100), an updated variable-to-check node message matrix based on a previous variable-to-check node message matrix as input.

38. The method according to claim 37, wherein the one or more further electrically interconnected analogue crossbar arrays (10010, 10020, 10030, 10040, 10050, 10060, 10070, 10080, 10090, 100100) comprises a further first analogue crossbar array (10010) of memristors for which all memristors are configured with a value of 1 / 2, a further second analogue crossbar array (10020) of memristors for calculating a tanh-function of an output from the further first analogue crossbar array (10010), a further third analogue crossbar array (10030) of memristors, and wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises: programming memristors of the further third analogue crossbar array (10030) with elements of the parity check matrix; and calculating, by the further third analogue crossbar array (10030), element- wise multiplication of the outputs from the further second analogue crossbar array (10020) with the parity check matrix.

39. The method according to claim 38, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further fourth analoguecrossbar array (10040) of memristors and wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises: programming a respective memristor of the further fourth analogue crossbar array with a corresponding output from the further third analogue crossbar array; and calculating a product of the outputs from the further third analogue crossbar array.

40. The method according to claim 39, wherein the one or more further electrically interconnected analogue crossbar arrays comprises a further fifth analogue crossbar array (10050) of memristors and a further sixth analogue crossbar array (10060) of memristors comprising a memristor (10061) connected to the output of the fifth analogue crossbar array (10050) and configured with a value of two, and wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises: calculating, by the further fifth analogue crossbar array (10050), an inverse tanh value of the output from the further fourth analogue crossbar array (10040); and calculating, by the further sixth analogue crossbar array (10060), an element of a check-to-variable node message matrix41. The method according to any of the claims 31-40, wherein updating (901) the probability distributions of the bits in the obtained codeword further comprises reprogramming each memristor of the first row of memristors with a respective second symbol value of a received noisy coded second wireless communications signal, wherein a second code length of the second symbol value differs from a first code length of the symbol value of the wireless communications signal.

42. The method according to any of the claims 29-41, wherein the method is for nonbinary decoding.

43. A method for encoding of non-binary block coded wireless communications signals with an electronic encoder (411) comprising an analogue crossbar array (310) of memristors (311 , 312), the method comprising: programming (701) each memristor (311 , 312) of the analogue crossbar array (310) with a respective matrix element of a non-binary generator matrix for nonbinary block code generation;providing (702) a message vector based on wireless communications signals as input to crossbar rows of the analogue crossbar array (310); and obtaining (703) non-binary block coded wireless communications signals at outputs of crossbar columns of the analogue crossbar array.

44. A computer program (1403, 1503), comprising computer readable code units which when executed on a processor (1404, 1504) of a receiving device (511 , 513) causes the receiving device (511, 513) to perform the method according to any one of claims 29-42, wherein the receiving device (511 , 513) comprises the decoder according to any one of claims 1-23.

45. A computer program (1403, 1503), comprising computer readable code units which when executed on a processor (1404, 1504) of a of a transmitting device (511 , 513) causes the transmitting device (511 , 513) to perform the method according to claim 43, wherein the transmitting device (511 , 513) comprises the encoder according to claim 25.

46. A carrier (1405, 1505) comprising the computer program according to the preceding claim, wherein the carrier (1405, 1505) is one of an electronic signal, an optical signal, a radio signal and a computer readable medium.

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