A gate-level circuit partitioning method based on clustering
By dividing the gate-level circuit into undirected graphs and applying cyclic clustering and genetic algorithms, the problem of low efficiency and accuracy of gate-level circuit division in the prior art is solved, and efficient circuit division is achieved.
Patent Information
- Application Number
- CN202111076048.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-14
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2041-09-14
AI Technical Summary
In the prior art, gate-level circuit division efficiency and accuracy are poor, making it difficult to effectively deal with large-scale circuits.
The gate-level circuit division method based on clustering is adopted, and the adjacency matrix of the reading circuit is characterized as an undirected graph, and the cyclic clustering algorithm is used to roughen it, and the genetic algorithm is used to subdivide it to generate an efficient initial division scheme.
It improves the efficiency and accuracy of circuit division, realizes stable roughening and fine division, and can effectively handle large-scale circuits.
Smart Images
Figure CN113779909B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to the field of electrical technology, and in particular to a gate-level circuit partitioning method based on clustering. Background Art
[0002] At present, gate-level simulation is an important verification process in electronic design automation (EDA). With the increasing complexity of very large-scale integration (VLSI), the running time of gate-level simulation has become very long, and it has become more difficult to analyze gate-level circuits. Therefore, circuit parallelization simulation is one of the cutting-edge research issues in the field of EDA, and gate-level circuit partitioning has become the key to parallel simulation.
[0003] In circuit partitioning, there are usually two requirements, namely, reducing the number of connecting lines between subsets and making the number of gate circuits contained in each subset relatively balanced.
[0004] In the study of circuit partitioning, some basic partitioning algorithms such as KL and FM algorithms were proposed in the early stage. Later, spectral partitioning, simulated annealing, genetic algorithm, etc. appeared. However, these algorithms can only handle small-scale circuits. Later, multi-level partitioning algorithms appeared. They partition large-scale circuits by first roughening the large graph and then subdividing the small graph. The core of multi-level partitioning algorithms lies in roughening, and roughening generally includes two types, namely matching-based and clustering-based. Traditional multi-level partitioning algorithms such as METIS and DIBAP algorithms use matching algorithms to shrink edges in the roughening stage of the METIS algorithm, and use KL improved algorithms in the refinement stage. The calculation of this algorithm is relatively simple, but it can only handle small-scale circuits. The DIBAP algorithm uses the AMG algorithm for clustering in the roughening stage, and the propagation algorithm in the refinement stage. This algorithm can handle large-scale circuits, but it has the defects of complex calculations and unstable roughening (i.e., it is easy to form a denser roughened graph).
[0005] It can be seen that there is an urgent need for a clustering-based gate-level circuit partitioning method with high partitioning efficiency and partitioning accuracy. Summary of the invention
[0006] In view of this, an embodiment of the present disclosure provides a clustering-based gate-level circuit partitioning method, which at least partially solves the problem of poor partitioning efficiency and partitioning accuracy in the prior art.
[0007] The embodiment of the present disclosure provides a gate-level circuit partitioning method based on clustering, including:
[0008] Reading an adjacency matrix of the circuit to be divided and representing the adjacency matrix as an undirected graph;
[0009] Using a preprocessing operation to remove redundant points in the undirected graph to obtain a target graph;
[0010] According to the received partitioning instruction, the nodes in the target graph are partitioned into a plurality of sets using a cyclic clustering algorithm, wherein the number of the sets is the same as the number of partitions of the circuit to be partitioned in the partitioning instruction;
[0011] According to the genetic algorithm, the nodes in the target graph that are not divided into the set are allocated to a plurality of the sets to generate a plurality of initial division schemes;
[0012] The modularity of each of the initial partitioning schemes is calculated, and the initial partitioning scheme with the highest modularity is selected as the target partitioning scheme.
[0013] According to a specific implementation of the embodiment of the present disclosure, the step of dividing the nodes in the target graph into multiple sets using a cyclic clustering algorithm according to the received division instruction includes:
[0014] Taking the node with the highest degree in the target graph as the initial node of each round, a breadth-first search is performed on all nodes in the undirected graph;
[0015] When the search algorithm searches for the point with the highest mean value, and the number of nodes searched is greater than the threshold, the search is stopped, and the searched nodes are formed into a set and removed from the target graph;
[0016] The breadth-first search is continued from the remaining nodes in the target graph until a set corresponding to the number of partition instructions is obtained.
[0017] According to a specific implementation of the embodiment of the present disclosure, after the step of dividing the nodes in the target graph into multiple sets using a cyclic clustering algorithm according to the received division instruction, the method further includes:
[0018] The nodes in the target graph that are not divided into the set are formed into a small-scale graph.
[0019] According to a specific implementation of the embodiment of the present disclosure, the step of allocating nodes in the target graph that are not divided into the set to multiple sets according to the genetic algorithm to generate multiple initial division schemes includes:
[0020] Generate multiple arrays according to the number of the sets and the nodes in the small-scale graph, each array serving as a chromosome;
[0021] Performing a crossover operation between different chromosomes, and performing a mutation operation on each chromosome to obtain a new generation population;
[0022] Splicing the new generation population with the plurality of the sets, and calculating the modularity corresponding to the whole after splicing;
[0023] Taking the relative value of the modularity as a fitness function;
[0024] According to the fitness function, using roulette wheel to select and separate high-quality offspring from the new generation population;
[0025] If the number of times of the genetic algorithm is less than the preset number, the small-scale graph after separating the high-quality offspring continues to be crossover operated, and each chromosome is mutated until the number of times of the genetic algorithm is equal to the predicted number;
[0026] The population of each generation is respectively spliced with multiple sets to obtain multiple initial partitioning schemes.
[0027] According to a specific implementation of the embodiment of the present disclosure, the modularity is
[0028]
[0029] Among them, e it represents the ratio of the edges between community i and community t to the total number of edges, a i It represents the ratio of the number of endpoints of the edges connected to community i to the total number of endpoints, and Tre represents the ratio of all edges classified into the same camp to the total number of edges.
[0030] According to a specific implementation of the embodiment of the present disclosure, after the step of calculating the modularity of each of the initial partitioning schemes and selecting the initial partitioning scheme with the highest modularity as the target partitioning scheme, the method further includes:
[0031] According to the set corresponding to the target partitioning scheme and the node numbers contained therein, a partitioning circuit diagram corresponding to the partitioning instruction is drawn.
[0032] The clustering-based gate-level circuit partitioning scheme in the embodiment of the present disclosure includes: reading the adjacency matrix of the circuit to be divided and representing the adjacency matrix as an undirected graph; using a preprocessing operation to remove redundant points in the undirected graph to obtain a target graph; according to the received partitioning instruction, using a cyclic clustering algorithm to divide the nodes in the target graph into multiple sets, wherein the number of the sets is the same as the number of divisions of the circuit to be divided in the partitioning instruction; according to a genetic algorithm, allocating the nodes in the target graph that are not divided into the sets to multiple sets to generate multiple initial partitioning schemes; calculating the modularity of each of the initial partitioning schemes, and selecting the initial partitioning scheme with the highest modularity as the target partitioning scheme.
[0033] The beneficial effects of the embodiments of the present disclosure are as follows: through the scheme of the present disclosure, a cyclic clustering algorithm is used to achieve stable coarsening of the target graph, and then a multi-way genetic algorithm is used to perform fine division, thereby improving the efficiency and accuracy of circuit division. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0035] Figure 1 A schematic diagram of a flow chart of a gate-level circuit partitioning method based on clustering provided in an embodiment of the present disclosure;
[0036] Figure 2 An undirected graph of a circuit to be divided involved in a clustering-based gate-level circuit division method provided in an embodiment of the present disclosure;
[0037] Figure 3 A schematic diagram of a cyclic clustering algorithm flow chart involved in a clustering-based gate-level circuit partitioning method provided in an embodiment of the present disclosure;
[0038] Figure 4 A schematic diagram of the result after being processed by a clustering algorithm involved in a clustering-based gate-level circuit partitioning method provided in an embodiment of the present disclosure;
[0039] Figure 5 A schematic diagram of a genetic algorithm flow chart involved in a clustering-based gate-level circuit partitioning method provided in an embodiment of the present disclosure;
[0040] Figure 6 A schematic diagram of a partitioning result after being processed by a clustering-based gate-level circuit partitioning method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0041] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
[0042] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0043] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.
[0044] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The drawings only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0045] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0046] The embodiment of the present disclosure provides a clustering-based gate-level circuit partitioning method, which can be applied to the circuit segmentation process in an integrated circuit manufacturing scenario.
[0047] See also Figure 1 , is a flow chart of a clustering-based gate-level circuit partitioning method provided by an embodiment of the present disclosure. Figure 1 As shown, the method mainly comprises the following steps:
[0048] S101, reading an adjacency matrix of a circuit to be divided and representing the adjacency matrix as an undirected graph;
[0049] In specific implementation, the circuit diagram to be divided can be converted to obtain the corresponding undirected graph as follows: Figure 2 As shown, this is a graph with obvious partitioning features. Intuitively, the graph can be divided into three parts: left, middle and right. According to the undirected graph, the generated node data can be more easily clustered and roughly divided.
[0050] S102, removing redundant points in the undirected graph by preprocessing operations to obtain a target graph;
[0051] In a specific implementation, considering that there may be scattered points or a small number of dispersed point sets in the undirected graph, the redundant points in the undirected graph can be removed through the preprocessing operation to obtain the target graph.
[0052] S103, according to the received partitioning instruction, using a cyclic clustering algorithm to partition the nodes in the target graph into a plurality of sets, wherein the number of the sets is the same as the number of partitions of the circuit to be partitioned in the partitioning instruction;
[0053] Specifically, the partitioning instruction may include the number of divisions of the circuit to be divided, and then the cyclic clustering algorithm may be used to cluster in sequence to divide the nodes in the target graph into multiple sets, and the circuit to be divided may be coarsened by the cyclic clustering algorithm to facilitate the next division process.
[0054] S104, allocating nodes in the target graph that are not divided into the set into a plurality of the sets according to a genetic algorithm, and generating a plurality of initial division schemes;
[0055] After clustering the nodes in the target graph to obtain multiple sets, for the nodes in the target graph that are not divided into the sets, the nodes in the target graph that are not divided into the sets can be allocated according to the genetic algorithm and spliced with the multiple sets, thereby improving the optimization and subdivision of the multiple sets and obtaining multiple initial division schemes.
[0056] S105, calculating the modularity of each of the initial partitioning schemes, and selecting the initial partitioning scheme with the highest modularity as the target partitioning scheme.
[0057] Optionally, the modularity is
[0058]
[0059] Among them, e it represents the ratio of the edges between community i and community t to the total number of edges, a iIt represents the ratio of the number of endpoints of the edges connected to community i to the total number of endpoints, and Tre represents the ratio of all edges classified into the same camp to the total number of edges.
[0060] For example, suppose community partitioning divides a network into k communities and defines a k*k matrix e. ij represents the ratio of the number of edges connecting community i and community j to the total number of edges. In particular, e it It represents the ratio of the edges between community i and community t to the total number of edges.
[0061] The trace of the matrix Tre = ∑ i e it , which means the ratio of all edges that are divided into the same camp to the total number of edges. Obviously, the better the community division is, the denser the connections between nodes in the community, and the fewer the number of connections between different subsets, the higher the value. The trace of the matrix alone cannot fully reflect the community structure, because if the network is divided into only one community, then Tre = 1, so another value a is defined. i =∑ j e it , which represents the ratio of the number of endpoints connected to the edge in community i (equivalent to the sum of the degrees of all the points in the community) to the total number of endpoints (2m). This quantity can be understood in circuit partitioning as a quantity set to prevent load imbalance and the situation where the ratio of the edges within the camp to the total number of edges is still large. The Q value can be used as a standard to evaluate the quality of circuit partitioning. The larger the Q value, the better the balance of the divided circuit and the number of connections between different subsets.
[0062] The clustering-based gate-level circuit partitioning method provided in this embodiment achieves stable coarsening of the target graph by using a cyclic clustering algorithm, and then performs fine partitioning by using a multi-way genetic algorithm, thereby improving the efficiency and accuracy of circuit partitioning.
[0063] On the basis of the above embodiment, in step S103, according to the received partitioning instruction, the nodes in the target graph are partitioned into multiple sets using a cyclic clustering algorithm, including:
[0064] Taking the node with the highest degree in the target graph as the initial node of each round, a breadth-first search is performed on all nodes in the undirected graph;
[0065] When the search algorithm searches for the point with the highest mean value, and the number of nodes searched is greater than the threshold, the search is stopped, and the searched nodes are formed into a set and removed from the target graph;
[0066] The breadth-first search is continued from the remaining nodes in the target graph until a set corresponding to the number of partition instructions is obtained.
[0067] In specific implementation, the degree value and the betweenness value corresponding to each node in the target graph can be calculated, and then the breadth-first search can be performed. When performing the breadth-first search, the degree value can represent the correlation between a node and its neighboring nodes. The node with the highest degree value in the target graph can be used as the initial node of each round, and a breadth-first search can be performed on all nodes in the undirected graph. When the search algorithm searches for the point with the highest betweenness value, and the number of nodes searched is greater than the threshold, the search is stopped, and the searched nodes are formed into a set and removed from the target graph, and then the breadth-first search is continued from the remaining nodes in the target graph until the number of sets corresponding to the division instruction is obtained. It should be noted that the point with the highest betweenness value can be used as the boundary point in the set corresponding to the current round of the search algorithm, that is, the point in the set Y. The number of collection points can be set according to the division needs. For example, when the circuit diagram to be divided needs to be divided into 2 blocks, a point with the highest betweenness value is searched, and when the circuit diagram to be divided needs to be divided into 3 blocks, 2 points with the highest betweenness value are searched.
[0068] This step will be described below in conjunction with a specific embodiment. Figure 3 As shown,
[0069] S301, the preprocessed graph G is used as input and the clustering algorithm is started;
[0070] S302, set the number of blocks N for circuit segmentation, the minimum number of nodes M for the search algorithm to be terminated, find out the points with relatively high graph intermediary values, and put them into set Y;
[0071] In the specific implementation, in the subsequent breadth-first search, if the starting point of the search algorithm is directly connected to the points in the set Y, the search algorithm will stop immediately. In order to avoid this situation, a cutoff condition is set for the search algorithm, that is, the search algorithm will only stop when the number of points currently searched is greater than a set threshold M.
[0072] S303, the initial clustering algorithm will perform multiple rounds of breadth-first search, each time searching for the point with the largest degree in the current circuit as the initial node of this round of breadth-first search;
[0073] S304, performing a breadth-first search;
[0074] During the specific implementation, the node numbers and quantities found must be recorded and saved;
[0075] S305, determining whether the breadth-first search has found a node in the set Y;
[0076] In specific implementation, if yes, proceed to the next step of judgment, if not, continue with breadth-first search;
[0077] S306, determining whether the number of nodes that have been searched is greater than M;
[0078] In specific implementation, if yes, proceed to the next step, if not, record and save the current node and continue to perform breadth-first search;
[0079] S307, when both of the above conditions are met, the breadth-first search of this round is terminated, and the nodes searched in this round are removed from the graph G;
[0080] S308, after a round of search ends, N decreases by 1;
[0081] That is, N not only represents the number of blocks into which the circuit is divided, but also the number of BFS search rounds required.
[0082] S309, initial clustering algorithm cutoff judgment condition, that is, judging whether the number of rounds of the search algorithm is greater than 0;
[0083] In the specific implementation, if yes, the next round of breadth-first search is performed, and the updated graph G is used as the search object of breadth-first search. If not, the initial clustering algorithm is terminated, and the result after division is obtained as follows Figure 4 As shown, three clustering rough divisions are performed, and the relatively dense node areas in the target graph are respectively aggregated into one category to obtain three subsets. After the clustering rough division, there may still be relatively sparse and undivided nodes around each subset, then step S310 can be executed to perform a genetic algorithm. The above is a process of initial cyclic clustering, and the clustering algorithm outputs the graph G after removing the nodes searched by the N-round search algorithm, and the remaining nodes are all some points around the set Y.
[0084] On the basis of the above embodiment, in step S103, after dividing the nodes in the target graph into multiple sets using a cyclic clustering algorithm according to the received division instruction, the method further includes:
[0085] The nodes in the target graph that are not divided into the set are formed into a small-scale graph.
[0086] For example, after clustering to obtain a plurality of the sets, the remaining nodes are used to form the small-scale graph G', and the genetic algorithm is used to assign these points to the N cluster subsets mentioned above, thereby finding the optimal partitioning result.
[0087] Further, such as Figure 5 As shown, in step S104, according to the genetic algorithm, the nodes in the target graph that are not divided into the set are allocated to multiple sets to generate multiple initial division schemes, including:
[0088] S501, generating multiple arrays according to the number of the sets and the nodes in the small-scale graph, each array serving as a chromosome;
[0089] Considering that the original graph G has much fewer nodes after the clustering operation, this will greatly improve the efficiency and accuracy of the genetic algorithm in processing the circuit partitioning problem. Multiple arrays can be generated according to the number of the sets and the nodes in the small-scale graph, and each array serves as one of the chromosomes. For example, the population and chromosomes can be initialized according to the number of segmented subsets N and the number of nodes x in the graph G', that is, each segmented subset corresponds to an integer in [0, N], and an array of length x is generated. Integers in the interval [0, N] are randomly generated as array elements to ensure that each number of 0 and N is taken and their number is consistent, and the array is used as one of the chromosomes.
[0090] S502, performing a crossover operation between different chromosomes, and performing a mutation operation on each chromosome to obtain a new generation population;
[0091] Then, the different chromosomes can be crossovered according to the preset crossover probability and mutation probability to exchange parts of the structure. For a single chromosome, the elements on the chromosome array mutate according to the preset mutation probability, and then a new generation of population is obtained.
[0092] S503, splicing the new generation population with the plurality of the sets, and calculating the modularity corresponding to the whole after splicing;
[0093] After obtaining the new generation population, the new generation population can be spliced with a plurality of the sets to obtain a partitioning scheme corresponding to the circuit to be divided, and the modularity corresponding to the whole after splicing can be calculated.
[0094] S504, taking the relative value of the modularity as a fitness function;
[0095] In the specific implementation, modularity is also called modularity metric, which is a commonly used method to measure the strength of network community structure. For circuit partitioning, modularity Q can also be used as an indicator to evaluate the quality of partitioning. The Q value is usually a number between (-0.5, 1). Generally, the higher the Q value, the fewer the number of connecting lines between subsets, and the number of gate circuits contained in each subset is relatively balanced. If modularity Q is directly used as the fitness function of each gene in each generation of population, the difference in Q value on each gene will be very small, and the convexity and convergence of the genetic algorithm will be very poor. I subtract the Q of each gene from the Q value with the smallest Q value in this generation of population, and the number obtained is used as the fitness function of each gene.
[0096] The relative value of the modularity can be used as a fitness function to improve the convexity and convergence of the algorithm. For example, the relative value of the modularity can be expressed as:
[0097] fitness=f i =Q i =Q min ,
[0098] Among them, Q i represents the modularity of each gene in each generation of the population, Q min Indicates the minimum modularity in this generation of population, f i Represents the fitness function of each gene.
[0099] S505, selecting and separating high-quality offspring from the new generation population using roulette according to the fitness function;
[0100] In specific implementation, after a genetic algorithm is performed, the roulette wheel can be used to select high-quality offspring from the population obtained by this genetic algorithm according to the fitness function, and the selected high-quality offspring can be separated to avoid crossover mutation from occurring in the clustered node set, which affects the generation of the optimal result.
[0101] S506, if the number of times of the genetic algorithm is less than the preset number, the small-scale graph after separating the high-quality offspring continues to be crossover operated, and each chromosome is mutated until the number of times of the genetic algorithm is equal to the predicted number;
[0102] In specific implementation, after each completion of the genetic algorithm, a judgment can be made. If the number of times the genetic algorithm is completed is less than the preset number, the small-scale graph after separating the high-quality offspring will continue to be crossover operated, and each chromosome will be mutated until the number of times the genetic algorithm is equal to the predicted number, so as to obtain a better division result.
[0103] S507, respectively concatenating the population of each generation with the plurality of sets to obtain a plurality of initial partitioning schemes.
[0104] Then the population of one generation is spliced with multiple sets to obtain multiple initial partitioning schemes such as Figure 6 As shown in the figure, the number of nodes protected in the three sets is 25, 24 and 17 respectively, which meets the requirement of balanced circuit partitioning. Modularity can also be used as a criterion for judging the density of connections between subsets. Generally, when Q is greater than 0.3, it means that the structure between subsets in the circuit is relatively strong and the number of connecting edges is small. The Q value of the circuit after algorithm partitioning is about 0.574, which meets the requirement of the number of connections for circuit partitioning.
[0105] On the basis of the above embodiment, after calculating the modularity of each of the initial partitioning schemes and selecting the initial partitioning scheme with the highest modularity as the target partitioning scheme as described in step S105, the method further includes:
[0106] According to the set corresponding to the target partitioning scheme and the node numbers contained therein, a partitioning circuit diagram corresponding to the partitioning instruction is drawn.
[0107] For example, after obtaining the target partitioning scheme, the node numbers contained in the N subsets at this time can be output, and a partitioning circuit diagram corresponding to the partitioning instruction can be drawn using drawing software such as networkx.
[0108] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A gate-level circuit partitioning method based on clustering, characterized in that: include: Reading an adjacency matrix of the circuit to be divided and representing the adjacency matrix as an undirected graph; Using a preprocessing operation to remove redundant points in the undirected graph to obtain a target graph; According to the received partitioning instruction, the nodes in the target graph are partitioned into a plurality of sets using a cyclic clustering algorithm, wherein the number of the sets is the same as the number of partitions of the circuit to be partitioned in the partitioning instruction; The step of dividing the nodes in the target graph into multiple sets using a cyclic clustering algorithm according to the received division instruction includes: Taking the node with the highest degree in the target graph as the initial node of each round, a breadth-first search is performed on all nodes in the undirected graph; When the search algorithm searches for the node with the highest betweenness value, and the number of nodes searched is greater than the threshold, the search is stopped, and the searched nodes are formed into a set and removed from the target graph; Continue the breadth-first search from the remaining nodes in the target graph until a set corresponding to the number of partition instructions is obtained; After the step of dividing the nodes in the target graph into a plurality of sets using a cyclic clustering algorithm according to the received division instruction, the method further comprises: The nodes in the target graph that are not divided into the set are formed into a small-scale graph; According to the genetic algorithm, the nodes in the target graph that are not divided into the set are allocated to a plurality of the sets to generate a plurality of initial division schemes; The step of allocating the nodes in the target graph that are not divided into the set into a plurality of the sets according to the genetic algorithm to generate a plurality of initial division schemes comprises: Generate multiple arrays according to the number of the sets and the nodes in the small-scale graph, each array being a chromosome; Performing a crossover operation between different chromosomes, and performing a mutation operation on each chromosome to obtain a new generation population; Splicing the new generation population with the plurality of the sets, and calculating the modularity corresponding to the whole after splicing; Taking the relative value of the modularity as a fitness function; According to the fitness function, using roulette wheel to select and separate high-quality offspring from the new generation population; If the number of times of the genetic algorithm is less than the preset number, the small-scale graph after separating the high-quality offspring continues to be crossover operated, and each chromosome is mutated until the number of times of the genetic algorithm is equal to the preset number; Splicing the population of each generation with the plurality of sets respectively to obtain a plurality of initial partitioning schemes; The modularity of each of the initial partitioning schemes is calculated, and the initial partitioning scheme with the highest modularity is selected as the target partitioning scheme.
2. The method according to claim 1, characterized in that , the modularity is Among them, e it represents the ratio of the edges between community i and community t to the total number of edges, a i It represents the ratio of the number of endpoints of the edges connected to community i to the total number of endpoints, and Tre represents the ratio of all edges classified into the same camp to the total number of edges.
3. The method according to claim 1, characterized in that After the step of calculating the modularity of each of the initial partitioning schemes and selecting the initial partitioning scheme with the highest modularity as the target partitioning scheme, the method further includes: According to the set corresponding to the target partitioning scheme and the node numbers contained therein, a partitioning circuit diagram corresponding to the partitioning instruction is drawn.