Power supply and display device including the same

Abstract

A power supply and a display device including the same are provided. The display device includes a display panel including scan lines, first power lines, second power lines, and pixels connected with the scan lines, the first power lines, and the second power lines; a gate driver sequentially providing a scan signal to the scan lines based on a clock signal; and a power supply including a plurality of transistors, converting an input power voltage into a first power voltage and supplying the first power voltage to the first power lines through a first output terminal by switching operation of the plurality of transistors. In response to an amount of current flowing through the pixels being less than a first reference current amount, the power supply is configured to change one or more of a cutoff duty ratio of at least one transistor of the plurality of transistors, a channel capacitance of at least one transistor of the plurality of transistors, a switching frequency of at least one transistor of the plurality of transistors, and a conversion rate of at least one control signal for the plurality of transistors.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0070437, filed on June 10, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. TECHNICAL FIELD

[0002] Exemplary embodiments of the present invention relate generally to a power supply, and more particularly, to a power supply and a display apparatus including the same. BACKGROUND

[0003] The display apparatus includes a DC-DC converter configured to generate a high potential power supply and a low potential power supply required to drive a pixel by converting an input power voltage supplied from the outside. The DC-DC converter supplies the generated high potential power supply and the generated low potential power supply to the pixel through a power line.

[0004] A driving current flowing through the pixel is dependent on the high potential power supply. In order to stably provide a desired driving current to the pixel, the DC-DC converter generates the high potential power supply while operating in a continuous conduction mode (hereinafter, referred to as CCM) among various driving methods. Under the CCM, the DC-DC converter switches internal transistors without pausing.

[0005] The above information disclosed in this Background section is only for understanding of the background of the inventive concepts, and, therefore, it can contain information that does not constitute prior art. SUMMARY

[0006] The applicant recognized that a voltage generating circuit (such as a DC-DC converter) can have a lower current and / or power efficiency under a CCM than another mode (such as a mode for partially stopping and / or holding switching operations of a plurality of transistors of the voltage generating circuit when a load of a pixel is relatively small).

[0007] A power supply and a display device including the same constructed according to the principles of the present application and exemplary embodiments can have improved efficiency. For example, the power supply can select one of a plurality of modes based on a load of a display unit and / or a current supplied from the power supply to the display unit, and can adjust one or more of an off duty ratio of at least one of a plurality of transistors of the power supply, a channel capacitance of at least one of the plurality of transistors, a switching frequency of at least one of the plurality of transistors, and a slew rate (or a transition time) of at least one of control signals for the plurality of transistors according to the selected mode. Accordingly, the power supply can have improved current and / or power efficiency, and power loss of the power supply can be minimized. For example, the power supply can have improved current and / or power efficiency when increasing the off duty ratio, decreasing the channel capacitance, decreasing the switching frequency, and / or increasing the slew rate (or decreasing the transition time). In addition, the power supply can provide the control signals having a relatively low frequency by shifting a clock signal of a scan driver by an offset frequency. Accordingly, the power supply can reduce power loss caused by switching and reduce interference between the power supply and the scan driver.

[0008] Other features of the inventive concept will be set forth in the description below, and in part will become apparent from the description, or can be learned by practice of the inventive concept.

[0009] According to one aspect of the present application, a display device includes a display panel including scan lines, first power lines, second power lines, and pixels connected to the scan lines and the first and second power lines, a gate driver sequentially providing scan signals to the scan lines based on a clock signal, and a power supply including a plurality of transistors converting an input power voltage into a first power voltage and supplying the first power voltage to the first power lines through a first output terminal by switching operation of the plurality of transistors. In response to an amount of current flowing through the pixels being less than a first reference current amount, the power supply is configured to change one or more of an off duty ratio of at least one of the plurality of transistors, a channel capacitance of at least one of the plurality of transistors, a switching frequency of at least one of the plurality of transistors, and a slew rate of at least one of control signals for the plurality of transistors.

[0010] The power supply can include: a frequency generation circuit that generates a switching signal having a first switching frequency in the first mode and generates a switching signal having a second switching frequency in the second mode; a first voltage generation circuit including a plurality of transistors that generates a first power voltage in response to the switching signal; a sensing circuit that senses an amount of current flowing through the first output terminal by measuring the current at the first output terminal; and a function circuit that generates a mode control signal to control the frequency generation circuit to operate in the first mode or the second mode by comparing the amount of current with a first reference current amount. The second switching frequency can be lower than the first switching frequency and be set to avoid a frequency of the clock signal.

[0011] The power supply can further include an oscillation circuit that generates a reference clock signal having a reference frequency. The frequency generation circuit can be configured to generate the switching signal by performing frequency division on the reference clock signal in the first mode.

[0012] The power supply can be configured to receive the clock signal through the clock signal input terminal, and the frequency generation circuit can be configured to shift the clock signal by an offset frequency to generate the switching signal in the second mode.

[0013] The power supply can further include an oscillation circuit that generates a reference clock signal having a reference frequency, and the frequency generation circuit can be configured to generate the switching signal based on the reference clock signal in the first mode.

[0014] The frequency generation circuit can include: a frequency divider that generates a divided reference clock signal by performing frequency division on the reference clock signal in response to a first mode control signal generated by the function circuit; a clock processor that generates a compensated clock signal by shifting the clock signal by an offset frequency in response to a second mode control signal generated by the function circuit; and a selector that outputs one selected from among the reference clock signal, the divided reference clock signal, and the compensated clock signal as the switching signal in response to the first mode control signal or the second mode control signal.

[0015] The clock processor can be configured to generate the compensated clock signal by delaying a pulse of the clock signal.

[0016] The function circuit can be configured to: perform a mode change from the first mode to the second mode when the amount of current becomes less than a first reference current amount; and perform a mode change from the second mode to the first mode when the amount of current becomes greater than a second reference current amount. The second reference current amount can be greater than the first reference current amount.

[0017] The function circuit can be configured to perform the mode change from the first mode to the second mode after a predetermined debounce time elapses from a time when the amount of current becomes less than the first reference current amount.

[0018] The power supply can further include a drive control circuit that generates a drive control signal in response to the mode control signal, the first voltage generation circuit can include: a first switch controller that generates a first control signal and a second control signal, and changes a waveform of each of the first control signal and the second control signal in response to the drive control signal, each of the first control signal and the second control signal having a frequency corresponding to a frequency of the switching signal; an inductor connected between a power input terminal to which an input power voltage is applied and a first node; a first transistor connected between the first node and a reference power source, the first transistor operating in response to the first control signal; and a second transistor connected between the first node and a first output terminal, the second transistor operating in response to the second control signal.

[0019] A slew rate of the control signal can be defined as a transition time between an on level and an off level of the control signal, and the first switch controller can be configured to reduce a transition time of the first control signal in the second mode to be less than a transition time of the first control signal in the first mode in response to the drive control signal.

[0020] The first voltage generation circuit can be configured to operate in a first drive mode to alternately turn on the first transistor and the second transistor in the first mode, and operate in a second drive mode in the second mode. In the second drive mode, the first voltage generation circuit can be configured to alternately turn on the first transistor and the second transistor in a first period, and turn off the first transistor and the second transistor in a second period.

[0021] The first voltage generation circuit can further include: a first auxiliary transistor connected in parallel with the first transistor; and a second auxiliary transistor connected in parallel with the second transistor. The first voltage generation circuit can be configured to alternately turn on the first transistor and the second transistor in the first mode, turn off the first transistor and the second transistor, and alternately turn on the first auxiliary transistor and the second auxiliary transistor in the second mode.

[0022] The power supply can further include a second voltage generation circuit that generates a second power voltage in response to the switching signal and supplies the second power voltage to a second power line through a second output terminal.

[0023] The second voltage generating circuit can include a second switch controller generating a third control signal and a fourth control signal, and changing a waveform of each of the third control signal and the fourth control signal in response to the driving control signal, each of the third control signal and the fourth control signal having a frequency corresponding to a frequency of the switch signal; a third transistor connected between a power input terminal to which an input power voltage is applied and a second node, the third transistor operating in response to the third control signal; an inductor connected between the second node and a reference power source; and a fourth transistor connected between the second node and a second output terminal, the fourth transistor operating in response to the fourth control signal.

[0024] The second voltage generating circuit can be configured to operate in a third driving mode in the second mode in response to the driving control signal. In the third driving mode, the second voltage generating circuit can be configured to alternately turn on the third transistor and the fourth transistor in a third period, and turn off the third transistor and the fourth transistor in a fourth period, the fourth period being greater than or equal to the third period.

[0025] The second voltage generating circuit can be configured to operate in the first mode in response to the driving control signal in one selected from among the first driving mode, the second driving mode, and the third driving mode.

[0026] The display apparatus can further include a data driver providing a data signal to the pixels through a data line, and the power supply can further include a third voltage generating circuit generating a third power voltage in response to the switch signal and providing the third power voltage to the data driver through a third output terminal.

[0027] According to another aspect of the present application, a power supply for outputting a power voltage through an output terminal includes an input terminal receiving a clock signal; a sensing circuit measuring an amount of current at the output terminal; a function circuit generating a first mode control signal or a second mode control signal by comparing the amount of current with a reference amount of current; an oscillation circuit generating a reference clock signal having a reference frequency; a frequency generating circuit generating a switch signal by performing frequency division on the reference clock signal in response to the first mode control signal, or by shifting the clock signal by an offset frequency in response to the second mode control signal; and a voltage generating circuit including a plurality of transistors converting an input power voltage into the power voltage by switching the plurality of transistors in response to the switch signal. A switching frequency of the switch signal is set to avoid a frequency of the clock signal.

[0028] The power supply can further include a drive control circuit that generates the drive control signal in response to the first mode control signal or the second mode control signal. The voltage generation circuit can include a switch controller that generates the first control signal and the second control signal and changes a waveform of each of the first control signal and the second control signal in response to the drive control signal, each of the first control signal and the second control signal having a frequency corresponding to a frequency of the switching signal, an inductor connected between a power input terminal to which an input power voltage is applied and a first node, a first transistor connected between the first node and a reference power source, the first transistor operating in response to the first control signal, and a second transistor connected between the first node and an output terminal, the second transistor operating in response to the second control signal, the switch controller can be configured to change a slew rate of the first control signal in response to the drive control signal corresponding to the second mode control signal.

[0029] It will be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the principles of the application.

[0031] Figure 1 is a block diagram of a display apparatus constructed in accordance with the principles of the application.

[0032] Figure 2 is Figure 1 is a circuit diagram of an exemplary embodiment of a representative pixel in the pixels of

[0033] Figure 3 is Figure 1 is a block diagram of an exemplary embodiment of a power supply of

[0034] Figure 4 is Figure 3 is a circuit diagram of an exemplary embodiment of a first voltage generator of

[0035] Figure 5 is Figure 3 is a circuit diagram of an exemplary embodiment of a second voltage generator of

[0036] Figure 6 is Figure 4 is a timing chart of signals in which the first voltage generator of

[0037] Figure 7 is Figure 4a timing chart of another exemplary embodiment of a signal of the DCM driving method performed by the first voltage generator of

[0038] Figure 8 is Figure 4 a timing chart of yet another exemplary embodiment of a signal of the PSM driving method performed by the first voltage generator of

[0039] Figure 9 is a graph showing an exemplary embodiment of the operation of the power supply of Figure 3

[0040] Figure 10 is a graph showing an exemplary embodiment of the switching operation of the first voltage generator of Figure 4

[0041] Figure 11 is a timing chart of an exemplary embodiment of one of the control signals used in the first voltage generator of Figure 4

[0042] Figure 12 is a graph showing the relationship between the switching frequency of the switching signal generated in the frequency generation circuit of Figure 3

[0043] Figure 13 is a block diagram of an exemplary embodiment of the frequency generation circuit of Figure 3

[0044] Figure 14 is a graph showing an exemplary embodiment of the operation of the functional circuit and the frequency generation circuit of Figure 3

[0045] Figure 15A Figure 15B and Figure 15C are graphs of exemplary embodiments of the register setting values for the power supply of Figure 3

[0046] Figure 16 is a graph showing the efficiency of the power supply of Figure 3 DETAILED DESCRIPTION

[0047] ​​​​​​​​​In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable terms and are non-limiting examples of an apparatus or method that employs one or more of the inventive concepts disclosed herein. It will be apparent, however, that various exemplary embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, any reference to "one embodiment" or "an embodiment" or "example embodiment" means that a particular feature, structure, characteristic, or property described in connection with the embodiment is included in at least one embodiment or implementation of the present invention. The appearance of the phrase "in one embodiment" or "an embodiment" or "example embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0048] Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification, discussions utilizing terms such as "processing," "computing," "calculating," "determining," "displaying," "generating," "identifying," "selecting," "establishing," "receiving," "sending," "transmitting," "updating," "determining," "displaying," or the like, can refer to actions or processes of a machine that manipulates or transforms data or physical devices into other data or physical devices.

[0049] The use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries and regions of the various elements more clearly understood. As used herein, the presence or absence of cross-hatching or shading therefore does not convey or imply any preference or requirement for particular material, material properties, dimensions, proportions, commonality of elements between illustrated elements, or any other characteristic, attribute, property, or the like of the elements. In addition, the size and relative sizes of elements in the drawings can be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific order in the descriptions of processes may

[0050] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intervening elements or layers present. In this regard, the term “connected” can refer to physical or electrical and / or fluid connection with or without intervening elements. Also, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system such as an x-axis, a y-axis, and a z-axis, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any one of X, Y, and Z only, or any combination of any two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ, for example. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms “first”, “second”, etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

[0052] Spatially relative terms such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, “on”, “over”, “higher”, “side” (e.g., as in “sidewall”) and the like, can be used herein for descriptive purposes, and can be interpreted to include different orientations of devices in use, operation, and / or manufacture in addition to the orientation depicted in the figures. For example, if a device is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Moreover, devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "comprise," "have," "contain," and / or "include" are used in the detailed description and / or claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as an open transition term without precluding any additional or other elements. It is also noted that, as used herein, the terms "substantially," "approximately," and other similar terms are used as synonyms for "about," and are intended to have a meaning analogous to "about," specifically within a reasonable amount of deviation that is within the capabilities of ordinary skill in the art.

[0054] As is conventional in the art, some of the example embodiments are described and shown in the attached figures with functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are nothing more than a conceptualization of the electronic (or optical) circuitry (such as logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc.) that is used to physically implement the blocks, units, and / or modules. In the case where the blocks, units, and / or modules are implemented with microprocessors or other similar hardware, they can be programmed and controlled with software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented with dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Additionally, each block, unit, and / or module of some of the example embodiments can be physically separated into two or more interacting and discrete blocks, units, and / or modules without departing from the scope of the inventive concepts. Moreover, blocks, units, and / or modules of some of the example embodiments can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the inventive concepts.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Figure 1 is a block diagram of a display device constructed in accordance with the inventive principles.

[0057] Referring to Figure 1 , the display device 100 can include a display unit 110 (or a display panel), a scan driver 120 (or a gate driver), a data driver 130, a timing controller 140, and a power supply 150 (or a power supply device).

[0058] The display unit 110 can include scan lines SL1 to SLn (n is a positive integer) (or gate lines), data lines DL1 to DLm (m is a positive integer), and pixels PXL. Also, the display unit 110 can include a first power line PL1 and a second power line PL2.

[0059] The pixels PXL can be disposed in an area (e.g., a pixel area) defined by the scan lines SL1 to SLn and the data lines DL1 to DLm.

[0060] Each pixel PXL can be connected to the first power line PL1, the second power line PL2, a corresponding one of the scan lines SL1 to SLn, and a corresponding one of the data lines DL1 to DLm. Hereinafter, the term "connected" includes not only electrical connection but also physical connection, and can include not only direct connection but also indirect connection through another component.

[0061] The pixel PXL can include a light emitting device and at least one transistor for providing a driving current to the light emitting device.

[0062] The pixel PXL can emit light having a luminance corresponding to a data voltage (or a data signal) provided through the data line in response to a scan signal provided through the scan line. For example, the pixel PXL located on the nth row and the mth column can emit light having a luminance corresponding to a data voltage (or a data signal) provided through the mth data line DLm in response to a scan signal provided through the nth scan line SLn.

[0063] The scan driver 120 can generate scan signals based on a scan control signal SCS and sequentially provide the scan signals to the scan lines SL1 to SLn. The scan control signal SCS can include a scan start signal, a scan clock signal, etc., and can be provided from the timing controller 140. For example, the scan driver 120 can include a shift register that sequentially generates and outputs a scan start signal in the form of a pulse (e.g., a pulse having a gate-on voltage level) by using a scan clock signal.

[0064] The data driver 130 can generate a data voltage (or a data signal) based on the image data DATA2 and a data control signal DCS provided from the timing controller 140, and provide the data voltage to the data lines DL1 to DLm. The data control signal DCS can be a signal for controlling the operation of the data driver 130, and include a load signal (or a data enable signal) for indicating the output of a valid data voltage.

[0065] For example, the data driver 130 can generate a data voltage corresponding to a data value (or a gray value) included in the image data DATA2 by using a gamma voltage. The gamma voltage can be generated by the data driver 130, or provided from a separate gamma voltage generation circuit (e.g., a gamma integrated circuit). For example, the data driver 130 can select one of the gamma voltages based on the data value, and output the selected gamma voltage as a data signal.

[0066] The timing controller 140 can receive input image data DATA1 and a control signal CS from the outside (e.g., a graphic processor), and generate a scan control signal SCS and a data control signal DCS based on the control signal CS. The control signal CS can include a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. In addition, the timing controller 140 can generate the image data DATA2 by converting the input image data DATA1. For example, the timing controller 140 can convert the input image data DATA1 to the image data DATA2 having a format available in the data driver 130.

[0067] The power supply 150 can generate a first power voltage VDD to be supplied to the first power line PL1, and generate a second power voltage VSS to be supplied to the second power line PL2. The first power voltage VDD and the second power voltage VSS are voltages required for the operation of the pixels PXL, and the first power voltage VDD can have a voltage level higher than that of the second power voltage VSS. For example, the power supply 150 can be implemented with a power management integrated circuit (PMIC), and convert an input power voltage VIN to each of the first power voltage VDD and the second power voltage VSS by a switching operation performed on a transistor provided therein.

[0068] In addition, the power supply 150 can generate a third power voltage AVDD and provide the third power voltage AVDD to the data driver 130. The third power voltage AVDD is a voltage required to drive the data driver 130 (e.g., to generate a gamma voltage).

[0069] In some example embodiments, the power supply 150 can change one or more of an off-duty (or on-duty) of at least one of the transistors in the power supply 150, a size (or channel capacitance) of at least one of the transistors, a switching frequency of at least one of the transistors, and a slew rate of a switching control signal (or control signal) (such as a gate signal for at least one of the transistors) based on a total current amount flowing through the pixel PXL. The off-duty can represent a ratio of a time in which the transistor is off to a switching period, the switching frequency can represent a number of times per unit time in which the transistor is turned on or off, and the slew rate of the switching control signal can be defined as a gradient and / or a slope at an edge (e.g., a rising edge or a falling edge) of the switching control signal. The slew rate of the switching control signal can be represented as a time (such as a transition delay and / or time) required for a state change between an on state and an off state of the transistor and / or in relation to the time (such as the transition delay and / or time) required for the state change between the on state and the off state of the transistor.

[0070] For example, the power supply 150 can measure a total current amount at at least one selected among a first output terminal through which a first power voltage VDD is output, a second output terminal through which a second power voltage VSS is output, and a third output terminal through which a third power voltage AVDD is output. For example, when the total current amount is less than a first reference current amount (or a first reference current value), the power supply 150 can increase an off-duty of at least one of the transistors in the power supply 150, decrease a channel capacitance and / or a channel capacity of at least one of the transistors, decrease a switching frequency of at least one of the transistors, and increase a slew rate (or decrease a transition time) of at least one of the switching control signals for the transistors. When the slew rate is increased, the transition time can be decreased, and power loss occurring in a transition process of the transistors can be decreased. That is, when a load of the display unit 110 is relatively low, the power supply 150 can decrease a switching operation and decrease power loss due to the switching operation.

[0071] The operation of changing at least one of the off-duty, the channel capacitance, the switching frequency, and the slew rate of the transistors will be described later with reference to FIGS. 10 to 13. Figure 9 The operation of changing at least one of the off-duty, the channel capacitance, the switching frequency, and the slew rate of the transistors will be described later with reference to FIGS. 10 to 13.

[0072] In an exemplary embodiment, the power supply 150 can receive an external clock signal T HCLK from the scan driver 120, and generate a switching control signal for a transistor by using the external clock signal T HCLK. The external clock signal T HCLK can have a frequency corresponding to a frequency of a scan signal provided from the scan driver 120 to the display unit 110. For example, the external clock signal T HCLK can correspond to a horizontal synchronization signal, or can be a scan clock signal (i.e., a clock signal used when the scan driver 120 generates a scan signal). The power supply 150 generates a switching control signal for a transistor by using the external clock signal T HCLK, so that a switching control signal having a more optimized frequency can be generated. Accordingly, it is possible to minimize power consumption (i.e., power consumption caused by switching) of the power supply 150 while not interfering with signals of the scan driver 120.

[0073] Although the case in which the scan driver 120, the data driver 130, and the timing controller 140 are separated from each other has been shown in Figure 1 , this is merely illustrative, and exemplary embodiments are not limited thereto. For example, at least one of the scan driver 120, the data driver 130, and the timing controller 140 can be formed in the display unit 110, or implemented as an IC, and then mounted on a flexible circuit board to be connected to the display unit 110. For example, the scan driver 120 can be formed in the display unit 110. In addition, at least two of the scan driver 120, the data driver 130, and the timing controller 140 can be implemented as a single IC.

[0074] Figure 2 is Figure 1 a circuit diagram of an exemplary embodiment of a representative pixel among pixels of Figure 1 The pixels PXL shown in Figure 2 will be described as an example of the pixel PXL including an nthm pixel PXLnm in an nth row and an mth column.

[0075] Referring to Figure 1 and Figure 2 , the nthm pixel PXLnm can be connected to an nth scan line SLn and an mth data line DLm. In addition, the pixel PXLnm can be connected between a first power line PL1 and a second power line PL2.

[0076] The nth pixel PXLnm can include at least one light emitting device LD, a first transistor T1 (or a driving transistor), a second transistor T2 (or a switching transistor), and a storage capacitor Cst. Each of the first transistor T1 and the second transistor T2 can include a silicon semiconductor, and can be implemented with, for example, a P-type transistor. However, the first transistor T1 and the second transistor T2 are not limited thereto. At least one of the first transistor T1 and the second transistor T2 can include an oxide semiconductor or be implemented with an N-type transistor.

[0077] An anode electrode of the light emitting device LD can be connected to the first power line PL1 through the first transistor T1, and a cathode electrode of the light emitting device LD can be connected to the second power line PL2. The light emitting device LD can generate light having a predetermined brightness corresponding to an amount of a current (or a driving current ID) supplied from the first transistor T1. The light emitting device LD can be configured as an organic light emitting diode (organic LED) or an inorganic LED such as a micro LED or a quantum dot LED. In addition, the light emitting device LD can be a light emitting device made of a combination of an organic material and an inorganic material. In Figure 2 In the above, a case in which the nth pixel PXLnm includes a single light emitting device LD is shown. However, in another exemplary embodiment, the pixel PXLnm can include a plurality of light emitting devices, and the plurality of light emitting devices can be connected in parallel with each other, in series, or in series / parallel.

[0078] A first electrode (or a first transistor electrode) of the first transistor T1 can be connected to the first power line PL1, a second electrode (or a second transistor electrode) of the first transistor T1 can be connected to an anode electrode of the light emitting device LD, and a gate electrode of the first transistor T1 can be connected to a second electrode of the second transistor T2. For example, the first electrode of the first transistor T1 can be a source electrode, and the second electrode of the first transistor T1 can be a drain electrode. However, the exemplary embodiment is not limited thereto. The first transistor T1 can control an amount of the driving current ID flowing through the light emitting device LD in correspondence to a voltage applied to the gate electrode of the first transistor T1. For example, the driving current ID can be proportional to a square of a difference between the first power voltage VDD and a data voltage VDATA (i.e., ID ∝ (VDD - VDATA) 2 ). As such, the driving current ID flowing through each pixel can vary in accordance with the data voltage VDATA, which indicates that the driving current ID can vary in accordance with an image displayed by the display unit 110.

[0079] The first electrode of the second transistor T2 can be connected to the mth data line DLm, the second electrode of the second transistor T2 can be connected to the gate electrode of the first transistor T1, and the gate electrode of the second transistor T2 can be connected to the nth scan line SLn. When a scan signal having a gate-on voltage level is supplied to the nth scan line SLn, the second transistor T2 can be turned on, and a data voltage VDATA can be transmitted from the mth data line DLm to the gate electrode of the first transistor T1.

[0080] The storage capacitor Cst can be formed or connected between the first power line PL1 and the gate electrode of the first transistor T1. The storage capacitor Cst can store a voltage of the gate electrode of the first transistor T1, that is, the data voltage VDATA.

[0081] In Figure 2 , it has been shown that the nthm pixel PXLnm includes the second transistor T2 for transmitting the data voltage VDATA to the inside of the nthm pixel PXLnm, the storage capacitor Cst for storing the data voltage VDATA, and the first transistor T1 for providing a driving current ID corresponding to the data voltage VDATA to the light emitting device LD.

[0082] However, exemplary embodiments are not limited thereto, and various modifications and implementations can be made to the structure of the nthm pixel PXLnm. In an example, the nthm pixel PXLnm can additionally include at least one transistor, such as a transistor for compensating for a threshold voltage of the first transistor T1, a transistor for initializing the gate electrode of the first transistor T1, and / or a transistor for controlling an emission time of the light emitting device LD.

[0083] Figure 3 is Figure 1 a block diagram of an exemplary embodiment of a power supply.

[0084] Referring to Figure 1 and Figure 3 , the power supply 150 can include a sensing circuit 310, a function circuit 320, a frequency generation circuit 330, an oscillation circuit 340, a voltage generation circuit 350, and a driving control circuit 360. In addition, the power supply 150 can further include a clock input terminal IN_C, a power input terminal IN_P, and output terminals OUT1, OUT2, and OUT3. An external clock signal T_HCLK from the scan driver 120 can be applied to the clock input terminal IN_C, an input power voltage VIN can be applied to the power input terminal IN_P, and power voltages VDD, VSS, and AVDD can be output through the output terminals OUT1, OUT2, and OUT3.

[0085] The sensing circuit 310 can measure and / or sense a load of the display unit 110. For example, the sensing circuit 310 can measure a total amount of current flowing through the pixels PXL in the display unit 110. For example, the sensing circuit 310 can sense an amount of current flowing through at least one selected among the output terminals OUT1, OUT2, and OUT3 and the power input terminal IN_P. For example, the sensing circuit 310 can sense an amount of current flowing through the first output terminal OUT1 through which the first power voltage VDD is output, or sense an amount of current flowing through the second output terminal OUT2 through which the second power voltage VSS is output.

[0086] The sensing circuit 310 can output a sensing signal corresponding to the sensed amount of current. The sensing signal can have an analog form or a digital form, but the form of the sensing signal is not limited thereto.

[0087] The function circuit 320 can determine a mode of the frequency generation circuit 330 based on the sensing signal (e.g., the total amount of current). For example, the function circuit 320 can generate a mode control signal for controlling the frequency generation circuit 330 to operate in a first mode or a second mode by comparing the total amount of current with a first reference amount of current (or a first reference current value). For example, when the total amount of current is greater than or equal to the first reference amount of current (i.e., when a load of the display unit 110 is large), the function circuit 320 can select the first mode (e.g., a normal load mode or a heavy load mode). For example, when the total amount of current is less than the first reference amount of current (i.e., when a load of the display unit 110 is small), the function circuit 320 can select the second mode (e.g., a light load mode). Although a case in which the function circuit 320 selects the first mode or the second mode has been described, the exemplary embodiments are not limited thereto. For example, even in the second mode, the function circuit 320 can select the normal load mode or the heavy load mode, etc., according to the total amount of current.

[0088] In the exemplary embodiments, the function circuit 320 can include a first function block SFD1 and a second function block SFD2.

[0089] The first function block SFD1 can control the frequency generation circuit 330 to generate a switching signal by using a predetermined reference clock signal CLK_REF (or a reference switching signal) in the first mode, and generate a first mode control signal for the frequency generation circuit 330. The reference clock signal CLK_REF can be provided from the oscillation circuit 340. The second function block SFD2 can control the frequency generation circuit 330 to generate a switching signal by using an external clock signal T_HCLK provided through a clock input terminal IN_C in the second mode, and generate a second mode control signal for the frequency generation circuit 330.

[0090] Whether each of the first functional block SFD1 and the second functional block SFD2 is to operate can be determined according to whether the external clock signal T_HCLK is to be provided. For example, when the external clock signal T_HCLK is normally applied from the scan driver 120 to the clock input terminal IN_C, the functional circuit 320 can turn on and / or activate the second functional block SFD2, and turn off and / or deactivate the first functional block SFD1. In another example, when the external clock signal T_HCLK is not applied from the scan driver 120 to the clock input terminal IN_C (or when the scan driver 120 and the clock input terminal IN_C are electrically separated from each other), the functional circuit 320 can turn on and / or activate the first functional block SFD1, and turn off and / or deactivate the second functional block SFD2. In some exemplary embodiments, the functional circuit 320 can turn off both the first functional block SFD1 and the second functional block SFD2. It will be described later with reference to FIG. 4 that the functional circuit 320 can determine whether each of the first functional block SFD1 and the second functional block SFD2 is to operate according to whether the external clock signal T_HCLK is to be provided. Figure 15B The set value of the functional circuit 320 is described.

[0091] The frequency generation circuit 330 (e.g., a switching signal generation circuit or a switching clock signal generation circuit) can generate a switching signal (or a switching clock signal) by using one of the reference clock signal CLK_REF and the external clock signal T_HCLK in response to a mode control signal. The mode control signal can be a first mode control signal provided from the first functional block SFD1 or a second mode control signal provided from the second functional block SFD2.

[0092] In some exemplary embodiments, the frequency generation circuit 330 can generate a first switching signal having a first switching frequency in a first mode (or a normal load mode), and generate a second switching signal having a second switching frequency in a second mode (or a light load mode). The second switching frequency is lower than the first switching frequency, and can be set while avoiding the frequency of the external clock signal T_HCLK. For example, a pulse of the second switching signal can have a transition time which does not overlap with a transition time of a pulse of the external clock signal T_HCLK.

[0093] In an exemplary embodiment, the frequency generation circuit 330 can generate the first switching signal having the first switching frequency by using the reference clock signal CLK_REF provided from the oscillation circuit 340 in the first mode.

[0094] For example, when the first mode control signal is provided from the first functional block SFD1, the frequency generation circuit 330 can generate a divided reference clock signal by performing frequency division on the reference clock signal CLK_REF, and generate the first switching signal having the first switching frequency by using the divided reference clock signal. For example, the frequency generation circuit 330 can perform 8-division, 6-division, 4-division, or 3-division on the reference clock signal CLK_REF.

[0095] In an exemplary embodiment, the frequency generation circuit 330 can generate a second switching signal having a second switching frequency by using the external clock signal T_HCLK in the second mode.

[0096] For example, when the second mode control signal is provided from the second function block SFD2, the frequency generation circuit 330 can generate a compensated external clock signal (or a compensated clock signal) by adding a predetermined offset frequency (or offset) to the frequency of the external clock signal T_HCLK in the second mode. For example, the frequency generation circuit 330 can shift the external clock signal T_HCLK by the offset frequency to generate the compensated external clock signal. The frequency generation circuit 330 can generate the second switching signal having the second switching frequency by using the compensated external clock signal.

[0097] The frequency of a reference signal (for example, a reference clock signal CLK_REF or a switching control signal for a transistor in the voltage generation circuit 350) is set to be higher than the frequency of the external clock signal T_HCLK (or the driving frequency of the scan driver 120). For example, in the first mode, the first switching frequency of the first switching signal can be about 1.5 MHz, and the frequency of the driving frequency (for example, a scan frequency or the frequency of the external clock signal T_HCLK) of the scan driver 120 can be 193 KHz. When the frequency generation circuit 330 performs frequency division on the reference clock signal CLK_REF, the first switching frequency of the first switching signal can be reduced, and the power loss of the voltage generation circuit 350 due to switching can be reduced. However, the driving frequency of the scan driver 120 is set differently according to products. Therefore, when the frequency of the divided reference clock signal becomes similar to or equal to the driving frequency of the scan driver 120, interference between the scan driver 120 and the power supply 150 can occur. When the frequency generation circuit 330 generates the compensated external clock signal by adding an offset frequency (for example, ±50 KHz) to the frequency of the external clock signal T_HCLK in the second mode, the compensated external clock signal is set to be different from the driving frequency of the scan driver 120, and can have the lowest frequency. That is, when the compensated external clock signal is generated by using the external clock signal T_HCLK, the power consumption of the power supply 150 can be minimized without generating any interference between the scan driver 120 and the power supply 150 regardless of products.

[0098] The detailed configuration and operation of the frequency generation circuit 330 will be described later with reference to Figure 13 and Figure 14

[0099] ​The oscillation circuit 340 can generate a reference clock signal CLK_REF (or a reference switching signal). The oscillation circuit 340 can be implemented as a general oscillation circuit or a clock generation circuit. In some exemplary embodiments, the oscillation circuit 340 can change a frequency of the reference clock signal CLK_REF. For example, the oscillation circuit 340 can decrease the frequency of the reference clock signal CLK_REF as a load of the display unit 110 decreases.

[0100] The voltage generation circuit 350 can include transistors, and convert the input power voltage VIN into each of the first power voltage VDD, the second power voltage VSS, and the third power voltage AVDD by switching the transistors based on a switching signal provided from the frequency generation circuit 330.

[0101] In some exemplary embodiments, the voltage generation circuit 350 can include a first voltage generator 351, a second voltage generator 352, and a third voltage generator 353. Each of the first voltage generator 351, the second voltage generator 352, and the third voltage generator 353 can be implemented as a DC-DC converter.

[0102] The first voltage generator 351 can convert the input power voltage VIN into the first power voltage VDD. For example, the first voltage generator 351 can be implemented as a boost converter, and generate the first power voltage VDD by increasing a voltage level of the input power voltage VIN. The first voltage generator 351 can generate a switching control signal by using the switching signal, and switch an internal transistor by using the switching control signal. When a frequency of the switching signal changes (e.g., decreases), a frequency of the switching control signal can change (e.g., decrease), and a number of internal transistor switching can change (e.g., decrease). A detailed configuration of the first voltage generator 351 will be described with reference to FIGS. 4A and 4B. Figure 4 A detailed configuration of the first voltage generator 351 will be described with reference to FIGS. 4A and 4B.

[0103] The second voltage generator 352 can convert the input power voltage VIN into the second power voltage VSS. For example, the second voltage generator 352 can be implemented as an inverting buck converter, and generate the second power voltage VSS by decreasing a voltage level of the input power voltage VIN. A detailed configuration of the second voltage generator 352 will be described with reference to FIGS. 5A and 5B. Figure 5 A detailed configuration of the first voltage generator 351 will be described with reference to FIGS. 4A and 4B.

[0104] The third voltage generator 353 can convert the input power voltage VIN into the third power voltage AVDD. For example, similar to the first voltage generator 351, the third voltage generator 353 can be implemented as a boost converter, and generate the third power voltage AVDD by increasing a voltage of the input power voltage VIN.

[0105] The drive control circuit 360 may generate a drive control signal in response to the mode control signal. The drive control signal may be used to change at least one of the cutoff ratio (or driving method) of the internal transistor of the voltage generating circuit 350, the channel capacitance of the internal transistor, and the conversion rate of the switch control signal for the internal transistor. Figure 6 、 Figure 7 and Figure 8 Describe the configuration for changing the cutoff ratio of the transistor, which will be referred to later. Figure 10 Describes the configuration for changing the channel capacitance of the transistor, which will be referred to later. Figure 11 Describes a configuration for changing the slew rate of a switch control signal.

[0106] For example, when the second mode control signal is provided from the second functional block SFD2 (or when the first mode control signal is provided from the first functional block SFD1), the drive control circuit 360 may generate a drive control signal for increasing the off-duty of the internal transistor of the voltage generating circuit 350 (or changing the mode to a drive mode in which the off-duty is relatively large), reducing the channel capacitance of the internal transistor, or increasing the slew rate of the switch control signal for the internal transistor (or reducing the transition time). In another example, when no mode control signal is provided from the functional circuit 320, the drive control circuit 360 may generate a drive control signal for reducing the off-duty of the internal transistor of the voltage generating circuit 350, increasing the channel capacitance of the internal transistor, or reducing the slew rate of the switch control signal for the internal transistor.

[0107] Will refer to it later Figure 15C Described are setting values ​​of a driving control signal (and a mode control signal) for changing at least one of an off-duty of an internal transistor of the voltage generating circuit 350 , a channel capacitance of the internal transistor, and a slew rate of a switching control signal for the internal transistor.

[0108] As reference Figure 3 As described, the power supply 150 can determine the mode of the power supply 150 based on the load of the display unit 110 (for example, the total current of the pixel PXL), and change at least one of the switching frequency of the transistor in the power supply 150, the cutoff ratio (or driving mode) of the transistor, the channel capacitance of the transistor, and the conversion rate of the switching control signal (or gate signal) for the transistor under the determined mode (for example, the second mode).

[0109] In addition, the power supply 150 generates a switching signal (or a switching control signal for a transistor) by using the external clock signal T_HCLK, so that power loss of the power supply 150 can be minimized while not interfering with driving of the scan driver 120 .

[0110] Figure 4is Figure 3 a circuit diagram of an exemplary embodiment of the first voltage generator.

[0111] Referring to Figure 3 and Figure 4 , the first voltage generator 351 can include a switching unit and a first switch controller 351a. The switching unit can include a first inductor L1, a first transistor M1, and a second transistor M2. In addition, the switching unit can further include a first power saving transistor PSM1 and a second power saving transistor PSM2.

[0112] Each of the first transistor M1, the second transistor M2, the first power saving transistor PSM1, and the second power saving transistor PSM2 can include an oxide semiconductor, and can be implemented with an N-type transistor. However, exemplary embodiments are not limited thereto. Each of the first transistor M1, the second transistor M2, the first power saving transistor PSM1, and the second power saving transistor PSM2 can include a silicon semiconductor, and can be implemented with a P-type transistor.

[0113] The first voltage generator 351 can output a first power voltage VDD by converting an input power voltage VIN based on a switching signal S_SW (or a switching clock signal). The input power voltage VIN can be supplied through a power input terminal IN_P, and the first power voltage VDD can be output through a first output terminal OUT1.

[0114] The first inductor L1 can be connected between the power input terminal IN_P and a first node N1. The first power voltage VDD can be controlled based on a first inductor current flowing through the first inductor L1.

[0115] The first transistor M1 can be connected between the first node N1 and a ground (or a reference voltage line to which a reference voltage is applied). The first transistor M1 can be turned on by being applied with a first control signal G1 from the first switch controller 351a, and control a current to flow through the first inductor L1.

[0116] The first power saving transistor PSM1 can be connected in parallel with the first transistor M1. The first power saving transistor PSM1 can be turned on by being applied with a first power saving control signal G11 from the first switch controller 351a, and control a current to flow through the first inductor L1. The first power saving transistor PSM1 can substantially perform the same operation as that of the first transistor M1.

[0117] The first power saving transistor PSM1 can have a size (e.g., channel capacitance) equal to or different from that of the first transistor M1. For example, the first power saving transistor PSM1 can have a size smaller than that of the first transistor M1. The allowable current amount of the first power saving transistor PSM1 can be smaller than that of the first transistor M1. For example, the channel width and / or the channel length of the first power saving transistor PSM1 can be smaller than those of the first transistor M1.

[0118] The second transistor M2 can be connected between the first node N1 and the first output terminal OUT1. The second transistor M2 can be turned on by being applied with the second control signal G2 from the first switch controller 351a. The second transistor M2 can be turned on alternately with the first transistor M1. After an electromotive force is generated in the first inductor L1 when the first transistor M1 is turned on, the second transistor M2 is turned on so that the first node voltage V1 is converted into the first power voltage VDD.

[0119] The second power saving transistor PSM2 can be connected in parallel with the second transistor M2. The second power saving transistor PSM2 can be turned on by being applied with the second power saving control signal G22 from the first switch controller 351a. The second power saving transistor PSM2 can be turned on alternately with the first power saving transistor PSM1. The second power saving transistor PSM2 can substantially perform the same operation as that of the second transistor M2.

[0120] The second power saving transistor PSM2 can have a size (e.g., channel capacitance) equal to or different from that of the second transistor M2. For example, the second power saving transistor PSM2 can have a size smaller than that of the second transistor M2.

[0121] The first switch controller 351a can control the turn-on / off of the first transistor M1, the second transistor M2, the first power saving transistor PSM1, and the second power saving transistor PSM2. The first transistor M1 and the second transistor M2 can be turned on / off alternately under the control of the first switch controller 351a. The first power saving transistor PSM1 and the second power saving transistor PSM2 can be turned on / off alternately under the control of the first switch controller 351a.

[0122] In an exemplary embodiment, the first switch controller 351a can change the switching frequency (or driving frequency) in response to the switching signal S_SW. For example, the first switch controller 351a can change the switching frequency (i.e., the frequency of the first control signal G1 and the second control signal G2) of the first transistor M1 and the second transistor M2 and the switching frequency (i.e., the frequency of the first power saving control signal G11 and the second power saving control signal G22) of the first power saving transistor PSM1 and the second power saving transistor PSM2. For example, the switching frequency in the first mode can be about 1.5 MHz, and the switching frequency in the second mode can be about 500 KHz.

[0123] In an exemplary embodiment, as the load of the display unit 110 (see Figure 1 ) decreases, the switching frequency in the second mode can decrease to a predetermined set value. Accordingly, as the load of the display unit 110 decreases, the switching times of the first power saving transistor PSM1 and the second power saving transistor PSM2 decrease, and power loss caused by transistor switching can be minimized.

[0124] In some exemplary embodiments, the first switch controller 351a can control the total size (or channel capacitance) of the first transistor M1 and the first power saving transistor PSM1 connected in parallel and the total size (or channel capacitance) of the second transistor M2 and the second power saving transistor PSM2 connected in parallel based on the first driving control signal DCS1. The first driving control signal DCS1 can be included in the driving control signal described with reference to Figure 3 FIG. 10, and is provided to the first switch controller 351a from the driving control circuit 360.

[0125] In an exemplary embodiment, the first transistor M1 and the second transistor M2 can operate (i.e., perform switching operations) only in the first mode (or normal load mode), and the first power saving transistor PSM1 and the second power saving transistor PSM2 can operate only in the second mode (or light load mode). For example, in the second mode, the first transistor M1 and the second transistor M2 can maintain an off state in response to the first control signal G1 and the second control signal G2. Also, in the first mode, the first power saving transistor PSM1 and the second power saving transistor PSM2 can maintain an off state in response to the first power saving control signal G11 and the second power saving control signal G22.

[0126] In another exemplary embodiment, the first power saving transistor PSM1 and the second power saving transistor PSM2 can operate in both the first mode and the second mode. For example, in the first mode, the first power saving transistor PSM1 and the second power saving transistor PSM2 can perform switching operations in response to the first power saving control signal G11 and the second power saving control signal G22, and the first transistor M1 and the second transistor M2 can perform switching operations in response to the first control signal G1 and the second control signal G2. In the second mode, the first power saving transistor PSM1 and the second power saving transistor PSM2 can perform switching operations in response to the first power saving control signal G11 and the second power saving control signal G22, and the first transistor M1 and the second transistor M2 can be turned off in response to the first control signal G1 and the second control signal G2.

[0127] When a transistor is switched, power loss can occur due to a parasitic capacitance between electrodes of the transistor. The parasitic capacitance can increase as the size of the transistor increases, and the amount of power loss can also increase according to the increase in the parasitic capacitance. Accordingly, in the second mode, only the first power saving transistor PSM1 and the second power saving transistor PSM2 having a small size are switched, so that power loss can be reduced.

[0128] In an exemplary embodiment, the first switch controller 351a can control the turn-off duty ratio of the transistors M1, M2, PSM1, and PSM2 based on the first driving control signal DCS1. For example, the first switch controller 351a can control the switching unit to operate in a continuous conduction mode (hereinafter, referred to as CCM) (or a first driving method) in the first mode, and to operate in a discontinuous conduction mode (hereinafter, referred to as DCM) (or a second driving method) in the second mode. The DCM driving method and the CCM driving method will be described later with reference to FIGS. 6 and 7. Figure 6 and Figure 7 The DCM driving method and the CCM driving method are described.

[0129] The turn-off duty ratio of the transistors M1, M2, PSM1, and PSM2 in the switching unit operated using the DCM driving method can be greater than the turn-off duty ratio of the transistors M1, M2, PSM1, and PSM2 in the switching unit operated using the CCM driving method. As the turn-off duty ratio of the transistors M1, M2, PSM1, and PSM2 becomes greater, the total switching time decreases, and power loss caused by switching can be reduced.

[0130] In an example embodiment, the first switch controller 351a can change a slew rate (or a transition time) of the control signals G1 and G2 and the power saving control signals G11 and G22 in response to the first drive control signal DCS1. For example, the slew rate of the power saving control signals G11 and G22 in the second mode can be greater than the slew rate of the control signals G1 and G2 in the first mode. In other words, a slope of a rising edge / falling edge of the power saving control signals G11 and G22 in the second mode can be greater than a slope of a rising edge / falling edge of the control signals G1 and G2 in the first mode. The transition time decreases as the slew rate increases, and power loss occurring during the transition can be reduced.

[0131] The third voltage generator 353 included in the power supply 150 shown in Figure 3 may be configured to be substantially the same as or similar to the first voltage generator 351 shown in Figure 4 .

[0132] Figure 5 is a circuit diagram of an example embodiment of the second voltage generator. Figure 3

[0133] Referring to Figure 3 and Figure 5 , the second voltage generator 352 can include a switching unit and a second switch controller 352a. The switching unit can include a second inductor L2, a third transistor M3, and a fourth transistor M4. In addition, the second voltage generator 352 can further include a third power saving transistor PSM3 and a fourth power saving transistor PSM4.

[0134] Each of the third transistor M3, the fourth transistor M4, the third power saving transistor PSM3, and the fourth power saving transistor PSM4 can include an oxide semiconductor, and can be implemented with an N-type transistor.

[0135] The second voltage generator 352 can output a second power supply voltage VSS by converting an input power supply voltage VIN based on a switching signal S_SW (or a switching clock signal). The input power supply voltage VIN can be supplied through a power input terminal IN_P, and the second power supply voltage VSS can be output through a second output terminal OUT2.

[0136] The second inductor L2 can be connected between a second node N2 and a ground. The second power supply voltage VSS can be controlled based on a second inductor current flowing through the second inductor L2.

[0137] ​The third transistor M3 can be connected between the power input terminal IN_P and the second node N2. The third transistor M3 can be turned on by being applied with the third control signal G3 from the second switch controller 352a, and control current to flow through the second inductor L2.

[0138] The third power saving transistor PSM3 can be connected in parallel with the third transistor M3. The third power saving transistor PSM3 can be turned on by being applied with the third power saving control signal G33 from the second switch controller 352a, and control current to flow through the second inductor L2. The third power saving transistor PSM3 can substantially perform the same operation as that of the first transistor M1.

[0139] The third power saving transistor PSM3 can have a size (e.g., channel capacitance) equal to or different from that of the third transistor M3. For example, the third power saving transistor PSM3 can have a size smaller than that of the third transistor M3.

[0140] The fourth transistor M4 can be connected between the second node N2 and the second output terminal OUT2. The fourth transistor M4 can be turned on alternately with the third transistor M3 in response to the fourth control signal G4 supplied from the second switch controller 352a. The fourth transistor M4 is turned on after an electromotive force is generated in the second inductor L2 when the third transistor M3 is turned on. Accordingly, the input power voltage VIN is converted into the second power voltage VSS, and the second power voltage VSS is output through the second output terminal OUT2.

[0141] The fourth power saving transistor PSM4 can be connected in parallel with the fourth transistor M4. The fourth power saving transistor PSM4 can be turned on by being applied with the fourth power saving control signal G44 from the second switch controller 352a. The fourth power saving transistor PSM4 can be turned on alternately with the third power saving transistor PSM3. The fourth power saving transistor PSM4 can substantially perform the same operation as that of the fourth transistor M4.

[0142] The fourth power saving transistor PSM4 can have a size (e.g., channel capacitance) equal to or different from that of the fourth transistor M4. For example, the fourth power saving transistor PSM4 can have a size smaller than that of the fourth transistor M4.

[0143] The second switch controller 352a can control the turn-on / turn-off of the third transistor M3, the fourth transistor M4, the third power saving transistor PSM3, and the fourth power saving transistor PSM4. The third transistor M3 and the fourth transistor M4 can be turned on / turned off alternately under the control of the second switch controller 352a. The third power saving transistor PSM3 and the fourth power saving transistor PSM4 can be turned on / turned off alternately under the control of the second switch controller 352a.

[0144] In an exemplary embodiment, the second switch controller 352a can change the switching frequency (or driving frequency) in response to the switching signal S_SW. For example, the second switch controller 352a can change the switching frequency (i.e., the frequency of the third control signal G3 and the fourth control signal G4) of the third transistor M3 and the fourth transistor M4 and the switching frequency (i.e., the frequency of the third power saving control signal G33 and the fourth power saving control signal G44) of the third power saving transistor PSM3 and the fourth power saving transistor PSM4. For example, the switching frequency in the first mode can be about 1.5 MHz, and the switching frequency in the second mode can be about 500 KHz.

[0145] In some exemplary embodiments, the second switch controller 352a can control the total size (or channel capacitance) of the third transistor M3 and the third power saving transistor PSM3 connected in parallel and the total size (or channel capacitance) of the fourth transistor M4 and the fourth power saving transistor PSM4 connected in parallel based on the second driving control signal DCS2. The second driving control signal DCS2 can be included in the driving control signal described with reference to FIG. 6, and is provided from the driving control circuit 360 to the second switch controller 352a. Figure 3

[0146] In an exemplary embodiment, the third transistor M3 and the fourth transistor M4 can operate (i.e., perform a switching operation) only in the first mode (or normal load mode), and the third power saving transistor PSM3 and the fourth power saving transistor PSM4 can operate only in the second mode (or light load mode). For example, in the second mode, the third transistor M3 and the fourth transistor M4 can maintain an off state in response to the third control signal G3 and the fourth control signal G4. Also, in the first mode, the third power saving transistor PSM3 and the fourth power saving transistor PSM4 can maintain an off state in response to the third power saving control signal G33 and the fourth power saving control signal G44.

[0147] In another exemplary embodiment, the third power saving transistor PSM3 and the fourth power saving transistor PSM4 can operate in both the first mode and the second mode. For example, in the first mode, the third power saving transistor PSM3 and the fourth power saving transistor PSM4 can perform a switching operation in response to the third control signal G33 and the fourth control signal G44, and the third transistor M3 and the fourth transistor M4 can perform a switching operation in response to the third control signal G3 and the fourth control signal G4. In the second mode, the third power saving transistor PSM3 and the fourth power saving transistor PSM4 can perform a switching operation in response to the third power saving control signal G33 and the fourth power saving control signal G44, and the third transistor M3 and the fourth transistor M4 can be off in response to the third control signal G3 and the fourth control signal G4.​

[0148] In an exemplary embodiment, the second switch controller 352a can control the cut-off ratios of the transistors M3, M4, PSM3, and PSM4 based on the second driving control signal DCS2. For example, the second switch controller 352a can control the switch unit to operate in one mode selected from CCM, DCM, and pulse skipping mode (hereinafter referred to as PSM) in the first mode, and control the switch unit to operate by using the PSM driving method in the second mode. Figure 8 Describe the PSM driving method.

[0149] That is, the driving method of the second voltage generator 352 in the first mode may be based on the display unit 110 (see FIG. Figure 1 ) load. In the case of high-brightness driving where the load of the display unit 110 is large, the second voltage generator 352 can output the second power voltage VSS by using the CCM driving method. In the case of medium-brightness driving where the load of the display unit 110 is smaller than a predetermined second reference load, the second voltage generator 352 can output the second power voltage VSS by using the PSM driving method.

[0150] The off-ratio of transistors M3, M4, PSM3, and PSM4 in the switch unit operated by the PSM driving method can be greater than the off-ratio of transistors M3, M4, PSM3, and PSM4 in the switch unit operated by the DCM driving method. As the off-ratio of transistors M3, M4, PSM3, and PSM4 increases, the total switching time is reduced, and the power loss caused by switching can be reduced.

[0151] In an exemplary embodiment, the second switch controller 352a can change the slew rate of the control signals G3 and G4 and the power-saving control signals G33 and G44 in response to the second drive control signal DCS2. For example, the transition time of the power-saving control signals G33 and G44 in the second mode can be shorter than the transition time of the control signals G3 and G4 in the first mode. As the slew rate increases, the transition time is further reduced, and the power loss incurred during the transition process can be reduced.

[0152] Figure 6 yes Figure 4 FIG. 1 is a timing diagram of an exemplary embodiment of signals of a first voltage generator for performing a CCM driving method. Figure 7 yes Figure 4 FIG. 1 is a timing diagram of another exemplary embodiment of signals of a first voltage generator for executing a DCM driving method. Figure 8 yes Figure 4 FIG. 1 is a timing diagram of another exemplary embodiment of signals of the first voltage generator for performing the PSM driving method.

[0153] Referring to Figure 4 , Figure 6 , Figure 7 and Figure 8 , the first voltage generator 351 can operate in the first mode by using the CCM driving method and in the second mode by using the DCM driving method. The second voltage generator 352 can operate in the first mode by using one selected from among the CCM driving method, the DCM driving method, and the PSM driving method and in the second mode by using the PSM driving method. The driving method of the second voltage generator 352 (and the third voltage generator 353) in each mode is substantially the same as or similar to that of the first voltage generator 351 in each mode, and thus, the driving method of the first voltage generator 351 will be mainly described below.

[0154] In the CCM driving method, the first inductor current IL can be generated by alternately turning on the first transistor M1 and the second transistor M2. As shown in Figure 6 , the first transistor M1 and the second transistor M2 can be repeatedly turned on / off in a predetermined switching period T. The switching period T can be determined by the switching signal S_SW described with reference to Figure 4 and Figure 5 . In the switching period T, the on state of the first transistor M1 and the on state of the second transistor M2 can not overlap each other.

[0155] When the first transistor M1 is turned on in the first period P1, the first node voltage V1 of the first node N1 can have a ground level, and the magnitude of the first inductor current IL can increase due to a difference between the voltage of the power input terminal IN_P and the first node voltage V1 of the first node N1.

[0156] When the first transistor M1 is turned off and the second transistor M2 is turned on in the second period P2, the first node voltage V1 of the first node N1 can increase to have a voltage level of the first power voltage VDD, and the magnitude of the first inductor current IL can decrease due to a difference between the voltage of the power input terminal IN_P and the first node voltage V1 of the first node N1. The width of the second period P2 can be equal to that of the first period P1.

[0157] The switching period T can be repeated, and the magnitude of the first inductor current IL can be continuously changed. In the CCM driving method, the output ripple is minimized, and thus, high output stability can be obtained.

[0158] As shown in Figure 7As shown in , the DCM driving method may include a third period P3 (or a first discontinuous period) in which the first transistor M1 and the second transistor M2 are simultaneously turned off in one switching period T. The width of the third period P3 may be smaller than the width of the first period P1 and / or the width of the second period P2.

[0159] In the third period P3, the first node voltage V1 of the first node N1 may have a voltage level of the input power voltage VIN. Since one end of the first inductor L1 is open, the first inductor current IL may maintain a ground level and may not change during the third period P3.

[0160] The amplitude of the first inductor current IL can be smaller than the amplitude of the first inductor current IL in the CCM driving method. For example, the peak value of the first inductor current IL in the DCM driving method can be smaller than the peak value of the first inductor current IL in the CCM driving method. This is because the first period P1 is relatively shortened when the third period P3 is inserted into the same switching cycle T. Similarly, the second period P2 can be relatively shortened.

[0161] like Figure 8 As shown in , the PSM driving method may include a fourth period P4 (or a second discontinuous period) in which the first transistor M1 and the second transistor M2 are simultaneously turned off in one switching period T. The width of the fourth period P4 may be greater than the width of the third period P3. The width of the fourth period P4 may be greater than the total width of the first period P1 and the second period P2.

[0162] In an exemplary embodiment, in the PSM driving method, a portion of the switching cycle may be skipped. The switching cycles of the first transistor M1 and the second transistor M2 may be skipped, and the first inductor current IL may not flow during the skipped switching cycle. Therefore, the magnitude of the first inductor current IL may be smaller than that in the second driving method.

[0163] In the PSM driving method, compared to other driving methods in which the switching operation of the first transistor M1 and the second transistor M2 is performed every cycle, the switching operation of the first transistor M1 and the second transistor M2 is skipped during a predetermined period, thereby reducing the total number of switching times (the number of conduction times) and / or the total switching time. Therefore, the power loss caused by the switching of the first transistor M1 and the second transistor M2 can be improved.

[0164] Figure 9 It shows Figure 3 A diagram of an exemplary embodiment of the power supply for each mode of operation. Figure 10 It shows Figure 4 FIG. 1 is a diagram of an exemplary embodiment of a switching operation of a first voltage generator. Figure 11 isFigure 4 a timing diagram of an exemplary embodiment of one of the control signals used in the first voltage generator.

[0165] Referring to Figure 1 , Figure 3 and Figure 9 , the power supply 150 can operate in the first mode or the second mode based on a load of the display unit 110. For example, when a total amount of current flowing through the pixels PXL in the display unit 110 is greater than or equal to a first reference amount of current (or a first reference current value), the power supply 150 can operate in the first mode (e.g., a normal load mode or a heavy load mode). When the total amount of current is less than the first reference amount of current, the power supply 150 can operate in the second mode (or a light load mode). For example, the first reference amount of current can be equal to an amount of current flowing through the display unit 110 when a brightness of the display unit 110 is 100 nits (or when the brightness of the display unit 110 is equal to a brightness value at a boundary between an intermediate brightness and a low brightness).

[0166] In the first mode and the second mode, a driving method of the power supply 150, a size SIZE (or a channel capacitance) of the internal transistor TR, a switching frequency SW FREQ, and a slew rate SLEW RATE (i.e., a transition time of a switching control signal for the internal transistor TR) can be differently set.

[0167] First, an operation of the power supply 150 in the first mode will be described.

[0168] First, the power supply 150 can generate the first power voltage VDD by allowing the first voltage generator 351 to operate by using the CCM driving method.

[0169] Further, the power supply 150 can generate the second power voltage VSS and the third power voltage AVDD by allowing the second voltage generator 352 and the third voltage generator 353 to operate by using one selected from the CCM driving method, the DCM driving method, and the PSM driving method, respectively. In an exemplary embodiment, the third voltage generator 353 is implemented as a boost converter, similar to the first voltage generator 351. In another exemplary embodiment, the third voltage generator 353 can operate by using a driving method similar to that of the second voltage generator 352. Since the first power voltage VDD generated by the first voltage generator 351 has a direct influence on a driving current ID (see Figure 2 ), a driving method of the first voltage generator 351 can be differently set from driving methods of the second voltage generator 352 and the third voltage generator 353, while the driving method of the second voltage generator 352 and the driving method of the third voltage generator 353 can be similarly set to each other.

[0170] Examples will be described with reference to the accompanying drawings. Figure 3 The function circuit 320 can select one of the CCM driving method, the DCM driving method, and the PSM driving method based on the sensing signal (i.e., the total current amount) in the first mode, and generate a mode control signal including a first set value (or code) corresponding to the selected driving method. The driving control circuit 360 can allow the second voltage generator 352 and the third voltage generator 353 to operate by using the selected driving method.

[0171] Second, the power supply 150 can adjust the size SIZE (or channel capacitance) of the internal transistor TR to be the maximum (e.g., 100%). As described with reference to Figure 4 and Figure 5 The power supply 150 can switch all of the transistors M1, M2, M3, and M4 and the power saving transistors PSM1, PSM2, PSM3, and PSM4, as described with reference to

[0172] Third, the power supply 150 can set the switching frequency SW FREQ to be within a reference frequency range. The highest frequency of the reference frequency range can be about 1.5 MHz, and the lowest frequency of the reference frequency range can be 500 KHz.

[0173] Examples will be described with reference to the accompanying drawings. Figure 3 The function circuit 320 can determine the switching frequency SW FREQ or determine a division value of the reference clock signal CLK_REF based on the sensing signal (i.e., the total current amount) in the first mode, and generate a mode control signal including a third set value (or code) corresponding to the determined switching frequency SW FREQ or the determined division value. For example, the division value can increase as the total current amount decreases. The frequency generation circuit 330 can generate a switching signal (or a switching clock signal) having the determined switching frequency SW FREQ by performing division on the reference clock signal CLK_REF according to the third set value.

[0174] Fourth, the power supply 150 can set the slew rate SLEW to be within a reference slew rate range. For example, the reference slew rate range can be greater than 1 ns and less than or equal to 10 ns. The reference slew rate range can include 1 ns, 3 ns, 5 ns, 10 ns, etc.

[0175] Examples will be described with reference to the accompanying drawings. Figure 3An example is described. Based on the sensing signal in the first mode (i.e., the total current amount), the function circuit 320 can determine the slew rate SLEW, and generate the mode control signal including the fourth set value (or code) corresponding to the determined slew rate SLEW. For example, the transition time according to the slew rate SLEW can decrease as the total current amount decreases. The drive control circuit 360 can control the size of the output terminal (e.g., the size of the output buffer) of each of the first and second switch controllers 351a and 352a to change corresponding to the determined slew rate SLEW. For example, when the transition time according to the slew rate SLEW is set to decrease, the size of the output buffer can increase.

[0176] In the first mode, the power supply 150 can control all circuits (e.g., the voltage generation circuit 350) to operate (all functions are on). This will be described with reference to FIG. 4. Figure 3 An example is described. The function circuit 320 can generate the mode control signal including the fifth set value representing the on / off of each of the circuits in the power supply 150. The circuits directly / indirectly receiving the mode control signal can operate based on the fifth set value.

[0177] Hereinafter, the operation of the power supply 150 in the second mode will be described.

[0178] First, the power supply 150 can generate the first power voltage VDD by allowing the first voltage generator 351 to operate by using the DCM driving method. In addition, the power supply 150 can generate the second power voltage VSS and the third power voltage AVDD by allowing the second and third voltage generators 352 and 353 to operate by using the PSM driving method.

[0179] Second, the power supply 150 can adjust the size of the internal transistor TR to be the minimum (e.g., 17%). This will be described with reference to FIG. 5. Figure 10 An example is described. The power supply 150 can switch all of the first and second transistors M1 and M2 and the first and second power saving transistors PSM1 and PSM2 of the first voltage generator 351 in the first mode, or switch only the first and second power saving transistors PSM1 and PSM2 of the first voltage generator 351 in the second mode while keeping the first and second transistors M1 and M2 of the first voltage generator 351 in the off state. Similarly, the power supply 150 can switch all of the third and fourth transistors M3 and M4 and the third and fourth power saving transistors PSM3 and PSM4 of the second voltage generator 352 in the first mode, or switch only the third and fourth power saving transistors PSM3 and PSM4 of the second voltage generator 352 in the second mode.

[0180] Third, the power supply 150 can set the switching frequency SW FREQ to have a second lowest frequency. For example, the second lowest frequency can be 500 KHz.

[0181] Examples will be described with reference to Figure 3 The first function block SFD1 can select a maximum division value (e.g., 8-division) among a plurality of division values in the first mode. The frequency generation circuit 330 can generate a switching signal (or a switching clock signal) having a second lowest frequency by performing division on the reference clock signal CLK_REF using the maximum division value. In another example, the second function block SFD2 can determine an offset frequency. The frequency generation circuit 330 can generate a switching signal (or a switching clock signal) having a second lowest frequency by adding the offset frequency to the external clock signal T_HCLK. In this case, the switching signal can have the second lowest frequency while avoiding interfering with a driving frequency of the scan driver 120. For example, the switching signal can include a pulse having the second lowest frequency (such as the same frequency as the external clock signal T_HCLK) and having a transition time that does not overlap with a transition time of a pulse of the external clock signal T_HCLK.

[0182] Fourth, the power supply 150 can set the slew rate SLEW such that a transition time according to the slew rate SLEW becomes the smallest. For example, the smallest transition time can be 0.9 ns, 0.8 ns, 0.7 ns, etc. Examples will be described with reference to Figure 4 and Figure 11 Examples will be described with reference to the first voltage generator 351. The first power saving control signal G11 (or the third power saving control signal G33 (see Figure 5 )) in the second mode can become smaller than a transition time of the first power saving control signal G11 (or the third power saving control signal G33) in the first mode.

[0183] The drive control circuit 360 can set a size (e.g., a size of an output buffer) of an output terminal of each of the first and second switch controllers 351a and 352a to be the largest in the second mode.

[0184] In the second mode, the power supply 150 can turn off some (partially turn off) of the circuits (e.g., the voltage generation circuit 350).

[0185] For example, the power supply 150 can partially turn off (or partially turn off) the third voltage generator 353 in the second mode.

[0186] As described above with reference to Figure 9As described, the power supply 150 operates in a plurality of modes (e.g., the first mode and the second mode) based on a load of the display unit 110. In the plurality of modes (e.g., the first mode and the second mode), a driving method, a size SIZE (or a channel capacitance) of the internal transistor TR, a switching frequency SW FREQ, and a slew rate SLEW RATE (i.e., a transition time of a switching control signal for the internal transistor TR) of the power supply 150 can be differently set.

[0187] Specifically, in the second mode, the power supply 150 allows the first voltage generator 351 to operate by using the DCM driving method in which an off duty ratio of the internal transistor TR is relatively large, and allows the second voltage generator 352 and the third voltage generator 353 to operate by using the PSM driving method, so that power loss caused by switching can be reduced. In addition, in the second mode, the power supply 150 sets the size SIZE (or the channel capacitance) of the internal transistor TR to be the smallest, so that power loss caused by a parasitic capacitance can be reduced. Further, in the second mode, the power supply 150 sets the frequency of the switching signal to be the lowest by adding an offset frequency to the external clock signal T_HCLK, and sets the transition time of the control signal for the internal transistor TR to be the smallest, so that power loss caused by switching can be reduced. According to an embodiment, in the second mode, when at least one of the above-described operations of the power supply 150 is implemented, power loss of the power supply 150 can be reduced.

[0188] Figure 12 is a graph showing a relationship between a switching frequency of a switching signal generated in a frequency generation circuit of Figure 3 .

[0189] Referring to Figure 1 , Figure 3 and Figure 12 , the external clock signal T_HCLK conforms to a driving frequency (or a scan frequency) of the scan driver 120, and can be, for example, about 193 KHz. A period T of the external clock signal T_HCLK can be about 5.16 µs.

[0190] A reference frequency Main Freq. of the reference clock signal CLK_REF can be variously changed. For example, as shown in Figure 12 , the reference frequency can be changed at intervals of 0.03 MHz between 1.26 MHz and 1.71 MHz.

[0191] When the frequency generation circuit 330 generates the switching signal by performing 8-division on the reference clock signal CLK_REF, the frequency of the switching signal (i.e., 8-division frequency 1 / 8Freq.) can change between about 0.1575 MHz (or about 157.5 KHz) and about 0.21375 MHz at intervals of 3.75 KHz. The period of the switching signal can change between about 6.349206 μs and about 4.678363 μs at intervals of about 0.14 μs.

[0192] When the frequency of the switching signal is located between about 0.18 MHz and 0.2025 MHz, flicker can occur in the display unit 110. For example, when the frequency of the switching signal is in the range of about -130 KHz to about +90 KHz or in the range of about -7% to about +5% with respect to the frequency of the external clock signal T_HCLK, interference between the scan driver 120 and the power supply 150 can occur.

[0193] The frequency generation circuit 330 can generate a switching signal that can minimize power consumption without causing any interference to the scan driver 120 by adding an offset frequency (e.g., ±50 KHz, ±100 KHz, ±150 KHz, or ±200 KHz) to the external clock signal T_HCLK.

[0194] Figure 13 is a block diagram of an exemplary embodiment of a frequency generation circuit. Figure 3

[0195] Referring to Figure 3 and Figure 13 , the frequency generation circuit 330 can include a frequency divider 331, a clock processor 332, a selector 333, and a switching signal generator 334.

[0196] The frequency divider 331 can generate a divided reference clock signal by performing division on the reference clock signal CLK_REF in response to a first mode control signal provided from a first function block SFD1.

[0197] As described above, the first mode control signal can include a set value corresponding to a division value, and the frequency divider 331 can perform division on the reference clock signal using the division value. For example, the division value can correspond to 8-division, 4-division, 3-division, etc.

[0198] In some exemplary embodiments, the frequency divider 331 can perform division on the reference clock signal CLK_REF in response to a second mode control signal (i.e., a second mode control signal including a division value) provided from a second function block SFD2.

[0199] ​The clock processor 332 can generate the compensated external clock signal by adding an offset frequency to a frequency of the external clock signal T_HCLK in response to a second mode control signal provided from the second function block SFD2.

[0200] As described above, the second mode control signal can include a set value corresponding to the offset frequency, and the clock processor 332 can generate the compensated external clock signal by selecting an offset frequency corresponding to the set value among a plurality of offset frequencies. The offset frequencies can include ±50 KHz, ±100 KHz, ±150 KHz, and ±200 KHz. For example, the clock processor 332 can be configured as a delay circuit, and generate the compensated external clock signal by sequentially delaying pulses of the external clock signal T_HCLK by a time corresponding to the offset frequency.

[0201] The selector 333 can select and output one selected from among the reference clock signal CLK_REF, the divided reference clock signal, and the compensated external clock signal in response to a first mode control signal provided from the first function block SFD1 and a second mode control signal provided from the second function block SFD2.

[0202] For example, when the first mode control signal includes a division value, the selector 333 can output the divided reference clock signal. For example, when the second mode control signal includes a set value corresponding to the offset frequency, the selector 333 can output the compensated external clock signal. For example, when the first mode control signal and the second mode control signal do not include a valid value related to the switching frequency, the selector 333 can output the reference clock CLK_REF.

[0203] The switching signal generator 334 can output a switching signal based on the output signal provided from the selector 333. For example, the switching signal generator 334 can output the output signal provided from the selector 333 as the switching signal. For example, the switching signal generator 334 can be configured as a buffer. In some exemplary embodiments, the switching signal generator 334 can be omitted.

[0204] The frequency generation circuit 330 can individually sense a scan frequency (e.g., a phase of a scan signal or a change in the phase) of the scan driver 120, and generate a switching signal having a switching frequency different from the sensed scan frequency based on the scan frequency. However, the configuration of the frequency generation circuit 330 that senses the scan frequency can be complex. On the other hand, the frequency generation circuit 330 uses a method of individually receiving the external clock signal T_HCLK and adding an offset frequency to a frequency of the external clock signal T_HCLK. Accordingly, the frequency generation circuit 330 can generate the switching signal while having a simple structure.

[0205] Figure 14 is shownFigure 3 FIG2 is a diagram of an exemplary embodiment of the functional circuitry and operation of a frequency generation circuit.

[0206] Reference Figure 1 、 Figure 3 and Figure 14 , the functional circuit 320 may determine the mode MODE based on the total current amount I_EL of the display unit 110 .

[0207] like Figure 14 As shown in FIG, at the first time t1, the total current amount I_EL may be greater than the second reference current value I_REF2. The functional circuit 320 may prepare for a mode change from the second mode (or light load mode) to the first mode (or heavy load mode).

[0208] In an exemplary embodiment, the functional circuit 320 may perform a mode change from the second mode to the first mode after a debounce time T_DEB has elapsed since the first time t1 (i.e., at a second time t2). For example, the debounce time T_DEB may be set to approximately 100 μs, approximately 300 μs, approximately 500 μs, approximately 1000 μs, etc. By setting the debounce time T_DEB, frequent mode changes can be prevented.

[0209] The mode signal SFD_ENB indicating on / off of the first mode may be changed from a logic low level (ie, an off state of the first mode) to a logic high level (ie, an on state of the first mode) at the second time t2 .

[0210] In the first mode, the mode control signal for the first mode may be provided from the first functional block SFD1 or the second functional block SFD2 to the frequency generating circuit 330, and the frequency generating circuit 330 may generate the first mode frequency by using the internal signal INTERNAL (ie, the reference clock signal CLK_REF (see Figure 3 )) to generate a switching signal. For example, in the first mode, the switching frequency of the switching signal may be about 1.5 MHz.

[0211] At the third time t3, the total current amount I_EL may become less than the first reference current value I_REF1. The functional circuit 320 may prepare for a mode change from the first mode to the second mode. The first reference current value I_REF1 may be smaller than the second reference current value I_REF2 by a predetermined value. The interval between the first reference current value I_REF1 and the second reference current value I_REF2 may be defined as a hysteresis interval R_HYS, and no mode change may be performed during the hysteresis interval R_HYS. When the hysteresis interval R_HYS is set, frequent mode changes can be prevented.

[0212] Similar to the second time t2, the functional circuit 320 can perform the mode change from the first mode to the second mode at a time (i.e., a fourth time t4) after the de-bounce time T_DEB from a third time t3. The mode signal SFD_ENB can change from the logic high level (i.e., the on state of the first mode) to the logic low level (i.e., the off state of the first mode) at the fourth time t4.

[0213] For example, in the second mode, when the first mode control signal related to the second mode is provided to the frequency generation circuit 330 from the first functional block SFD1, the frequency generation circuit 330 can generate the switching signal by using the internal signal INTERNAL (i.e., the reference clock signal CLK_REF). For example, in the second mode, the switching frequency of the switching signal can be about 500 KHz.

[0214] In another example, in the second mode, when the second mode control signal related to the second mode is provided to the frequency generation circuit 330 from the second functional block SFD2, the frequency generation circuit 330 can generate the switching signal by using the external signal EXTERNAL (i.e., the external clock signal T_HCLK (see Figure 3 ). For example, the frequency generation circuit 330 can generate the switching signal by adding an offset frequency to the frequency of the external clock signal T_HCLK. For example, the offset frequency can be about ±50 KHz.

[0215] As described with reference to Figure 14 , the functional circuit 320 can prevent the mode change between the first mode and the second mode from frequently occurring by using the de-bounce time T_DEB and the hysteresis interval R_HYS.

[0216] Figure 15A , Figure 15B and Figure 15C are graphs of exemplary embodiments of the register set values for the power supply of Figure 3 .

[0217] With reference to Figure 1 , Figure 3 , Figure 15A , Figure 15B and Figure 15C , the functional circuit 320 of the power supply 150 can store the register set values.

[0218] The register setting values ​​may include a setting value SFD_Transistion_Level for mode change, a setting value SFD_Hys_Level for the hysteresis interval R_HYS, a setting value SFD_Decounce_time for the de-bounce time T_DEB, a setting value SFD_Mode for function block activation, a setting value SFD_Function for the function changed according to the mode control signal, a setting value SFD_Block for the output block, a first setting value SFD1_Freq for the switching frequency, and a second setting value SFD2_Freq for the switching frequency.

[0219] The setting value SFD_Transistion_Level for mode change is a setting value for the load of the display unit 110, which becomes a reference for the change from the first mode to the second mode. That is, the setting value SFD_Transission_level for mode change can be the first reference current amount (or the first reference current value I_REF1 (see Figure 14 The value of )) is defined as a reference in which the second mode (eg, sequential frequency drive (SFD)) is turned on (or activated) or turned off (or deactivated).

[0220] Reference Figure 15B As shown in the first table TABLE 1, the set value SFD_Transition_Level for mode change can be represented by 2 bits. For example, the set value SFD_Transition_Level for mode change can be set to one of 20mA, 30mA, 40mA, and 50mA. However, this is merely illustrative, and the set value SFD_Transition_Level for mode change can be represented by 3 bits or more, which can be set in various ways.

[0221] For example, the set value SFD_Transition_Level for mode change may be set by external input during the manufacturing process of the display device 100. The set value SFD_Transition_Level for mode change may be set in proportion to the maximum load of the display unit 110. In another example, when the mode change between the second mode and the first mode occurs frequently (for example, when the number of mode transitions between the second mode and the first mode occurring for a specific time exceeds a predetermined number of times), the set value SFD_Transition_Level for mode change may be updated to have a smaller value (for example, the set value may be changed from 11 to 10).

[0222] The set value SFD_Hys_Level for the hysteresis interval R_HYS is for referenceFigure 14 That is, the set value SFD_Hys_Level for the hysteresis interval R_HYS may define a hysteresis value maintained in the second mode (or SFD operation) according to the load of the display unit 110 .

[0223] 15 , the set value SFD_Hys_Level for the hysteresis interval R_HYS can be represented by 2 bits. For example, the set value SFD_Hys_Level for the hysteresis interval R_HYS can be set to one of 5 mA, 10 mA, and 15 mA. However, this is merely illustrative, and the set value SFD_Hys_Level for the hysteresis interval R_HYS can be set to more different values.

[0224] For example, the set value SFD_Hys_Level for the hysteresis interval R_HYS may be set by external input during the manufacturing process of the display device 100. In another example, when the mode change between the second mode and the first mode occurs frequently (for example, when the number of mode transitions between the second mode and the first mode occurs for a specific time exceeds a predetermined number of times), the set value SFD_Hys_Level for the hysteresis interval R_HYS may be updated to have a larger value (for example, the set value may be changed from 00 to 01).

[0225] The setting value SFD_Decounce_time for the debounce time T_DEB is for reference Figure 14 That is, the set value SFD_Decounce_time for the debouncing time T_DEB may define the time from when the second mode (or SFD operation) is determined to when the second mode (or SFD operation) is applied according to the load of the display unit 110 .

[0226] Reference Figure 15B As shown in the third table TABLE3, the set value SFD_Decounce_time for the de-jitter time T_DEB can be represented by 2 bits. For example, the set value SFD_Decounce_time for the de-jitter time T_DEB can be set to one of 100 μs, 300 μs, 500 μs, and 1000 μs. However, this is merely illustrative, and the set value SFD_Decounce_time for the de-jitter time T_DEB can be set to more different values.

[0227] For example, the set value SFD_Decounce_time for the de-bounce time T_DEB can be set through external input during a manufacturing process of the display device 100. In another example, when mode conversion between the second mode and the first mode frequently occurs (e.g., when the number of times that mode conversion between the second mode and the first mode occurs for a certain time exceeds a predetermined number of times), the set value SFD_Decounce_time for the de-bounce time T_DEB can be updated to have a greater value (e.g., the set value can change from 00 to 01).

[0228] The set value SFD_Mode for the function block activation can be a set value for an activated function block selected from the function blocks SFD1 and SFD2 in the function circuit 320.

[0229] Referring to a fourth table TABLE4 shown in FIG. 4, Figure 15B The set value SFD_Mode for the function block activation can be represented with 2 bits, referring to the fourth table TABLE4 shown in FIG. 4. For example, the set value SFD_Mode for the function block activation can include activation of the first function block SFD1, activation of the second function block SFD2, and function block deactivation SFD OFF.

[0230] For example, the set value SFD_Mode for the function block activation can be set through external input during a manufacturing process of the display device 100. In another example, when the external clock signal T_HCLK is input to the power supply 150, the set value SFD_Mode for the function block activation can be set to 01. When the external clock signal T_HCLK is not input to the power supply 150 or when input of the external clock signal T_HCLK is suspended, the set value SFD_Mode for the function block activation can be set to 00 or updated.

[0231] The set value SFD_Function for the function changed according to the mode control signal can be a set value for whether to perform a function of changing a switching frequency, a slew rate, a size of a transistor, a driving mode (i.e., a driving mode of the voltage generators 351, 352, and 353).

[0232] Referring to a fourth table TABLE4 shown in FIG. 4, Figure 15CThe set value SFD_Function for the function changed according to the mode control signal can be represented with 3 bits, for example, as shown in the fifth table TABLE 5. For example, the set value SFD_Function for the function changed according to the mode control signal can be set to one of only selecting a function of changing a frequency (Frequency only), only selecting a function of changing a slew rate (Slew rate only), only selecting a function of changing a size of a transistor (TR size only), only selecting a function of changing a driving mode (Driving Mode only), only selecting a function of not changing a slew rate (Slew rate off) (i.e., selecting functions of changing a frequency, changing a size of a transistor, and changing a driving mode), only selecting a function of not changing a size of a transistor (TR size off), only selecting a function of not changing a driving mode (Driving Mode off), and selecting all functions (All on). However, this is merely illustrative, and the set value SFD_Function for the function changed according to the mode control signal can be represented with 4 bits or more, which can be more variously set.

[0233] For example, the set value SFD_Function for the function changed according to the mode control signal can be included in the mode control signal generated by the function circuit 320, and is provided to the frequency generation circuit 330 and the driving control circuit 360. For example, when the set value SFD_Function for the function changed according to the mode control signal includes one of 000, 100, 101, 110, and 111, the frequency generation circuit 330 can change a switching frequency of a switching signal. In another example, when the set value SFD_Function for the function changed according to the mode control signal includes 001, the driving control circuit 360 can change only a slew rate of a control signal for a transistor in the voltage generation circuit 350.

[0234] The set value SFD_Block for the output block is a selection value for the output block controlled according to the mode control signal (or under the SFD operation), and is defined as a selection value for at least one of the first voltage generator 351, the second voltage generator 352, and the third voltage generator 353.

[0235] Referring to Figure 15CThe sixth table TABLE 6 shown in FIG. 12, the set value SFD_Block for the output block can be expressed with 3 bits. For example, the set value SFD_Block for the output block can be set to one of only selecting the first voltage generator 351 (VO1 only), only selecting the second voltage generator 352 (VO2 only), only selecting the third voltage generator 353 (VO3 only), selecting the first voltage generator 351 and the second voltage generator 352 (VO1 / VO2 only), selecting the second voltage generator 352 and the third voltage generator 353 (VO2 / VO3 only), and selecting all of the voltage generators 351, 352, and 353 (all on).

[0236] For example, the set value SFD_Block for the output block can be included in the mode control signal generated by the function circuit 320, and provided to the driving control circuit 360. For example, when the set value SFD_Block for the output block includes 000, the driving control circuit 360 can apply the set value SFD_Block for the output block to only the first voltage generator 351.

[0237] The first set value SFD1_Freq for the switching frequency can be defined as information on the switching frequency provided from the first function block SFD1.

[0238] Referring to Figure 15C The seventh table TABLE 7 shown in FIG. 13, the first set value SFD1_Freq for the switching frequency can be expressed with 2 bits. For example, the first set value SFD1_Freq for the switching frequency can be set to one of 1 MHz, 500 KHz, 300 KHz, and 250 KHz. This is merely illustrative, and the first set value SFD1_Freq for the switching frequency can be expressed with 3 bits or more, which can be more variously set.

[0239] For example, the first set value SFD1_Freq for the switching frequency can be included in the mode control signal output from the function circuit 320, and provided to the frequency generation circuit 330. For example, when the first set value SFD1_Freq for the switching frequency includes 11, the frequency generation circuit 330 can generate a switching signal having a switching frequency of 250 KHz by performing 6-division on a reference clock signal CLK_REF (for example, 1.5 MHz).

[0240] The second set value SFD2_Freq for the switching frequency can be defined as information on the offset frequency provided from the second function block SFD2.

[0241] Referring to Figure 15CThe second set value SFD2_Freq for the switching frequency can be expressed with 2 bits, as shown in the eighth table TABLE8. For example, the second set value SFD2_Freq for the switching frequency can be set to one of ±50KHz, ±100KHz, ±150KHz, and ±200KHz. However, this is merely illustrative, and the second set value SFD2_Freq for the switching frequency can be expressed with 3 bits or more, which can be more variously set.

[0242] For example, the second set value SFD2_Freq for the switching frequency can be included in the mode control signal output from the function circuit 320 (or the second mode control signal output from the second function block SFD2), and provided to the frequency generation circuit 330. For example, when the second set value SFD2_Freq for the switching frequency includes 00, the frequency generation circuit 330 can generate a switching signal having a switching frequency of, for example, 243KHz by adding an offset frequency of ±50KHz to the external clock signal T_HCLK (for example, 193KHz).

[0243] As described with reference to Figure 15A , Figure 15B and Figure 15C , the register set value is stored in the power supply 150, and can be set in the manufacturing process of the display device 100 or included in the mode control signal of the function circuit 320. Accordingly, the efficiency of the power supply 150 can be further improved by various combinations of the register set value.

[0244] Figure 16 is a graph showing the efficiency of the power supply of Figure 3 . In Figure 16 , the horizontal axis represents the total current amount I_EL, and the vertical axis represents the current efficiency of the power supply in percentage units.

[0245] With reference to Figure 3 , Figure 9 and Figure 16 , the first curve C_NORMAL represents the efficiency of the power supply according to the total current amount I_EL of the power supply operating only in the first mode according to the comparative example. The second curve C_SFD represents the efficiency of the power supply 150 according to the total current amount I_EL of the power supply 150 performing the change between the first mode and the second mode. According to the total current amount I_EL, the difference graph G_DIFF can represent the efficiency difference between the efficiency of the power supply 150 and the efficiency of the power supply according to the comparative example.

[0246] As described above, as the total current I_EL decreases, the efficiency of the power supply 150 decreases, and the power loss rate of the power supply 150 increases. For example, according to the first curve C_NORMAL, when the total current I_EL is 30 mA, the efficiency of the power supply according to the comparative example can be approximately 86%. As the total current I_EL decreases, the efficiency decreases. When the total current I_EL is 2 mA, the efficiency can be reduced to approximately 46%.

[0247] The power supply 150 changes at least one of a driving mode, a size of a transistor, a switching frequency, and a slew rate in the second mode, so that efficiency of the power supply 150 may be represented as higher than that of the power supply according to the comparative example.

[0248] According to the second curve C_SFD, when the total current I_EL is 30 mA, the power supply 150 can operate in the second mode, and the efficiency of the power supply 150 can be approximately 89%. In other words, the efficiency of the power supply 150 can be approximately 3.0% higher than the efficiency of the power supply according to the comparative example. Although the efficiency of the power supply 150 decreases as the total current I_EL decreases, the efficiency difference between the efficiency of the power supply 150 and the efficiency of the power supply according to the comparative example can increase as the total current I_EL decreases. When the total current I_EL is 2 mA, the efficiency of the power supply 150 decreases to approximately 58.4%, but can be approximately 12.4% higher than the efficiency of the power supply according to the comparative example.

[0249] That is, the power supply 150 changes at least one of the driving mode, the size of the transistor, the switching frequency, and the slew rate in the second mode. Specifically, the power supply 150 sets the switching frequency and changes the slew rate by using the external clock signal T_HCLK, so that the efficiency of the power supply 150 can be further improved than that of the power supply according to the comparative example.

[0250] Furthermore, the power supply 150 sets an optimal switching frequency by using the external clock signal T_HCLK, thereby minimizing power loss without any interference between the power supply 150 and the scan driver 120 , ie, minimizing power loss while maintaining display quality.

[0251] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, comprising: A display panel comprising a scan line, a first power line, a second power line, and pixels connected to the scan line, the first power line, and the second power line; a gate driver that sequentially supplies scan signals to the scan lines based on a clock signal; as well as a power supply including a plurality of transistors that converts an input power voltage into a first power voltage through switching operations of the plurality of transistors and supplies the first power voltage to the first power line through a first output terminal, Wherein, in response to an amount of current flowing through the pixel that is less than a first reference current amount, the power supply is configured to perform one or more of increasing an off-time ratio of at least one transistor among the multiple transistors, reducing a channel capacitance of at least one transistor among the multiple transistors, reducing a switching frequency of at least one transistor among the multiple transistors, and increasing a conversion rate of at least one control signal among the control signals for the multiple transistors.

2. The display device according to claim 1, wherein The power supply comprises: a frequency generating circuit for generating a switching signal having a first switching frequency in a first mode and generating the switching signal having a second switching frequency in a second mode; a first voltage generating circuit comprising the plurality of transistors, generating the first power voltage in response to the switching signal; a sensing circuit that senses the amount of current by measuring a current at the first output terminal; and a functional circuit that generates a mode control signal to control the frequency generating circuit to operate in the first mode or the second mode by comparing the current amount with the first reference current amount, and The second switching frequency is lower than the first switching frequency and is set to avoid the frequency of the clock signal.

3. The display device according to claim 2, wherein: The power supply further includes an oscillation circuit that generates a reference clock signal having a reference frequency, and The frequency generating circuit is configured to generate the switching signal by performing frequency division on the reference clock signal in the first mode.

4. The display device according to claim 2, wherein The power supply is configured to receive the clock signal through a clock signal input terminal, and The frequency generating circuit is configured to shift the clock signal by an offset frequency to generate the switching signal in the second mode.

5. The display device according to claim 4, wherein The power supply further includes an oscillation circuit that generates a reference clock signal having a reference frequency, and The frequency generating circuit is configured to generate the switching signal based on the reference clock signal in the first mode. The display device according to claim 5 , wherein: The frequency generating circuit comprises: a frequency divider generating a divided reference clock signal by performing frequency division on the reference clock signal in response to a first mode control signal generated by the functional circuit; a clock processor that generates a compensated clock signal by shifting the clock signal by the offset frequency in response to a second mode control signal generated by the functional circuit; and The selector outputs one selected from among the reference clock signal, the divided reference clock signal, and the compensation clock signal as the switching signal in response to the first mode control signal or the second mode control signal.

7. The display device according to claim 6, wherein: The clock processor is configured to generate the compensated clock signal by delaying pulses of the clock signal.

8. The display device according to claim 2, wherein: The functional circuit is configured as follows: When the current amount becomes smaller than the first reference current amount, performing a mode change from the first mode to the second mode; and When the current amount becomes greater than a second reference current amount, a mode change from the second mode to the first mode is performed, and The second reference current is greater than the first reference current.

9. The display device according to claim 8, wherein The functional circuit is configured to perform the mode change from the first mode to the second mode after a predetermined debounce time has elapsed from a time when the current amount becomes smaller than the first reference current amount.

10. A power supply for outputting a power voltage through an output terminal, the power supply comprising: Input terminal, receiving clock signal; a sensing circuit for measuring the amount of current at the output terminal; a functional circuit that generates a first mode control signal or a second mode control signal by comparing the current amount with a reference current amount; an oscillation circuit for generating a reference clock signal having a reference frequency; a frequency generating circuit that generates a switching signal by performing frequency division on the reference clock signal in response to the first mode control signal, or generates the switching signal by shifting the clock signal by an offset frequency in response to the second mode control signal; as well as a voltage generating circuit including a plurality of transistors, converting an input power voltage into the power voltage by switching the plurality of transistors in response to the switching signal, The switching frequency of the switching signal is set to avoid the frequency of the clock signal.

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