System and method for processing input / output requests

Abstract

Systems and methods are disclosed for processing input / output requests by which storage devices can process I / O commands in the order in which the I / O commands are provided by a host and return the I / O commands to the host, thereby reducing host overhead, the methods including, but not limited to, the steps of: receiving a first I / O command and a second I / O command, the first I / O command and the second I / O command being assigned sequence tags; issuing the first I / O command and the second I / O command to one or more storage channels based on the respective sequence tags of the first I / O command and the second I / O command; collecting a command completion notification for the first I / O command or the second I / O command when the first I / O command or the second I / O command has been completed, respectively; and issuing the command completion notification to the host based on the associated sequence tag of the completed first I / O command or the completed second I / O command.

Description

Technical Field

[0001] This disclosure relates to methods and systems for orderly I / O command management between a host system and a storage device. Background Technology

[0002] The following background information is intended only to provide the information necessary for understanding the inventive ideas and concepts disclosed herein. Therefore, this background section may contain patentable subject matter and should not be considered a disclosure of prior art.

[0003] From the perspective of a storage device, there is generally no guarantee that a given I / O command will be executed before any other given I / O command. There are several reasons for this, but three important ones are noteworthy: First, I / O commands may have different sizes and complexities (e.g., small writes are generally faster than large writes, and for some media, reads are much faster than writes); second, there are multiple internal channels for processing commands, each associated with the storage medium in the storage device, and each channel has a processing queue independent of the host's processing queue (e.g., multiple channels to multiple NAND flash chips, each individual channel serving a specific physical address); third, some storage devices have background operations that occupy one or more internal processing channels at unpredictable time intervals (e.g., garbage collection in NAND flash).

[0004] When utilizing storage systems, write consistency is often a fundamental property that should be maintained. For example, when a computer system requests to write data first and then read data in that order, the system should ensure that commands are actually processed in that order. Otherwise, if a read command is executed before a write command, the read command will return incorrect (old) data. As another example, if an older write request is processed after a newer write request, an illegal overwrite will occur, and the data recorded on the device will be incorrect. This management problem is amplified if multiple applications are allowed to access the same data, and if there are multiple queues through which the host can issue I / O commands.

[0005] Therefore, a mechanism is desired to enhance the storage device's ability to manage write scheduling. Summary of the Invention

[0006] Embodiments of the concepts disclosed herein relate to systems and methods by which a computing system (more specifically, a storage device) can sequentially execute I / O command processing and notifications with minimal host operation. Some embodiments may include and use sequence tag generator logic to provide sequence tags to I / O commands. Some embodiments may include command processor logic for initiating I / O command processing in an order dependent on the sequence tags of the I / O commands. Some embodiments may include notification logic configured to coalesce I / O command notifications and return them to the host in the order of the sequence tags of the I / O commands.

[0007] According to an example embodiment, a method is provided for sequentially processing I / O requests by a storage device, the method comprising: receiving a first I / O command and a second I / O command, the first I / O command and the second I / O command being assigned sequence tags; issuing the first I / O command and the second I / O command to one or more storage channels based on their respective sequence tags; collecting command completion notifications for the first I / O command or the second I / O command when the first I / O command or the second I / O command has been completed respectively; and issuing a command completion notification to a host based on the associated sequence tag of the completed first I / O command or the completed second I / O command.

[0008] According to another example embodiment, a storage device is provided, the storage device comprising: at least two command queues; command processor logic; at least two physical channels, each physical channel associated with one or more solid-state storage media, the corresponding storage media being associated with a corresponding physical address; at least two physical channel queues, each physical channel queue associated with a corresponding storage channel of the at least two storage channels; and notification manager logic. The at least two command queues are configured to receive I / O commands from a host, the I / O commands being associated with sequence tags. The command processor logic is configured to issue I / O commands from the at least two command queues to the at least two physical channel queues based on the physical address associated with the I / O command and the sequence tag of the command. The notification manager logic is configured to issue an I / O command completion notification to the host based on the sequence tag of each completed I / O command.

[0009] According to another example embodiment, a system is provided, the system comprising: a host computer system; and a storage device communicatively connected to the host computer system. The storage device includes: at least two command queues; command processor logic; at least two storage channels, each channel associated with one or more solid-state storage media, each storage media associated with a corresponding storage address; at least two storage channel queues, each storage channel queue associated with a corresponding storage channel of the at least two storage channels; and notification manager logic. The at least two command queues are configured to receive I / O commands from the host computer system, the I / O commands being associated with sequence tags. The command processor logic is configured to issue I / O commands from the at least two command queues to the at least two storage channel queues based on the storage address associated with the I / O command and the sequence tag of the command. The notification manager logic is configured to issue a command completion notification to the host computer system based on the sequence tag of each completed I / O command. Attached Figure Description

[0010] These and other features and aspects of this disclosure will be appreciated and understood by referring to the specification, claims and drawings, wherein:

[0011] Figure 1 This is a schematic block diagram of an information processing system that may include an apparatus formed according to exemplary embodiments of the present disclosure;

[0012] Figure 2 This is an example flowchart depicting the I / O command processing technology of a computer system;

[0013] Figure 3 This is an example block diagram of a computing system used to process I / O commands;

[0014] Figure 4 This is an example flowchart depicting an I / O command processing technique for a computer system for sequentially processing I / O commands according to an example embodiment of the present disclosure;

[0015] Figure 5 This is an example block diagram of a computing system for sequentially processing I / O commands according to an example embodiment of the present disclosure;

[0016] Figure 6 This is an example flowchart of a process for ensuring that the host is notified of I / O operations completed in sequence, according to an example embodiment of this disclosure; and

[0017] Figure 7 This is an example flowchart of a storage device sequentially processing I / O command completion notifications according to an example embodiment of the present disclosure. Detailed Implementation

[0018] In the following description, various exemplary embodiments will be described more fully with reference to the accompanying drawings, which illustrate some exemplary embodiments. However, the subject matter of this disclosure can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter of this disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0019] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “bonded to” another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or layers. When an element or layer is referred to as being “directly” on, directly connected to, or directly bonded to another element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0020] It will be understood that although terms such as “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of the subject matter currently disclosed, the first element, first component, first region, first layer, or first part discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0021] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature and another shown in the accompanying drawings. It will be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, an element or feature described as “below” or “under” other elements or features will subsequently be positioned “above” other elements or features. Thus, the term “below” can include both “above” and “below” orientations. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the subject matter currently disclosed. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, processes, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, processes, operations, elements, components, and / or groups thereof.

[0023] The exemplary embodiments are described herein with reference to cross-sectional views as schematic illustrations of idealized example embodiments (and intermediate structures). Thus, variations in shape are expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations caused by manufacturing processes. For example, an injection area shown as rectangular typically has rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary variation from an injection area to a non-injection area. Similarly, an embedded area formed by injection can result in some injection in the area between the embedded area and the surface through which the injection occurs. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the subject matter currently disclosed.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their corresponding meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense.

[0025] In the following text, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic block diagram of an information processing system 100, which may include semiconductor devices formed according to the principles of the disclosed subject matter.

[0027] Reference Figure 1 The information processing system (or computing system) 100 may include one or more means constructed according to the principles of the disclosed subject matter. In one or more other embodiments, the information processing system 100 may employ or perform one or more techniques according to the principles of the disclosed subject matter.

[0028] In various embodiments, the information processing system 100 may include a computing device (such as a laptop computer, desktop computer, workstation, server, blade server, personal digital assistant, smartphone, tablet computer, and other suitable computer or its virtual machine or virtual computing device). In various embodiments, the information processing system 100 may be used by a user.

[0029] The information processing system 100 according to the disclosed subject matter may also include a central processing unit (CPU) and a logic or processor 110. In some embodiments, the processor 110 may include one or more functional unit blocks (FUBs) or combinational logic blocks (CLBs) 115. In such embodiments, the combinational logic blocks may include various Boolean logic operations (e.g., AND NOT NAND, OR NOT NOR, NOT, XOR), stable logic devices (e.g., flip-flops, latches), other logic devices, or combinations thereof. These combinational logic operations may be configured in a simple or complex manner to process input signals to achieve desired results. It will be understood that while several illustrative examples of synchronous combinational logic operations have been described, the disclosed subject matter is not limited thereto and may include asynchronous operations, or a mixture of synchronous and asynchronous operations. In one embodiment, the combinational logic operation may include a plurality of complementary metal-oxide-semiconductor (CMOS) transistors. In various embodiments, these CMOS transistors may be arranged as gates to perform logic operations; however, it should be understood that other techniques may be used, and these techniques are within the scope of the disclosed subject matter.

[0030] The information processing system 100 according to the disclosed subject matter may also include volatile memory 120 (e.g., random access memory (RAM)). The information processing system 100 according to the disclosed subject matter may also include non-volatile memory 130 (e.g., hard disk drive, optical storage, NAND or flash memory, and / or other solid-state memory). In some embodiments, volatile memory 120, non-volatile memory 130, or combinations or portions thereof may be referred to as a "storage medium". In various embodiments, volatile memory 120 and / or non-volatile memory 130 may be configured to store data in a semi-permanent or substantially permanent form.

[0031] In various embodiments, the information processing system 100 may include one or more network interfaces 140 configured to allow the information processing system 100 to communicate as part of a communication network via wired and / or wireless and / or cellular protocols. Examples of wireless protocols may include, but are not limited to, IEEE 802.11g and IEEE 802.11n. Examples of cellular protocols may include, but are not limited to, IEEE 802.16m (also known as Advanced Wireless MAN (Metropolitan Area Network), Advanced Long Term Evolution (LTE), Enhanced Data Rate for Evolution of GSM (Global System for Mobile Communications) (EDGE), and Evolved High Speed ​​Packet Access (HSPA+)). Examples of wired protocols may include, but are not limited to, IEEE 802.3 (also known as Ethernet), Fibre Channel, and power line communications (e.g., HomePlug, IEEE 1901). It should be understood that the above are merely a few illustrative examples, and the subject matter is not limited thereto. As a result of being connected to a network via network interface 140, information processing system 100 can access other resources (e.g., whether as a standalone network resource or as a component of an external attached system, such as external volatile memory, non-volatile memory, processor / logic, and software).

[0032] The information processing system 100 according to the disclosed subject matter may also include a user interface unit 150 (e.g., a display adapter, a haptic interface, and / or a human-machine interface device). In various embodiments, the user interface unit 150 may be configured to receive input from a user and / or provide output to a user. Other types of devices may also be used to provide interaction with the user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, and / or haptic feedback); and input from the user may be received in any form (including sound, speech, and / or haptic input).

[0033] In various embodiments, the information processing system 100 may include one or more other devices or hardware components 160 (e.g., a display or monitor, keyboard, mouse, camera, fingerprint reader, and / or video processor). It should be understood that the above are merely a few illustrative examples, and the subject matter is not limited thereto.

[0034] The information processing system 100 according to the disclosed subject matter may also include one or more system buses 105. In such embodiments, the system bus 105 may be configured to communicatively connect the processor 110, volatile memory 120, non-volatile memory 130, network interface 140, user interface unit 150, and one or more hardware components 160. Data processed by the processor 110 or data input from outside the non-volatile memory 130 may be stored in the non-volatile memory 130 or the volatile memory 120.

[0035] In various embodiments, the information processing system 100 may include or execute one or more software components 170. In some embodiments, the software component 170 may include an operating system (OS) and / or applications. In some embodiments, the OS may be configured to provide one or more services to the applications and manage the applications with various hardware components of the information processing system 100 (e.g., processor 110 and / or network interface 140), or act as an intermediary between the applications and various hardware components of the information processing system 100 (e.g., processor 110 and / or network interface 140). In such embodiments, the information processing system 100 may include one or more native applications that may be locally installed (e.g., installed in non-volatile memory 130) and configured to be executed directly by the processor 110 and interact directly with the OS. In such embodiments, the native applications may include pre-compiled machine-executable code. In some embodiments, the native application may include a script interpreter (e.g., Cshell (csh), AppleScript, AutoHotkey) and / or a virtual execution machine (VM) (e.g., Java Virtual Machine, Microsoft Common Language Runtime)) configured to convert source code or object code into executable code that is then executed by the processor 110.

[0036] As discussed herein, the apparatus may include logic configured to perform various tasks. The logic may be implemented as hardware, software, or a combination thereof. When the logic includes hardware, the hardware may be in the form of a special-purpose circuit arrangement (e.g., an ASIC), a programmable array of gate logic and memory (e.g., an FPGA), or specially programmed general-purpose logic (e.g., a CPU and a GPU). When the logic includes software, the software may be configured to operate special-purpose circuitry, or to program circuitry, an array of memory, or to operate a general-purpose processor. Logic implemented in software may be stored on any available storage medium (e.g., DRAM, flash memory, EEPROM, resistive memory, etc.).

[0037] Figure 2 An embodiment of a mechanism 200 for communication between host 205 and solid-state drive (SSD) 210 to coordinate the processing of I / O commands is shown. Figure 3 It shows that it can be executed Figure 2 A block diagram of embodiment 300 of the host 205 and SSD 210 described in the method is shown. In some embodiments, host 205 may be similar to Figure 1 The computing system 100. The SSD 210 can be used as volatile memory 120 or non-volatile memory 130, or as a means of communication. Figure 1Network interface 140 has available resources. I / O commands can be any kind of I / O command, including key-value based commands, logical block address (LBA) based commands, and / or other commands.

[0038] Now refer to Figures 2 to 3 According to the example mechanism, host 205 is responsible for tracking I / O commands issued by the operating system or various applications 305 running on host 205 as thread 310. As disclosed more thoroughly below, host 205 is responsible for preventing I / O errors caused by possible out-of-order processing of commands by SSD 210. Such errors include, but are not limited to: illegal overwrite (where older data overwrites newer data), reading stale data (where a read is issued after a write but processed before the write), and out-of-order notification to the application (where an application is notified of a sequence of actions that differs from the actual sequence of actions, causing the application to believe an error has occurred when no error has occurred, or not to believe an error has occurred when an error has occurred). As described more thoroughly below, disregarding other factors, the host can achieve this by issuing a lock (e.g., a lock queue) on the SSD resource and delaying the issuance of dependent commands (e.g., reads that follow and thus depend on earlier writes) until the host has received completion notification of the commands it depends on.

[0039] During processing 215, host 205 prepares to issue I / O commands (such as I / O commands issued by the OS or any application 305 using host 205) (which ultimately become commands 345a to 345d), and tracks the order in which the I / O commands are issued and the identity of the application issuing the I / O commands. During processing 215, the I / O commands (along with the order of receipt and the indication of the issuing application) can be stored in memory (such as memory, Figure 1 The data is temporarily stored in the volatile memory 120 for processing.

[0040] In process 220, I / O commands are sent sequentially to the SSD. This sending action can be performed by placing I / O commands into one or more host-side I / O submission queues 320, which can be read into and associated with command queues 325 on the SSD 210. I / O commands can be placed in multiple I / O submission queues 320a to 320b; two queues are shown, but any number greater than two is also possible. I / O commands can be placed in I / O queues 320a to 320b through various mechanisms, including association of a specific queue with processor core / thread 310, association of a specific queue with application / OS 305, and / or via hashing logic 315 (e.g., determining the I / O queue 320 by hashing the keys in key-value pairs). The sequential sending of I / O commands can involve waiting until the I / O command on which the sent I / O command depends completes, or until the lock on the resource is released.

[0041] In process 225, SSD 210 receives and buffers I / O commands (as shown in I / O commands 345a to 345d). Four commands are shown, but any suitable number is possible, as will be understood by those skilled in the art. I / O commands 345a to 345d are shown with corresponding timestamps (t1 to t4), but this is for illustrative purposes only and does not represent system processing. The commands are also labeled with tags W2, W1, R1, and W3 respectively to indicate the nature of the command (read or write) and the address associated with it. This labeling only describes example commands 345a to 345d and does not represent system processing. Commands 345a to 345d may be buffered or internally stored in SSD 210 in one or more command queues 325a to 325b, which may correspond to the respective sets of I / O submission queues 320a to 320b on host 205. Similar to the host, two queues are shown, but more queues are possible. Command queues 325a to 325b allow their I / O commands 345a to 345d to be fetched for polling processing by command processor logic 330 in the storage device (e.g., for actual fetching from the solid-state memory). This command processor logic 330 can be implemented in the controller circuitry of the storage device (not shown). This polling process prevents, or substantially prevents, any given queue (and associated application) from monopolizing the SSD 210.

[0042] In processing 230, commands 345a to 345d obtained from command queues 325a to 325b of the SSD can be issued by command processor logic 330 to multiple memory device channel queues 340a to 340b of the SSD 210 for actual execution by flash memory chips located on channels 335a to 335b (flash memory is one example of many feasible solid-state memories that can be used in one or more embodiments).

[0043] For example, in some embodiments, within SSD 210, physical solid-state memory (e.g., flash memory chips) is placed across multiple parallel physical channels on the SSD to allow parallel processing of I / O commands. Flash memory chips occupy physical channels (e.g., physical channels or flash memory channels) 335a and 335b (two channels 335a to 335b with four chips are shown, but more channels and different numbers of chips are feasible). When I / O commands (such as 345a to 345b) are sent to the physical memory for processing, they can be placed into a set of memory device channel queues 340a to 340b associated with the respective physical channels 335a, 335b. I / O commands can be sent to one or more specific memory device channel queues 340a to 340b based on the physical address associated with each I / O command. For example, when an I / O command (such as one of 345a to 345d) is to be processed, the command processor logic 330 may determine the physical address associated with the command, determine one or more memory device channel queues 340a to 340b that contain the physical address (such as flash memory chips on channels 335a to 335b), and place the I / O command in the channel queues 340a to 340b associated with the memory having those addresses.

[0044] exist Figure 3In the example, it should be noted that due to the combination of the polling of the command queue by the command processor logic 330 and the placement of commands determined by physical addresses in the channel queues 340a to 340b, the physical processing of commands 345a to 345d may be completed out of order. For example, it should be noted that channel queue 340a receives commands 345a(t1, W2), and channel queue 340b receives commands 345b(t2, W1) and 345d(t4, W3), where, due to polling, command 345d precedes command 345b. Therefore, commands 345a and 345d are located at the head of their respective channel queues 340a to 340b. Consequently, command 345d is likely to be completed before command 345a (especially if command 345d is a “small” write command). This out-of-order processing may be exacerbated by certain background operations required by the solid-state memory. For example, if garbage collection must be performed on the flash memory chip in channel 335a, the entire channel 335a and the associated channel queue 340a (and possibly other channels) may not be available to process commands, while other channels not occupied by garbage collection are free to process their respective queues 340.

[0045] Now return to Figures 2 to 3 In process 235, SSD 210 notifies host 205 of the completed I / O commands 345a to 345d in the order they were completed (i.e., possibly out of order, as described above) via notification logic 350. In the illustrated embodiment, the notification order would be 345d, then 345a, then 345b (with 345c still not completed). Notification logic 350 may be included within the storage controller (not shown) of SSD 210.

[0046] In process 240, host 205 receives I / O completion notifications sent from SSD 210 in the order (i.e., possibly out of order) they were sent. For example, as Figure 3 As shown, the order of command completion notifications is 345d, 345a, then 345b, while command 345c has not yet been processed. The host can then accumulate completion notifications required to confirm that no timing / consistency errors have occurred, destage the I / O command requests, and send I / O completion notifications to application / OS 305 in the order in which application / OS 305 requested them (i.e., in the order of 345a, 345b, and waiting for 345c before notification 345d). Locks on resources can be released. If a potential consistency error is detected, the I / O request can be repeated instead of destaged, and no completion notification can be sent to application / OS 305.

[0047] If the inspection is passed Figures 2 to 3As can be observed from the related discussion, the above mechanism generally avoids the most severe forms of consistency errors because a series of I / O commands from a given application to a given address will be limited to a single host-side I / O queue 320, a single SSD command queue 325, and a predetermined set of channel queues 340. Furthermore, inter-application consistency errors can be reduced by locking one or more queues. However, this mechanism requires significant resource utilization from the host and introduces inefficiencies within the SSD. Specifically, the host must cache and uncache all I / O requests in the order they are received and must adequately track completion notifications to ensure no consistency errors have occurred. Furthermore, queue locking reduces the total number of I / O operations that can be processed by the queues within a given time, and the polling of I / O commands 345a to 345d from command queues 325a to 325b to channel queue 340 can cause one or more of these queues to be underutilized.

[0048] Figure 4 An embodiment of a mechanism 400 for communication between host 205' and solid-state drive (SSD) 210' to coordinate the processing of I / O commands with reduced host overhead is shown. Figure 5 It shows the ability to execute Figure 4 A block diagram of embodiment 500 of the method described herein, comprising host 205' and SSD 210'. In some embodiments, host 205' may be similar to Figure 1 The computing system 100. In some embodiments, the SSD 210' can be used as... Figure 1 The volatile memory 120 or non-volatile memory 130 may be used as a resource available through the network interface 140. I / O commands can be any kind of I / O command, including key-value based commands, logical block address (LBA) based commands, or other commands.

[0049] As will be further shown below, Figures 4 to 5 The example embodiment shown is configured to allow SSD 210' to receive I / O commands from host 205' in a defined order, and to notify host 205' of command completion in the same order. This allows host 205' to discard the above references. Figures 3 to 4 The discussion focuses primarily on host-side I / O management, allowing the SSD 210' to utilize its own internal resources more efficiently.

[0050] Go to Figures 4 to 5In process 405, host 205' sends I / O commands to SSD 210' in the order they are generated by application / OS 505. The sending action can be performed through one or more host-side I / O submission queues 520a to 520c, which can be read into and associated with command queues 525a to 525c on SSD 210'. I / O commands can be placed in multiple I / O submission queues 520a to 520c; three queues are shown, but any number greater than two is possible. I / O requests can be placed directly into I / O submission queues 520a to 520c through association of a specific queue with user I / O thread 510, and / or association of a specific queue with application / OS 505. As a result of processing 405, commands 545a to 545h are placed in command queues 525a to 525c of SSD 210'.

[0051] As will be more readily understood below, in this embodiment, host 205' can simply queue I / O commands directly with minimal processing, and does not need to pause I / O requests (including tracking the sequence of issuance and the identity of the issuer), lock resources, cancel I / O requests upon completion, or monitor the order and / or consistency of I / O completion notifications, thereby freeing up host resources.

[0052] In some embodiments, during processing 405, each I / O command is associated with a timestamp or with another sequence number (such as an integer of order) determined by the order in which each I / O command is sent. The timestamp or sequence number (sequence tag) may be generated by sequence tag generator logic 546. Sequence tag generator logic 546 may reside on host 205' or SSD 210'. In embodiments where host 205' includes sequence tag generator logic 546, the sequence tag is sent along with the I / O commands to SSD 210'. In embodiments where host 205' includes sequence tag generator logic 546, the sequence tag generator can be used to ensure that if an I / O command can be broken down into operations guided by a set of Logical Block Addresses (LBAs), all broken-down commands utilize consecutive sequence tags. In one example, sequence tag generator 546 includes logic configured to apply sequence tags to LBA requests according to the order in which applications running on the host need to access them. In embodiments where SSD 210' includes sequence tag generator logic 546, it is not necessary to send I / O commands from host 205' using sequence tags; when an I / O command is received by SSD 210', a sequence tag is added to the I / O command. The sequence tags are shown as tags t1 to t8 on commands 545a to 545h. In various embodiments where sequence tag generator logic 546 is located on SSD 210', sequence tag generator logic 546 may communicate with indexing logic, command processor logic, and / or command queues, depending in part on where the sequence tags (and / or their association with I / O commands) are stored.

[0053] Now go to Figure 5 It should be noted that I / O commands 545a to 545h are associated with corresponding sequence tags t1 to t8. It should also be noted that the commands have been placed in command queues 525a to 525c associated with corresponding I / O command submission queues 520a to 520c, which in turn are associated with user I / O thread 510. It should also be noted that within each queue, I / O commands 545a to 545h are in chronological order, but there is no specific order between queues. It should also be noted that each I / O command 545a to 545h is shown using an example operation type (read or write) and address (e.g., 1 to 3). This is to illustrate the effect of the embodiment and does not reflect any action of the embodiment.

[0054] Again targeting Figure 5SSD 210' includes indexing logic 533. Indexing logic 533 indexes all I / O commands 545a to 545h in command queues 525a to 525c in sequence tag order, and may be a mechanism that associates sequence tags with specific I / O commands 545a to 545h. Indexing logic 533 may include a min-heap index; however, many other indexes are also possible. In some embodiments, as discussed below, indexing logic 533 may also track the activity of physical memory channels 535a to 535b and their associated queues 540a, 540b; however, in other embodiments, other logic may track these activities (also discussed below). SSD 210' also includes command processor logic 530. Indexing logic 533 may additionally include or communicate with an index memory (not shown) for housing the index. Indexing logic 533 may also communicate with sequence tag generator logic 546, command processor logic 530, and / or command queues 525a to 525c.

[0055] Now return to Figures 4 to 5 In processing 410, the command processor logic 530 retrieves I / O commands 545a to 545h from command queues 525a to 525c in sequence tag order, determines the physical block address associated with each specific I / O command 545a to 545h, and places each specific I / O command 545a to 545h (in order) into one or more physical channel queues 540a to 540b associated with the corresponding physical memory channels (i.e., physical channels) 535a, 535b, each physical memory channel including a solid-state memory chip associated with the determined physical address.

[0056] For example, in some embodiments, within SSD 210', physical solid-state memory (e.g., flash memory chips) is placed across multiple parallel physical channels on the SSD to allow parallel processing of I / O commands. This is illustrated by the flash memory chips occupying physical channels 535a, 535b (two channels 535a to 535b with four chips are shown; however, more channels and different numbers of chips are feasible). When I / O commands (such as 545a to 545h) are sent to the physical memory for processing, they can be placed into a set of memory device physical channel queues 540a to 540b. I / O commands can be sent to one or more specific memory device physical channel queues 540a to 540b based on the physical address associated with each I / O command. For example, when an I / O command (such as one of 545a to 545d) is to be processed, the command processor logic 530 may determine the physical address associated with the command, determine one or more memory device channel queues 540a to 540b that contain the physical address (such as flash memory chips on physical channels 535a to 535b), and place the I / O command in the channel queues 540a to 540b associated with the memory having those addresses.

[0057] Command processor logic 530 can utilize a sequence ID-based command retriever 531, and further utilize indexing logic 533, to ensure that command processor logic 530 places commands from I / O command queues 525a to 525c into physical channel queues 540a and 540b in tag sequence order. When a specific I / O command 545a to 545h is issued to channel queues 540a and 540b, the I / O command is removed from index 533 and command queues 525a to 525c. As will be discussed further below, when an I / O command is placed in channel queues 540a and 540b, it can be indexed by an index (not shown) in the I / O sequencer logic 551 of notification manager logic 550.

[0058] about Figure 5It should be noted that because the command processor logic 530 has already sent I / O commands 545a to 545h sequentially to the physical channel queues 540a and 540b, this results in each of the channel queues 540a and 540b having all commands listed in sequence. This prevents any data consistency errors: all operations on a given physical address will be processed sequentially, so there is no possibility of write-after-read errors or old-write-after-new-write errors (or essentially no possibility of write-after-read errors or old-write-after-new-write errors). It should also be noted that if a command includes operations on address ranges spanning multiple channels (e.g., writing to a very large key value, or a command whose LBA range can be translated to a completely different physical address), then the command will be dispatched concurrently (e.g., simultaneously) to multiple channels in a given order to maintain the consistency of data items even across channels. However, the fact that each physical channel 535a, 535b can process requests at different rates (due to reasons similar to those discussed above, such as garbage collection) may still result in limited out-of-order I / O completions. However, as stated above, such out-of-order processing will not lead to data consistency errors or severe data consistency errors.

[0059] Now return to Figures 4 to 5 In processing 415, SSD 210' processes I / O requests out of order. For example, as described above, the command processor logic 530, utilizing the sequence ID-based command fetcher 531, can sequentially fetch I / O commands 545a to 545h from command queues 525a to 525c and place them sequentially into the corresponding physical channel queues 540a and 540b. Each physical channel 535a and 535b will process its corresponding channel queue 540a and 540b at its own rate (possibly out of order).

[0060] In processing 420, SSD 210' can notify host 205' of I / O command completion in the same order as host 205' issues I / O commands. For example, SSD 210' may include notification manager logic 550. Notification manager logic 550 may include I / O sequencer logic 551, notification buffer 552, and host notification logic (or host notifier) ​​553. Notification buffer 552 may receive command completion notifications from the flash memory chips of physical channels 535a, 535b for the corresponding completion commands 545a to 545h. I / O sequencer logic 551 may associate the completion notification with the corresponding I / O commands 545a to 545h and their associated sequence tags.

[0061] In addition to tracking commands issued to physical channel queues 540a and 540b but not to I / O command queues 525a to 525c, I / O sequencer logic 551 may include indexing logic (not shown) similar to indexing logic 533. In other embodiments, the I / O sequencer logic communicates with indexing logic 533, which in some embodiments may track both command queues 525a to 525c and physical channel queues 540a and 540b. When notification manager logic 550 receives a command completion notification from physical channels 535a and 535b, the command completion notification is buffered in notification buffer 552, and I / O sequencer logic 551 associates the notification with the corresponding I / O commands 545a to 545h and a sequence tag. Notification manager logic 550 may check I / O sequencer logic 551 to see if pending command completion notifications in notification buffer 552 are for I / O commands 545a to 545h with the lowest sequence tag. Based on the discovery that a command completion notification in notification buffer 552 is associated with an I / O command with the lowest sequence tag, notification manager logic 550 may invoke host notification logic 553 to notify host 205' that the I / O command with the lowest sequence tag has been completed. In a particular embodiment, notification logic 553 may also notify host 205' that any subsequent I / O command in notification buffer 552 with a sequence tag immediately following the I / O command with the lowest sequence tag, or with a sequence tag succeeding the sequence tag of the I / O command with the lowest sequence tag, has been completed. When sending the command completion notification to host 205', the command completion notification and the associated list of I / O commands, as well as the sequence tags, are removed from notification buffer 552 and I / O sequencer logic 551 (e.g., by clearing items from the buffer and index structure). Therefore, the command completion notification sent to host 205' is returned in the same order as the original I / O command was sent.

[0062] Now return to Figures 4 to 5 In process 425, host 205' receives I / O command completion notifications in an order corresponding to the order in which the original I / O commands 545a to 545h were sent to SSD 210'. Host 205' can then notify various application / OS 505 and / or user I / O threads 510 of I / O command completion. Therefore, application / OS 505 and user I / O threads 510 are notified of their successful operations in an appropriate order.

[0063] During the inspection Figures 4 to 5It is clear that, in some embodiments, the use of host resources is significantly reduced. More specifically, I / O commands do not need to undergo extensive staging and unstaging on host 205', as well as associated completion tracking and sorting. Furthermore, separate I / O queues 520a to 520c, or any given address range, do not need to induce any form of locking to prevent or mitigate consistency errors. Additionally, host 205' does not need to operate any I / O allocation mechanisms (such as...). Figure 3 (Hash logic 315). Finally, processor cycles and memory dedicated to these tasks can be freed up for other uses.

[0064] Now go to Figures 5 to 6 , Figure 6 Provided Figure 5 The notification manager logic 550 determines the direction of the notification. Figure 5 The flowchart illustrates an embodiment of the process used when host 205' issues a command to complete a notification. In process 605, notification manager logic 550 receives a subject I / O command completion notification from a flash memory chip residing on a physical channel (e.g., flash memory channel) 535a, 535b and stores it in a notification buffer 552.

[0065] In process 610, the target I / O command completion notification is associated with a specific I / O command (e.g., a KV request) among I / O commands 545a to 545h and its associated sequence tag. As described above, this can be accomplished by referencing the command completion notification using indexing logic (e.g., an internal index or indexing logic 533) associated with I / O sequencer logic 551. In some embodiments, if I / O commands 545a to 545h have been distributed across multiple channels as described above, then in this process, the individual channel completions are merged into a single "completion" for the I / O command.

[0066] In process 615, the sequence tag of the target I / O command completion notification is examined to see if it is the lowest sequence tag of the completion notification of a currently pending I / O command in the associated indexer logic (e.g., internal index or index logic 533) of the I / O sequencer logic 551. In some embodiments, this can be done by comparing the sequence tag of the target I / O command completion notification with the sequence tag number of the last notification. For example, in embodiments where the sequence tag is an integer, the notification manager logic 550 may check whether the sequence tag of the target I / O command completion notification is "one" greater than the sequence ID of the most recent I / O command completion notification sent to the host; if so, the target I / O command is the lowest-tagged pending I / O command completion notification. In other embodiments, such as where the sequence tag is a timestamp, the notification manager logic 550 may utilize the index logic (e.g., internal index or index logic 533) associated with the I / O sequencer logic 551 to determine whether the target I / O command completion notification is the lowest-tagged notification. More specifically, for example, if the target I / O command completion notification is at the root of the min-heap index, then it is the lowest-marked notification.

[0067] In process 620, if the target I / O command completion notification is not the lowest-tagged I / O command among the associated pending I / O commands, the notification may be temporarily stored in a notification buffer for future notifications (e.g., as shown below, when an I / O command with an earlier sequence tag is processed), and the process returns to process 605, ready to receive more I / O command completion notifications.

[0068] In process 625, based on the association of the target I / O command completion notification with the lowest incomplete command, notification manager logic 550 may search in notification buffer 552 to locate any buffered I / O command completion notifications that may follow the target I / O command completion notification. In some embodiments, this can be done by comparing the contents of notification buffer 552 with the order provided in the index of I / O sequencer logic 551. In some alternative embodiments, this can be done by checking the sequence tag of the buffer contents for the numerical ordering of the target I / O command completion notification. The target I / O command completion notification thus identified and any I / O command completion notifications in any order may be sent to host notification logic 553, cleared from notification buffer 552, removed from the index associated with I / O sequencer logic 551 (e.g., internal index or index logic 533), and the last sequence ID of the notification (in process 615) may be updated.

[0069] In process 630, host notification logic 530 sends a target I / O command completion notification and any subsequent I / O command completion notifications identified in process 625 to host 205'. Then, Figure 6 The process can be restarted as needed.

[0070] Figure 7 A method 700 is shown for an SSD (such as SSD 210') to sequentially receive I / O commands from a host 205' and to notify the host 205' of completed I / O commands in the same order. Those skilled in the art will recognize that, without departing from the concept disclosed herein, Figure 7 The processes can be completed in an optional order, or specific processes can be added or removed.

[0071] In processing 705, I / O commands associated with the corresponding sequence tag can be placed on one or more command queues on SSD 210' (such as, Figure 5 In command queues 525a to 525c). This can be achieved through sequence tag generator logic (such as...). Figure 5 The sequence tag generator logic 546 associates the sequence tag with I / O commands on the host 205' or SSD 210'.

[0072] When processing 710, indexing can be done in the I / O command queue (such as, Figure 5 In the indexing logic 533), I / O commands are indexed, thereby indexing the association between I / O commands and sequence tags, and sorting the entries according to the order of the sequence tags.

[0073] In processing 715, I / O commands can be moved from the I / O command queue to one or more physical channel queues (such as, based on the order of their sequence tags) according to their sequence labels. Figure 5 The channel queues 540a and 540b are used. One or more physical channel queues may correspond to physical channels housing solid-state memory chips containing physical addresses corresponding to I / O commands. For example, in some embodiments, this can be accomplished by: determining an I / O command with the lowest sequence tag; determining one or more memory channels associated with the address of the determined I / O command; and placing the determined I / O command into one or more memory channel queues of the memory channel associated with the address of the determined I / O command. More specifically, in some embodiments, the physical address can be derived from the key of a key-value pair. For example, in some embodiments, the key may be mapped to one or more physical addresses. In other embodiments, the physical address can be derived from one or more logical block addresses (LBAs) (e.g., in some embodiments, one or more LBAs may be mapped to one or more physical addresses).

[0074] In process 720, I / O commands that have been moved to the physical channel queue are removed from the I / O command queue, and the I / O command queue index is updated.

[0075] In processing 725, each flash channel queue processes its own I / O command. When an I / O command completes, a corresponding I / O command completion notification is sent to the notification manager logic (e.g., ...). Figure 5 Notification Manager Logic 550).

[0076] In process 730, I / O command completion notifications are collected. I / O command completion notifications can be collected in a notification buffer (such as...). Figure 5 In the notification buffer 552 of the notification manager 550.

[0077] In processing 735, I / O command completion notifications are sent to the host in the same order as the corresponding I / O commands were received. This can be achieved through the above-mentioned... Figure 6 The processes discussed are similar to those used to complete process 735.

[0078] The method process can be executed by one or more programmable processors that execute computer programs to perform functions by manipulating input data and generating output. The method process can also be executed by special-purpose logic circuitry (e.g., FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit)), and the device can be implemented as special-purpose logic circuitry (e.g., FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit)).

[0079] In various embodiments, a computer-readable medium may include instructions that, when executed, cause a device to perform at least a portion of a method process or handling. In some embodiments, the computer-readable medium may be contained in a magnetic medium, an optical medium, other media, or combinations thereof (e.g., a CD-ROM, a hard disk drive, a read-only memory, a flash drive). In such embodiments, the computer-readable medium may be a tangible and non-transitory article of manufacture.

[0080] While the principles of the disclosed subject matter have been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of these disclosed concepts. Therefore, it should be understood that the above embodiments are not restrictive but merely illustrative. Consequently, the scope of the disclosed concepts will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be constrained or limited by the foregoing description. Therefore, it should be understood that the appended claims are intended to cover all such modifications and changes falling within the scope of the embodiments.

[0081] Embodiments of the inventive concept can be extended without limitation to the following statement:

[0082] Statement 1: A method for sequentially processing I / O requests by a storage device, the method comprising:

[0083] Receive the first I / O command and the second I / O command, and assign sequence tags to the first I / O command and the second I / O command;

[0084] Based on the sequence tags of the first I / O command and the second I / O command, the first I / O command and the second I / O command are sent to one or more storage channels;

[0085] When the first I / O command or the second I / O command has been completed, collect command completion notifications for the first I / O command or the second I / O command, respectively; and

[0086] A command completion notification is sent to the host based on the associated sequence tag of the completed first I / O command or the completed second I / O command.

[0087] Statement 2: The method described in Statement 1, wherein the first I / O command and the second I / O command received are indexed according to their sequence labels.

[0088] Statement 3: The method as described in Statement 1, wherein the step of issuing the first I / O command and the second I / O command to one or more memory channels based on their respective sequence tags includes:

[0089] Determine the I / O command with the lowest sequence tag;

[0090] Identify one or more memory channels associated with the address of the I / O command that is identified as having the lowest sequence tag;

[0091] The determined I / O command with the lowest sequence tag is placed into one or more memory channel queues of the memory channel associated with the determined address of the I / O command with the lowest sequence tag; and

[0092] Update the index to remove the identified I / O commands with the lowest sequence tag.

[0093] Statement 4: The method described in Statement 3, wherein the address is based on the key of the key-value pair.

[0094] Statement 5: The method described in Statement 3, wherein the address includes a logical block address (LBA).

[0095] Statement 6: As described in Statement 1, wherein the sequence tag is determined by the host.

[0096] Statement 7: The method described in Statement 1, wherein the sequence tag is determined by the storage device.

[0097] Statement 8: The method described in Statement 1, wherein the step of issuing a command to the host to complete the notification includes:

[0098] Determine whether the sequence tag associated with the completed I / O command is the lowest sequence tag among all sequence tags associated with pending I / O commands;

[0099] Based on the fact that the sequence label of the determined completed I / O command is the sequence label of the lowest pending I / O command, a notification of completion for all completed I / O commands with sequence labels succeeding the determined lowest sequence label is sent to the host. Completed I / O commands include those with the lowest sequence label.

[0100] Based on the fact that the sequence tag of the confirmed completed I / O command is not the sequence tag of the lowest pending I / O command, the I / O command completion notification is placed in the buffer.

[0101] Statement 9: A storage device comprising:

[0102] At least two command queues;

[0103] Command processor logic;

[0104] At least two physical channels, each physical channel being associated with one or more solid-state storage media, and the corresponding storage media being associated with a corresponding physical address;

[0105] At least two physical channel queues, associated with corresponding physical channels of the at least two physical channels; and

[0106] Notification manager logic,

[0107] in,

[0108] The at least two command queues are configured to receive I / O commands from the host, the I / O commands being associated with sequence tags;

[0109] The command processor logic is configured to: issue I / O commands from the at least two command queues to the at least two physical channel queues based on the physical address associated with the I / O command and the sequence tag of the I / O command; and

[0110] The notification manager logic is configured to send I / O command completion notifications to the host based on the sequence tags of each completed I / O command.

[0111] Statement 10: The storage device as described in Statement 9 further includes: sequence tag generator logic, the sequence tag generator logic being configured to: communicate with command processor logic or command queue, and receive I / O commands received from the host from the command queue, and associate the received I / O commands with sequence tags determined by the order in which the I / O commands are received.

[0112] Statement 11: The storage device as described in Statement 10 further includes: indexing logic and index memory, wherein the indexing logic is configured to communicate with sequence tag generator logic, command processor logic, or command queue, and to index I / O commands in the index memory using the corresponding sequence tags of the I / O commands.

[0113] Statement 12: The storage device as described in Statement 11, wherein the command processor logic is configured as follows:

[0114] Determine the I / O command with the lowest sequence tag in the index;

[0115] Identify one or more memory channels associated with the address of the I / O command that is identified as having the lowest sequence tag;

[0116] The determined I / O command is placed into one or more memory channel queues associated with a solid-state storage medium, the solid-state storage medium being associated with a determined address of the I / O command; and

[0117] Update the index to remove the identified I / O commands with the lowest sequence tag.

[0118] Statement 13: The storage device as described in Statement 12, wherein the I / O command includes a key-value command, and the storage address is determined based on the key of the key-value command.

[0119] Statement 14: The storage device as described in Statement 12, wherein the I / O command includes one or more logical block addresses (LBAs), and the storage address is determined based on the LBA.

[0120] Statement 15: The storage device as described in Statement 9, wherein the notification manager logic includes:

[0121] Notification buffer;

[0122] I / O sequencer logic; and

[0123] Host notification logic,

[0124] in,

[0125] The notification buffer is configured to receive and store command completion notifications for the corresponding I / O commands that have been completed by the physical channel;

[0126] The I / O sequencer logic is configured to: determine the sequence tag associated with a command completion notification received from the physical channel, and is also configured to: determine whether the command completion notification in the notification buffer has a sequence tag that is the lowest sequence tag not yet notified to the host; and

[0127] The host notification logic is configured to notify the host of the completion of the associated I / O command when it is determined that the notification buffer contains a command completion notification corresponding to the lowest sequence tag that has not yet been notified to the host.

[0128] Statement 16: A system comprising:

[0129] Mainframe computer system; and

[0130] Storage device, communicatively connected to host computer system,

[0131] The storage device includes:

[0132] At least two command queues;

[0133] Command processor logic;

[0134] At least two storage channels, each channel being associated with one or more solid-state storage media, and the corresponding storage media being associated with a corresponding storage address;

[0135] At least two storage channel queues, associated with corresponding storage channels of the at least two storage channels; and

[0136] Notification manager logic,

[0137] in,

[0138] The at least two command queues are configured to receive I / O commands from the host computer system, the I / O commands being associated with sequence tags;

[0139] The command processor logic is configured to: issue I / O commands from the at least two command queues to the at least two memory channel queues based on the memory address associated with the I / O command and the sequence tag of the I / O command; and

[0140] The notification manager logic is configured to send command completion notifications to the host computer system based on the sequence tags of each completed I / O command.

[0141] Statement 17: The system as described in Statement 16, wherein the host computer system includes: a sequence tag generator, and the sequence tag generator is configured to: associate sequence tags with I / O commands for transfer to a storage device.

[0142] Statement 18: The system as described in Statement 17, wherein the sequence tag generator includes logic configured to apply sequence tags to LBA requests according to the order in which applications running on the host computer system request access.

Claims

1. A method of processing input / output requests in order by a storage device, the method comprising: receiving a first input / output command and a second input / output command, the first input / output command and the second input / output command being assigned a sequence tag; issuing the first input / output command and the second input / output command to one or more storage channels based on the respective sequence tags of the first input / output command and the second input / output command; collecting a command completion notification of the first input / output command or the second input / output command when the first input / output command or the second input / output command has been completed, respectively; and issuing the command completion notification to a host based on the associated sequence tag of the completed first input / output command or the completed second input / output command, wherein the step of issuing the command completion notification to the host comprises: determining whether the sequence tag associated with the completed input / output command is the lowest sequence tag among all sequence tags associated with pending input / output commands; based on determining that the sequence tag of the completed input / output command is the sequence tag of the lowest pending input / output command, issuing all command completion notifications of completed input / output commands having sequence tags sequential to the determined lowest sequence tag to the host, the completed input / output commands including the completed input / output command having the lowest sequence tag; and based on determining that the sequence tag of the completed input / output command is not the sequence tag of the lowest pending input / output command, placing the command completion notification in a buffer.

2. The method of claim 1, wherein, The received first input / output command and the received second input / output command are indexed according to their sequence tags.

3. The method of claim 2, wherein, The step of issuing the first input / output command and the second input / output command to one or more storage channels based on the respective sequence tags of the first input / output command and the second input / output command comprises: determining an input / output command having a lowest sequence tag; determining one or more storage channels associated with an address of the determined input / output command having the lowest sequence tag; placing the determined input / output command having the lowest sequence tag in one or more storage channel queues of the storage channels associated with the determined address of the input / output command having the lowest sequence tag; and updating the index to remove the determined input / output command having the lowest sequence tag.

4. The method of claim 3, wherein, The address is based on a key of a key-value pair.

5. The method of claim 3, wherein, The address comprises a logical block address.

6. The method of claim 1, wherein, The sequence tag is determined by the host.

7. The method of claim 1, wherein, The sequence tag is determined by the storage device.

8. A storage device comprising: at least two command queues; command processor logic; at least two physical channels, each physical channel being associated with one or more solid state storage media, the respective storage media being associated with a respective physical address; at least two physical channel queues, associated with respective ones of the at least two physical channels; and notification manager logic, wherein the at least two command queues are configured to receive input / output commands from a host, the input / output commands being associated with sequence tags; ​ The command processor logic is configured to: issue input / output commands from the at least two command queues to the at least two physical channel queues based on physical addresses associated with the input / output commands and sequence tags of the input / output commands; and the notification manager logic is configured to: issue input / output command completion notifications to the host based on sequence tags of respective completed input / output commands, wherein the notification manager logic includes: a notification buffer; an input / output sequencer logic; and a host notification logic, wherein the notification buffer is configured to:

9. The storage device of claim 8, further comprising: receive and store command completion notifications of respective input / output commands that have been completed by a physical channel; 10. The storage device of claim 9, further comprising: the input / output sequencer logic is configured to:

11. The memory device of claim 10, wherein, determine sequence tags associated with command completion notifications received from a physical channel, and is further configured to: determine whether a command completion notification in the notification buffer has a sequence tag that is the lowest sequence tag that has not been notified to the host; and the host notification logic is configured to: notify the host of an associated input / output command completion upon determining that the notification buffer contains a command completion notification corresponding to the lowest sequence tag that has not been notified to the host. sequence tag generator logic, the sequence tag generator logic being configured to: communicate with the command processor logic or the command queues, and receive input / output commands received from the host from the command queues, and associate the received input / output commands with sequence tags determined by an order of receipt of the input / output commands.

12. The memory device of claim 11, wherein, index logic and an index store, wherein the index logic is configured to:

13. The memory device of claim 11, wherein, communicate with the sequence tag generator logic, the command processor logic, or the command queues, and index the input / output commands within the index store using respective sequence tags of the input / output commands. the command processor logic is configured to: determine an input / output command in the index that has a lowest sequence tag; determine one or more physical channels associated with an address of the input / output command determined to have the lowest sequence tag; place the determined input / output command into one or more of the physical channel queues associated with solid state storage media associated with the determined address of the input / output command; and update the index to remove the determined input / output command having the lowest sequence tag. the input / output commands include key-value commands, and the storage addresses are determined based on keys of the key-value commands. the input / output commands include one or more logical block addresses, and the storage addresses are determined based on the logical block addresses.

14. A system to process input / output requests, comprising: a host computer system; and a storage device communicatively connected to the host computer system, wherein the storage device includes: at least two command queues; command processor logic; at least two storage channels, each storage channel being associated with one or more solid state storage media, respective storage media being associated with respective storage addresses; at least two storage channel queues, associated with respective storage channels of the at least two storage channels; and notification manager logic, wherein the command processor logic is configured to: issue input / output commands from the at least two command queues to the at least two physical channel queues based on physical addresses associated with the input / output commands and sequence tags of the input / output commands; and the notification manager logic is configured to: issue input / output command completion notifications to the host based on sequence tags of respective completed input / output commands, wherein the notification manager logic includes: a notification buffer; an input / output sequencer logic; and a host notification logic, wherein the notification buffer is configured to: receive and store command completion notifications of respective input / output commands that have been completed by a physical channel; the input / output sequencer logic is configured to: determine sequence tags associated with command completion notifications received from a physical channel, and is further configured to: determine whether a command completion notification in the notification buffer has a sequence tag that is the lowest sequence tag that has not been notified to the host; and the host notification logic is configured to: notify the host of an associated input / output command completion upon determining that the notification buffer contains a command completion notification corresponding to the lowest sequence tag that has not been notified to the host. The at least two command queues are configured to receive input / output commands from the host computer system, the input / output commands being associated with sequence tags; The command processor logic is configured to issue input / output commands from the at least two command queues to the at least two storage channel queues based on storage addresses associated with the input / output commands and sequence tags of the input / output commands; and The notification manager logic is configured to issue command completion notifications to the host computer system based on sequence tags of respective completed input / output commands, wherein the notification manager logic comprises: a notification buffer; input / output sequencer logic; and host notification logic, wherein the notification buffer is configured to receive and store command completion notifications of respective input / output commands that have been completed by the storage channels; the input / output sequencer logic is configured to determine sequence tags associated with command completion notifications received from the storage channels, and is further configured to determine whether command completion notifications in the notification buffer have sequence tags that are the lowest sequence tags that have not been notified to the host; and the host notification logic is configured to notify the host of associated input / output command completions upon determining that the notification buffer contains command completion notifications corresponding to the lowest sequence tags that have not been notified to the host.

15. The system of claim 14, wherein, The host computer system comprises a sequence tag generator, and the sequence tag generator is configured to associate sequence tags with input / output commands for transmission to the storage device.

16. The system of claim 15, wherein, The sequence tag generator comprises logic configured to apply sequence tags to logical block address requests in an order required for access by an application running on the host computer system.

Images