Chip package and method of forming the same

Abstract

Structures of chip packages and methods of forming the same are provided. One method includes disposing a semiconductor die on a carrier substrate. The method also includes disposing a interposer substrate on the carrier substrate. The interposer substrate has a recess that passes through opposite faces of the interposer substrate. The interposer substrate has an inner sidewall that surrounds the semiconductor die, and the semiconductor die is level or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. Additionally, the method includes removing the carrier substrate and stacking a package structure on the interposer substrate.

Description

[0001] This application is a divisional application of the application with the application date of July 5, 2018, the application number of 201810730689.1, and the title of Chip Package and Forming Method Thereof. TECHNICAL FIELD

[0002] The present disclosure relates to a structure of a semiconductor device and a forming method thereof, and particularly to a structure of a fan-out chip package and a forming method thereof. BACKGROUND

[0003] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. The manufacture of semiconductor devices typically involves sequentially depositing materials for insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using photolithography and etching processes to form circuit components and elements on the semiconductor substrate.

[0004] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuing to shrink the size of the individual components that are integrated onto a given area. In some applications, these smaller electronic components are also using smaller packages that have a smaller footprint or lower height.

[0005] New packaging technologies, such as package on package (PoP), have been developed in which a top package with a device chip is bonded to a bottom package with another device chip. By employing these new packaging technologies, various packages with different or similar functionalities can be integrated together. These newer packaging technologies for semiconductor devices present process challenges. SUMMARY

[0006] A method of forming a chip package is provided in accordance with some embodiments. The method includes disposing a semiconductor die on a carrier substrate. The method also includes disposing an interposer substrate on the carrier substrate. The interposer substrate has a recess that extends through opposite faces of the interposer substrate. The interposer substrate has an inner sidewall that surrounds the semiconductor die, and the semiconductor die is level with or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure on the interposer substrate.

[0007] A method of forming a chip package is provided in accordance with some embodiments. The method includes forming a first redistribution structure over a carrier substrate and bonding a semiconductor die to the first redistribution structure. The method also includes bonding an interposer substrate to the first redistribution structure. The interposer substrate has a ring-shaped structure surrounding the semiconductor die and the semiconductor die is level or higher than the interposer substrate. The method further includes forming a protective layer to surround the semiconductor die. A portion of the protective layer is between the interposer substrate and the semiconductor die. In addition, the method includes removing the carrier substrate and bonding a package structure over the interposer substrate. The semiconductor die is between the package structure and the first redistribution structure.

[0008] A chip package is provided in accordance with some embodiments. The chip package includes a first redistribution structure and a semiconductor device bonded over the first redistribution structure. The chip package also includes an interposer substrate bonded over the first redistribution structure. The interposer substrate has an inner sidewall surrounding the semiconductor device and the semiconductor device is level or higher than the interposer substrate. The chip package further includes a protective layer surrounding the semiconductor device. In addition, the chip package includes a second redistribution structure over the protective layer. A first conductive component of the second redistribution structure is electrically connected to a second conductive component of the interposer substrate. BRIEF DESCRIPTION OF DRAWINGS

[0009] The concepts of the present disclosure can be more readily understood from the following detailed description with reference to the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various elements are not drawn to scale and are merely intended to illustrate examples. In fact, the dimensions of the various elements can be arbitrarily increased or decreased for the sake of clarity in discussion.

[0010] Figures 1A-1K is a cross-sectional view illustrating various stages of a process of forming a chip package in accordance with some embodiments.

[0011] Figures 2A-2D is a cross-sectional view illustrating various stages of a process of forming a chip package in accordance with some embodiments.

[0012] Figures 3A-3E is a cross-sectional view illustrating various stages of a process of forming a chip package in accordance with some embodiments.

[0013] Figures 4A-4B is a cross-sectional view illustrating various stages of a process of forming a chip package in accordance with some embodiments.

[0014] Figures 5A-5F is a cross-sectional view illustrating various stages of a process of forming a chip package in accordance with some embodiments.

[0015] Figures 6A-6B is a cross-sectional view illustrating various stages of a process of forming a chip package in accordance with some embodiments.

[0016] Figures 7A-7I is a cross-sectional view illustrating various stages of a process of forming a chip package according to some embodiments.

[0017] Figure 8 is a top view illustrating stages of a process of forming a chip package according to some embodiments.

[0018] Figure 9 is a top view illustrating stages of a process of forming a chip package according to some embodiments.

[0019] Figure 10 is a top view illustrating stages of a process of forming a chip package according to some embodiments.

[0020] Figure 11 is a top view illustrating stages of a process of forming a chip package according to some embodiments.

[0021] Figure 12 is a cross-sectional view illustrating a chip package according to some embodiments.

[0022] Figure 13 is a cross-sectional view illustrating a chip package according to some embodiments.

[0023] BRIEF DESCRIPTION OF DRAWINGS

[0024] 100 - carrier substrate

[0025] 102, 136, 504 - interconnect structure

[0026] 104, 506 - insulating layer

[0027] 106, 116, 116', 137, 508 - conductive feature

[0028] 108, 108A, 108B, 134 - semiconductor die, element

[0029] 110, 122, 140, 206, 540 - bonding structure

[0030] 112 - interposer substrate

[0031] 114 - pedestal portion

[0032] 118, 120 - passivation layer

[0033] 124 - internal sidewall

[0034] 126 - recess

[0035] 128, 128', 142, 208, 542 - underfill layer

[0036] 130 - protective layer

[0037] 131, 132, 138, 502, 510 Conductive element

[0038] 133 Encapsulation structure

[0039] 202 Adhesion layer

[0040] 204 Substrate

[0041] 302 Opening

[0042] 702 Barrier element

[0043] H1, H2 Height

[0044] W1, W2 Distance DETAILED DESCRIPTION

[0045] A number of different embodiments or examples are provided below for implementing different components of the disclosure. Specific examples of components and configurations are described below to provide a thorough description of embodiments of the disclosure. These examples are, of course, merely examples and are in no way intended to limit the scope of the disclosure. For example, in describing a first component formed over a second component, the example can include embodiments where the first and second components are formed in direct contact with each other, or embodiments where additional components are formed between the first and second components such that the first and second components do not contact each other. Additionally, embodiments of the disclosure can repeat reference symbols and / or letters in various examples. This repetition of reference symbols and / or letters is for the purpose of simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0046] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing one (or more) element's or component's relationship to another (or more) element(s) or component(s) as the illustrations can appear on a printed page or in an apparatus. Such spatially relative terms can be interpreted differently when the apparatus in question is in different orientations. Thus, the spatially relative terms are intended to encompass different orientations of the apparatus and the apparatus can be rotated 90 degrees or at other orientations and the spatially relative descriptions used herein interpreted accordingly.

[0047] Some embodiments of the disclosure are discussed. In these embodiments, additional steps can be provided before, during, and / or after the stages described. Some of these stages can be replaced or eliminated for different embodiments. Additional components can be added to the semiconductor device structure. Some of the components discussed below can be replaced or eliminated for different embodiments. Although some of the embodiments discussed below are performed in a particular order, the steps can be performed in other logical order.

[0048] Other components or processes may also be included. For example, a testing structure may be included to support verification testing of 3D packaging or 3D integrated circuit (3DIC) devices. This testing structure may include, for example, a test pad formed in a cover layer or on a substrate, which allows the use of probes and / or probe cards, and similar devices, to test the 3D packaging or 3D integrated circuit device. This verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with testing methods as intermediate verification of chip yield to increase output and reduce costs.

[0049] Figures 1A-1K These are cross-sectional views illustrating various stages of the process for forming a chip package, based on some embodiments. For example... Figure 1A As shown, a carrier substrate 100 is provided or received. The carrier substrate 100 may serve as a temporary support substrate in subsequent fabrication processes. The carrier substrate 100 may comprise an insulating substrate, a semiconductor substrate, a conductive substrate, one or more other suitable substrates, or a combination thereof. In some embodiments, the carrier substrate 100 is a glass substrate, such as a glass wafer. In some other embodiments, the carrier substrate 100 is a semiconductor substrate, such as a silicon wafer. In some other embodiments, the carrier substrate 100 is a support frame, such as a metal frame.

[0050] like Figure 1A As shown, according to some embodiments, an interconnect structure 102 is formed on the carrier substrate 100. The interconnect structure 102 can be used as a redistribution structure for routing. Figure 1A As shown, the interconnect structure 102 includes multiple insulating layers 104 and multiple conductive components 106. In some embodiments, some conductive components 106 are exposed on the top surface of the top of the insulating layer 104 or protrude from the top surface of the top of the insulating layer 104. The exposed or protruding conductive components 106 may serve as bonding pads, and conductive bumps (e.g., tin-containing solder bumps) and / or conductive pillars (e.g., copper pillars) may subsequently be formed thereon.

[0051] The insulating layers 104 can be formed of or include one or more polymeric materials. The polymeric material can include polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymeric materials, or combinations of the foregoing. In some embodiments, the polymeric material is photosensitive. In some embodiments, some or all of the insulating layers 104 are formed of or include a dielectric material other than a polymeric material. The dielectric material can include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or combinations of the foregoing. The conductive features 106 can include conductive lines that provide horizontal electrical connections and conductive vias that provide vertical electrical connections. The conductive features 106 can be formed of or include copper, aluminum, gold, cobalt, titanium, graphene, one or more other suitable conductive materials, or combinations of the foregoing.

[0052] Formation of the interconnect structure 102 can include multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes. Deposition or coating processes can be used to form insulating layers and / or conductive layers. The deposition or coating processes can include spin-on processes, electroplating processes, electroless plating processes, Chemical Vapor Deposition (CVD) processes, Physical Vapor Deposition (PVD) processes, one or more other applicable processes, or combinations of the foregoing. Patterning processes can be used to pattern the formed insulating layers and / or the formed conductive layers. The patterning processes can include photolithography processes, energy beam drilling processes, etching processes, mechanical drilling processes, one or more other applicable processes, or combinations of the foregoing. Planarization processes can be used to provide a planar top surface to the formed insulating layers and / or the formed conductive layers. The planarization processes can include mechanical grinding processes, Chemical Mechanical Polish (CMP), one or more other applicable processes, or combinations of the foregoing.

[0053] However, many changes and / or modifications can be made to the embodiments of the present disclosure. In some other embodiments, the interconnect structure 102 is not formed.

[0054] As Figure 1BAs shown, according to some embodiments, a semiconductor device (e.g., semiconductor die 108) is disposed on a carrier substrate 100. The semiconductor device may comprise a single chip, multiple chips, or a system-on-integrated-circuit (SoIC) chip device. In some embodiments, multiple semiconductor dies 108 are disposed on the carrier substrate 100. The semiconductor die 108 may have a system-on-chip (SoC) chip. In some other embodiments, the element 108 is a system-on-integrated-circuit (SoIC) device comprising two or more chips with integrated functionality. In these cases, the reference numeral "108" is used to denote the semiconductor device. In some embodiments, the semiconductor die 108 is disposed on an interconnect structure 102 formed on the carrier substrate 100. In some embodiments, the semiconductor die 108 is bonded to some conductive components 106 of the interconnect structure 102 via a bonding structure 100.

[0055] In some embodiments, the bonding structure 110 is conductive. Electrical connections between device elements in the semiconductor die 108 and some conductive components 106 of the interconnect structure 102 can be formed by the bonding structure 110. In some embodiments, the bonding structure 110 is or includes solder bumps, such as tin-containing solder bumps. The tin-containing solder bumps may further comprise copper, silver, gold, aluminum, lead, one or more other suitable materials, or combinations thereof. In some embodiments, the tin-containing solder bumps do not contain lead. The formation of the bonding structure 110 may include one or more reflow processes and / or one or more electroplating processes.

[0056] In some embodiments, the bonding structure 110 includes metal pillars, such as copper pillars. The formation of the bonding structure 110 may include an electroplating process or an electroless plating process. In some embodiments, a tin-containing soldering material may be formed between the bonding structure 110 and some conductive components 106 of the interconnect structure 102.

[0057] like Figure 1C As shown, according to some embodiments, an interposer substrate 112 is disposed on a carrier substrate 100. In some embodiments, the interposer substrate 112 is disposed on an interconnect structure 102 formed on the carrier substrate 100. In some embodiments, the interposer substrate 112 is bonded to some conductive components 106 of the interconnect structure 102 via a bonding structure 122. The material and formation method of the bonding structure 122 may be the same as or similar to the material and formation method of the bonding structure 110.

[0058] In some embodiments, the interposer substrate 112 includes a base portion 114 and a plurality of conductive components 116. The base portion 114 can be formed of or include one or more insulating materials, one or more semiconductor materials, one or more other suitable materials, or combinations of the foregoing. In some embodiments, the base portion 114 includes a high molecular material (e.g., an epoxy-based resin) with fillers dispersed therein. In some embodiments, the fillers can include fibers, such as glass fibers. In some embodiments, the base portion 114 is a stack of multiple insulating layers.

[0059] In some embodiments, the conductive components 116 include conductive structures that pass through opposite faces of the base portion 114. In some other embodiments, the conductive components 116 include a plurality of conductive vias and conductive lines. In some other embodiments, the base portion 114 is formed of a semiconductor material (e.g., silicon). In these cases, an insulating layer (not shown) is formed between the base portion 114 and the conductive components 116.

[0060] In some embodiments, the interposer substrate 112 includes passivation layers 118 and 120 formed on opposite faces of the base portion 114. In some embodiments, the passivation layers 118 and 120 have openings that expose some of the conductive components 116. For example, the exposed conductive components 116 can be conductive pads. In some embodiments, the bonding structure 122 partially covers the passivation layer 118.

[0061] Figure 8 is a top view showing stages of a process of forming a chip package according to some embodiments. In some embodiments, Figure 8 is a top view showing stages of a process of forming a chip package according to some embodiments. In some embodiments, Figure 1C is a top view showing stages of a process of forming a chip package according to some embodiments. In some embodiments, Figure 1C , Figure 8 As shown, the interposer substrate 112 is a ring-shaped structure with a recess 126. The recess 126 passes through opposite faces of the interposer substrate 112. As shown, Figure 1C , Figure 8 As shown, the interposer substrate 112 is a ring-shaped structure with a recess 126. The recess 126 passes through opposite faces of the interposer substrate 112. As shown,

[0062] In some embodiments, the recess 126 is wider than the semiconductor die 108. In some embodiments, the recess 126 exposes a portion of the interconnect structure 102. For example, a top face of the insulating layer 104 is exposed by the recess 126.

[0063] As shown, Figure 8As shown, semiconductor die 108 has a first edge, the distance of which to the nearest inner sidewall 124 is distance W1. Semiconductor die 108 has a second edge, the distance of which to the nearest inner sidewall 124 is distance W2. In some embodiments, distances W1 and W2 are substantially the same. Distance W1 can range from about 20 micrometers (μm) to about 400 micrometers (μm). In some other embodiments, distance W1 can range from about 400 micrometers (μm) to about 1500 micrometers (μm). In some other embodiments, distances W1 and W2 are not the same.

[0064] In some embodiments, such as Figure 8 As shown, the top view of the recess 126 is rectangular. In some other embodiments, the top view of the recess 126 has a shape other than rectangular. The shape of the top view of the recess 126 may include square, elliptical, circular, or other suitable shapes.

[0065] In some embodiments, the semiconductor die 108 is higher than the interposer substrate 112. The top surface of the semiconductor die 108 is disposed at a height higher than the top surface of the interposer substrate 112. In some other embodiments, the semiconductor die 108 is higher than the interposer substrate 112. The top surface of the semiconductor die 108 is disposed at the same height as the top surface of the interposer substrate 112.

[0066] Many variations and / or modifications can be made to the embodiments of this disclosure. Although the interposer substrate 112 is disposed on the interconnect structure 102 after the semiconductor die 108 is processed, the embodiments of this disclosure are not limited thereto. In some other embodiments, the interposer substrate 112 is disposed on the interconnect structure 102 before the semiconductor die 108 is disposed. For example, the interposer substrate has a plurality of pre-formed grooves. The semiconductor die is then disposed on the interconnect structure. Each semiconductor die can be picked up and placed onto the corresponding area of ​​the interconnect structure surrounded by the groove.

[0067] like Figure 1D As shown, according to some embodiments, an underfill layer 128 is formed between the semiconductor die 108 and the interconnect structure 102. The underfill layer 128 surrounds and protects the bonding structure 110. In some embodiments, the underfill layer 128 is in direct contact with the bonding structure 110. In some embodiments, the underfill layer 128 extends laterally to the bonding structure 122. In some embodiments, the underfill layer 128 also surrounds and protects the bonding structure 122. In some embodiments, the underfill layer 128 is in direct contact with the bonding structure 122.

[0068] In some embodiments, the primer layer 128 is formed of or comprises a polymeric material. The primer layer 128 may comprise an epoxy-based resin. In some embodiments, the primer layer 128 comprises fillers dispersed within the epoxy-based resin. In some embodiments, the primer layer 128 is softer than the base portion 114 of the interposer substrate 112. In some embodiments, the filler concentration in the base portion 114 is greater than the filler concentration in the primer layer 128. In some embodiments, each filler in the base portion 114 is longer than each filler in the primer layer 128. For example, the filler in the base portion 114 is fiber, while the filler in the primer layer 128 is particle. In some embodiments, the formation of the primer layer 128 includes injection, spin-coating, dispensing, film lamination, application, one or more other applicable processes, or a combination thereof. In some embodiments, a thermal curing process is used during the formation of the base layer 128.

[0069] like Figure 1E As shown, according to some embodiments, a protective layer 130 is formed at... Figure 1D The structure shown is above the substrate. In some embodiments, the protective layer 130 extends into the recess 126 to surround and protect the semiconductor die 108. In some embodiments, the protective layer 130 is in direct contact with the semiconductor die 108. In some embodiments, the protective layer 130 is in direct contact with the interposer substrate 112. In some embodiments, the protective layer 130 is formed of or comprises a molding compound material. The molding compound material may comprise a polymeric material, such as an epoxy resin having fillers dispersed therein. In some embodiments, the protective layer 130 is softer than the base portion 114 of the interposer substrate 112. In some embodiments, the filler concentration in the base portion 114 is greater than the filler concentration in the protective layer 130. In some embodiments, each filler in the base portion 114 is longer than each filler in the protective layer 130. For example, the filler in the base portion 114 is fiber, while the filler in the protective layer 130 is particle.

[0070] In some embodiments, a liquid-molded composite material is applied over the interposer substrate 112 and the semiconductor die 108. The liquid-molded composite material can flow into the recess 126 to encapsulate the semiconductor die 108. A thermal process is then used to cure the liquid-molded composite material and convert it into a protective layer 130.

[0071] like Figure 1F As shown, according to some embodiments, the protective layer 130 is thinned to expose the conductive component 116. In some embodiments, a passivation layer 120 is also exposed after the protective layer 130 is thinned. A mechanical polishing process can be used to thin the protective layer 130. In some embodiments, an exposure molding process or a dispensing process is used to form the protective layer 130. In the exposure molding process, the conductive component 116 is protected by a mold during the injection molding of the composite material to form the protective layer 130. The protective layer 130 does not cover the conductive component 116. In these cases, because the conductive component 116 is already exposed, a thinning process may not be performed.

[0072] Then, as Figure 1F As shown, according to some embodiments, a conductive element 131 is formed on the conductive component 116 of the interposer substrate 112. In some embodiments, the conductive element 131 is a solder bump. In some embodiments, the conductive element 131 is or comprises a tin-containing solder bump. The tin-containing solder bump may further comprise copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination thereof. In some embodiments, the tin-containing solder bump does not contain lead. In some embodiments, the conductive element 131 may comprise one or more reflow processes and / or one or more electroplating processes.

[0073] Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, such as Figure 1E The protective layer 130 shown is not thinned to expose the conductive component 116. In some embodiments, an opening is then formed in the protective layer 130 to expose the conductive component 116. A conductive element 131 is then formed over the exposed conductive component 116. The conductive element 131 may be entirely within the opening formed in the protective layer 130. In these cases, the top surface of the conductive element 131 is lower than the top surface of the protective layer 130. In some other embodiments, each conductive element 131 has a height greater than the depth of the opening formed in the protective layer 130. In these cases, the conductive element 131 protrudes from the top surface of the protective layer 130.

[0074] Many changes and / or modifications can be made to embodiments of the present disclosure. In some other embodiments, the conductive elements 131 are formed before the interconnect structure 102 is disposed on the interposer substrate 112.

[0075] As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures. Figure 1G Figure 1F As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures. Figure 1F As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures.

[0076] As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures. Figure 1H As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures.

[0077] Figure 1I As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures. Figure 1H Figure 1I As shown in FIG. 1 1 1, according to some embodiments, the structure shown in FIG. 1 10 is flipped upside down and bonded to a package structure 133. In some embodiments, before being bonded to the package structure 133, the structure shown in FIG. 1 10 is cut to form a plurality of independent package structures.

[0078] ​​​Package structure 133 may include element 134, interconnect structure 136, and conductive element 138. In some embodiments, element 134 is a semiconductor die. The semiconductor die may include multiple dynamic random access memory (DRAM) devices, flash memory devices, solid-state random access memory (SRAM) devices, passive devices, radio frequency module devices, other suitable devices, or combinations thereof. In some embodiments, element 134 includes the semiconductor die and a package layer encapsulating the semiconductor die. The semiconductor die may include multiple dynamic random access memory (DRAM) devices, flash memory devices, solid-state random access memory (SRAM) devices, passive devices, radio frequency module devices, other suitable devices, or combinations thereof.

[0079] The structure, material, and forming method of interconnect structure 136 may be the same as or similar to the structure, material, and forming method of interconnect structure 102. For example, interconnect structure 136 includes a plurality of conductive lines and / or conductive vias. The material and forming method of conductive element 138 may be the same as or similar to the material and forming method of conductive element 132.

[0080] like Figure 1J As shown, according to some embodiments, the stacked package structure 133 is bonded to the interposer substrate 112. In some embodiments, the package structure 133 extends beyond the semiconductor die 108. In some embodiments, the package structure 133 extends beyond the protective layer 130 of the filling recess 126.

[0081] In some embodiments, the package structure 133 and the interposer substrate 112 are bonded via a bonding structure 140. One or more reflow processes can be used to form the bonding structure 140. In the aforementioned reflow process, conductive elements 131 and 138 (such as...) can be bonded together. Figure 1I (As shown) they are fused together to form a joint structure 140. Each joint structure 140 may include a weld material portion and a bonding pad. A bonding pad may be formed between the weld material portion and the interconnect structure 136.

[0082] Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, the package structure 133 is not stacked on the interposer substrate 112. In some other embodiments, the package structure 133 is not provided.

[0083] likeFigure 1K As shown, a base layer 142 is formed to surround and protect the bonding structure 140. The material and method of forming the base layer 142 may be the same as or similar to the material and method of forming the base layer 128.

[0084] Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, the primer layer 128 is not formed.

[0085] Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, the primer layer 128, the protective layer 130, and the primer layer 142 are not formed.

[0086] Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, a protective material layer is formed after bonding the package structure 133 to the interposer substrate 112. The protective material layer surrounds the bonding structure 140, the semiconductor die 108, and the bonding structures 122 and 110. In some embodiments, the protective material layer having portions surrounding the bonding structure and the semiconductor die is formed in a single forming process. The portion of the protective material layer surrounding the bonding structure may serve as an undercoat layer. The portion of the protective material layer surrounding the semiconductor die may serve as a protective layer.

[0087] Figures 2A-2D These are cross-sectional views illustrating various stages of the process for forming a chip package, based on some embodiments. For example... Figure 2A As shown, accepting or forming something similar to Figure 1C The structure is shown. In some embodiments, the semiconductor die 108 is higher than the interposer substrate 112. In some embodiments, the top surface of the semiconductor die 108 is disposed at a height higher than the top surface of the interposer substrate 112.

[0088] like Figure 2A As shown, the interposer substrate 112 has a height H1, while the semiconductor die has a height H2. In some embodiments, the height H2 is greater than the height H1. The height H1 of the interposer substrate 112 can range from about 20 micrometers (μm) to about 300 micrometers (μm).

[0089] like Figure 2B As shown, according to some embodiments, an undercoat layer 128 is formed to protect the bonding structures 110 and 122. Figure 2B The material and forming method of the base adhesive layer 128 shown can be compared with... Figure 1D The material and formation method of the base layer 128 shown are the same or similar. In some embodiments, such as Figure 2B As shown, the adhesive layer 128 extends upward to partially or completely fill the groove 126 surrounded by the inner sidewall 124 of the interposer substrate 112. In these cases, the adhesive layer 128 may also serve as a protective layer for the semiconductor die 108. In some embodiments, such asFigure 2B As shown, the top surface of the semiconductor die 108 is higher than the top surface of the underfill layer 128.

[0090] As shown, the top surface of the semiconductor die 108 is higher than the top surface of the underfill layer 128. Figure 2C As shown, similar to the embodiment shown in FIG. 1, the semiconductor die 108 is bonded to the package structure 133 according to some embodiments. The physical and electrical connections between the semiconductor die 108 and the package structure 133 are established through the interconnect structure 102. Figure 1J As shown, according to some embodiments, the package structure 133 is bonded to the interposer substrate 112 using a bonding structure 140. The material and formation method of the bonding structure 140 can be the same as or similar to the material and formation method of the bonding structure 122. In some embodiments, the interposer substrate 112 is a printed circuit board. In some embodiments, the interposer substrate 112 is a semiconductor substrate having conductive features formed thereon.

[0091] As shown, according to some embodiments, an adhesive layer 202 is used to increase the adhesion between the semiconductor die 108 and the package structure 133. The adhesive layer 202 can be a die attachment film (DAF). In some embodiments, the adhesive layer 202 is formed on the semiconductor die 108 before the package structure 133 and the interposer substrate 112 are bonded by the bonding structure 140. In some other embodiments, the adhesive layer 202 is formed on the package structure 133 before the package structure 133 and the interposer substrate 112 are bonded. Figure 2C Many changes and / or modifications can be made to the embodiments of the present disclosure. In some other embodiments, the adhesive layer 202 is not formed.

[0092] As shown, according to some embodiments, the structure shown in FIG. 2 is bonded to a substrate 204 through a bonding structure 206. The material and formation method of the bonding structure 206 can be the same as or similar to the material and formation method of the bonding structure 122. In some embodiments, the substrate 204 is a printed circuit board. In some embodiments, the substrate 204 is a semiconductor substrate having conductive features formed thereon.

[0093] Figure 2D As shown, according to some embodiments, an underfill layer 208 is formed on the substrate 204 to surround and protect the bonding structure 206. The material and formation method of the underfill layer 208 can be the same as or similar to the material and formation method of the underfill layer 128. In some embodiments, the underfill layer 208 extends upward to cover the sidewalls of the interconnect structure 102. In some embodiments, the underfill layer 208 extends upward to cover the sidewalls of the underfill layer 128. In some embodiments, the underfill layer 208 extends upward to partially cover the sidewalls of the interposer substrate 112. Figure 2C

[0094] In some embodiments, as shown in FIG. 3, an underfill layer 208 is formed on the substrate 204 to surround and protect the bonding structure 206. The material and formation method of the underfill layer 208 can be the same as or similar to the material and formation method of the underfill layer 128. In some embodiments, the underfill layer 208 extends upward to cover the sidewalls of the interconnect structure 102. In some embodiments, the underfill layer 208 extends upward to cover the sidewalls of the underfill layer 128. In some embodiments, the underfill layer 208 extends upward to partially cover the sidewalls of the interposer substrate 112. Figure 2D

[0095] Figures 3A-3E ​​​These are cross-sectional views illustrating various stages of the process for forming a chip package, based on some embodiments. For example... Figure 3A As shown, receiving or providing similar Figure 1E The structure is shown. In some embodiments, the semiconductor die 108 is at the same height as the interposer substrate 112. However, the embodiments of this disclosure are not limited thereto. In some other embodiments, similar to Figure 2A In the illustrated embodiment, the semiconductor die 108 is above the interposer substrate 112. In these cases, the distance between the top surface of the semiconductor die 108 and the interconnect structure 102 is greater than the distance between the top surface of the interposer substrate 112 and the interconnect structure 102.

[0096] Then, as Figure 3A As shown, according to some embodiments, an opening 302 is formed in the protective layer 130 to partially expose the conductive component 116. The opening 302 can be formed using energy beam drilling, mechanical drilling, photolithography, etching, one or more other applicable processes, or a combination thereof.

[0097] like Figure 3A As shown, according to some embodiments, a conductive element 131 is formed on the exposed conductive component 116 of the interposer substrate 112. Figure 3A The material and forming method of the conductive element 131 shown can be compared with those of the conductive element 131 shown. Figure 1F The conductive elements 131 shown are made of the same or similar materials and are formed using the same method. In some other embodiments, each conductive element 131 is disposed in a corresponding opening 302. In some other embodiments, a portion of the conductive element 302 protrudes from the opening 302 (not shown). In these cases, the top surface of the conductive element 302 is higher than the top surface of the protective layer 130.

[0098] like Figure 3B As shown, according to some embodiments, it is inverted from top to bottom. Figure 3A The structure shown is then used to remove the carrier substrate 100 to expose some conductive components 106. In some embodiments, the carrier substrate 100 is flipped from top to bottom before removal. Figure 3A The structure shown is attached to a second carrier substrate (not shown). The second carrier substrate may be a carrier tape frame. Then, as... Figure 3C As shown, according to some embodiments, a conductive element 132 is formed on the exposed conductive component 106. Figure 3C The material and forming method of the conductive element 132 shown can be compared with those of the conductive element 132 shown. Figure 1H The conductive element 132 shown is made of the same or similar material and is formed by the same or similar method.

[0099] likeFigure 3D As shown, according to some embodiments, similar to Figure 1I The illustrated embodiment is inverted from top to bottom. Figure 3C The structure shown is to the packaging structure 133.

[0100] like Figure 3E As shown, according to some embodiments, similar to Figure 1J In the illustrated embodiment, the package structure 133 is bonded to the interposer substrate 112 via a bonding structure 140. Subsequently, similar to... Figure 1K The illustrated embodiments, such as Figure 3E As shown, according to some embodiments, a base adhesive layer 142 is formed.

[0101] Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, the protective layer 130 is not formed. In some embodiments, an undercoat layer 142 is formed to protect the bonding structure 140. The undercoat layer 142 may fill the recess 126 surrounded by the inner sidewall 124 of the interposer substrate 112. Thus, the undercoat layer 142 may also surround the semiconductor die 108 and serve as a protective layer.

[0102] Figures 4A-4B These are cross-sectional views illustrating various stages of the process for forming a chip package, based on some embodiments. For example... Figure 4A As shown, forming a similar Figure 3E The structure of the illustrated embodiment. In some embodiments, the interposer substrate 112 includes a plurality of conductive members 116' formed in the base portion 114. In some embodiments, each conductive member 116' does not extend across the opposite side of the base portion 114.

[0103] In some embodiments, the primer layer 128 is in direct contact with the bonding structure 110. In some embodiments, the primer layer 128 is not in direct contact with the bonding structure 122. In some embodiments, the protective layer 130 is in direct contact with the bonding structure 122. In some embodiments, the protective layer 130 is not in direct contact with the bonding structure 110.

[0104] In some embodiments, the semiconductor die 108 is higher than the interposer substrate 112. The top surface of the semiconductor die 108 is positioned at a height higher than the interposer substrate 112. For example... Figure 4A As shown, the interconnect structure 136 of the package structure 133 includes a plurality of conductive components 137. Some of the conductive components 137 are electrically connected to the bonding structure 140.

[0105] like Figure 4B As shown, similar to Figure 2D The illustrated embodiment, according to some embodiments, is joined by the joining structure 206. Figure 4AThe structure shown is attached to the substrate 204. In some embodiments, an adhesive layer 208 is formed to protect the bonding structure 206.

[0106] Figures 5A-5F These are cross-sectional views illustrating various stages of the process for forming a chip package, based on some embodiments. For example... Figure 5A As shown, receiving or providing similar Figure 1E The structure shown is illustrated. In some embodiments, the semiconductor die 108 is above the interposer substrate 112. However, the embodiments of this disclosure are not limited thereto. In some other embodiments, similar to... Figure 2A In the embodiment shown, the semiconductor die 108 is above the interposer substrate 112.

[0107] After that, as Figure 5A As shown, according to some embodiments, an opening is formed in the protective layer 130 to partially expose the conductive component 116. Similar to the opening 302, the opening can be formed using energy beam drilling, mechanical drilling, photolithography, etching, one or more other applicable processes, or a combination thereof.

[0108] After that, as Figure 5A As shown, according to some embodiments, a conductive element 502 is formed on the exposed conductive component 116 to fill the opening formed in the protective layer 130. In some embodiments, the conductive element 502 is a conductive pillar. In some embodiments, the top surface of the conductive element 502 is substantially coplanar with the top surface of the protective layer 130. In some embodiments, a planarization process may be used to ensure that the top surface of the conductive element 502 is substantially coplanar with the top surface of the protective layer 130. The planarization process may include mechanical polishing, chemical mechanical polishing (CMP), one or more other applicable processes, or a combination thereof.

[0109] The conductive element 502 may be formed from or comprise copper, gold, cobalt, aluminum, platinum, graphene, one or more other suitable conductive materials, or combinations thereof. The conductive element 502 may be formed using electroplating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), printing, one or more other applicable processes, or combinations thereof.

[0110] like Figure 5BAs shown, according to some embodiments, an interconnect structure 504 is formed over the protective layer 130 and the conductive elements 502. The interconnect structure 504 can include an insulating layer 506 and a plurality of conductive components 508. The insulating layer 506 can include multiple sub-layers. The materials and formation methods of the interconnect structure 504 can be the same as or similar to those of the interconnect structure 102.

[0111] Thereafter, as shown, according to some embodiments, conductive elements 510 are formed over some of the conductive components 508 of the interconnect structure 504. Figure 5B The materials and formation methods of the conductive elements 510 can be the same as or similar to those of the conductive elements 131 shown in Figure 1F In some embodiments, a majority of the bottom surface of the interconnect structure 504 is in direct contact with a film layer of the same material (i.e., the protective layer 130). In some embodiments, both the protective layer 130 and the insulating layer 506 are formed of the same or similar polymer materials. Thus, the protective layer 130 and the insulating layer 506 have similar thermal expansion coefficients. As a result, the interconnect structure 504 can sustain less thermal stress during subsequent thermal processes. The quality and reliability of the interconnect structure 504 can be ensured.

[0112] As shown, according to some embodiments, the structure shown in Figure 5C is flipped upside down and bonded onto a package structure 133. Figure 5B In some embodiments, the structure shown in Figure 5B is flipped upside down onto a second carrier substrate (not shown) before the carrier substrate 100 is removed. The second carrier substrate can be a carrier tape frame.

[0113] Thereafter, as shown, according to some embodiments, conductive elements 132 are formed over the exposed conductive components 106. Figure 5D The materials and formation methods of the conductive elements 132 can be the same as or similar to those of the conductive elements 131 shown in Figure 5D . Figure 1H

[0114] As shown, similar to the embodiments shown in Figure 5E , according to some embodiments, the structure shown in Figure 1I is flipped upside down and bonded onto a package structure 133. Figure 5D The materials and formation methods of the conductive elements 132 can be the same as or similar to those of the conductive elements 131 shown in

[0115] As shown, similar to the embodiments shown in Figure 5F , according to some embodiments, the structure shown in Figure 1J ​The illustrated embodiment, according to some embodiments, involves bonding the package structure 133 to the interposer substrate 112 via a bonding structure 540. In some embodiments, a reflow process can be used to fuse the aligned conductive elements 138 and 510 together. Thus, the bonding structure 540 is formed. The material and formation method of the bonding structure 540 can be compared with... Figure 1J The materials and forming methods of the shown joint structure 140 are the same or similar.

[0116] After that, similar to Figure 1K The illustrated embodiments, such as Figure 5F As shown, according to some embodiments, an adhesive base layer 542 is formed to protect the bonding structure 540. The material and formation method of the adhesive base layer 542 can be compared with... Figure 1K The material and formation method of the base layer 142 shown are the same or similar.

[0117] Figures 6A-6B These are cross-sectional views illustrating various stages of the process for forming a chip package, based on some embodiments. For example... Figure 6A As shown, forming a similar Figure 5F The structure of the embodiment shown is illustrated. In some embodiments, the interposer substrate 112 includes a plurality of conductive members 116' formed in the base portion 114. In some embodiments, the interposer substrate 112 also includes conductive elements 502. The conductive elements 502 may be conductive vias. In some embodiments, each conductive member 116' does not penetrate the opposite side of the base portion 114.

[0118] In some embodiments, the primer layer 128 is in direct contact with the bonding structure 110. In some embodiments, the primer layer 128 is not in direct contact with the bonding structure 122. In some embodiments, the protective layer 130 is in direct contact with the bonding structure 122. In some embodiments, the protective layer 130 is not in direct contact with the bonding structure 110.

[0119] In some embodiments, the semiconductor die 108 is higher than the interposer substrate 112. The top surface of the semiconductor die 108 is positioned at a height higher than the interposer substrate 112. For example... Figure 6A As shown, the interconnect structure 136 of the package structure 133 includes a plurality of conductive components 137. Some of the conductive components 137 are electrically connected to the bonding structure 540.

[0120] In some embodiments, the protective layer 130 covers the top surface of the interposer substrate 112 and the semiconductor die 108, and an interconnect structure 504 is formed on the protective layer 130. Direct contact between the interconnect structure 504 and the interfaces between the semiconductor die 108 and the protective layer 130, which may have high stress, is avoided. Therefore, the interconnect structure 504 can have preferred reliability. Routing of the conductive component 506 is not restricted.

[0121] In some other embodiments, the interconnect structure is in direct contact with the interface between the semiconductor die and the protective layer. In some cases, portions of the interconnect structure extending beyond this interface may experience higher stress. Conductive components may need to be formed away from these high-stress areas (i.e., kick-out zones) to ensure reliable electrical connections. The routing of the conductive components is thus restricted.

[0122] like Figure 6B As shown, similar to Figure 2D The illustrated embodiments are joined via a joining structure 206 according to some embodiments. Figure 6A The structure shown is attached to the substrate 204. In some embodiments, an adhesive layer 208 is formed to protect the bonding structure 206.

[0123] Figures 7A to 7I are cross-sectional views illustrating various stages of a process for forming a chip package according to some embodiments. As shown in Figure 7A, receiving or forming a process similar to... Figure 1A The structure shown.

[0124] like Figure 7B As shown, according to some embodiments, a barrier element 702 is formed on the interconnect structure 102. In some embodiments, the barrier element 702 is a ring structure that continuously surrounds the bonding structure 110 and the semiconductor die 108. The barrier element 702 may be formed of an insulating material, a conductive material, a semiconductor material, or a combination thereof. In some embodiments, the barrier element 702 is formed of or comprises a photosensitive polymer material. In some embodiments, a photosensitive polymer material is formed on the interconnect structure 102. Then, a photolithography process is used to pattern this photosensitive polymer material layer. Thus, a barrier element 702 with the desired pattern is formed.

[0125] After that, similar to Figure 1B The illustrated embodiments, such as Figure 7B The diagram illustrates the picking and placing of semiconductor dies 108 onto interconnect structure 102 according to some embodiments. In some embodiments, semiconductor dies 108 are bonded to interconnect structure 102 via bonding structure 110.

[0126] like Figure 7C As shown, according to some embodiments, an undercoat layer 128' is formed between the semiconductor die 108 and the interconnect structure 102 to protect the bonding structure 110. The material and formation method of the undercoat layer 128' can be compared with... Figure 1DThe materials and formation methods of the base adhesive layer 128 shown are the same or similar. In some embodiments, the material used to form the base adhesive layer 128' (e.g., liquid polymer material) is limited in the surrounded area due to the barrier element 702. This prevents some conductive components 106 from being covered by the base adhesive layer 128', which is beneficial for subsequent bonding processes.

[0127] like Figure 7D As shown, similar to Figure 1C In the illustrated embodiment, according to some embodiments, an interposer substrate 112 is disposed on the interconnect structure 102. The interposer substrate 112 is bonded to the interconnect structure 102 via a bonding structure 122. Because the adhesive layer 128' is blocked by the barrier element 702 without covering the exposed conductive parts 106, the formation of the bonding structure 122 is easier to perform.

[0128] Figure 9 This is a top view illustrating the process stages of forming a chip package according to some embodiments. In some embodiments, Figure 9 Show Figure 7D The top view of the structure shown. The inner sidewall 124 of the interposer substrate 112 surrounds the recess 126. The recess 126 surrounds the semiconductor die 108. The recess 126 also exposes the undercoat layer 128', the barrier element 702, and the interconnect structure 102. Figure 9 As shown, the barrier element 702 has a ring structure surrounding the semiconductor die 108. The undercoat layer 128' is confined within the region surrounded by the barrier element 702. The barrier element 702 may also be formed in the embodiments shown in Figures 1, 2, 3, 4, 5, and / or 6.

[0129] like Figure 7E As shown, similar to Figure 1E The illustrated embodiment, according to some embodiments, forms a protective layer 130. Subsequently, similar to... Figure 1F The illustrated embodiments, such as Figure 7F As shown, according to some embodiments, the protective layer 130 is thinned to expose the conductive component 116. In some other embodiments, an exposure molding process or a dispensing process is used to form the protective layer 130. In the exposure molding process, the conductive component 116 is protected by a mold during the injection molding of the composite material to form the protective layer 130. The protective layer 130 does not cover the conductive component 116. In these cases, since the conductive component 116 is already exposed, a thinning process is not required. A conductive element 131 is then formed on top of the exposed conductive component 116.

[0130] like Figure 7GAs shown, similar to the embodiment shown in FIGS. 1G-1H, according to some embodiments, the carrier substrate 100 is removed, and the conductive element 132 is formed.

[0131] As shown, similar to the embodiments shown in FIGS. 1I and 1J, according to some embodiments, the package structure 133 is bonded to the interposer substrate 112 by the bonding structure 140. In some embodiments, similar to the embodiment shown in FIG. 1K, an adhesive layer 202 is formed to improve the adhesion between the semiconductor die 108 and the package structure 133. In some embodiments, the adhesive layer 202 is formed of or includes one or more materials having high thermal conductivity. In some embodiments, the adhesive layer 202 having high thermal conductivity has the same size of area as the top surface of the semiconductor die 108. Thus, the heat generated during the operation of the device elements in the semiconductor die 108 can be more efficiently dissipated. In some embodiments, the adhesive layer 202 having high thermal conductivity has a size of area larger than the top surface of the semiconductor die 108. Thus, it is ensured that the top surface of the semiconductor die 108 is completely covered by the adhesive layer 202. Figure 7H Figure 2C As shown, similar to the embodiments shown in FIGS. 1I and 1J, according to some embodiments, the package structure 133 is bonded to the interposer substrate 112 by the bonding structure 140. In some embodiments, similar to the embodiment shown in FIG. 1K, an adhesive layer 202 is formed to improve the adhesion between the semiconductor die 108 and the package structure 133. In some embodiments, the adhesive layer 202 is formed of or includes one or more materials having high thermal conductivity. In some embodiments, the adhesive layer 202 having high thermal conductivity has the same size of area as the top surface of the semiconductor die 108. Thus, the heat generated during the operation of the device elements in the semiconductor die 108 can be more efficiently dissipated. In some embodiments, the adhesive layer 202 having high thermal conductivity has a size of area larger than the top surface of the semiconductor die 108. Thus, it is ensured that the top surface of the semiconductor die 108 is completely covered by the adhesive layer 202.

[0132] However, embodiments of the present disclosure are not limited thereto, and in some embodiments, the adhesive layer 202 is not formed.

[0133] As shown, similar to the embodiments shown in FIGS. 1I and 1J, according to some embodiments, the package structure 133 is bonded to the interposer substrate 112 by the bonding structure 140. In some embodiments, similar to the embodiment shown in FIG. 1K, an adhesive layer 202 is formed to improve the adhesion between the semiconductor die 108 and the package structure 133. In some embodiments, the adhesive layer 202 is formed of or includes one or more materials having high thermal conductivity. In some embodiments, the adhesive layer 202 having high thermal conductivity has the same size of area as the top surface of the semiconductor die 108. Thus, the heat generated during the operation of the device elements in the semiconductor die 108 can be more efficiently dissipated. In some embodiments, the adhesive layer 202 having high thermal conductivity has a size of area larger than the top surface of the semiconductor die 108. Thus, it is ensured that the top surface of the semiconductor die 108 is completely covered by the adhesive layer 202. Figure 7I Figure 1K As shown, similar to the embodiments shown in FIGS. 1I and 1J, according to some embodiments, the package structure 133 is bonded to the interposer substrate 112 by the bonding structure 140. In some embodiments, similar to the embodiment shown in FIG. 1K, an adhesive layer 202 is formed to improve the adhesion between the semiconductor die 108 and the package structure 133. In some embodiments, the adhesive layer 202 is formed of or includes one or more materials having high thermal conductivity. In some embodiments, the adhesive layer 202 having high thermal conductivity has the same size of area as the top surface of the semiconductor die 108. Thus, the heat generated during the operation of the device elements in the semiconductor die 108 can be more efficiently dissipated. In some embodiments, the adhesive layer 202 having high thermal conductivity has a size of area larger than the top surface of the semiconductor die 108. Thus, it is ensured that the top surface of the semiconductor die 108 is completely covered by the adhesive layer 202.

[0134] Many changes and / or modifications can be made to embodiments of the present disclosure. In some embodiments, two or more semiconductor dies can be picked and placed onto the conductive features 106 exposed by the same recess 126.

[0135] Figure 10 is a top view showing stages of a process of forming a chip package according to some embodiments. In some embodiments, Figure 10 is a top view showing the embodiments shown in FIGS. 1, 2, 3, 4, 5, 6, and / or 7. In some embodiments, two or more semiconductor dies (e.g., semiconductor dies 108A and 108B) are surrounded by the inner sidewalls of the interposer substrate 112. In some other embodiments, one or each of the elements 108A and 108B is a semiconductor device including a chip, multiple chips, or a system-on-integrated-circuit (SoIC) chip device. Thus, the reference symbols “108A and 108B” can also be used to represent the semiconductor devices.

[0136] ​​Many changes and / or modifications can be made to the embodiments of the present disclosure. Figure 11 is a top view showing process stages of forming a chip package according to some embodiments. In some embodiments, the inner sidewall 124 of the interposer substrate 112 surrounds an elliptical area. In some other embodiments, the area surrounded by the inner sidewall 124 of the interposer substrate 112 can be square, circular, or other similar shape. In some embodiments, the inner sidewall 124 of the interposer substrate 112 is an inclined sidewall. Figure 11 is a top view showing the embodiments shown in FIGS. 1, 2, 3, 4, 5, 6, and / or 7.

[0137] Many changes and / or modifications can be made to the embodiments of the present disclosure. For example, the inner sidewall 124 of the interposer substrate 112 can be an inclined sidewall.

[0138] Figure 12 is a cross-sectional view showing a chip package according to some embodiments. As shown, a structure similar to that shown in Figure 12 is formed. In some embodiments, as shown, the inner sidewall 124 is an inclined sidewall. The recess 126 widens along a direction from the bottom of the interposer substrate 112 toward the top. The inner sidewall 124 of each of the embodiments shown in FIGS. 1-7 can be modified to be an inclined sidewall. Figure 4B Figure 12 is a cross-sectional view showing a chip package according to some embodiments. As shown, a structure similar to that shown in

[0139] is formed. In some embodiments, as shown, the inner sidewall 124 is an inclined sidewall. The recess 126 narrows along a direction from the bottom of the interposer substrate 112 toward the top. Figure 13 Figure 13 Embodiments of the present disclosure form a chip package with an interposer substrate. The interposer substrate and a semiconductor die are bonded onto a redistribution structure. The interposer substrate is a ring-shaped structure that surrounds the semiconductor die. The semiconductor die is higher than or above the interposer substrate. The semiconductor die is not stacked on the interposer substrate, and is partially surrounded by the interposer substrate. The overall height of the chip package is reduced, which can facilitate subsequent bonding with other packaging structures. Figure 4B Figure 13 Many changes and / or modifications can be made to the embodiments of the present disclosure. For example, the inner sidewall 124 of the interposer substrate 112 can be an inclined sidewall.

[0140] Embodiments of the present disclosure form a chip package with an interposer substrate. The interposer substrate and a semiconductor die are bonded onto a redistribution structure. The interposer substrate is a ring-shaped structure that surrounds the semiconductor die. The semiconductor die is higher than or above the interposer substrate. The semiconductor die is not stacked on the interposer substrate, and is partially surrounded by the interposer substrate. The overall height of the chip package is reduced, which can facilitate subsequent bonding with other packaging structures.

[0141] ​​A method of forming a chip package is provided according to some embodiments. The method includes disposing a semiconductor die on a carrier substrate. The method also includes disposing a interposer substrate on the carrier substrate. The interposer substrate has a recess that passes through opposite faces of the interposer substrate. The interposer substrate has an inner sidewall that surrounds the semiconductor die, and the semiconductor die is level with or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure on the interposer substrate. In some embodiments, where the protective layer covers the interposer substrate and the semiconductor die, and the method further includes forming an opening in the protective layer to expose a conductive feature of the interposer substrate, and forming a conductive element on the conductive feature of the interposer substrate. In some embodiments, the method further includes forming an interconnect structure on the carrier substrate before disposing the semiconductor die and the interposer substrate on the carrier substrate. In some embodiments, where the protective layer overfills the recess to cover the semiconductor die, and the method further includes forming a second interconnect structure on the protective layer before stacking the package structure on the interposer substrate, and bonding the package structure to the second interconnect structure. In some embodiments, where the second interconnect structure does not directly contact an interface between the semiconductor die and the protective layer. In some embodiments, where the semiconductor die is disposed on the interconnect structure before disposing the interposer substrate on the interconnect structure. In some embodiments, the method further includes forming a plurality of conductive bumps on a surface of the interconnect structure after removing the carrier substrate, where the surface of the interconnect structure originally faces the carrier substrate. In some embodiments, where the package structure extends beyond the semiconductor die. In some embodiments, the method further includes disposing a second semiconductor die on the carrier substrate, where the inner sidewall of the interposer substrate surrounds the second semiconductor die. In some embodiments, where the interposer substrate is a printed circuit board.

[0142] A method of forming a chip package is provided according to some embodiments. The method includes forming a first redistribution structure over a carrier substrate and bonding a semiconductor die to the first redistribution structure. The method also includes bonding an interposer substrate to the first redistribution structure. The interposer substrate has a ring-shaped structure surrounding the semiconductor die, and the semiconductor die is level or higher than the interposer substrate. The method further includes forming a protective layer to surround the semiconductor die. A portion of the protective layer is between the interposer substrate and the semiconductor die. In addition, the method includes removing the carrier substrate and bonding a package structure over the interposer substrate. The semiconductor die is between the package structure and the first redistribution structure. In some embodiments, the method further includes, after removing the carrier substrate and before bonding the package structure over the interposer substrate, forming a plurality of conductive bumps over the first redistribution structure, where the first redistribution structure is between the conductive bumps and the semiconductor die. In some embodiments, the method further includes, before bonding the package structure over the interposer substrate, thinning the protective layer to expose the interposer substrate. In some embodiments, the method further includes forming a conductive element in the protective layer, where the conductive element is electrically connected to a conductive part of the interposer substrate. In some embodiments, the method further includes forming a second redistribution structure over the protective layer, where a portion of the protective layer is between the second redistribution structure and the semiconductor die.

[0143] A chip package is provided according to some embodiments. The chip package includes a first redistribution structure and a semiconductor device bonded over the first redistribution structure. The chip package also includes an interposer substrate bonded over the first redistribution structure. The interposer substrate has an inner sidewall surrounding the semiconductor device, and the semiconductor device is level or higher than the interposer substrate. The chip package further includes a protective layer surrounding the semiconductor device. In addition, the chip package includes a second redistribution structure over the protective layer. A first conductive part of the second redistribution structure is electrically connected to a second conductive part of the interposer substrate. In some embodiments, a portion of the protective layer is between the second redistribution structure and the semiconductor device. In some embodiments, the chip package further includes a second semiconductor device bonded over the first redistribution structure, where the inner sidewall of the interposer substrate surrounds the second semiconductor device. In some embodiments, the chip package further includes a package structure bonded to the second redistribution structure. In some embodiments, the inner sidewall of the interposer structure is a sloped sidewall.

[0144] A chip package is provided according to some embodiments. The chip package includes a first redistribution structure, and a semiconductor device bonded over the first redistribution structure. The chip package also includes an interposer substrate bonded over the first redistribution structure. The interposer substrate has an inner sidewall surrounding the semiconductor device, and the semiconductor device is level or higher than the interposer substrate. The chip package further includes a protective layer surrounding the semiconductor device and the second redistribution structure over the protective layer. A first conductive component of the second redistribution structure is electrically connected to a second conductive component of the interposer substrate.

[0145] The foregoing outlines some embodiments of the present disclosure so that those skilled in the art can better understand the present disclosure. Those skilled in the art should appreciate that they can freely use the present disclosure as a basis for designing or modifying other processes or structures for the same purpose and / or achieve the same benefits without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that such equivalent structures do not deviate from the concept and scope of the present disclosure, and various changes, substitutions and replacements can be made herein without deviating from the concept and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined by the claims.

Claims

1. A method for forming a chip package, comprising: forming an interconnect structure over a carrier substrate; disposing a semiconductor die over the carrier substrate; forming a barrier element over the interconnect structure and around the semiconductor die; forming an underfill layer between the semiconductor die and the interconnect structure, wherein the barrier element surrounds the underfill layer; disposing a interposer substrate over the carrier substrate, wherein the interposer substrate has a base portion, a conductive member, a passivation layer, and a recess that passes through opposite faces of the interposer substrate, the recess exposes the barrier element, the interposer substrate has inner sidewalls that surround the semiconductor die, and the semiconductor die is level or higher than the interposer substrate, the passivation layer is formed on the base portion and has an opening that exposes the conductive member, the conductive member passes through opposite faces of the base portion; forming a protection layer in the recess of the interposer substrate to surround the semiconductor die and cover the semiconductor die, the interposer substrate, and the barrier element; thinning the protection layer to expose the conductive member and the passivation layer; removing the carrier substrate; stacking a package structure over the interposer substrate; and forming an adhesive layer between the semiconductor die and the package structure, wherein the package structure is wider than the adhesive layer in a normal direction of the adhesive layer.

2. The method for forming a chip package of claim 1, wherein the protection layer also covers the semiconductor die, and the method further comprises: forming a conductive element over the conductive member of the interposer substrate.

3. The method for forming a chip package of claim 1, wherein the protection layer overfills the recess to cover the semiconductor die, and the method further comprises: forming a second interconnect structure over the protection layer before stacking the package structure over the interposer substrate; and bonding the package structure to the second interconnect structure.

4. The method for forming a chip package of claim 3, wherein the second interconnect structure does not directly contact an interface between the semiconductor die and the protection layer.

5. The method for forming a chip package of claim 1, wherein the semiconductor die is disposed over the interconnect structure before the interposer substrate is disposed over the interconnect structure. forming conductive bumps over a surface of the interconnect structure after removing the carrier substrate, wherein the surface of the interconnect structure originally faces the carrier substrate.

7. The method for forming a chip package of claim 1, wherein the package structure extends beyond the semiconductor die.

6. The method of claim 1, further comprising:

8. The method for forming a chip package of claim 1, further comprising disposing a second semiconductor die over the carrier substrate, wherein the inner sidewalls of the interposer substrate surround the second semiconductor die.

9. The method for forming a chip package of claim 1, wherein the interposer substrate is a printed circuit board.

10. A method for forming a chip package, comprising: forming a first redistribution structure over a carrier substrate; bonding a semiconductor die with the first redistribution structure; ​ ​ forming a barrier element over the first redistribution structure and around the semiconductor die; forming an underfill layer between the semiconductor die and the first redistribution structure, wherein the barrier element surrounds the underfill layer; bonding an interposer substrate to the first redistribution structure, wherein the interposer substrate has a ring-shaped structure around the semiconductor die and a recess exposing the barrier element, and the semiconductor die is higher than or higher than the interposer substrate, a base portion, a conductive member, and a passivation layer formed on the base portion and having an opening exposing the conductive member, the conductive member passing through opposite surfaces of the base portion; forming a protection layer around the semiconductor die, wherein a portion of the protection layer is between the interposer substrate and the semiconductor die, the protection layer covering the semiconductor die, the interposer substrate, and the barrier element; thinning the protection layer to expose the conductive member and the passivation layer; removing the carrier substrate; bonding a package structure over the interposer substrate, wherein the semiconductor die is between the package structure and the first redistribution structure; and forming an adhesive layer between the semiconductor die and the package structure, wherein the package structure is wider than the adhesive layer in a normal direction of the adhesive layer.

11. The method of claim 10, further comprising: forming a plurality of conductive bumps over the first redistribution structure after removing the carrier substrate and before bonding the package structure over the interposer substrate, wherein the first redistribution structure is between the conductive bumps and the semiconductor die.

12. The method of claim 10, further comprising: forming a conductive element in the protection layer, wherein the conductive element is electrically connected to the conductive member of the interposer substrate.

13. The method of claim 10, further comprising: forming a second redistribution structure over the protection layer, wherein a portion of the protection layer is between the second redistribution structure and the semiconductor die.

14. A chip package, comprising: a first redistribution structure; a semiconductor device bonded over the first redistribution structure; a barrier element bonded over the first redistribution structure and around the semiconductor device; an underfill layer between the semiconductor device and the first redistribution structure, wherein the barrier element surrounds the underfill layer; an interposer substrate bonded to the first redistribution structure, wherein the interposer substrate has an inner sidewall around the semiconductor device and a recess exposing the barrier element, and the semiconductor device is higher than or higher than the interposer substrate, a base portion, a conductive member, and a passivation layer formed on the base portion and having an opening exposing the conductive member, the conductive member passing through opposite surfaces of the base portion; a protection layer around the semiconductor device and covering the semiconductor device, the interposer substrate, and the barrier element, wherein the conductive member and the passivation layer are exposed from the protection layer; a second redistribution structure over the protection layer, wherein a first conductive member of the second redistribution structure is electrically connected to a second conductive member of the interposer substrate; a package structure over the interposer substrate; and a semiconductor device bonded over the first redistribution structure; a barrier element bonded over the first redistribution structure and around the semiconductor device; an underfill layer between the semiconductor device and the first redistribution structure, wherein the barrier element surrounds the underfill layer; an interposer substrate bonded to the first redistribution structure, wherein the interposer substrate has an inner sidewall around the semiconductor device and a recess exposing the barrier element, and the semiconductor device is higher than or higher than the interposer substrate, a base portion, a conductive member, and a passivation layer formed on the base portion and having an opening exposing the conductive member, the conductive member passing through opposite surfaces of the base portion; a protection layer around the semiconductor device and covering the semiconductor device, the interposer substrate, and the barrier element, wherein the conductive member and the passivation layer are exposed from the protection layer; a second redistribution structure over the protection layer, wherein a first conductive member of the second redistribution structure is electrically connected to a second conductive member of the interposer substrate; a package structure over the interposer substrate; and a semiconductor device bonded over the first redistribution structure; a barrier element bonded over the first redistribution structure and around the semiconductor device; an underfill layer between the semiconductor device and the first redistribution structure, wherein the barrier element surrounds the underfill layer; an interposer substrate bonded to the first redistribution structure, wherein the interposer substrate has an inner sidewall around the semiconductor device and a recess exposing the barrier element, and the semiconductor device is higher than or higher than the interposer substrate, a base portion, a conductive member, and a passivation layer formed on the base portion and having an opening exposing the conductive member, the conductive member passing through opposite surfaces of the base portion; a protection layer around the semiconductor device and covering the semiconductor device, the interposer substrate, and the barrier element, wherein the conductive member and the passivation layer are exposed from the protection layer; a second redistribution structure over the protection layer, wherein a first conductive member of the second redistribution structure is electrically connected to a second conductive member of the interposer substrate; a package structure over the interposer substrate; and a bonding layer between the semiconductor device and the encapsulation structure, wherein the encapsulation structure is wider than the bonding layer in a normal direction of the bonding layer.

15. The chip package of claim 14, wherein a portion of the protective layer is between the second redistribution structure and the semiconductor device.

16. The chip package of claim 14, further comprising: a second semiconductor device bonded over the first redistribution structure, wherein the inner sidewall of the interposer substrate surrounds the second semiconductor device.

17. The chip package of claim 14, wherein the encapsulation structure is bonded to the second redistribution structure.

18. The chip package of claim 14, wherein the inner sidewall of the interposer substrate is an inclined sidewall.

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