Integrated circuit device and method of manufacturing an integrated circuit device

Abstract

An integrated circuit device can include a fin-type active region extending in a first horizontal direction on a substrate, a gate line extending in a second horizontal direction on the fin-type active region, a source / drain region on the fin-type active region and adjacent to the gate line, and a source / drain contact pattern connected to the source / drain region. The source / drain contact pattern can include a first portion having a first height and a second portion having a second height less than the first height. The source / drain contact pattern can include a metal plug in the first portion and the second portion, and a conductive barrier film on sidewalls of the metal plug in the first portion and the second portion. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0069845, filed on June 9, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to integrated circuit devices and methods of manufacturing the same, and more specifically, to integrated circuit devices including fin field-effect transistors and methods of manufacturing the integrated circuit devices. Background Technology

[0004] As the size of integrated circuit devices shrinks, the accuracy and speed of their operation become critical considerations. Therefore, techniques have been developed to reduce the area occupied by wiring and contacts, reliably ensure the electrical isolation distance between wiring and contacts, and improve reliability. Summary of the Invention

[0005] Embodiments of the present invention provide an integrated circuit device whose structure improves the reliability of an integrated circuit device having a device region reduced by size reduction.

[0006] Embodiments of the present invention also provide a method for manufacturing an integrated circuit device, the structure of which improves the reliability of the integrated circuit device having a device region reduced by size reduction.

[0007] According to some embodiments of the present invention, an integrated circuit device is provided, comprising: a fin-type active region extending in a first horizontal direction on a substrate; a gate line extending in the fin-type active region in a second horizontal direction intersecting the first horizontal direction; a source / drain region on the fin-type active region and adjacent to the gate line; and a source / drain contact pattern electrically connected to the source / drain region and comprising a first portion and a second portion, the first portion having a first height in a vertical direction, and the second portion having a second height in a vertical direction less than the first height, wherein the source / drain contact pattern comprises a metal plug and a conductive barrier film, the metal plug being in the first portion and the second portion, and the conductive barrier film being in the first portion and the second portion on the sidewall of the metal plug, and a first top surface of the conductive barrier film in the second portion being lower than the top surface of the metal plug in the second portion relative to the substrate.

[0008] According to some embodiments of the present invention, an integrated circuit device is provided, comprising: a plurality of finned active regions extending parallel to each other in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction intersecting the first horizontal direction on the plurality of finned active regions; a source / drain region on the plurality of finned active regions and adjacent to the gate line; and a source / drain contact pattern electrically connected to the source / drain region, wherein the source / drain contact pattern includes a first portion and a second portion, the first portion having a first height in a vertical direction, and the second portion having a second height in a vertical direction less than the first height; the first portion includes a first portion of a metal plug and a first portion of a conductive barrier film on the sidewall of the first portion of the metal plug, and the second portion includes a second portion of the metal plug and a second portion of the conductive barrier film on the sidewall of the second portion of the metal plug; a first top surface of the first portion of the conductive barrier film and a second top surface of the first portion of the metal plug are coplanar and at the first vertical height level; and relative to the substrate, a third top surface of the second portion of the conductive barrier film is lower than a fourth top surface of the second portion of the metal plug.

[0009] According to some embodiments of the present invention, an integrated circuit device is provided, comprising: a first finned active region and a second finned active region, both extending parallel to each other in a first horizontal direction on a substrate and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a gate line extending longitudinally in the second horizontal direction on the first finned active region and the second finned active region; a source / drain region on the first finned active region and the second finned active region; and a source / drain contact pattern electrically connected to the source / drain region, wherein the source / drain contact pattern includes a first portion. The source / drain contact pattern comprises a first portion that overlaps with the first fin-shaped active region in the vertical direction and has a first height in the vertical direction, and a second portion that overlaps with the second fin-shaped active region in the vertical direction and has a second height less than the first height in the vertical direction; and the source / drain contact pattern comprises a metal plug and a conductive barrier film, the metal plug comprising a protruding top in the second portion, and the conductive barrier film in the second portion being on the sidewall of the metal plug in the second portion and comprising a first top surface, the first top surface being lower than the top surface of the protruding top relative to the substrate.

[0010] According to some embodiments of the present invention, a method for manufacturing an integrated circuit device is provided. In the method, a fin-shaped active region extending in a first horizontal direction is formed on a substrate. Source / drain regions are formed on the fin-shaped active region. A source / drain contact pattern electrically connected to the source / drain regions is formed. The source / drain contact pattern includes a first portion and a second portion, the first portion having a first height in a vertical direction, and the second portion having a second height in a vertical direction less than the first height. The source / drain contact pattern includes a metal plug and a conductive barrier film, the metal plug being in the first portion and the second portion, and the conductive barrier film being in the first portion and the second portion on the sidewalls of the metal plug, wherein the conductive barrier film in the second portion includes a first top surface that is lower than the top surface of the metal plug in the second portion relative to the substrate.

[0011] According to some embodiments of the present invention, a method for manufacturing an integrated circuit device is provided. In the method, a fin-shaped active region extending in a first horizontal direction is formed on a substrate. Source / drain regions are formed on the fin-shaped active region. An insulating film is formed on the source / drain regions. Source / drain contact holes are formed in the insulating film to expose the source / drain regions. A source / drain contact pattern is formed in the source / drain contact holes to include a first portion and a second portion, the first portion having a first height in a vertical direction, and the second portion having a second height in the vertical direction less than the first height. Forming the source / drain contact pattern includes: forming a preliminary source / drain contact portion in the source / drain contact holes, the preliminary source / drain contact portion including a preliminary conductive barrier film and a preliminary metal plug; forming a mask pattern on a portion of the preliminary source / drain contact portion; and etching the preliminary conductive barrier film and the preliminary metal plug using the mask pattern as an etching mask to form a metal plug and a conductive barrier film. The metal plug is located in the first portion and the second portion, and the conductive barrier film covers the sidewalls of the metal plug in the first portion and the second portion, and the conductive barrier film in the second portion includes a first top surface that is lower than the top surface of the metal plug in the second portion relative to the substrate.

[0012] According to some embodiments of the present invention, a method for manufacturing an integrated circuit device is provided. In this method, a first finned active region and a second finned active region are formed on a substrate, extending parallel to each other in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction. Source / drain regions are formed on the first and second finned active regions to be electrically connected to them. An insulating film is formed on the source / drain regions. A source / drain contact pattern is formed to pass through the insulating film and be electrically connected to the source / drain regions. The source / drain contact pattern includes a first portion and a second portion, the first portion overlapping the first finned active region in a vertical direction and having a first height in the vertical direction, and the second portion overlapping the second finned active region in the vertical direction and having a second height in the vertical direction less than the first height. Forming the source / drain contact pattern includes: forming a metal plug and a conductive barrier film, the metal plug including a protruding top in the second portion, and the conductive barrier film in the second portion on the sidewall of the metal plug and including a first top surface that is lower than the uppermost surface of the protruding top relative to the substrate. Attached Figure Description

[0013] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a layout of an integrated circuit device according to some embodiments of the present invention;

[0015] Figure 2A It shows along Figure 1 The cross-sectional view taken by lines X1-X1′ and X2-X2′ in the diagram; Figure 2B It is along Figure 1 A cross-sectional view taken from line Y1-Y1′ in the diagram;

[0016] Figure 3A and Figure 3B Is with Figure 1 An enlarged cross-sectional view of the portion corresponding to region C1 in the diagram, where... Figure 3A yes Figure 2A An enlarged cross-sectional view of region C2A in the image, and Figure 3B yes Figure 2B Enlarged cross-sectional view of region C2B in the image;

[0017] Figure 4A and Figure 4B These are cross-sectional views of integrated circuit devices according to some embodiments of the present invention;

[0018] Figure 5A and Figure 5B These are cross-sectional views of integrated circuit devices according to some embodiments of the present invention;

[0019] Figure 6A and Figure 6B These are cross-sectional views of integrated circuit devices according to some embodiments of the present invention;

[0020] Figure 7A and Figure 7B These are cross-sectional views of integrated circuit devices according to some embodiments of the present invention;

[0021] Figure 8A This is a layout of an integrated circuit device according to some embodiments of the present invention; Figure 8B It is along Figure 8A A cross-sectional view taken from line X8-X8′;

[0022] Figure 9 These are cross-sectional views of integrated circuit devices according to some embodiments of the present invention;

[0023] Figure 10A This is a layout of an integrated circuit device according to some embodiments of the present invention; Figure 10B It is along Figure 10A A cross-sectional view taken by line X9-X9′ in the diagram; Figure 10C It is along Figure 10A A cross-sectional view taken from line Y9-Y9′ in the diagram;

[0024] Figures 11A to 22B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention, wherein... Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A It shows the respective and the respective along Figure 1 The corresponding portions of the cross-sections intercepted by lines X1-X1′ and X2-X2′, and Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B and Figure 22B It shows the relationship with along Figure 1The portion corresponding to the cross section intercepted by line Y1-Y1′ in the middle;

[0025] Figures 23A to 23D This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention;

[0026] Figure 24A and Figure 24B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention; and

[0027] Figures 25A to 31 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention, wherein... Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A and Figure 31 It shows the relationship with along Figure 10A The portion corresponding to the cross section intercepted by line X9-X9′ in the diagram, and Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B and Figure 30B It shows the relationship with along Figure 10A The part corresponding to the cross section intercepted by line Y9-Y9′ in the middle. Detailed Implementation

[0028] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, similar reference numerals and characters refer to similar elements, and redundant descriptions may be omitted.

[0029] Figure 1 This is the layout of an integrated circuit device 100 according to some embodiments of the present invention. Figure 2A It shows along Figure 1 The cross-sectional views taken by lines X1-X1′ and X2-X2′ in the diagram, and Figure 2B It is along Figure 1 The cross-sectional view taken from line Y1-Y1′ in the diagram. Figure 3A and Figure 3B Is with Figure 1 An enlarged cross-sectional view of the portion corresponding to region C1 in the diagram, where... Figure 3A yes Figure 2A An enlarged cross-sectional view of region C2A in the image, and Figure 3B yes Figure 2B An enlarged cross-sectional view of region C2B in the image.

[0030] refer to Figures 1 to 3BThe integrated circuit device 100 includes a logic cell LC, which is formed on the substrate 110 in a region defined by a cell boundary BN. The logic cell LC may include a fin field-effect transistor (FinFET).

[0031] Substrate 110 has a main surface 110M extending in a horizontal direction (e.g., the XY plane direction). Substrate 110 may include semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe, SiC, GaAs, InAs, or InP. Substrate 110 may include conductive regions, such as doped wells or doped structures.

[0032] The logic cell LC includes a first device region RX1 and a second device region RX2. Multiple fin-type active regions FA protruding from the substrate 110 can be formed in each of the first device region RX1 and the second device region RX2. A device isolation region DTA can be located between the first device region RX1 and the second device region RX2.

[0033] Fin-type active regions (FAs) can extend parallel to each other in the width direction (i.e., the first horizontal direction, e.g., the X direction) of the logic cell (LC). For example... Figure 2B As shown, an isolation film 112 can be formed in the substrate 110 between fin-type active regions FA, and an isolation insulating film 114 can be formed in the substrate 110 in the device isolation region DTA. Each of the isolation film 112 and the isolation insulating film 114 may include, for example, an oxide film. The fin-type active regions FA may protrude from the isolation film 112 to have a fin shape in the first device region RX1 and the second device region RX2.

[0034] Multiple gate insulating films 132 and multiple gate lines GL are formed on the substrate 110 to extend in the height direction (i.e., the second horizontal direction, e.g., the Y direction) of the logic cell LC, thereby intersecting with the fin active regions FA. The gate insulating films 132 and gate lines GL may cover the top surface and two sidewalls of each of the fin active regions FA, the top surface of the isolation film 112, and the top surface of the isolation insulating film 114. As used herein, “element A covers the surface of element B” (or similar wording) may mean that element A is on the surface of element B and overlaps with the surface of element B, but does not necessarily mean that element A completely covers the surface of element B.

[0035] Multiple metal-oxide-semiconductor (MOS) transistors can be formed along the gate line GL in the first device region RX1 and the second device region RX2. Each of the MOS transistors can have a three-dimensional (3D) structure in which channels are formed on the top surface and two sidewalls of each of the fin active regions FA.

[0036] A dummy gate line DGL may extend along the cell boundary BN in a second horizontal direction (Y direction). The dummy gate line DGL may comprise the same material as the gate line GL, but may serve as an electrical isolation region between a logic cell LC and another adjacent logic cell by remaining electrically floating during operation of the integrated circuit device 100. The gate line GL and multiple dummy gate lines DGL may have the same width in a first horizontal direction (X direction) and may be arranged at specific intervals in the first horizontal direction (X direction).

[0037] The gate insulating film 132 may include, for example, a silicon oxide film, a high-k dielectric film, or a combination thereof. The high-k dielectric film may include a material having a higher dielectric constant than the silicon oxide film. The high-k dielectric film may include, for example, a metal oxide or a metal oxynitride. An interface film (not shown) may be located between the finned active region FA and the gate insulating film 132. The interface film may include, for example, an oxide film, a nitride film, or an oxynitride film.

[0038] The gate line GL and dummy gate line DGL may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-filling metal film are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf. The gap-filling metal film may include a W film or an Al film. The gate line GL and dummy gate line DGL may include a work function metal layer. The work function metal layer may include at least one metal selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, the gate line GL and dummy gate line DGL may include a stacked structure of TiAlC / TiN / W, TiN / TaN / TiAlC / TiN / W, or TiN / TaN / TiN / TiAlC / TiN / W, but are not limited thereto.

[0039] Multiple insulating spacers 120 may cover the two sidewalls of the gate line GL and the two sidewalls of the dummy gate line DGL. Each of the insulating spacers 120 may have a linear shape extending in the longitudinal direction (Y direction) of the logic cell LC. The insulating spacers 120 may include, for example, a silicon nitride film, a SiOCN film, a SiCN film, or a combination thereof, but are not limited thereto.

[0040] The top surface of each of the gate line GL, the gate insulating film 132, the insulating spacer 120, and the dummy gate line DGL may be covered with an insulating cover line 140. Multiple insulating cover lines 140 may include, for example, a silicon nitride film.

[0041] Multiple recessed regions RR can be formed on the top surface of the finned active region FA at the side of each of the gate lines GL, and multiple source / drain regions SD can be formed in the recessed regions RR. Each of the source / drain regions SD can be between adjacent gate lines GL. The gate lines GL can be separated from the source / drain regions SD, wherein the gate insulating film 132 and the insulating spacer 120 are between the gate lines GL and the source / drain regions SD. The multiple source / drain regions SD can include, for example, a semiconductor epitaxial layer or a combination of semiconductor epitaxial layers epitaxially grown on the multiple recessed regions RR in the finned active region FA. The source / drain regions SD can include, for example, an epitaxially grown Si layer, an epitaxially grown SiC layer, or an epitaxially grown SiGe layer. The inter-gate insulating film 128 can include, for example, a silicon oxide film. In an example embodiment, the source / drain regions SD can be covered with an insulating liner (not shown). The insulating liner can conformally cover the surface of each of the source / drain regions SD. The insulating liner may include, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or combinations thereof.

[0042] In an example embodiment, the first device region RX1 may correspond to an N-channel MOS (NMOS) transistor region, and the second device region RX2 may correspond to a P-channel MOS (PMOS) transistor region. In this case, the plurality of source / drain regions SD in the first device region RX1 may include epitaxially grown Si layers or epitaxially grown SiC layers, and the plurality of source / drain regions SD in the second device region RX2 may include multiple epitaxially grown SiGe layers. Figure 2B As shown, the source / drain regions SD in the first device region RX1 may have different shapes and sizes than the source / drain regions SD in the second device region RX2. However, the embodiments are not limited to this, and the multiple source / drain regions SD in the first device region RX1 and the second device region RX2 may have different shapes and sizes.

[0043] Multiple source / drain contact patterns CAP can be formed on the source / drain region SD. The source / drain region SD can be connected to a conductor (not shown) above the source / drain region SD via the source / drain contact patterns CAP. The source / drain contact patterns CAP may include a conductive barrier film 154 and a metal plug 156. The conductive barrier film 154 may cover the sidewalls and bottom surface of the metal plug 156. A metal silicide film 152 may be formed between the source / drain region SD and the source / drain contact patterns CAP. As used herein, "component A is connected to component B" (or similar wording) may mean that component A is electrically connected to component B or that component A is physically in contact with component B.

[0044] In an example embodiment, the metal silicide film 152 may include, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 152 may include titanium silicide. The conductive barrier film 154 may include, for example, Ti, Ta, TiN, TaN, or combinations thereof, and the metal plug 156 may include, for example, W, Co, Cu, Ru, Mn, or combinations thereof.

[0045] Each of the source / drain contact patterns CAP may have its sidewalls covered with contact insulating spacers 150. In example embodiments, contact insulating spacers 150 may include, for example, SiCN, SiCON, silicon nitride (SiN), or combinations thereof, but are not limited thereto.

[0046] The source / drain contact pattern CAP can have different heights depending on its location. Each of the source / drain contact patterns CAP can include a first part S1 and a second part S2, which have different heights in the vertical direction (Z direction) and are integrally connected to each other. As used herein, the term "part" may be used interchangeably with the term "section".

[0047] like Figure 3B As shown, the first part S1 of the source / drain contact pattern CAP above the fin-type active region FA can have a first height H1 in the vertical direction (Z direction), and the second part S2 of the source / drain contact pattern CAP can have a second height H2 in the vertical direction (Z direction), the second height H2 being less than the first height H1.

[0048] In each source / drain contact pattern CAP, the conductive barrier film 154 and the metal plug 156 may extend on the first portion S1 and the second portion S2 to be included in the first portion S1 and the second portion S2.

[0049] In the first part S1 of each source / drain contact pattern CAP, the top surface of the conductive barrier film 154 may be coplanar with the top surface of the metal plug 156 at a vertical height level LV1. In this specification, the term "height level" refers to the distance from the main surface 110M of the substrate 110 in the vertical direction (Z direction).

[0050] In the second part S2 of each source / drain contact pattern CAP, the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 is lower than the vertical height level LV3 of the uppermost surface of the metal plug 156. The height difference DH1 between the vertical height level LV3 of the uppermost surface of the metal plug 156 and the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 in the second part S2 can be about 1 nm to about 5 nm, for example, about 2 nm to about 3 nm. As used herein, "the vertical height level X of surface A is lower than the vertical height level Y of surface B" (or similar wording) can indicate that surface A is lower than surface B in the vertical direction relative to the substrate, and therefore the substrate is closer to surface A in the vertical direction than surface B.

[0051] In the vertical direction (Z direction), the vertical height level LV1 of the uppermost surface of the first portion S1 can be higher than the vertical height level of the uppermost surface of the gate line GL, and the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 in the second portion S2 and the vertical height level LV3 of the uppermost surface of the metal plug 156 in the second portion S2 can be lower than the vertical height level of the uppermost surface of the gate line GL. In other words, in the vertical direction (Z direction), the distance from the main surface 110M of the substrate 110 to the uppermost surface of the first portion S1 can be greater than the distance from the main surface 110M of the substrate 110 to the uppermost surface of each of the gate lines GL, and in the vertical direction (Z direction), the distance from the main surface 110M of the substrate 110 to the uppermost surface of the second portion S2 can be less than the distance from the main surface 110M of the substrate 110 to the uppermost surface of each of the gate lines GL. However, the embodiments are not limited to this. For example, the uppermost surface of each of the first portion S1 and the second portion S2 can be higher than the uppermost surface of each of the gate lines GL. As used in this paper, “the vertical height level X of surface A is higher than the vertical height level Y of surface B” (or similar wording) can indicate that surface A is higher than surface B in the vertical direction relative to the substrate, and therefore the substrate is closer to surface B in the vertical direction than surface A.

[0052] In the second portion S2 of each source / drain contact pattern CAP, the metal plug 156 may include a protruding top 156P at a height level higher than the vertical height level LV2 of the uppermost surface of the conductive barrier film 154 in the second portion S2. In the second portion S2 of each source / drain contact pattern CAP, the sidewalls of the protruding top 156P of the metal plug 156 may not be covered by the conductive barrier film 154. The protruding top 156P may protrude beyond the uppermost surface of the conductive barrier film 154 in the second portion S2, such as... Figure 3A and Figure 3B As shown in the image.

[0053] The protruding top 156P can have a flat top surface (e.g., a substantially planar top surface). In an example embodiment, the uppermost surface of the protruding top 156P can extend substantially flat in a direction parallel to the main surface 110M of the substrate 110. However, the embodiments are not limited to this, and various changes can be made to the shape of the protruding top 156P. Reference will be made below. Figures 5A to 7B Describe specific examples of various shapes that highlight the top 156P.

[0054] The insulation cover wire 140 can have different thicknesses at different locations. For example, as... Figure 2A As shown, the portion of the insulating cover line 140 between two adjacent first portions S1 can be relatively thick, and the portion of the insulating cover line 140 between two adjacent second portions S2 can be relatively thin. The portion of the insulating cover line 140 between a first portion S1 of one source / drain contact pattern CAP and a second portion S2 of another source / drain contact pattern CAP can have a certain thickness, which can vary in a first horizontal direction (X direction) and decrease from the first portion S1 toward the second portion S2.

[0055] The integrated circuit device 100 may include a buried insulating film 170 and an insulating structure 180, wherein the buried insulating film 170 covers a second portion S2 of each of a plurality of source / drain contact patterns CAP, a gate line GL and a plurality of insulating cover lines 140, and the insulating structure 180 covers the top surface of the buried insulating film 170.

[0056] The buried insulating film 170 can contact the top surface of each of the plurality of second portions S2 and the top surface of each of the insulating cover lines 140. The buried insulating film 170 can include a main buried portion 170M and a buried protrusion 170P. The main buried portion 170M covers the top surface of the metal plug 156 included in each of the second portions S2, the portions of the plurality of contact insulating spacers 150 adjacent to the second portions S2, and the insulating cover lines 140. The buried protrusion 170P protrudes from the main buried portion 170M toward the substrate 110. The buried protrusion 170P can be on the second portion S2 of each of the source / drain contact patterns CAP to contact the top surface of the conductive barrier film 154. The buried protrusion 170P can also contact the sidewalls of the protruding top 156P of the metal plug 156 and the sidewalls of the contact insulating spacers 150. The buried protrusion 170P can fill spaces (e.g., Figure 19A and Figure 19B The recessed portion LR shown in the figure has an internal space defined by the uppermost surface of the conductive barrier film 154, the sidewall of the protruding top 156P of the metal plug 156, and the sidewall of the contact insulating spacer 150.

[0057] The buried insulating film 170 may have a planarized top surface. The buried insulating film 170 may include a portion filling the space above the second portion S2 of each of the source / drain contact patterns CAP between gate lines GL. The top surface of the buried insulating film 170 may be coplanar with the uppermost surface of the conductive barrier film 154 and the uppermost surface of the metal plug 156, which are included in the first portion S1 of each of the source / drain contact patterns CAP and may be substantially at a vertical height level LV1. The buried insulating film 170 may include, for example, a silicon oxide film, SiOC, SiOCN, SiON, SiCN, SiN, or combinations thereof, but is not limited thereto.

[0058] The insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184, which are sequentially stacked on the buried insulating film 170. The bottom surface of the etch stop film 182 may contact the topmost surface of the buried insulating film 170. The etch stop film 182 may include, for example, silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The interlayer insulating film 184 may include, for example, an oxide film, a nitride film, an ultra-low k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or combinations thereof. For example, the interlayer insulating film 184 may include a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) film, a borosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or combinations thereof.

[0059] Multiple through-hole contacts (CAVs) can be formed on the source / drain contact pattern (CAP). Each of the through-hole contacts (CAVs) can pass through the insulating structure 180 and contact the top surface of the first portion S1 of the source / drain contact pattern (CAP).

[0060] Multiple gate contacts CB can be formed on the gate line GL. Each of the gate contacts CB can pass through the insulating structure 180, the buried insulating film 170, and the insulating cover line 140, and can be connected to the gate line GL. Each gate contact CB can pass through a relatively thin portion of the insulating cover line 140 and contact the top surface of the gate line GL.

[0061] Each of some gate contacts CB can contact the gate line GL at a location adjacent to the second portion S2 of the source / drain contact pattern CAP. In this case, as... Figure 2A and Figure 3AAs shown, the buried protrusion 170P of the buried insulating film 170 can be located between the gate line GL and the second portion S2 of the source / drain contact pattern CAP, which are adjacent to each other in the first horizontal direction (X direction). In other words, the gate contact CB and the second portion S2 of the source / drain contact pattern CAP can be separated from each other in the first horizontal direction (X direction), wherein the buried protrusion 170P of the buried insulating film 170 is located between the gate contact CB and the second portion S2 of the source / drain contact pattern CAP. Therefore, at least the buried protrusion 170P can ensure the spacing distance from the conductive barrier film 154 and the metal plug 156 forming the second portion S2 to the gate line GL. Therefore, even when the gate contact CB and the second portion S2 of the source / drain contact pattern CAP are formed to be adjacent to each other, the insulation margin between the gate contact CB and the source / drain contact pattern CAP can be ensured, thereby reducing or preventing undesirable short circuits between the gate contact CB and the source / drain contact pattern CAP.

[0062] Each of the via contact CAV and the gate contact CB may include a buried metal film and a conductive barrier film surrounding the buried metal film. The buried metal film may include, for example, Co, Cu, W, Ru, Mn, or combinations thereof, and the conductive barrier film may include, for example, Ti, Ta, TiN, TaN, or combinations thereof. The sidewalls of each of the via contact CAV and the gate contact CB may be covered with an insulating liner (not shown). The insulating liner may include, for example, a silicon nitride film, but is not limited thereto. As used herein, “element A surrounds element B” (or similar wording) may mean that element A is on element B and partially surrounds element B, but does not necessarily mean that element A completely surrounds the surface of element B.

[0063] In the logic cell LC, the ground line VSS can be connected to the finned active region FA in the first device region RX1 through some of the source / drain contact patterns CAP, and the power line VDD can be connected to the finned active region FA in the second device region RX2 through others of the source / drain contact patterns CAP. The ground line VSS and the power line VDD can be formed at a height level higher than the top surface of each of the source / drain contact patterns CAP and the gate contact CB. Each of the ground line VSS and the power line VDD may include a conductive barrier film and a wiring conductive layer. The conductive barrier film may include, for example, Ti, Ta, TiN, TaN, or combinations thereof. The wiring conductive layer may include, for example, Co, Cu, W, alloys thereof, or combinations thereof.

[0064] Figure 4A and Figure 4B This is a cross-sectional view of an integrated circuit device 200 according to some embodiments of the present invention. Figure 4A It shows along Figure 1The cross-sectional view of integrated circuit device 200 taken by lines X1-X1′ and X2-X2′ is shown in the figure. Figure 4B It shows along Figure 1 The cross-sectional view of integrated circuit device 200 taken by line Y1-Y1′ in the figure.

[0065] refer to Figure 4A and Figure 4B Integrated circuit device 200 can be compared with reference Figures 1 to 3B The described integrated circuit device 100 is substantially the same as or similar to the original. However, the integrated circuit device 200 includes multiple wires ML that extend on the via contact CAV in a direction intersecting with multiple gate lines GL.

[0066] Some of the wires ML can be connected to the source / drain region SD via the via contact CAV and the source / drain contact pattern CAP. Although not shown, others of the wires ML can be connected to the gate line GL via the gate contact CB.

[0067] The conductor ML can be formed on the substrate 110 at the same height level as the ground line VSS and the power line VDD. The conductor ML may include a plurality of unidirectional wiring layers extending parallel to each other in a first horizontal direction (X direction). Each of the conductors ML may include a conductive barrier film and a wiring conductive layer. The conductive barrier film may include, for example, Ti, Ta, TiN, TaN, or combinations thereof. The wiring conductive layer may include, for example, Co, Cu, W, alloys thereof, or combinations thereof.

[0068] Figure 5A and Figure 5B This is a cross-sectional view of an integrated circuit device 300 according to some embodiments of the present invention. Specifically, Figure 5A It is along Figure 1 The line X1-X1′ intercepts Figure 1 An enlarged cross-sectional view of region C1 in the image, and Figure 5B It is along Figure 1 The line Y1-Y1′ intercepted in Figure 1 An enlarged cross-sectional view of region C1 in the diagram.

[0069] refer to Figure 5A and Figure 5B Integrated circuit device 300 can be compared with reference Figures 1 to 3BThe described integrated circuit device 100 is substantially the same as or similar to the one described above. However, the source / drain contact pattern CAP of the integrated circuit device 300 includes a metal plug 356 instead of a metal plug 156. The metal plug 356 may include a protruding top 356P, which is located at a height level higher than the conductive barrier film 154 in the second portion S2 of the source / drain contact pattern CAP. The protruding top 356P may have rounded corners 356C in its outer edges. The top surface portion 356T, which is substantially located in the middle of the protruding top 356P in the first horizontal direction (X direction), may extend substantially flat in a direction parallel to the main surface 110M of the substrate 110. Specific configuration of the metal plug 356 is referenced. Figures 1 to 3B The specific configuration of the metal plug 156 of the described integrated circuit device 100 is basically the same or similar.

[0070] Figure 6A and Figure 6B This is a cross-sectional view of an integrated circuit device 400 according to some embodiments of the present invention. Specifically, Figure 6A It is along Figure 1 The line X1-X1′ intercepts Figure 1 An enlarged cross-sectional view of region C1 in the image, and Figure 6B It is along Figure 1 The line Y1-Y1′ intercepted in Figure 1 An enlarged cross-sectional view of region C1 in the diagram.

[0071] refer to Figure 6A and Figure 6B Integrated circuit device 400 can be compared with reference Figures 1 to 3B The described integrated circuit device 100 is substantially the same as or similar to the one described above. However, the source / drain contact pattern CAP of the integrated circuit device 400 includes a metal plug 456 instead of a metal plug 156. The metal plug 456 may include a protruding top 456P, which is located at a height level higher than the conductive barrier film 154 in the second portion S2 of the source / drain contact pattern CAP. The protruding top 456P may have a top surface portion 456T that protrudes in a direction away from the substrate 110. In the first horizontal direction (X direction), the top surface portion 456T of the protruding top 456P may not extend flat but in a curved shape. In the second horizontal direction (Y direction), the protruding top 456P may have a rounded corner 456C in its outer edge. The specific configuration of the metal plug 456 can be compared with the reference. Figures 1 to 3B The specific configuration of the metal plug 156 of the described integrated circuit device 100 is basically the same or similar.

[0072] Figure 7A and Figure 7BThis is a cross-sectional view of an integrated circuit device 500 according to some embodiments of the present invention. Specifically, Figure 7A It is along Figure 1 The line X1-X1′ intercepts Figure 1 An enlarged cross-sectional view of region C1 in the image, and Figure 7B It is along Figure 1 The line Y1-Y1′ intercepted in Figure 1 An enlarged cross-sectional view of region C1 in the diagram.

[0073] refer to Figure 7A and Figure 7B Integrated circuit device 500 can be compared with reference Figures 1 to 3B The described integrated circuit device 100 is substantially the same or similar. However, the source / drain contact pattern CAP of the integrated circuit device 500 includes a metal plug 556 instead of a metal plug 156. The metal plug 556 may include a protruding top 556P, which is located at a height level higher than the conductive barrier film 154 in the second portion S2 of the source / drain contact pattern CAP. The protruding top 556P may have a bimodal protrusion that bulges in a direction away from the substrate 110.

[0074] Specifically, the protruding top 556P may include a bimodal protrusion comprising a first peak T1 and a second peak T2, the first peak T1 and the second peak T2 protruding in a direction away from the substrate 110. A recess 556D may be located between the first peak T1 and the second peak T2. Opposite sidewalls of the first peak T1 of the protruding top 556P may be symmetrical or asymmetrical about the first vertex P1. Opposite sidewalls of the second peak T2 may be symmetrical or asymmetrical about the second vertex P2. In the vertical direction (Z direction), the height of the first vertex P1 may be equal to or similar to the height of the second vertex P2. In some embodiments, the first vertex P1 and the second vertex P2 may be equidistant from the substrate 110.

[0075] The protruding top 556P may have a rounded corner 556C in its outer edge in the second horizontal direction (Y direction). The recess 556D of the protruding top 556P may extend substantially flat in the second horizontal direction (Y direction). Specific configuration and reference of the metal plug 556. Figures 1 to 3B The specific configuration of the metal plug 156 of the described integrated circuit device 100 is substantially the same.

[0076] exist Figures 5A to 7BIn the integrated circuit devices 300, 400, and 500 shown, the metal plugs 356, 456, and 556 of the second portion S2 of the source / drain contact pattern CAP may each include protruding tops 356P, 456P, and 556P at a height level higher than the conductive barrier film 154 in the second portion S2, and each of the protruding tops 356P, 456P, and 556P may include rounded corners 356C, 456C, or 556C in its outer edge and include a top surface portion, which may be flat (e.g., substantially planar) (e.g., top surface portion 356T), may be convex (e.g., top surface portion 456T), or may include a bi-peaked protrusion containing a first peak T1 and a second peak T2 (e.g., the top surface portion of the protruding top 556P). Therefore, even when each of some gate contacts CB is arranged adjacent to the second portion S2 of the source / drain contact pattern CAP, the spacing between the second portion S2 of the source / drain contact pattern CAP and the adjacent gate contact CB in the first horizontal direction (X direction) can be sufficiently ensured. Thus, even when the gate contact CB and the second portion S2 of the source / drain contact pattern CAP are arranged adjacent to each other, the insulation margin between the gate contact CB and the source / drain contact pattern CAP can be more easily ensured, thereby reducing or preventing undesirable short circuits between the gate contact CB and the source / drain contact pattern CAP.

[0077] Figure 8A and Figure 8B This is a diagram illustrating an integrated circuit device 600 according to some embodiments of the present invention, wherein, Figure 8A It is the layout of integrated circuit device 600, and Figure 8B It is along Figure 8A The cross-sectional view taken by line X8-X8′ in the diagram. Figures 1 to 3B as well as Figure 8A and Figure 8B In the accompanying drawings, similar reference numerals denote similar elements, and their detailed descriptions may be omitted. Figure 8A and Figure 8B The integrated circuit device 600 shown may include an SRAM array, which includes a plurality of SRAM cells arranged in a matrix on a substrate 110.

[0078] refer to Figure 8A and Figure 8BThe integrated circuit device 600 includes multiple finned active regions FA and multiple gate lines GL, wherein the multiple finned active regions FA extend parallel to each other in a first horizontal direction (X direction), and the multiple gate lines GL extend parallel to each other in a second horizontal direction (Y direction) on the finned active regions FA. Transistors may be formed at corresponding intersections between the finned active regions FA and the gate lines GL. The integrated circuit device 600 may include multiple shared contacts SC, all of which are connected to the gate lines GL and the source / drain regions SD.

[0079] In the integrated circuit device 600, each of the source / drain contact patterns CAP may include a conductive barrier film 154 and a metal plug 156. Each of the source / drain contact patterns CAP may include a first portion S1 and a second portion S2, which have different heights in the vertical direction (Z direction) and are integrally connected to each other. In each of the source / drain contact patterns CAP, the conductive barrier film 154 and the metal plug 156 may extend on the first portion S1 and the second portion S2 to be included within the first portion S1 and the second portion S2.

[0080] In the first portion S1 of each of the source / drain contact patterns CAP, the top surface of the conductive barrier film 154 may be coplanar with the top surface of the metal plug 156 at a vertical height level LV61. In the second portion S2 of each of the source / drain contact patterns CAP, the vertical height level LV62 of the uppermost surface of the conductive barrier film 154 is lower than the vertical height level LV63 of the uppermost surface of the metal plug 156. The height difference between the vertical height level LV63 of the uppermost surface of the metal plug 156 and the vertical height level LV62 of the uppermost surface of the conductive barrier film 154 in the second portion S2 may be from about 1 nm to about 5 nm, for example, from about 2 nm to about 3 nm.

[0081] In the second portion S2 of each of the source / drain contact patterns CAP, the metal plug 156 may include a protruding top 656P at a height level higher than the vertical height level LV62 of the uppermost surface of the conductive barrier film 154. In the second portion S2 of each of the source / drain contact patterns CAP, the sidewalls of the protruding top 656P of the metal plug 156 may not be covered by the conductive barrier film 154.

[0082] and Figure 3A and Figure 3B Similar to the protruding top 156P shown, the protruding top 656P may have a flat top surface (e.g., a substantially planar top surface). However, the embodiments are not limited to this. For example, the metal plug 156 of the integrated circuit device 600 may include a surface with a similar shape to the metal plug 156 of the integrated circuit device 600. Figures 5A to 7BThe convex top shown is of the same or similar shape as one of the convex tops 356P, 456P, and 556P, instead of the convex top 656P.

[0083] The buried insulating film 170 may cover the top surface of the second portion S2 of each of the source / drain contact patterns CAP and the top surface of the insulating cover line 140. The buried insulating film 170 may include a main buried portion 170M and a buried protrusion 170P, wherein the buried protrusion 170P protrudes from the main buried portion 170M toward the substrate 110. The main buried portion 170M may contact the top surface of the metal plug 156 included in each of the plurality of second portions S2, a portion of the inter-gate insulating film 128, and the plurality of insulating cover lines 140. The buried protrusion 170P may be on the second portion S2 of each of the source / drain contact patterns CAP to contact the uppermost surface of the conductive barrier film 154. The buried protrusion 170P may also contact the sidewall of the protruding top 656P of the metal plug 156. The buried protrusion 170P can fill a space defined by the uppermost surface of the conductive barrier film 154 of the second part S2, the sidewalls of the protruding top 656P of the metal plug 156, and the contact insulating spacer 150.

[0084] The buried insulating film 170 may have a planarized top surface. The buried insulating film 170 may include a portion filling the space above the second portion S2 of each of the source / drain contact patterns CAP between the gate lines GL. The top surface of the buried insulating film 170 may be coplanar with the uppermost surface of the conductive barrier film 154 and the uppermost surface of the metal plug 156, which are included in the first portion S1 of each of the source / drain contact patterns CAP and may be substantially at the vertical height level LV61.

[0085] Integrated circuit device 600 includes a metal plug 156, which includes a protruding top 656P in the second portion S2 of a source / drain contact pattern CAP. The sidewalls of the protruding top 656P may be covered by a buried protrusion 170P of a buried insulating film 170. Therefore, at least the buried protrusion 170P can ensure the spacing distance from the conductive barrier film 154 forming the second portion S2 and the metal plug 156 to another conductive region adjacent to the second portion S2. Thus, an insulation margin between the second portion S2 of the source / drain contact pattern CAP and the adjacent conductive region can be ensured, thereby reducing or preventing undesirable short circuits between the second portion S2 and the adjacent conductive region and improving the reliability of integrated circuit device 600.

[0086] Figure 9 This is a cross-sectional view of an integrated circuit device 700 according to some embodiments of the present invention. Figure 9It shows the relationship with Figure 8B An enlarged cross-sectional view of the portion corresponding to region C9 in the diagram.

[0087] refer to Figure 9 The integrated circuit device 700 can be compared with the reference. Figure 8A and Figure 8B The described integrated circuit device 600 is substantially the same as or similar to the one described above. However, the integrated circuit device 700 includes a metal plug 756 in the source / drain contact pattern CAP instead of a metal plug 156. The metal plug 756 may include a protruding top 756P, which is located at a height level higher than the conductive barrier film 154 in the second portion S2 of the source / drain contact pattern CAP. The protruding top 756P may have rounded corners 756C in its outer edges. The top surface portion 756T, which is substantially in the middle of the protruding top 756P in the first horizontal direction (X direction), may extend substantially flat in a direction parallel to the main surface 110M of the substrate 110. However, the embodiments are not limited thereto. For example, the protruding top 756P may have a shape similar to that of the reference design. Figure 6A and Figure 6B The description highlights the raised, curved shape of the top 456P. In another example, similar to the reference... Figure 7A and Figure 7B The described protruding top 556P, 756P may include a bimodal protrusion that protrudes in a direction away from the substrate 110. The specific configuration of the metal plug 756 can be compared with the reference. Figures 1 to 3B The specific configuration of the metal plug 156 of the described integrated circuit device 100 is basically the same or similar.

[0088] Figures 10A to 10C This is a diagram illustrating an integrated circuit device 900 according to some embodiments of the present invention, wherein, Figure 10A It is the layout of integrated circuit device 900. Figure 10B It is along Figure 10A The cross-sectional view taken by line X9-X9′ in the diagram, and Figure 10C It is along Figure 10A The cross-sectional view taken from line Y9-Y9′ in the diagram.

[0089] refer to Figures 10A to 10C The integrated circuit device 900 includes a plurality of finned active regions F9 and a plurality of nanosheet stacks NSS. The plurality of finned active regions F9 protrude from a substrate 902 and extend in a first horizontal direction (e.g., the X direction) (e.g., longitudinally), and each of the plurality of nanosheet stacks NSS is separated from the underlying finned active region F9 in a vertical direction (Z direction) and faces the top surface FT of the finned active region F9. In this specification, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. It will be understood that nanosheets include nanowires.

[0090] Trench T9 defining multiple fin-type active regions F9 can be formed in substrate 902 and filled with isolation film 912. Substrate 902, fin-type active regions F9, and isolation film 912 can be respectively connected to… Figure 2A and Figure 2B The substrate 110, fin-type active region FA and isolation film 112 shown are the same or similar.

[0091] Multiple gate lines 960 extend in a second horizontal direction (Y direction) on the fin active region F9. Each of the nanosheet stacked NSSs may be located at the intersection between one of the fin active regions F9 and one of the gate lines 960, above the top surface FT of one of the fin active regions F9, facing the top surface FT of one of the fin active regions F9, and at a location separate from one of the fin active regions F9. Multiple nanosheet transistors may be formed on the substrate 902 at the corresponding intersections between the fin active regions F9 and the gate lines 960.

[0092] Each of the nanosheet stacks in the NSS can include multiple nanosheets that overlap each other in the vertical direction (Z direction) above the top surface FT of one of the fin active regions F9. The nanosheets can include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, each at a different vertical distance from the top surface FT of each of the fin active regions F9. As used herein, "element A overlaps with element B in the vertical direction" (or similar wording) can indicate the existence of at least one vertical line intersecting both element A and element B.

[0093] Although Figure 10A The nanosheet stacked NSS is shown to have a rectangular shape, but the embodiments are not limited to this. The nanosheet stacked NSS can have various shapes in a planar view depending on the shape of the finned active region F9 and the gate line 960. Furthermore, although... Figure 10A , Figure 10B and Figure 10C This illustration shows multiple nanosheet stacked NSSs and multiple gate lines 960 formed on a finned active region F9, with the nanosheet stacked NSSs arranged along a first horizontal direction (X direction) on the finned active region F9; however, the inventive concept is not limited thereto. The number of nanosheet stacked NSSs on a single finned active region F9 is not particularly limited. For example, a single nanosheet stacked NSS can be formed on a single finned active region F9. Furthermore, although... Figure 10B and Figure 10CThe illustration shows that each of the nanosheet stacked NSS comprises three nanosheets, but the embodiments are not limited thereto. For example, each of the nanosheet stacked NSS may include at least two (e.g., two, four or more) nanosheets, and the number of nanosheets included in each nanosheet stacked NSS is not particularly limited.

[0094] Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have a channel region. In an example embodiment, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may include, for example, a Si layer, a SiGe layer, or a combination thereof.

[0095] Multiple recessed regions R9 can be formed in the upper part of the fin-type active region F9, and multiple source / drain regions 930 can be formed in the recessed regions R9. The source / drain regions 930 may include, for example, epitaxially grown semiconductor layers. The source / drain regions 930 may be related to the above-referenced... Figure 2A and Figure 2B The described source / drain SDs are basically the same or similar.

[0096] Gate lines 960 may be located on the finned active region F9 to cover the nanosheet stack NSS and surround each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3. Each of the gate lines 960 may include a main gate portion 960M and a plurality of sub-gate portions 960S. The main gate portion 960M extends in a second horizontal direction (Y direction) (e.g., longitudinally) to cover the top surface of the nanosheet stack NSS, and the plurality of sub-gate portions 960S are integrally connected to the main gate portion 960M and are respectively located between the third nanosheet N3 and the second nanosheet N2, between the second nanosheet N2 and the first nanosheet N1, and between the first nanosheet N1 and the finned active region F9. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have a gate-all-around (GAA) structure surrounded by the gate lines 960. Gate lines 960 may include, for example, a metal, a metal nitride, a metal carbide, or a combination thereof. Metals can be selected from, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. Metal nitrides can be selected from, for example, TiN and TaN. Metal carbides can include, for example, TiAlC. The gate insulating film 952 can be located between the nanosheet stacked NSS and the gate line 960. The gate insulating film 952 can be connected to a reference... Figure 2A and Figure 2B The gate insulating film 132 described is substantially the same as or similar to that described.

[0097] A metal silicide film 982 can be formed on the top surface of each of the source / drain regions 930. The metal silicide film 982 can be used with a reference... Figure 2A and Figure 2BThe metal silicide film 152 described is essentially the same as or similar to the metal silicide film 982.

[0098] Each of the gate lines 960 may have its two sidewalls covered by a plurality of external insulating spacers 918. The external insulating spacers 918 may be on a stack of multiple nanosheets (NSS) to cover the two sidewalls of the main gate portion 960M. The external insulating spacers 918 and the source / drain regions 930 may be covered by an insulating liner 942. The external insulating spacers 918 and the insulating liner 942 may comprise, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or combinations thereof. The insulating liner 942 may be omitted.

[0099] Multiple internal insulating spacers 928 are located between the third nanosheet N3 and the second nanosheet N2, between the second nanosheet N2 and the first nanosheet N1, and between the first nanosheet N1 and the fin-type active region F9. Each of the two sidewalls of each of the sub-gate portions 960S may be covered with an internal insulating spacer 928, wherein a gate insulating film 952 is located between the sidewall of each sub-gate portion 960S and the internal insulating spacer 928. Multiple internal insulating spacers 928 may be located between the sub-gate portion 960S and the source / drain region 930. In an example embodiment, the external insulating spacer 918 and the internal insulating spacer 928 may comprise the same insulating material as each other. In an example embodiment, the external insulating spacer 918 and the internal insulating spacer 928 may comprise different insulating materials as each other. The internal insulating spacer 928 may comprise, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or combinations thereof. The internal insulating spacer 928 may also include an air gap.

[0100] The insulating liner 942 may be covered with an inter-gate insulating film 944. The inter-gate insulating film 944 may include, for example, a silicon oxide film. Multiple source / drain contact patterns CAP9 may be located in multiple contact holes 980, which pass through the inter-gate insulating film 944 and the insulating liner 942. Each of the source / drain contact patterns CAP9 may be connected to the source / drain region 930 via a metal silicide film 982. Each of the source / drain contact patterns CAP9 may include a conductive barrier film 954 and a metal plug 956. Each of the source / drain contact patterns CAP9 may include a first portion S91 and a second portion S92, which have different heights in the vertical direction (Z direction) and are integrally connected to each other.

[0101] In each of the source / drain contact patterns CAP9, a conductive barrier film 954 and a metal plug 956 may extend on the first portion S91 and the second portion S92 to be included in the first portion S91 and the second portion S92.

[0102] In the first portion S91 of each of the source / drain contact patterns CAP9, the top surface of the conductive barrier film 954 may be coplanar with the top surface of the metal plug 956 at a vertical height level LV91. In the second portion S92 of each of the source / drain contact patterns CAP9, the vertical height level LV92 of the uppermost surface of the conductive barrier film 954 is lower than the vertical height level LV93 of the uppermost surface of the metal plug 956. The height difference between the vertical height level LV93 of the uppermost surface of the metal plug 956 and the vertical height level LV92 of the uppermost surface of the conductive barrier film 954 in the second portion S92 may be from about 1 nm to about 5 nm, for example, from about 2 nm to about 3 nm.

[0103] In the second portion S92 of each of the source / drain contact patterns CAP9, the metal plug 956 may include a protruding top 956P at a height level higher than the vertical height level LV92 of the uppermost surface of the conductive barrier film 954. In the second portion S92 of each of the source / drain contact patterns CAP9, the sidewalls of the protruding top 956P of the metal plug 956 may not be covered by the conductive barrier film 954.

[0104] and Figure 3A and Figure 3B Similar to the protruding top 156P shown, the protruding top 956P can have a flat top surface (e.g., a substantially planar top surface). However, the embodiments are not limited to this. For example, the metal plug 956 may include a surface with a similar shape to... Figures 5A to 7B The convex top shown is of the same or similar shape as one of the convex tops 356P, 456P, and 556P, instead of the convex top 956P.

[0105] The conductive barrier film 954 and metal plug 956 in each of the source / drain contact patterns CAP9 can be respectively referenced Figures 2A to 3B The conductive barrier film 154 and the metal plug 156 described are substantially the same or similar. Each of the gate lines 960 may be covered by an insulating cover line 940. The insulating cover line 940 may have different thicknesses at different locations. For example, the insulating cover line 940 may have a variable thickness in a first horizontal direction (X direction). The insulating cover line 940 may be related to a reference... Figure 2A and Figure 2B The insulation covering wire 140 described is substantially the same as or similar to the insulation covering wire 140.

[0106] The buried insulating film 970 can cover the top surface of the second portion S92 and the top surface of the insulating cover line 940 of each of the source / drain contact patterns CAP9. The buried insulating film 970 can contact the top surface of the second portion S92 and the top surface of the insulating cover line 940.

[0107] The buried insulating film 970 may include a main buried portion 970M and a buried protrusion 970P, the buried protrusion 970P protruding from the main buried portion 970M toward the substrate 902. The main buried portion 970M may contact the top surface of the metal plug 956, a portion of the insulating liner 942, a portion of the inter-gate insulating film 944, and a plurality of insulating cover lines 940 included in each of the plurality of second portions S92. The buried protrusion 970P may be on the second portion S92 of each of the source / drain contact patterns CAP9 to contact the top surface of the conductive barrier film 954. The buried protrusion 970P may also contact the sidewall of the protruding top 956P of the metal plug 956. The buried protrusion 970P may fill a space defined by the top surface of the conductive barrier film 954, the sidewall of the protruding top 956P of the metal plug 956, and the sidewall of the inter-gate insulating film 944 of the second portion S92.

[0108] The buried insulating film 970 may have a planarized top surface. The buried insulating film 970 may include a portion filling the space above a second portion S92 of each of the source / drain contact patterns CAP9 between gate lines 960. The top surface of the buried insulating film 970 may be coplanar with the respective uppermost surfaces of the conductive barrier film 954 and the metal plug 956, which are included in a first portion S91 of each of the source / drain contact patterns CAP9 and may be substantially at a vertical height level LV91. A specific configuration of the buried insulating film 970 may be referenced above. Figures 2A to 3B The specific configuration of the buried insulating film 170 described is the same as or similar to that described. (Reference) Figures 10A to 10C The described integrated circuit device 900 includes a metal plug 956, which includes a protruding top 956P in the second portion S92 of each of the source / drain contact patterns CAP9. The sidewalls of the protruding top 956P may be covered by a buried protrusion 970P of the buried insulating film 970. Therefore, at least by the buried protrusion 970P, the spacing distance from the conductive barrier film 954 forming the second portion S92 and the metal plug 956 to another conductive region adjacent to the second portion S92 can be ensured. Thus, an insulation margin between the second portion S92 of each of the source / drain contact patterns CAP9 and the adjacent conductive region can be ensured, thereby reducing or preventing undesirable short circuits between the second portion S92 and the adjacent conductive region and improving the reliability of the integrated circuit device 900.

[0109] In the following, specific examples will be used to describe methods for manufacturing integrated circuit devices according to some embodiments of the present invention.

[0110] Figures 11A to 22B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention. Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A and Figure 22A It shows the respective and the respective along Figure 1 The corresponding portions of the cross-sections intercepted by lines X1-X1′ and X2-X2′, and Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B and Figure 22B It shows the relationship with along Figure 1 The portion corresponding to the cross section intercepted by line Y1-Y1′. In the following text, reference will be made to... Figures 11A to 22B Description of manufacturing Figures 1 to 3B An example of a method for the integrated circuit device 100 shown.

[0111] refer to Figure 11A and Figure 11B A plurality of finned active regions FA and an isolation film 112 can be formed by partially etching the substrate 110 in the first device region RX1 and the second device region RX2. The plurality of finned active regions FA protrude from the main surface 110M of the substrate 110 in the vertical direction (Z direction) and extend parallel to each other in the first horizontal direction (X direction), and the isolation film 112 covers the two sidewalls of the lower portion of each of the finned active regions FA. A deep trench DT defining the first device region RX1 and the second device region RX2 can be formed by etching a portion of the isolation film 112 and a portion of the substrate 110, and the deep trench DT can be filled with an isolation insulating film 114. Therefore, the deep trench DT in the device isolation region DT can be filled with an isolation insulating film 114. In the first device region RX1 and the second device region RX2, the finned active regions FA can protrude upward from the top surface of the isolation film 112.

[0112] refer to Figure 12Aand Figure 12B Multiple dummy gate structures DGS extending to intersect with the fin-type active region FA are formed on the isolation film 112 and the isolation insulating film 114. Each of the dummy gate structures DGS may include a dummy gate insulating film D12, a dummy gate line D14, and a dummy insulating capping layer D16 sequentially stacked on the fin-type active region FA. The dummy gate insulating film D12 may include, for example, silicon oxide. The dummy gate line D14 may include, for example, polysilicon. The dummy insulating capping layer D16 may include, for example, silicon nitride.

[0113] Insulating spacers 120 can be formed on each of the two sidewalls of each of the dummy gate structures DGS, and multiple recessed regions RR can be formed on the upper portion of each of the multiple finned active regions FA by partially etching the exposed finned active regions FA at the two sidewalls of each dummy gate structure DGS. Multiple source / drain regions SD can then be formed to fill the recessed regions RR.

[0114] A separator 112, a barrier insulating film 114, source / drain regions SD, and an inter-gate insulating film 128 covering the source / drain regions SD can be formed between the dummy gate structures DGS. In an example embodiment, an insulating liner (not shown) covering the source / drain regions SD can also be formed before forming the inter-gate insulating film 128. The insulating liner may include, for example, SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or combinations thereof.

[0115] refer to Figure 13A and Figure 13B From the obtained by using, for example, chemical mechanical polishing (CMP) processes Figure 12A and Figure 12B The structure removes the dummy insulating capping layer D16 and the insulating film surrounding the dummy insulating capping layer D16, exposing the dummy gate line D14. At this time, the height of the inter-gate insulating film 128 and the insulating spacer 120 can be reduced.

[0116] refer to Figure 14A and Figure 14B By obtaining Figure 13A and Figure 13B The structure removes multiple dummy gate lines D14 and multiple dummy gate insulating films D12, providing multiple gate spaces GA. The insulating spacer 120, the fin-type active region FA, the isolation film 112, and the isolation insulating film 114 can be exposed through the gate spaces GA.

[0117] refer to Figure 15A and Figure 15B In the obtained Figure 14A and Figure 14BA gate insulating film 132, a gate line GL, and an insulating cover line 140 are formed in the gate space GA of the structure.

[0118] To form the gate insulating film 132, gate lines GL, and insulating cover line 140, multiple gate insulating films 132 and multiple gate lines GL can be formed to fill the gate space GA. Then, the multiple gate insulating films 132 and multiple gate lines GL are etched back to reduce their height, thereby filling only the lower portion of the gate space GA. During the etch-back of the gate insulating films 132 and gate lines GL, the upper portion of the insulating spacer 120 defining the gate space GA can also be removed, allowing the height of the insulating spacer 120 to be reduced. Subsequently, the insulating cover line 140 can be formed to cover the top surface of each of the gate lines GL, gate insulating films 132, and insulating spacers 120 in the gate space GA, and to fill the upper portion of the gate space GA.

[0119] In an example embodiment, an interface film (not shown) may be formed prior to forming the gate insulating film 132 to cover the surface of each of the finned active regions FA exposed by the gate space GA. For example, to form the interface film, the finned active regions FA exposed in the gate space GA may be partially oxidized.

[0120] refer to Figure 16A and Figure 16B A plurality of source / drain contact holes (CAHs) are formed through the inter-gate insulating film 128 to expose the source / drain region SD, and contact insulating spacers 150 are formed to cover the inner sidewall of each of the source / drain contact holes (CAHs). To form the contact insulating spacers 150, an insulating spacer film can be formed to conformally cover the inner sidewall of each of the source / drain contact holes (CAHs), and then the insulating spacer film is anisotropically etched to expose the source / drain region SD through each source / drain contact hole (CAH). Thus, a plurality of contact insulating spacers 150 can be obtained, each of the plurality of contact insulating spacers 150 including a portion of the insulating spacer film remaining on the sidewall of the source / drain contact hole (CAH).

[0121] Multiple metal silicide films 152 and multiple preliminary source / drain contacts RCAs are formed. The multiple metal silicide films 152 respectively cover the source / drain regions SD in the lower part of the source / drain contact holes CAH, and the multiple preliminary source / drain contact holes RCAs respectively fill the source / drain contact holes CAH. The preliminary source / drain contact holes RCAs may include a conductive barrier film 154 and a metal plug 156. In this specification, the conductive barrier film 154 included in the preliminary source / drain contact holes RCAs may be referred to as a "preliminary conductive barrier film", and the metal plug 156 included in the preliminary source / drain contact holes RCAs may be referred to as a "preliminary metal plug".

[0122] In an example embodiment, the metal silicide film 152, the conductive barrier film 154, and the metal plug 156 can be formed by performing the processes described below. First, a metal substrate conformally covering the source / drain region SD can be formed in the source / drain contact hole CAH. The metal substrate may include, for example, Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, Pd, or combinations thereof. Then, the conductive barrier film 154 can be formed to cover the exposed surface of the metal substrate and the inner sidewalls of the source / drain contact hole CAH. The metal substrate and the conductive barrier film 154 can be formed using, for example, physical vapor deposition (PVD), CVD, or atomic layer deposition (ALD). Subsequently, a thermal treatment can be performed on the resulting structure, including the metal substrate and the conductive barrier film 154, to induce a reaction between the semiconductor material of the source / drain region SD and the metal of the metal substrate, thereby forming the metal silicide film 152 covering the source / drain region SD. In an example embodiment, after the metal silicide film 152 is formed, a portion of the metal substrate may remain between each of the metal silicide films 152 and the conductive barrier film 154. In an example embodiment, the entire metal substrate may be used to form the metal silicide film 152, so no metal substrate remains between each of the metal silicide films 152 and the conductive barrier film 154.

[0123] Subsequently, a metal film can be formed on the resulting structure, including the metal silicide film 152 and the conductive barrier film 154, to a thickness sufficient to fill the interior of each of the source / drain contact holes CAH. The metal film can be formed using, for example, CVD, PVD, or electroplating. Then, unwanted portions of the conductive barrier film 154 and the metal film can be removed using, for example, CMP to expose the top surface of the inter-gate insulating film 128, thereby forming a metal plug 156 in each of the source / drain contact holes CAH, including the metal film remaining on the conductive barrier film 154.

[0124] refer to Figure 17A and Figure 17B By executing the method used in the obtained Figure 16A and Figure 16B A selective etching process in the structure removes a portion (e.g., the upper part) of the conductive barrier film 154 to reduce the height of the top surface of the conductive barrier film 154. Therefore, an upper recess UR can be formed between the metal plug 156 and the contact insulating spacer 150 in each of the source / drain contact holes (CAH) to expose the top surface of the conductive barrier film 154. The outer sidewall of the metal plug 156 and the inner sidewall of the contact insulating spacer 150 can be exposed through the upper recess UR.

[0125] In an example embodiment, the vertical height URH of the upper recess UR on the top surface of the exposed conductive barrier film 154 can be from about 1 nm to about 5 nm, for example, from about 2 nm to about 3 nm.

[0126] refer to Figure 18A and Figure 18B An etch stop film 160 is formed to cover the obtained... Figures 17A to 17B The top surface of the structure can be used to form multiple mask patterns MP on the etch stop film 160 to partially cover the initial source / drain contact RCA. The mask patterns MP can be positioned to... Figure 1 The source / drain via contact portion CAV corresponds to this. In some embodiments, each of the mask pattern MP may overlap with the first portion of the upper recess UR, but may not overlap with the second portion of the upper recess UR, such as... Figure 18A and Figure 18B As shown.

[0127] The etch stop film 160 may include a material different from the mask pattern MP. In an example embodiment, the etch stop film 160 may include, for example, SiOC, SiN, or a combination thereof, and the mask pattern MP may include, for example, a silicon oxide film, a spin-on hard mask (SOH) film, a photoresist film, or a combination thereof, but the embodiments are not limited thereto.

[0128] refer to Figure 19A and Figure 19B Using a mask pattern MP as an etching mask, the etch stop film 160 is etched, and the exposed initial source / drain contact RCA is etched in a specific etching atmosphere to reduce its density. Therefore, multiple source / drain contact patterns CAP with different heights at different locations can be formed. Each of the source / drain contact patterns CAP may include a first portion S1 and a second portion S2, which have different heights in the vertical direction (Z direction) and are integrally connected to each other. The first portion S1 may include a first portion of a metal plug 156, and the second portion S2 may include a second portion of the metal plug 156. Each of the first and second portions of the metal plug 156 may be part of a metal film formed as a monolithic or single-piece film by a single process, and the first and second portions of the metal plug 156 may be connected to each other without an interface or boundary. The first portion S1 may include a first portion of a conductive barrier film 154, and the second portion S2 may include a second portion of the conductive barrier film 154. Each of the first and second portions of the conductive barrier film 154 may be part of a barrier film formed as a monolithic or single-piece film and through a single process, and the first and second portions of the conductive barrier film 154 may be connected to each other without an interface or boundary.

[0129] A specific etching atmosphere can be provided to etch the metal-containing film forming the initial source / drain contact RCA. In this specific etching atmosphere, the etching amount of the metal-containing film forming the initial source / drain contact RCA can be greater than the etching amount of the insulating film forming the plurality of insulating cover lines 140, and the etching amount of the insulating film forming the insulating cover lines 140 can be greater than 0. While etching the exposed portion of the initial source / drain contact RCA using a mask pattern MP as an etching mask, the metal plug 156 and each of the contact insulating spacers 150 are reduced. Figure 17A and Figure 17B The outline of the top surface of the preliminary source / drain contact RCA, including the upper recess UR, can be shifted downwards. Therefore, after forming the source / drain contact pattern CAP, a lower recess LR can be formed on the top surface of the second portion S2 of each of the source / drain contact patterns CAP, exposing the top surface of the conductive barrier film 154 between the metal plug 156 and the contact insulating spacer 150. The outer sidewall of the metal plug 156 and the inner sidewall of the contact insulating spacer 150 of each of the source / drain contact patterns CAP can be exposed through the lower recess LR.

[0130] In an example embodiment, the vertical height LRH of the recess LR on the top surface of the exposed conductive barrier film 154 can be from about 1 nm to about 5 nm, for example, from about 2 nm to about 3 nm.

[0131] The height of the portion of the insulating cover line 140 exposed to a specific etching atmosphere while using the mask pattern MP as an etching mask to etch the exposed portion of the initial source / drain contact RCA can be reduced.

[0132] In a specific etching atmosphere, while forming the source / drain contact pattern CAP including the first portion S1 and the second portion S2, the height of each of the mask pattern MP, the plurality of insulating spacers 120 and the inter-gate insulating film 128 can be reduced.

[0133] refer to Figure 20A and Figure 20B The insulating film obtained Figure 19A and Figure 19B The structure is formed to have a thickness sufficient to fill the space between the mask patterns MP, and the resulting structure including the insulating film is planarized to form a buried insulating film 170 including the planarized insulating film. While performing planarization until the buried insulating film 170 is obtained, the upper part of each of the mask patterns MP, the etch stop film 160, and the source / drain contact patterns CAP is removed, such that the respective top surfaces of the conductive barrier film 154 and the metal plug 156 forming the first portion S1 of each of the source / drain contact patterns CAP can be coplanar with each other and can be substantially at the vertical height level LV1.

[0134] The second portion S2 of each of the source / drain contact patterns CAP and the insulating cover line 140 may be covered with a buried insulating film 170. The buried insulating film 170 may be formed to fill the space above the second portion S2 of each of the source / drain contact patterns CAP between the gate lines GL. The buried insulating film 170 may include a buried protrusion 170P that fills a lower recess LR on the top surface of the second portion S2 (see [link to documentation]). Figure 19A and Figure 19B ).

[0135] The buried insulating film 170 may have a planarized top surface (e.g., a flat or substantially faceted top surface). The top surface of the buried insulating film 170 may extend substantially at a vertical height level LV1 on the same plane as the respective top surfaces of the conductive barrier film 154 and the metal plug 156 forming the first portion S1.

[0136] refer to Figure 21A and Figure 21B In the obtained Figure 20A and Figure 20B An insulating structure 180 is formed on the structure. The insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184, which are sequentially formed on the buried insulating film 170 and the source / drain contact pattern CAP.

[0137] refer to Figure 22A and Figure 22B Multiple source / drain via contacts CAV are formed, which are connected to the corresponding first portion S1 of the source / drain contact pattern CAP, and multiple gate contacts CB are connected to multiple gate lines GL.

[0138] In an example embodiment, the source / drain via contact CAV and the gate contact CB can be formed simultaneously. Alternatively, the source / drain via contact CAV and the gate contact CB can be formed sequentially using separate processes. In this case, the gate contact CB can be formed after the source / drain via contact CAV, or vice versa.

[0139] Each of the source / drain via contacts CAV can pass through the insulating structure 180 and contact the top surface of the first portion S1 of one of the source / drain contact patterns CAP. Each of the gate contacts CB can pass through one of the interlayer insulating film 184, the etch stop film 182, the buried insulating film 170, and the insulating cover line 140 and contact the top surface of one of the gate lines GL.

[0140] Each of some gate contacts CB can contact the gate line GL contact in a location adjacent to the second portion S2 of the source / drain contact pattern CAP. In this case, as... Figure 22A As shown, the buried protrusion 170P of the buried insulating film 170 can be located between the second portion S2 of the source / drain contact pattern CAP and the gate line GL adjacent to the second portion S2 in the first horizontal direction (X direction). Therefore, at least the buried protrusion 170P can ensure the spacing distance from the conductive barrier film 154 and the metal plug 156 forming the second portion S2 to the gate line GL. Therefore, even when the gate contact portion CB is adjacent to the second portion S2 of the source / drain contact pattern CAP, the insulation margin between the gate contact portion CB and the source / drain contact pattern CAP can be ensured, thereby reducing or preventing undesirable short circuits between the gate contact portion CB and the source / drain contact pattern CAP.

[0141] Figures 23A to 23D This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention. Figures 23A to 23D The stages in sequence are shown separately and separately along... Figure 1 The cross-sectional views are of the corresponding portions of the sections intercepted by lines X1-X1′ and X2-X2′. Referring to the following text... Figures 23A to 23D Description of manufacturing Figures 1 to 3B Another example of the method of the integrated circuit device 100 shown.

[0142] refer to Figure 23A Use reference Figure 18A and Figure 18B The described method, in order to execute the reference Figures 11A to 16B The method described for forming multiple preliminary source / drain contacts (RCAs) is used to form an etch stop film 160 and multiple mask patterns MP on the obtained structure.

[0143] refer to Figure 23B In the obtained Figure 23A The structure uses a mask pattern MP as an etching mask to etch the etch stop film 160, thereby exposing some of the initial source / drain contacts RCA in the initial source / drain contacts RCA.

[0144] refer to Figure 23C The result obtained by using the mask pattern MP as the etching mask pair Figure 23B The structure performs a back-etching process, enabling the reference... Figure 17A and Figure 17B The described method selectively removes a portion of the conductive barrier film 154 from each exposed initial source / drain contact RCA. Consequently, the height of the top surface of the conductive barrier film 154 is reduced, and an upper recess UR is formed.

[0145] refer to Figure 23D Through reference Figure 19A and Figure 19B The method described is similar to the method obtained by etching using a mask pattern MP as an etch mask. Figure 23C The initial source / drain contact portion RCA in the structure is used to form multiple source / drain contact patterns CAP. Each source / drain contact pattern CAP includes a first portion S1 and a second portion S2, which are integrally connected to each other. A recess LR can be formed on the top surface of the top surface of the exposed conductive barrier film 154 between the metal plug 156 and the contact insulating spacer 150 in each of the source / drain contact patterns CAP.

[0146] Afterwards, you can execute the reference. Figures 20A to 22B The described manufacturing process Figures 1 to 3B The integrated circuit device 100 shown is shown.

[0147] Figure 24A and Figure 24B This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention. Figure 24A and Figure 24B The stages in sequence are shown separately and separately along... Figure 1 The cross-sectional views are of the corresponding portions of the sections intercepted by lines X1-X1′ and X2-X2′. Referring to the following text... Figure 24A and Figure 24B Description of manufacturing Figures 1 to 3B Another example of the method of the integrated circuit device 100 shown.

[0148] refer to Figure 24A When the obtained includes through reference Figure 23A and Figure 23B After forming an etch stop film 160 and a mask pattern MP on the structure including the initial source / drain contact RCA as described in the method described, the etch stop film 160 and mask pattern MP are formed by referring to a reference. Figure 23D The method described is similar to the one described above, using a mask pattern MP as an etching mask to etch the initial source / drain contact RCA, so that it is similar to the method described above. Figure 2A and Figure 2B The height of the corresponding portion of the second part S2 in each of the source / drain contact patterns CAP shown is reduced.

[0149] While reducing the height of some of the initial source / drain contact RCA by using a mask pattern MP as an etching mask to etch the exposed portion of the initial source / drain contact RCA, Figure 23BThe profile of the top surface of each of the initial source / drain contacts RCA can be shifted downwards. Therefore, in the portion of the initial source / drain contacts RCA where the height is reduced, the top surface of the conductive barrier film 154 can be at substantially the same height level as the top surface of the metal plug 156.

[0150] refer to Figure 24B The result obtained by using the mask pattern MP as the etching mask pair Figure 24A The structure performs a back-etching process, enabling it to pass through the reference... Figure 17A and Figure 17B A similar method is described to selectively remove a portion of the conductive barrier film 154 from each exposed initial source / drain contact RCA, thereby reducing the height of the top surface of the conductive barrier film 154 and forming a recess LR. Thus, multiple source / drain contact patterns CAP can be formed, each including a first portion S1 and a second portion S2 integrally connected to each other.

[0151] In some embodiments, instead of executing the reference Figure 24B The described process can be referenced. Figure 24A The described process uses a mask pattern MP as an etching mask to etch the initial source / drain contact RCA while applying an etching atmosphere, performing a one-step etching of the initial source / drain contact RCA, based on the obtained... Figure 23B The structure obtained Figure 24B The structure allows for appropriate control of the etching selectivity of each of the conductive barrier film 154 and the metal plug 156 in an etching atmosphere. This can be achieved by using a mask pattern MP as an etching mask pair. Figure 23B The structure shown is formed by performing a single etching process. Figure 24B The structure shown.

[0152] Afterwards, you can execute the reference. Figures 20A to 22B The described manufacturing process Figures 1 to 3B The integrated circuit device 100 shown is shown.

[0153] Although it has been referenced Figures 11A to 22B , Figures 23A to 23D ,as well as Figure 24A and Figure 24B Describes manufacturing Figures 1 to 3B The method of the integrated circuit device 100 shown is an example, but those skilled in the art will understand that, without departing from the scope of the inventive concept, the method can be modified by referring to the reference. Figures 11A to 22B , Figures 23A to 23D ,as well as Figure 24A and Figure 24B The described method is modified and changed in various ways to manufacture Figure 4A and Figure 4B The integrated circuit device 200 shown Figure 5A and Figure 5B The integrated circuit device 300 shown Figure 6A and Figure 6B The integrated circuit device 400 shown Figure 7A and Figure 7B The integrated circuit device 500 shown Figure 8A and Figure 8B The integrated circuit device 600 shown Figure 9 The integrated circuit device 700 shown Figures 10A to 10C The integrated circuit device 900 shown, and other integrated circuit devices having various structures modified and altered based on the aforementioned integrated circuit device.

[0154] In the example embodiment, reference Figures 11A to 22B The process described for manufacturing integrated circuit device 100 can be used to manufacture... Figure 4A and Figure 4B The integrated circuit device 200 is shown. However, in the reference... Figure 22A and Figure 22B After the source / drain via contact CAV and gate contact CB are formed in the described stage, a process can also be performed to form multiple wires ML connected to the source / drain via contact CAV and gate contact CB.

[0155] In the example embodiment, in order to manufacture Figure 5A and Figure 5B The integrated circuit device 300 shown and Figure 6A and Figure 6B The integrated circuit device 400 shown can be used with reference to Figures 11A to 22B The process for manufacturing the integrated circuit device 100 is described. However, in reference... Figure 17A and Figure 17B The process for forming the upper recess UR described and / or referenced Figure 19A and Figure 19B In the described process for forming the recess LR, the etch selectivity of the conductive barrier film 154 relative to the metal plug 156 can be controlled, allowing the metal plug 356 (which has rounded corners 356C at the outer edge of the protruding top 356P, as shown in the reference) to be formed in the final structure including the recess LR. Figure 5A and Figure 5B The aforementioned) or metal plug 456 (which has a top surface portion 456T and a rounded corner 456C in the protruding top 456P, as referenced) Figure 6A and Figure 6B (as described above), instead of the metal plug 156.

[0156] In the example embodiment, in order to manufacture Figure 7A and Figure 7B The integrated circuit device 500 shown can be used with reference to Figures 11A to 22B The process for manufacturing the integrated circuit device 100 is described. However, in reference... Figure 16A and Figure 16B In the process of forming the metal plug 156, the metal plug 156 may be formed to have at least a slit or void in its interior, and in reference... Figure 17A and Figure 17B The process and / or reference for forming the upper recess UR Figure 19A and Figure 19B In the process of forming the lower recess LR, the etching selectivity of the conductive barrier film 154 relative to the metal plug 156 can be controlled, such that the relatively weaker portions of the metal plug 156 due to gaps or voids in the metal plug 156 are also etched during the etching process used to form the upper recess UR or the lower recess LR, thereby forming a metal plug 556 with a bimodal protrusion in the protruding top 556P in the final structure including the lower recess LR, instead of the metal plug 156.

[0157] Figures 25A to 31 This is a cross-sectional view illustrating a method for manufacturing an integrated circuit device according to some embodiments of the present invention, wherein... Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A and Figure 31 It shows the relationship with along Figure 10A The portion corresponding to the cross section intercepted by line X9-X9′ in the diagram, and Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B and Figure 30B It shows the relationship with along Figure 10A The portion corresponding to the cross section intercepted by line Y9-Y9′. In the following text, reference will be made to... Figures 25A to 31 Description of manufacturing Figures 10B to 10C An example of a method for the integrated circuit device 900 shown. In Figures 1 to 10C as well as Figure 25A and Figure 31 In this context, similar reference numerals and characters denote similar elements, and their detailed descriptions may be omitted.

[0158] refer to Figure 25A and Figure 25BMultiple sacrificial semiconductor layers 904 and multiple nanosheet semiconductor layers NS are alternately stacked on a substrate 902. The sacrificial semiconductor layers 904 may comprise a different material than the nanosheet semiconductor layers NS. In an example embodiment, the sacrificial semiconductor layer 904 may comprise, for example, SiGe, and the nanosheet semiconductor layers NS may comprise, for example, Si.

[0159] refer to Figure 26A and Figure 26B A trench T9 is formed by partially etching the sacrificial semiconductor layer 904, the nanosheet semiconductor layer NS, and the substrate 902, and an isolation film 912 is formed in the trench T9. Therefore, a fin-type active region F9 defined by the trench T9 can be formed. The stacked structure of the sacrificial semiconductor layer 904 and the nanosheet semiconductor layer NS remains on the top surface FT of the fin-type active region F9.

[0160] refer to Figure 27A and Figure 27B In the obtained Figure 26A and Figure 26B Multiple dummy gate structures DGS9 are formed on the stacked structure of the sacrificial semiconductor layer 904 and the nanosheet semiconductor layer NS, and multiple external insulating spacers 918 are formed covering the two sidewalls of each of the dummy gate structures DGS9. Then, using the dummy gate structures DGS9 and the external insulating spacers 918 as an etching mask, the sacrificial semiconductor layer 904 and the nanosheet semiconductor layer NS are partially etched, such that the nanosheet semiconductor layer NS is separated into multiple nanosheet stacks NSS, wherein the nanosheet stacks NSS include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. Subsequently, the fin-type active regions F9 exposed between the nanosheet stacks NSS are etched, thereby forming multiple recessed regions R9 in the upper part of the fin-type active regions F9.

[0161] Each of the dummy gate structures DGS9 may extend in a second horizontal direction (Y direction) (e.g., longitudinally). Each of the dummy gate structures DGS9 may have a structure in which an insulating layer D962, a dummy gate layer D964, and a capping layer D966 are sequentially stacked. In an example embodiment, the insulating layer D962 may include, for example, silicon oxide, the dummy gate layer D964 may include, for example, polysilicon, and the capping layer D966 may include, for example, silicon nitride.

[0162] refer to Figure 28A and Figure 28B By partially removing the exposure to the obtained Figure 27A and Figure 27BThe sacrificial semiconductor layer 904 around the recessed region R9 of the structure forms a plurality of notches (e.g., openings) between the first nanosheet N1, the second nanosheet N2 and the third nanosheet N3 and the top surface FT, and forms a plurality of internal insulating spacers 928 that fill the recesses.

[0163] refer to Figure 29A and Figure 29B By obtaining Figure 28A and Figure 28B Semiconductor material is epitaxially grown on the exposed surface of the recessed region R9 of the structure to form multiple source / drain regions 930. An insulating liner 942 is formed to cover the resulting structure including the source / drain regions 930. An inter-gate insulating film 944 is formed on the insulating liner 942, and the top surface of the capping layer D966 is exposed by planarizing the top surfaces of each of the insulating liner 942 and the inter-gate insulating film 944. Subsequently, a gate space GS is provided by removing the dummy gate structure DGS9, and the sacrificial semiconductor layer 904 is removed through the gate space GS, such that the gate space GS extends into the space between the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the top surface FT.

[0164] refer to Figure 30A and Figure 30B A gate insulating film 952 is formed to cover the exposed surfaces of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, as well as the fin-type active region F9. Multiple gate lines 960 are formed on the gate insulating film 952 to fill multiple gate spaces GS. The upper portion of each of the gate lines 960, as well as the upper portion of each of the gate insulating film 952 and the external insulating spacers 918 surrounding the gate lines 960, is removed to clear the upper portion of each of the gate spaces GS. Subsequently, the upper portion of each of the gate spaces GS is filled with an insulating cover line 940. Because planarization is performed during the formation of the gate lines 960 and the insulating cover line 940, the height of each of the insulating liner 942 and the inter-gate insulating film 944 can be reduced.

[0165] refer to Figure 31 By partially etching the inter-gate insulating film 944 and the insulating liner 942, a plurality of contact holes 980 are formed to expose the source / drain region 930, and a metal silicide film 982 and a preliminary source / drain contact RCA9 are formed in each of the contact holes 980.

[0166] In the example embodiment, the referenced... Figure 16A and Figure 16B The method described is for forming a metal silicide film 152 and a preliminary source / drain contact RCA to form a metal silicide film 982 and a preliminary source / drain contact RCA 9.

[0167] After that, you can analyze the results. Figure 31 Structural Execution and Reference Figures 17A to 19B The process described is similar to that described, thereby forming multiple source / drain contact patterns CAP9 based on multiple initial source / drain contact portions RCA9 (see...). Figure 10B At this point, the height of a portion of the insulating cover line 940 is reduced, allowing the insulating cover line 940 to have a variable thickness in the first horizontal direction (X direction). Subsequently, it can be achieved by using a previously referenced... Figure 20A and Figure 20B The described method for forming buried insulating film 170 forms buried insulating film 970 to manufacture Figures 10A to 10C The integrated circuit device shown is 900.

[0168] In the accompanying drawings, two elements are shown to be in direct contact with each other without any intermediate elements.

[0169] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the scope of the inventive concept. Therefore, the scope of the inventive concept shall be determined by the widest permissible interpretation of the appended claims and their equivalents, to the fullest extent permitted by law, and shall not be construed or limited by the preceding detailed description.

Claims

1. An integrated circuit device, comprising: The fin-shaped active region extends on the substrate in a first horizontal direction; A gate line extends over the fin-shaped active region in a second horizontal direction that intersects the first horizontal direction. Source / drain regions are located on the fin-type active region and adjacent to the gate line; as well as A source / drain contact pattern, electrically connected to the source / drain region, includes a first portion and a second portion, the first portion having a first height in the vertical direction, and the second portion having a second height in the vertical direction less than the first height. The source / drain contact pattern includes a metal plug and a conductive barrier film, wherein the metal plug is in the first portion and the second portion, and the conductive barrier film is on the sidewall of the metal plug in the first portion and the second portion, and the first top surface of the conductive barrier film in the second portion is lower than the top surface of the metal plug in the second portion relative to the substrate.

2. The integrated circuit device according to claim 1, wherein, The second top surface of the conductive barrier film in the first part and the top surface of the metal plug in the first part are equidistant from the substrate.

3. The integrated circuit device according to claim 1, further comprising: An insulating film is buried between the second portion of the source / drain contact pattern and the gate line. The buried insulating film includes a buried protrusion on the second portion of the source / drain contact pattern, and the buried protrusion contacts the first top surface of the conductive barrier film in the second portion.

4. The integrated circuit device according to claim 1, wherein, The metal plug in the second portion of the source / drain contact pattern includes a protruding top at a height level higher than the first top surface of the conductive barrier film, the protruding top including a flat top surface.

5. The integrated circuit device according to claim 1, wherein, The metal plug in the second portion of the source / drain contact pattern includes a protruding top at a height level higher than the first top surface of the conductive barrier film, and the protruding top includes rounded corners.

6. The integrated circuit device according to claim 1, wherein, The metal plug in the second portion of the source / drain contact pattern includes a protruding top at a height level higher than the first top surface of the conductive barrier film, the protruding top including a top surface that bulges in a direction away from the substrate.

7. The integrated circuit device according to claim 1, wherein, The metal plug in the second portion of the source / drain contact pattern includes a protruding top at a height level higher than the first top surface of the conductive barrier film, the protruding top including a bi-peaked protrusion that bulges in a direction away from the substrate.

8. An integrated circuit device, comprising: Multiple fin-shaped active regions extend parallel to each other in a first horizontal direction on the substrate; Gate lines extend over the plurality of finned active regions in a second horizontal direction that intersects the first horizontal direction; Source / drain regions are located on the plurality of finned active regions and are adjacent to the gate line; as well as Source / drain contact patterns are electrically connected to the source / drain regions. The source / drain contact pattern includes a first portion and a second portion, wherein the first portion has a first height in the vertical direction, and the second portion has a second height in the vertical direction that is less than the first height. The first part includes a first portion of a metal plug and a first portion of a conductive barrier film on the sidewall of the first portion of the metal plug, and the second part includes a second portion of the metal plug and a second portion of the conductive barrier film on the sidewall of the second portion of the metal plug. The first top surface of the first portion of the conductive barrier film and the second top surface of the first portion of the metal plug are coplanar and at a first vertical height level, and relative to the substrate, the third top surface of the second portion of the conductive barrier film is lower than the fourth top surface of the second portion of the metal plug.

9. The integrated circuit device according to claim 8, further comprising: Contact insulating spacers surrounding the first and second portions of the source / drain contact pattern; An insulating cover line extends on the gate line in the second horizontal direction; as well as An insulating film is buried on the insulating cover line and the contact insulating spacer. The buried insulating film includes a buried protrusion that protrudes toward the substrate and is located in a space defined by the third top surface of the second portion of the conductive barrier film, the sidewall of the second portion of the metal plug, and the sidewall of the contact insulating spacer.

10. The integrated circuit device according to claim 8, wherein, The second portion of the metal plug includes a protruding top at a height level higher than the third top surface of the second portion of the conductive barrier film, the protruding top including rounded corners.

11. An integrated circuit device, comprising: The first fin-shaped active region and the second fin-shaped active region extend parallel to each other in a first horizontal direction on the substrate and are spaced apart from each other in a second horizontal direction that intersects the first horizontal direction. Gate lines extend longitudinally in the second horizontal direction over the first finned active region and the second finned active region; Source / drain regions, located on the first finned active region and the second finned active region; and Source / drain contact patterns are electrically connected to the source / drain regions. The source / drain contact pattern includes a first portion and a second portion. The first portion overlaps with the first fin-shaped active region in the vertical direction and has a first height in the vertical direction. The second portion overlaps with the second fin-shaped active region in the vertical direction and has a second height in the vertical direction that is less than the first height. The source / drain contact pattern includes a metal plug and a conductive barrier film, the metal plug including a protruding top in the second portion, and the conductive barrier film in the second portion being on the sidewall of the metal plug in the second portion and including a first top surface, the first top surface being lower than the top surface of the protruding top relative to the substrate.

12. A method for manufacturing an integrated circuit device, the method comprising: A fin-shaped active region is formed on the substrate extending in a first horizontal direction; A source / drain region is formed on the fin-shaped active region; as well as A source / drain contact pattern electrically connected to the source / drain region is formed. The source / drain contact pattern includes a first portion and a second portion. The first portion has a first height in the vertical direction, and the second portion has a second height in the vertical direction that is less than the first height. The source / drain contact pattern includes a metal plug and a conductive barrier film. The metal plug is in the first portion and the second portion. The conductive barrier film is on the sidewall of the metal plug in the first portion and the second portion. The conductive barrier film in the second portion includes a first top surface that is lower than the top surface of the metal plug in the second portion relative to the substrate.

13. The method according to claim 12, wherein, Forming the source / drain contact pattern includes: planarizing the top surface of the first portion, wherein, after planarizing the top surface of the first portion, the second top surface of the conductive barrier film in the first portion and the top surface of the metal plug in the first portion are equidistant from the substrate.

14. The method according to claim 12, wherein, Forming the source / drain contact pattern includes: An insulating film is formed on the source / drain region; A source / drain contact hole is formed in the insulating film, and the source / drain contact hole exposes the source / drain region; A preliminary source / drain contact portion is formed in the source / drain contact hole, the preliminary source / drain contact portion including a preliminary conductive barrier film and a preliminary metal plug; A mask pattern is formed on a portion of the initial source / drain contact; and Then, the initial source / drain contact portion is etched using the mask pattern as an etching mask to form the second portion of the source / drain contact pattern.

15. The method according to claim 14, wherein, Forming the source / drain contact pattern further includes: after forming the initial source / drain contact portion and before forming the mask pattern, forming an upper recess on the sidewall of the initial metal plug that exposes the initial source / drain contact portion by removing a portion of the initial conductive barrier film. The mask pattern overlaps with the first portion of the upper recess but does not overlap with the second portion of the upper recess. The formation of the second portion includes: etching the preliminary conductive barrier film by using the mask pattern as an etching mask to form a recessed portion that exposes the sidewall of the metal plug in the second portion.

16. The method of claim 14, further comprising: After forming the mask pattern and before forming the second portion, a portion of the initial conductive barrier film is removed from the portion of the initial source / drain contact while simultaneously forming the mask pattern on that portion, thus forming an upper recess on the sidewall of the initial metal plug that exposes the initial source / drain contact. The formation of the second portion includes: etching the preliminary conductive barrier film by using the mask pattern as an etching mask to form a recessed portion that exposes the sidewall of the metal plug in the second portion.

17. The method of claim 14, further comprising: After the second portion is formed, the initial conductive barrier film is selectively etched using the mask pattern as an etching mask to form a recessed portion that exposes the sidewalls of the initial metal plug.

18. The method according to claim 12, wherein, Forming the source / drain contact pattern includes: A recess is formed that exposes a portion of the sidewall of the metal plug in the second portion and the first top surface of the conductive barrier film, wherein, after the recess is formed, the metal plug in the second portion includes a protruding top that protrudes beyond the first top surface of the conductive barrier film.

19. A method for manufacturing an integrated circuit device, the method comprising: A fin-shaped active region is formed on the substrate extending in a first horizontal direction; A source / drain region is formed on the fin-shaped active region; An insulating film is formed on the source / drain region; A source / drain contact hole is formed in the insulating film, and the source / drain contact hole exposes the source / drain region; as well as A source / drain contact pattern is formed in the source / drain contact hole. The source / drain contact pattern includes a first portion and a second portion. The first portion has a first height in the vertical direction, and the second portion has a second height in the vertical direction that is less than the first height. The formation of the source / drain contact pattern includes: A preliminary source / drain contact portion is formed in the source / drain contact hole, the preliminary source / drain contact portion including a preliminary conductive barrier film and a preliminary metal plug; A mask pattern is formed on a portion of the initial source / drain contact; and Then, the preliminary conductive barrier film and the preliminary metal plug are etched using the mask pattern as an etching mask to form a metal plug and a conductive barrier film, wherein the metal plug is in the first portion and the second portion, and the conductive barrier film covers the sidewalls of the metal plug in the first portion and the second portion, and the conductive barrier film in the second portion includes a first top surface that is lower than the top surface of the metal plug in the second portion relative to the substrate.

20. A method for manufacturing an integrated circuit device, the method comprising: A first fin-shaped active region and a second fin-shaped active region are formed. The first fin-shaped active region and the second fin-shaped active region extend parallel to each other in a first horizontal direction on the substrate and are spaced apart from each other in a second horizontal direction that intersects the first horizontal direction. Source / drain regions are formed on the first fin-shaped active region and the second fin-shaped active region, and the source / drain regions are electrically connected to the first fin-shaped active region and the second fin-shaped active region; An insulating film is formed on the source / drain region; as well as A source / drain contact pattern is formed that passes through the insulating film and connects to the source / drain region. The source / drain contact pattern includes a first portion and a second portion. The first portion overlaps with the first fin-shaped active region in the vertical direction and has a first height in the vertical direction. The second portion overlaps with the second fin-shaped active region in the vertical direction and has a second height in the vertical direction that is less than the first height. The formation of the source / drain contact pattern includes: forming a metal plug and a conductive barrier film, the metal plug including a protruding top in the second portion, and the conductive barrier film in the second portion on the sidewall of the metal plug and including a first top surface, the first top surface being lower than the top surface of the protruding top relative to the substrate.

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