Method for uniquely authenticating and serializing semiconductor devices at the die level using optoelectronic marking

Abstract

A method for marking a semiconductor substrate at the die level to provide unique authentication and serialization, the method comprising: projecting a first pattern of actinic radiation onto a photoresist layer on the substrate using mask-based lithography, the first pattern defining a semiconductor device structure; and projecting a second pattern of actinic radiation onto the photoresist layer using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 834,093, filed on April 15, 2019, and entitled “METHOD FOR DIE-LEVEL UNIQUE AUTHENTICATION AND SERIALIZATION OF SEMICONDUCTOR DEVICES USING ELECTRICAL AND OPTICAL MARKING,” and U.S. Non-Provisional Patent Application No. 16 / 528,099, filed on July 31, 2019, and entitled “METHOD FOR DIE-LEVEL UNIQUE AUTHENTICATION AND SERIALIZATION OF SEMICONDUCTOR DEVICES USING ELECTRICAL AND OPTICALMARKING,” both of which are incorporated herein by reference in their entireties. Background Art Technical Field

[0003] The present application relates to unique marking of semiconductor devices for counterfeit control and unique electrical authentication. More particularly, the present application relates to a method for placing unique wiring structures at specific locations on a semiconductor device wafer using direct-write lithography.

[0004] Description of related technologies

[0005] The sale of counterfeit semiconductor devices is a global problem, costing chip manufacturers billions of dollars annually. US chipmakers alone lose over $7 billion annually. The Pentagon estimates that 15% of all spare and replacement chips purchased by the Pentagon are counterfeit. A disproportionate number of these problematic chips originate from foreign sources and enter the supply chain undetected. Therefore, there is a strong desire to prevent the use of counterfeit semiconductor devices.

[0006] There are many challenges and aspects to addressing the problem of counterfeit chips. A fundamental capability in combating the sale of counterfeit products is the ability to identify counterfeit devices and / or identify genuine devices. Being able to accurately and reliably identify counterfeits is very useful in eliminating counterfeits from commerce. In addition, being able to verify genuine devices compared to all devices on the market helps quantify losses in the event of violations of international trade laws. There are some conventional systems to verify the authenticity / functionality of semiconductors. For example, standards from industry associations such as SEMI attempt to encrypt batch numbers from trusted manufacturers. However, once counterfeit devices enter the open market, it is almost impossible to verify the integrity. Summary of the Invention

[0007] The technology disclosed herein enables chip manufacturers to uniquely identify their devices at the device level, providing an authentication mechanism to combat existing counterfeit devices. The technology disclosed herein provides systems and methods that enable unique optical serialization at the die level for chip authentication and / or in combination with hardware-level identification using existing or conventional semiconductor processing methods. This allows for efficient, cost-effective, and unique identification to be added to semiconductor production processes.

[0008] Furthermore, the methods disclosed herein provide unique identifiers on a die-by-die basis at the process level across multiple wafers. Conventional serialization methods do not provide this unique die-level marking. More specifically, the marking described herein is accomplished using a direct-write patterning system configured to provide unique processing on a die-by-die basis. While conventional mask-based photolithography would be cost-prohibitive, the direct-write system described herein provides an economical marking solution.

[0009] In one embodiment, direct-write photolithography is used to place unique wiring structures, such as arrays of conductive paths, at specific locations on the wafer die. Furthermore, mask-based exposure is used to place the circuit pattern on the die. Exposure of the unique markings can occur before or after the mask-based exposure. The photoresist layer on the die is developed to create the relief pattern.

[0010] The shape of the wiring structure is changed by varying at least one of line length, line width, line path, line turns, and line cross-sectional area, thereby providing multiple resistance or capacitance values. The unique electrical value of the wiring structure, together with the unique visual signature, provides a dual electrical / graphic identifier.

[0011] In addition to optical serialization, the technology described in this article also enables die-level circuit performance to be customized for unique electrical authentication. Unique die-level circuit performance is achieved by using direct-write patterning systems that can achieve unique processing on a die-by-die basis.

[0012] For the sake of clarity, the order of the different steps as described herein is presented. Generally, these steps can be performed in any suitable order. In addition, although each different feature, technology, configuration, etc. herein may be discussed in different places of the present disclosure, it is intended that each concept can be performed independently of each other or in combination with each other. Therefore, the features of the present application can be implemented and viewed in many different ways.

[0013] This Summary does not specify every embodiment and / or novel aspect of the present application. Instead, this Summary provides only a preliminary discussion of various embodiments and corresponding points of novelty compared to conventional techniques. Additional details and / or possible aspects of the disclosed embodiments are described in the Detailed Description section of this disclosure and the accompanying drawings, as further discussed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present application will be better understood in view of the description given in a non-limiting manner, taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1A Schematic diagram of exemplary patterns resulting from mask-based projection lithography applied to a set of wafers.

[0016] Figure 1B is a schematic diagram of exemplary patterns obtained by applying direct-write lithography to a set of wafers.

[0017] Figure 2A It is a schematic diagram of the wiring pattern on the die.

[0018] Figure 2B It is a schematic diagram of the wiring pattern on the die.

[0019] Figure 3 is a schematic diagram of an exemplary assignment of patterns resulting from direct-write lithography applied to a group of dies.

[0020] Figure 4 is a schematic diagram of an exemplary cross-sectional view of a die-sized substrate segment having a unique wiring structure formed by a direct-write identifier process and die circuitry formed by mask-based exposure.

[0021] Figure 5 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths.

[0022] Figure 6 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths.

[0023] Figure 7 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths.

[0024] Figure 8 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths.

[0025] Figure 9 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths.

[0026] Figure 10 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths.

[0027] Figure 11 is a schematic diagram of the unique wiring structure formed on the die in the form of an array of conductive paths. DETAILED DESCRIPTION

[0028] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application, but do not imply that the feature, structure, material, or characteristic is present in every embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment of the present application. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0029] The technology herein provides a method for uniquely identifying semiconductor chips at the die level across multiple wafers and batches using commonly available semiconductor processing techniques. This includes the use of direct-write processing that provides unique markings on a die-by-die basis.

[0030] Semiconductor patterning typically involves the use of optical lithography systems. Such systems use, for example, deep ultraviolet (DUV) electromagnetic radiation to form a high-resolution relief image pattern in a photosensitive resist material. This relief image pattern is then used as a template for selective deposition, etching processes, and other microfabrication processes. The image achieved in the photoresist is a projection of the primary pattern onto a photomask. Photomasks are typically constructed of chromium and quartz, which combine to form opaque and transparent areas that determine the propagation of source radiation at the mask interface. The photomask effectively defines the pattern of actinic radiation that reaches the photosensitive material film or layer. This creates an implicit pattern within the photosensitive material by altering the solubility of the material where the pattern's light interacts with the material. The implicit pattern is developed with one or more developing chemicals, resulting in a relief pattern on the substrate. While mask-based lithography is effective, one limitation of the process is that the construction of the photomask is not straightforward. Constructing a photomask is both time-consuming and relatively expensive. Furthermore, a given photomask pattern is fixed or identical for all wafers processed using that photomask. Figure 1AA fixed pattern resulting from mask-based projection lithography applied to a set of wafers (eg, wafer 1 and wafer 2) is shown.

[0031] There are alternative maskless patterning technologies that use direct write techniques. Direct write systems include electron beam lithography, plasma lithography, grating light valve lithography, and digital light projection patterning systems, among others. In operation, direct write lithography typically involves providing a design file to a write engine. The write engine directs the exposure process to define a pattern in the sensitive material based on a coordinate grid to drive the write head(s). One advantage of a direct write system is that the exposure pattern is not constrained by a physical medium (such as a photomask), but is generated digitally. Therefore, each exposure can use a different design file or a modification of the design file so that each individual exposure can be different from the previous and subsequent exposures. The difference can be small or large. Figure 1B It shows how direct-write lithography can generate different exposure patterns (e.g., "A" and "B") for different wafers (e.g., Wafer 1 and Wafer 2). As used herein, by altering the information in the digital domain before the pattern is exposed, each wafer and / or each die can contain unique information.

[0032] In one non-limiting embodiment, direct write lithography is used to place electrical identifiers in a photoresist at specific locations on a wafer-by-wafer or device-by-device basis. The placement of this unique mark can be implemented as an implicit pattern in a photosensitive material combined with a conventional coating / development process. Since the wafer pattern data is stored in the digital domain, this unique direct write mark can be added without worrying about the physical mask (photomask) overhead. The serialization can then be permanently transferred to the lower layer using a conventional wet or dry etching process. In some embodiments, the lower layer can be a conductive layer or a dielectric layer. In other embodiments, the lower layer can be an oxide layer or a nitride layer.

[0033] The specific type of electrical identifier used in the marking method described herein can be selected by each user or system controller and / or based on the type of identification / authentication desired. This unique identifier can be simple or comprehensive. For example, a given unique identifier can be a simple serial number for each die. Alternatively, the unique identifier can include the production date, chip specifications, technology generation, factory of origin, batch, etc.

[0034] The technology described herein includes a standalone method that provides for the tagging of simple, unique circuit performance parameters that can be adjusted on a die-level basis. Adjustable characteristics include resistivity and capacitance, among others. For example, a simple doped polysilicon resistor can have its resistance adjusted based on its length, e.g. Figure 2A and Figure 2B Depicted. Figure 2AA wire on the die has a resistance of 15 ohms, and Figure 2B A length of wire on a die has a resistance of 30 ohms. Alternatively, various metals can be used, eliminating the need for additional processing steps (beyond direct write exposure). For example, the direct write pattern is filled as part of a dual damascene metallization process. During packaging, an electrically testable configuration can be made so that the resistance can be easily read to determine whether the optical serialization given to a particular die matches its electrical characteristics. In another embodiment, the technology herein is applied to security applications that require cryptographic parity for encoding / decoding. In other words, simple, electrically adjustable circuit components can be used for unique authentication.

[0035] In some embodiments, unique marking may include allocating or designating a specific area for the ID tag. Figure 3 A typical 2×2 die enumeration is shown, examining the enumeration field of four dies. Note that the majority of this area is dedicated to a specific circuit design. This can include placement of transistors, field-effect transistors, logic, memory, wiring, and so on. Smaller areas within the die boundaries are then designated or allocated for unique electrical wiring. In this example, these areas are the small boxes in the upper left corner of each die (ID001, ID002, ID003, ID004). The area designated for unique identification marks may be less than one square millimeter.

[0036] Exposure of the unique wiring structure can occur before or after the mask-based exposure. For example, the wafer is prepared for photolithographic exposure by coating it with a photoresist film in a coater-developer (tracker) tool. The wafer is then ready for transport to a scanner or stepper. Before being transferred to the scanner, the wafer can be moved to another tool or another module within the coater-developer to expose the unique mark by direct write exposure. Alternatively, the mask-based exposure is performed first, followed by direct write exposure (e.g., using a laser galvanometer projection device).

[0037] Figure 4 It is shown how a unique wiring structure can be formed in one area of ​​a given die by direct-write lithography exposure, while the die circuitry can be formed in the rest of the die. Note that the rest of the circuitry can also be formed by direct-write lithography, but for relatively small resolutions, mask-based lithography is generally required to ensure resolution and yield. The unique wiring structure herein does not need to be formed at the dimensions of advanced semiconductor nodes and can have a relaxed resolution within the capabilities of various laser galvanometer and other direct-write projection technologies. Direct-write lithography and mask-based lithography may not be required, as long as a unique wiring structure with a unique electrical signature is formed in the die.

[0038] The unique wiring structures herein can be simple or complex and can incorporate graphic design elements. In one embodiment, a set of conductive paths or a matrix of conductive paths can be used to create any combination of values ​​to provide a unique electrical identifier. By way of non-limiting example, Figure 5 An array or matrix of conductive paths is shown. For this example, six conductive paths are shown. Each conductive path is labeled Bit 1, Bit 2, Bit 3, Bit 4, Bit 5, and Bit 6. More or fewer conductive paths can be used depending on the number of different unique identifier combinations desired. These conductive paths can also be viewed as numbers or values ​​or value-character positions.

[0039] Each conductive path may have a corresponding value. This value may be a resistance / capacitance value. Multiple different resistance values ​​may be possible in a given conductive path as desired. For example, the range of values ​​may be 0 to 10, 0 to 500, or one thousand or more. Figure 6 As shown, the initial value can be zero. Note that there is no conductor formed between bit 1 and ground (or other conductive target or part of the corresponding circuit). Therefore, there is infinite resistance, and this state can be the first value of the first code (e.g., code 00). Similarly, there is no metal to complete the other conductive paths (e.g., bit 2 to ground). Each conductive path contact (bit 1, bit 2, ...) can be connected to the multiplexer. Since there is no poly or metal, all conductive paths are open.

[0040] Now refer to Figure 7 , there is a conductive structure connecting the bit 1 contact to ground, so that the electrical signal can be transmitted from the bit 1 contact to the ground / destination through the bit 1 conductive path. For example, a relatively thin wire is formed between the bit 1 contact and the ground, and the entire electrical structure is patterned by direct write lithography. In the case of a relatively thin wire, the resistance between the bit 1 contact and the ground may be relatively high. This resistance value can be associated with a second value or code (e.g., code 01).

[0041] Then, the first conductive paths may be formed with different geometries to produce different resistance values. Figure 8 Examples of producing different resistance values ​​are shown. Figure 8 In the direct-write pattern design, a section of the conductive path is defined as having a greater thickness. This can appear as a block along the wire. As the thickness of this section increases, the resistivity decreases, resulting in a different resistance value between bit 1 and ground than between bit 1 and ground. Figure 7 The different resistance value may be a third value (eg, code 03).

[0042] The conductive path resistance can be further modified on a per-die or wafer basis by directly writing new geometries for each conductive path. Figure 9It is shown that for the length of this particular conductive path, up to eight blocks can be added to the conductive path. The number of blocks can be increased by resizing the blocks and / or lengthening the conductive path. By adding up to eight blocks to the wire, the bit 1 conductive path can support ten different numbers / values / codes corresponding to different resistance values. For example, the first digit represents no wire, the second digit represents only wire, and the third through tenth digits represent up to eight blocks. A multiplexer or other circuit system can be used to test the resistance value of each conductive path. With eight polycrystalline blocks added, the resistance will be less than with seven polycrystalline blocks (along the wire). Similarly, with a total of six blocks on the wire, the resistance will be less than with seven blocks.

[0043] By using various geometric shapes, the resistance of the wiring structure can be changed. For example, in addition to adding blocks or segments to the wire, the width of the core or the core itself can be changed. Figure 10 In the example of the wiring structure of FIG, it is noted that the width of the wire (line) extending between the bit 1 contact and the ground is greater than that of the bit 2 contact. Figure 9 If a given design allows 10 different line widths per conductive path, and each line width can have 0 to 8 blocks (9 different resistances), then the bit 1 conductive path can support 91 different codes (including no line). The total number of different codes (resistance values) per conductive path can have any number of different values ​​from geometric variations.

[0044] The same resistance / capacitance design process can be repeated for the next conductive path and each subsequent conductive path. Note that for capacitance measurements, the lower plate can be used. If Figure 10 Each conductive path can support 100 different values, and with six conductive paths, 1e12 unique values ​​can be generated. Each conductive path / bit line can use a multiplexer type circuit to read the resistance or use other circuit systems to read the resistance (or capacitance).

[0045] In another embodiment, a unique electrical signature or unique resistance value from a unique electrical structure can be combined with an optical signature from a geometric shape. This combination can provide two-factor authentication if desired. It is understood that there are various geometric configurations of wiring structures, including placement of blocks. Now referring to Figure 11As well as the conductive path for position 1, 5 of the 8 possible blocks are formed. From top to bottom, these blocks are placed in the 1st, 3rd, 5th, 6th, and 8th positions. By placing these blocks in positions 1 to 5, the same resistance can be achieved. Although the resistance is the same, the visual placement is different. This visual difference can be used to form different optical / graphic patterns based on the wiring geometry. In the conductive path for position 3, four blocks are placed in the 5th to 8th sites, rather than the 1st to 4th sites, or even or odd sites, and so on. It can be understood that, compared to open space, each conductive path can accommodate different physical arrangements for a specific resistance value, depending on the number of blocks. It is also noted that blocks can be formed even when there is no wire between the contact and the target. For example, conductive paths positions 2 and 5 have no wire between the contact and the target, but still have blocks placed.

[0046] By selecting adjustable block placement, the physical arrangement of the blocks can serve as a graphic signature or pictogram. Line width can also be used as part of the optical key. In other words, the placement of the blocks along the conductive path can serve as the pixels of an image. This wiring structure can then be examined for unique electrical values, and can also be viewed microscopically to identify a unique graphic signature. Thus, this wiring structure can serve as both a unique electrical identifier and a graphic / optical identifier. The optical digital pattern provides a second level of security.

[0047] The unique wiring structure or resistive structure described herein can be built on any layer on a given chip. For example, the unique wiring structure can be placed on Metal 01, Metal 10, or the top layer. If the unique structure is built on a lower layer, the vias can extend several layers. The unique structure can surround an active parallel plate. The unique structure can be electrically connected to the corresponding chip, or it can be isolated from the chip and attached to a separate processor. The unique electrical identifier of each chip can be measured while the chips are packaged. For optical identifiers, some packaging may need to be removed to view the optical pattern. A multiplexer can be used to minimize the number of contacts / pins for the unique electrical pattern. An internal multiplexer device can help independently check each bit line. For example, there can be one input to the multiplexer and one output to the multiplexer. The multiplexer can then determine which clock line it is reading.

[0048] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that depart from these specific details, and that these details are for purposes of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. However, the embodiments can be practiced without these specific details. Components having substantially the same functional structure are represented by similar reference numerals, and therefore any redundant description can be omitted.

[0049] The various techniques have been described as multiple independent operations to facilitate understanding of the various embodiments. The order of description should not be interpreted as meaning that the operations are necessarily order-dependent. In fact, the operations do not need to be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0050] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer (such as a thin film) on or overlying a base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0051] Those skilled in the art will also appreciate that many changes may be made to the operation of the above-described technology while still achieving the same purpose. The scope of this disclosure is intended to encompass these changes. Therefore, the foregoing description of the embodiments is not intended to be restrictive. On the contrary, any limitations to the embodiments are presented in the appended claims.

Claims

1. A method for marking a substrate, the method comprising: forming a photoresist layer on a substrate; projecting a first pattern of actinic radiation onto the photoresist layer using a mask-based photolithography system, the first pattern defining a semiconductor device structure; projecting a second pattern of actinic radiation onto the photoresist layer using a direct-write projection system, the second pattern defining a unique wiring structure having a unique electrical signature and correlating to a unique marking of the substrate; developing the photoresist layer to generate a relief pattern; as well as forming said unique wiring structure having said unique electrical signature, wherein the unique wiring structure is a matrix of conductive paths, wherein at least one of the conductive paths has a block arranged thereon, the block being a portion of the conductive path having an increased thickness and a decreased resistivity, and The placement of the blocks on the conductive path is varied by coordinate position to define different graphical arrangements of the unique wiring structure.

2. The method according to claim 1, wherein The only wiring structure is the electrical wiring. 3 . The method of claim 1 , further comprising varying a resistance of the unique wiring structure between different dies by varying a shape of the unique wiring structure.

4. The method according to claim 1, wherein The shape of the unique wiring structure is changed by changing at least one of line length, line width, line path, number of line turns and line cross-sectional area.

5. The method according to claim 1, wherein Each conductive path has a different geometry, thereby providing one of a plurality of resistance values.

6. The method according to claim 1, wherein The unique electrical signature includes a unique resistance value or a unique capacitance value.

7. The method according to claim 1, wherein The unique wiring structure is located on the corresponding die at a location separate from the die circuitry.

8. The method according to claim 1, wherein The first pattern is projected after the second pattern is projected.

9. The method according to claim 1, wherein: The second pattern is projected after the first pattern is projected.

10. The method according to claim 1, wherein The unique wiring structure indicates a serial number or a production date, a chip specification or a technology generation.

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