A method and device for determining transmission delay of a standard unit

Abstract

The embodiment of the present invention discloses a method and device for determining the transmission delay of a standard cell, which relates to the field of semiconductor technology and can effectively improve the calculation accuracy of the standard cell after aging and enhance chip reliability. The method comprises: determining the capacitance of the input pin of the standard cell in the standard cell library under preset aging conditions according to a preset standard cell aging model to obtain the aging pin capacitance; when the standard cell in the standard cell library is used to construct a circuit, the transmission delay of the standard cell at this level is determined according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, wherein the external load capacitance comprises: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level. The present invention is applicable to chip design.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and device for determining a transmission delay of a standard unit. Background Art

[0002] For semiconductor chips, higher circuit speed and lower circuit power consumption are always the constant pursuit of the industry. One of the measurement parameters of CMOS (Complementary metal-oxide-semiconductor) circuit speed is the propagation delay of MOS tube, that is, the time that the output voltage change lags behind the input voltage change.

[0003] Taking MOS (metal-oxide-semiconductor) devices as an example, the speed of charging and discharging of MOS devices is an important factor affecting transmission delay, and the speed of charging and discharging is related to the load capacitance of the device. For example, the transmission delay of a CMOS inverter is caused by the PMOS and NMOS through the load capacitance C L The charging and discharging time is determined by the load capacitor C. L Taking the two cascaded CMOS inverters of the driver stage and the receiving stage as an example, for the driver stage CMOS, its load capacitance mainly comes from three sources: the first part is the intrinsic capacitance C of the driver stage CMOS device. GD (mainly the overlap capacitance between the gate and drain) and C DB (diffusion capacitance of the drain and substrate); the second part is the interconnect capacitance; the third part is the capacitance on the input pin of the external load device (i.e., the receiving-level CMOS), i.e., the NMOS gate capacitance C of the load device GN and PMOS gate capacitance C GP sum.

[0004] In the prior art, in order to ensure that the performance of the standard cell after aging can also meet the design requirements, a certain timing margin is reserved during chip design. However, this reserved margin is not accurate, for example, the margin is often large, resulting in unnecessary reduction in chip performance. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a method and device for determining the transmission delay of a standard cell, which can effectively improve the calculation accuracy of the transmission delay after aging of the standard cell and greatly enhance the chip reliability.

[0006] In a first aspect, an embodiment of the present invention provides a method for determining a transmission delay of a standard cell, comprising: determining the capacitance of an input pin of a standard cell in a standard cell library under preset aging conditions according to a preset standard cell aging model to obtain an aging pin capacitance; when a circuit is constructed using the standard cells in the standard cell library, determining the transmission delay of the standard cell at this level according to an input transition time of a signal input to the standard cell at this level and an external load capacitance of the standard cell at this level, wherein the external load capacitance comprises: the aging pin capacitance of a next-level standard cell connected to an output end of the standard cell at this level, and the capacitance of an interconnection line between the standard cell at this level and the standard cell at the next level.

[0007] Optionally, the aged pin capacitance includes an interface trap capacitance of a metal oxide semiconductor (MOS) device in the standard cell.

[0008] Optionally, before determining the transmission delay of the standard unit at this level according to the input transition time of the signal input to the standard unit at this level and the external load capacitance of the standard unit at this level, the method further includes: determining the capacitance of the interconnect after aging under the preset aging conditions according to a preset interconnect aging model to obtain an aged interconnect capacitance; determining the transmission delay of the standard unit at this level according to the input transition time of the signal input to the standard unit at this level and the external load capacitance of the standard unit at this level includes: determining the transmission delay of the standard unit at this level according to the input transition time of the signal input to the standard unit at this level, the aged interconnect capacitance and the aged pin capacitance.

[0009] Optionally, determining the transmission delay of the standard cell at this level based on the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level includes: searching for the transmission delay of the standard cell at this level in a preset transmission delay lookup table based on the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level; or performing simulation based on the input transition time of the signal input to the standard cell at this level, an equivalent circuit model of the standard cell at this level and the external load capacitance of the standard cell at this level to obtain the transmission delay of the standard cell at this level.

[0010] Optionally, the method further includes: determining an output transition time of a signal outputted from the standard cell of the current level according to an input transition time of a signal inputted into the standard cell of the current level and an external load capacitance of the standard cell of the current level; determining an input transition time of a signal inputted into the standard cell of the next level according to the output transition time of the signal outputted from the standard cell of the current level, so as to determine a transmission delay of the standard cell of the next level according to the input transition time of the signal inputted into the standard cell of the next level and an external load capacitance of the standard cell of the next level.

[0011] Optionally, determining the output transition time of the output signal of the standard unit at this level based on the input transition time of the signal input to the standard unit at this level and the external load capacitance of the standard unit at this level includes: searching for the output transition time of the signal output from the standard unit at this level in a preset output transition time lookup table based on the input transition time of the signal input to the standard unit at this level and the external load capacitance of the standard unit at this level; or performing simulation based on the input transition time of the signal input to the standard unit at this level, an equivalent circuit model of the standard unit at this level and the external load capacitance of the standard unit at this level to obtain the output transition time of the signal output from the standard unit at this level.

[0012] Optionally, the preset aging conditions include: PVT (Process-Voltage-Temperature), an excitation signal, and an aging time.

[0013] In a second aspect, an embodiment of the present invention further provides a transmission delay determination device for a standard cell, the device comprising: a capacitance determination module, for determining the capacitance of an input pin of a standard cell in a standard cell library under preset aging conditions according to a preset standard cell aging model, to obtain an aging pin capacitance; a delay determination module, for determining the transmission delay of the standard cell at this level according to an input transition time of a signal input to the standard cell at this level and an external load capacitance of the standard cell at this level when a circuit is constructed using the standard cells in the standard cell library, wherein the external load capacitance comprises: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level.

[0014] Optionally, the aged pin capacitance includes an interface trap capacitance of a metal oxide semiconductor (MOS) device in the standard cell.

[0015] Optionally, the capacitance determination module is further used to determine the capacitance of the interconnect line after aging under the preset aging conditions according to a preset interconnect line aging model before determining the transmission delay of the standard unit of this level according to the input transition time of the signal input to the standard unit of this level and the external load capacitance of the standard unit of this level, so as to obtain the aged interconnect line capacitance; the delay determination module is specifically used to determine the transmission delay of the standard unit of this level according to the input transition time of the signal input to the standard unit of this level, the aged interconnect line capacitance and the aged pin capacitance.

[0016] Optionally, the delay determination module includes: a first table lookup determination submodule, used to search the transmission delay of the standard unit at this level in a preset transmission delay lookup table according to the input transition time of the signal input to the standard unit at this level and the external load capacitance of the standard unit at this level; or a first simulation determination submodule, used to perform simulation according to the input transition time of the signal input to the standard unit at this level, the equivalent circuit model of the standard unit at this level and the external load capacitance of the standard unit at this level to obtain the transmission delay of the standard unit at this level.

[0017] Optionally, the device also includes: an output transition time determination module, used to determine the output transition time of the signal output of the standard cell of the current level according to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level; an input transition time determination module, used to determine the input transition time of the signal input to the standard cell of the next level according to the output transition time of the signal output to the standard cell of the current level, so as to determine the transmission delay of the standard cell of the next level according to the input transition time of the signal input to the standard cell of the next level and the external load capacitance of the standard cell of the next level.

[0018] Optionally, the output transition time determination module includes: a second table lookup determination submodule, used to search the output transition time of the signal output of the standard unit at this level in a preset output transition time lookup table according to the input transition time of the signal input to the standard unit at this level and the external load capacitance of the standard unit at this level; or a second simulation determination submodule, used to perform simulation according to the input transition time of the signal input to the standard unit at this level, the equivalent circuit model of the standard unit at this level and the external load capacitance of the standard unit at this level to obtain the output transition time of the signal output of the standard unit at this level.

[0019] Optionally, the preset aging conditions include: process voltage temperature PVT, excitation signal, and aging time.

[0020] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute any one of the transmission delay determination methods of the standard unit provided in the embodiments of the present invention.

[0021] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement a transmission delay determination method for any standard unit provided in an embodiment of the present invention.

[0022] The transmission delay determination method and device of the standard cell provided by the embodiment of the present invention, the electronic device, and the computer-readable storage medium can determine the capacitance of the input pin of the standard cell in the standard cell library under the preset aging condition according to the preset standard cell aging model, and obtain the aging pin capacitance. When the standard cell in the standard cell library is used to construct a circuit, the transmission delay of the standard cell at this level is determined according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level. In this way, since the aging pin capacitance is the input pin capacitance of the next level standard cell after aging under the preset aging condition, when determining the transmission delay of the standard cell at this level, the change of the input pin capacitance of the next level standard cell due to aging can also be reflected in the transmission delay calculation of the standard cell at this level as a part of the load capacitance, so that the delay calculation after the aging of the standard cell is closer to the actual situation, effectively improving the calculation accuracy of the transmission delay after the aging of the standard cell, and greatly enhancing the chip reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A flow chart of a method for determining a transmission delay of a standard cell provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of an equivalent capacitance of a MOS device in an embodiment of the present invention;

[0026] Figure 3 Another schematic diagram of equivalent capacitance of a MOS device in an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of updating the capacitance of each standard cell in the standard cell library after aging in an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of a circuit structure that needs to perform timing analysis in an embodiment of the present invention;

[0029] Figure 6 Based on Figure 5 A flow chart for timing analysis of standard cells;

[0030] Figure 7 A schematic diagram of a structure of a transmission delay determination device for a standard cell provided by an embodiment of the present invention;

[0031] Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] In a first aspect, an embodiment of the present invention provides a method for determining a transmission delay of a standard cell, which can effectively improve the calculation accuracy of the transmission delay of the standard cell after aging, and greatly enhance chip reliability.

[0035] like Figure 1 As shown, the method for determining the transmission delay of a standard cell provided by an embodiment of the present invention may include:

[0036] S11, determining the capacitance of the input pin of the standard cell in the standard cell library under a preset aging condition according to a preset standard cell aging model, and obtaining the aging pin capacitance;

[0037] The standard cell aging model may be a pre-established model for calculating the input pin capacitance of the aged standard cell. The standard cell may be included in a preset standard cell library.

[0038] The aged pin capacitance may be the input pin capacitance of the standard cell after aging under preset aging conditions. The preset aging conditions may include the PVT conditions of the standard cell, the excitation signal input to the standard cell, the aging time (e.g., 5 years), etc. After aging, the performance of the standard cell device may change, causing the capacitance on its input pin to also change.

[0039] S12, when a circuit is constructed using the standard cells in the standard cell library, the transmission delay of the standard cell at this level is determined according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the next level standard cell. Here, the input transition time can be the time required for the input signal to jump from a high level to a low level, or the time required for the input signal to jump from a low level to a high level.

[0040] When a circuit is constructed using the standard cells in the standard cell library, multiple identical or different standard cells may be used for electrical connection. Take any two connected standard cells as an example for illustration. Among them, the standard cell currently under study is the standard cell of this level, and the standard cell connected to the output end of the standard cell of this level is the standard cell of the next level. The standard cell of this level and the standard cell of the next level can be the same standard cell or different standard cells.

[0041] The external load capacitance of the standard cell at this level may include the capacitance of the input pin of the standard cell at the next level connected to the output end of the standard cell at this level under preset aging conditions (i.e., aging pin capacitance), and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level.

[0042] In this step, as the standard cell ages, the input pin capacitance of the next level standard cell also changes, and the input pin capacitance can be represented by the aged pin capacitance. Further, the transmission delay of the standard cell at this level can be calculated using the aged pin capacitance, the input transition time of the signal input to the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level.

[0043] The method for determining the transmission delay of a standard cell provided by an embodiment of the present invention can determine the capacitance of the input pin of a standard cell in a standard cell library under a preset aging condition according to a preset standard cell aging model to obtain the aging pin capacitance. When a circuit is constructed using the standard cells in the standard cell library, the transmission delay of the standard cell at this level is determined according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level. In this way, since the aging pin capacitance is the input pin capacitance of the next level standard cell after aging under the preset aging condition, when determining the transmission delay of the standard cell at this level, the change in the input pin capacitance of the next level standard cell due to aging can also be reflected as a part of the load capacitance in the transmission delay calculation of the standard cell at this level, thereby making the delay calculation of the standard cell after aging more in line with the actual situation, effectively improving the calculation accuracy of the transmission delay of the standard cell after aging, and greatly enhancing the reliability of the chip.

[0044] Aging can cause changes in standard cells, and these changes can be caused by a variety of factors. The inventor found in research that as the standard cell ages, more interface states may be generated at the interface between different materials of the standard cell device, thereby causing changes in the performance of the standard cell, including changes in the capacitance on the input pin of the standard cell. The inventor believes that the principle is as follows.

[0045] After the Si-H bond Si-H at the interface between silicon dioxide and silicon is broken under the action of the inversion layer holes and electric field, the silicon atom at the interface will have an unbonded electron, forming a dangling bond, forming a donor-like interface trap. These donor-like interface traps will change with the applied gate voltage (Fermi level), and the captured electrons will become electrically neutral or the uncaptured electrons will be positively charged, thereby generating an interface trap capacitance C. IT Therefore, as aging progresses, more interface traps will form at the interface between silicon dioxide and silicon, and the resulting interface trap capacitance will become larger and larger.

[0046] Since various standard cells in the standard cell library of CMOS circuit design, such as inverters and AND gates, are generally composed of MOS tubes, the aging pin capacitance in the standard cell can also include the interface trap capacitance of the MOS device in the standard cell. Analyzing the interface state of the MOS device will help understand the aging pin capacitance of the standard cell.

[0047] Specifically, when the gate of a MOS device is used as an input pin, the gate aging capacitance is the aging pin capacitance corresponding to the input pin of the MOS device. Depending on the gate voltage, the working state of the MOS device can include a depletion state and an inversion state. When the MOS device works in a depletion state, the width and charge density of the depletion layer change with the change of the gate voltage. In this case, Figure 2 As shown in the figure, substrate is the semiconductor substrate, oxide is the oxide layer, and metal is the metal layer. The gate aging capacitance of the MOS device may include: the insulation layer capacitance C of the MOS device OX , depletion layer capacitance C DEP , interface trap capacitance C IT , wherein the depletion layer capacitance is connected in parallel with the interface trap capacitance and then connected in series with the insulating layer capacitance. Exemplarily, in one embodiment of the present invention, the gate aging capacitance can be expressed by the following formula:

[0048]

[0049] When the MOS device works in the inversion state, the width and charge density of the depletion layer do not change, so the capacitance of the depletion layer disappears. In this case, Figure 3 As shown, the gate aging capacitor of the MOS tube may include: the insulation layer capacitor of the MOS tube and the interface trap capacitor, wherein the interface trap capacitor is connected in series with the insulation layer capacitor. Exemplarily, in one embodiment of the present invention, the gate aging capacitor may be represented by the following formula:

[0050]

[0051] In the gate aging capacitance of a MOS device in the inversion state, the insulation layer capacitance is related to the gate oxide layer process and does not change with device aging.

[0052] In order to know the change trend of gate capacitance with aging, the capacitance change value of the capacitor before and after aging is averaged in the whole range of gate voltage change, that is, the gate voltage is used as the horizontal coordinate and the capacitance change value is used as the vertical coordinate, and the ratio of the capacitance change value to the area enclosed by the horizontal axis and the voltage change value within the gate voltage change range (for example, 0V-0.8V) is calculated. The integral result is a positive value, indicating that within the whole range of gate voltage change, the gate capacitance of the MOS device increases with aging (because the interface trap capacitance increases with aging).

[0053] A standard cell generally includes multiple MOS devices. According to the above analysis of the capacitance of MOS devices, the capacitance of the input pin of the standard cell will also increase after aging. When the aged standard cell is used as the receiving level (i.e., the next level of the standard cell of this level), the capacitance of the input pin increases, which causes the external load capacitance of the driving level standard cell (i.e., the standard cell of this level) to increase. For example, at the 7nm process node, taking a standard cell buffer as an example, at the FFGNP (fastnMOS-fast pMOS global corner with N / P cancellation, the global process corner of fast noms and fast pmos with nmos-pmos cancellation effect), 1.0V, 0℃ PVT angle, the capacitance increases by about 12% after aging. At this time, the delay increases by about 5%. If the change of the capacitance of the input pin of the receiving level standard cell due to aging is not considered, some key paths will violate the timing after aging. Therefore, when calculating the delay of the device after aging, this part of the influencing factors should be taken into account, otherwise the delay obtained will be optimistic and inaccurate.

[0054] When performing delay calculation for each driver-level standard cell, the aging capacitance on the input pin of the next-level standard cell connected to the output end of the current-level standard cell can be taken into account based on the connection relationship between the standard cells in the circuit, thereby effectively improving the accuracy of the delay calculation.

[0055] Exemplarily, the process of calculating the input pin capacitance of the aged standard cell in the standard cell library can be as follows: Figure 4 As shown. Figure 4 As shown, the capacitance 31 of the input pin of the unaged standard cell is subjected to preset aging conditions 32 (such as aging time, PVT, excitation signal), and the input pin capacitance 33 after aging is calculated by applying the standard cell aging model, and then the input pin capacitance 34 after aging of the standard cell is updated. After repeating the above operation 35 for the entire standard cell library, a standard cell input pin capacitance value library 36 after aging can be obtained.

[0056] In an embodiment of the present invention, an aging pin capacitance is used to represent the capacitance on the input pin of a standard cell under a preset aging condition. The acquisition method thereof can apply the preset aging condition to the standard cell aging model to obtain the corresponding aging pin capacitance. Therefore, the standard cell aging model plays a key role in determining the aging pin capacitance. Optionally, a standard cell library may include multiple standard cells, each of which may have a different aging model.

[0057] After obtaining the aging pin capacitance of the standard cell, the transmission delay of the standard cell is calculated according to the connection relationship between the standard cells in the circuit and the aging pin capacitance of the standard cell. Specifically, in one embodiment of the present invention, step S12 determines the transmission delay of the standard cell of the current level according to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level, which may include:

[0058] According to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level, the transmission delay of the standard cell of the current level is searched in a preset transmission delay lookup table. For values ​​not recorded in the transmission delay lookup table, the corresponding transmission delay can be obtained by interpolation operation.

[0059] Optionally, in one embodiment of the present invention, the transmission delay of the standard cell can also be obtained by simulation using the equivalent circuit model of the standard cell. For example, the transmission delay of the standard cell of the current level can be obtained by simulation based on the input transition time of the signal input into the standard cell of the current level, the equivalent circuit model of the standard cell of the current level, and the external load capacitance of the standard cell of the current level.

[0060] In the above-mentioned embodiment, the method for determining the transmission delay of the standard cell of the present level is described in detail. When performing timing analysis on the critical path, any standard cell in the circuit can be used as the standard cell of the present level to further determine the transmission delay of the standard cell of the next level. The method for determining the transmission delay of the standard cell of the next level is similar to the method for determining the transmission delay of the standard cell of the present level, except that the input transition time of the signal input to the standard cell of the next level is associated with the output transition time (output transition) of the signal output from the standard cell of the present level. Here, the output transition time can be the time required for the output signal to jump from a high level to a low level, or the time required for the output signal to jump from a low level to a high level. Therefore, in order to determine the transmission delay of the standard cell of the next level, it is first necessary to determine the input transition time of the signal input to the standard cell of the next level based on the output transition time of the signal output from the standard cell of the present level.

[0061] In order to determine the transmission delay of the next-level standard cell, the transmission delay determination method of the standard cell provided by the embodiment of the present invention may further include:

[0062] Determining an output transition time of a signal outputted from the standard cell of the current level according to an input transition time of a signal inputted into the standard cell of the current level and an external load capacitance of the standard cell of the current level;

[0063] According to the output transition time of the signal output from the standard cell of the current level, the input transition time of the signal input to the standard cell of the next level is determined, so as to determine the transmission delay of the standard cell of the next level according to the input transition time of the signal input to the standard cell of the next level and the external load capacitance of the standard cell of the next level.

[0064] Specifically, similar to the step of determining the transmission delay of the standard cell of this level in the foregoing text, in this embodiment, according to the input transition time of the signal input to the standard cell of this level and the external load capacitance of the standard cell of this level, determining the output transition time of the signal output to the standard cell of this level can also be achieved by table lookup or simulation. That is, according to the input transition time of the signal input to the standard cell of this level and the external load capacitance of the standard cell of this level, the output transition time of the signal output to the standard cell of this level is searched in a preset output transition time lookup table; or, according to the input transition time of the signal input to the standard cell of this level, the equivalent circuit model of the standard cell of this level and the external load capacitance of the standard cell of this level, simulation is performed to obtain the output transition time of the standard cell of this level.

[0065] Since the output signal of the standard cell of this level reaches the standard cell of the next level after being transmitted through a section of metal interconnection line to form the input signal of the standard cell of the next level, the input transition time of the signal input to the standard cell of the next level can be determined according to the output transition time of the standard cell of this level and the circuit structure between the standard cell of the next level and the standard cell of this level, for example, by table lookup, simulation or other methods, so as to obtain the transmission delay of the standard cell of the next level by using the input transition time and the external load capacitance of the standard cell of the next level. In this way, by analogy, the transmission delay of each standard cell in the entire path can be obtained.

[0066] In the above embodiment, the effect of the aging of the next-level standard cell on the external load capacitance of the current-level standard cell is mainly described, but the embodiment of the present invention is not limited thereto. The interconnection between the current-level standard cell and the next-level standard cell also has aging, and the aging of the interconnection will also affect the external load capacitance of the current-level standard cell. In order to also reflect the effect of the aging of the interconnection on the external load capacitance of the current-level standard cell in the timing analysis of the circuit, in one embodiment of the present invention, before step S12 determines the transmission delay of the current-level standard cell according to the input transition time of the signal input to the current-level standard cell and the external load capacitance of the current-level standard cell, the transmission delay method of the standard cell provided by the embodiment of the present invention may also include: determining the capacitance of the interconnection after aging under the preset aging conditions according to a preset interconnection aging model, and obtaining the aged interconnection capacitance; then, based on this, the step S12 according to the input transition time of the signal input to the current-level standard cell and the external load capacitance of the current-level standard cell, the transmission delay of the current-level standard cell may specifically include: determining the transmission delay of the current-level standard cell according to the input transition time of the signal input to the current-level standard cell, the aged interconnection capacitance and the aged pin capacitance.

[0067] The transmission delay method of the standard unit provided by the embodiment of the present invention is described in detail below through specific embodiments.

[0068] Figure 5 The figure is a standard cell circuit diagram that needs to be analyzed for timing, wherein the standard cells cell0, cell1, cell2 and their interconnections have all aged. Figure 6 For Figure 5 Flowchart for timing analysis of standard cells in . Figure 5 and Figure 6 , the transmission delay method of the standard unit provided by the embodiment of the present invention may include:

[0069] S201, determining the capacitance of the input pin of the standard cell in the standard cell library under a preset aging condition according to the standard cell aging model, and obtaining the aging pin capacitance;

[0070] S202, find the aging pin capacitance C of cell1 from the standard cell library pin_age_1 ;

[0071] S203, according to the input transition time tr of cell0 fresh_input_0 , the aging pin capacitance C of cell1 pin_age_1 and interconnect capacitance C wire_1 , search for the transmission delay delay0 of cell0 in the transmission delay lookup table;

[0072] S204, according to the input transition time tr of cell0 fresh_input_0 , cell1 aging pin capacitance C pin_age_1 and interconnect capacitance C wire_1 , find the output transition time tr of cell0 in the output transition time lookup table aged_output_0 ;

[0073] S205, according to the output transition time tr of cell0 aged_output_0 Determine the input transition time tr of cell1 aged_input_1 ;

[0074] S206. Find the aging pin capacitance C of cell2 from the standard cell library pin_age_2 ;

[0075] S207, according to the input transition time tr of cell1 aged_input_1 , the aging pin capacitance C of cell2 pin_age_2 and interconnect capacitance C wire_2 , search for the transmission delay delay1 of cell1 in the transmission delay lookup table;

[0076] S208 , performing timing analysis on the circuit according to the transmission delay delay0 of cell0 , the transmission delay delay1 of cell1 , . . . .

[0077] In a second aspect, an embodiment of the present invention provides a transmission delay determination device for a standard unit, which can effectively improve the calculation accuracy of the delay time after device aging and greatly enhance chip reliability.

[0078] like Figure 7 As shown, an embodiment of the present invention provides a transmission delay determination device for a standard cell, and the device may include:

[0079] The capacitance determination module 41 is used to determine the capacitance of the input pin of the standard cell in the standard cell library under the preset aging condition according to the preset standard cell aging model, and obtain the aging pin capacitance;

[0080] The delay determination module 42 is used to determine the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level when constructing a circuit using the standard cells in the standard cell library, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the next level standard cell.

[0081] The transmission delay determination device of the standard cell provided by the embodiment of the present invention can determine the capacitance of the input pin of the standard cell in the standard cell library under the preset aging condition according to the preset standard cell aging model to obtain the aging pin capacitance. When the standard cell in the standard cell library is used to construct a circuit, the transmission delay of the standard cell at this level is determined according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level. In this way, since the aging pin capacitance is the input pin capacitance of the next level standard cell after aging under the preset aging condition, when determining the transmission delay of the standard cell at this level, the change of the input pin capacitance of the next level standard cell due to aging can also be reflected in the transmission delay calculation of the standard cell at this level as a part of the load capacitance, so that the delay calculation after the aging of the standard cell is closer to the actual situation, effectively improving the calculation accuracy of the transmission delay after the aging of the standard cell, and greatly enhancing the chip reliability.

[0082] Optionally, the aged pin capacitance includes an interface trap capacitance of a metal oxide semiconductor (MOS) device in the standard cell.

[0083] Optionally, the capacitance determination module 41 is further used to determine the capacitance of the interconnect line after aging under the preset aging conditions according to a preset interconnect line aging model before determining the transmission delay of the standard unit of the current level according to the input transition time of the signal input to the standard unit of the current level and the external load capacitance of the standard unit of the current level, so as to obtain the aged interconnect line capacitance;

[0084] The delay determination module 42 is specifically configured to determine the transmission delay of the standard cell of the current level according to the input transition time of the signal input to the standard cell of the current level, the aged interconnect capacitance and the aged pin capacitance.

[0085] Optionally, the delay determination module 42 may include:

[0086] A first table lookup determination submodule, configured to look up the transmission delay of the standard cell of the current level in a preset transmission delay lookup table according to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level;

[0087] or

[0088] The first simulation determination submodule is used to perform simulation according to the input transition time of the signal input to the standard cell of this level, the equivalent circuit model of the standard cell of this level and the external load capacitance of the standard cell of this level to obtain the transmission delay of the standard cell of this level.

[0089] Optionally, the device may further include:

[0090] An output transition time determination module 43, used to determine an output transition time of a signal outputted from the standard cell of the current level according to an input transition time of a signal inputted into the standard cell of the current level and an external load capacitance of the standard cell of the current level;

[0091] The input transition time determination module 44 is used to determine the input transition time of the signal input to the next-level standard cell according to the output transition time of the signal output from the current-level standard cell, so as to determine the transmission delay of the next-level standard cell according to the input transition time of the signal input to the next-level standard cell and the external load capacitance of the next-level standard cell.

[0092] Optionally, the output transition time determination module 43 may include:

[0093] A second table lookup determination submodule is used to look up the output transition time of the signal output of the standard cell of the current level in a preset output transition time lookup table according to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level;

[0094] or

[0095] The second simulation determination submodule is used to perform simulation based on the input transition time of the signal input to the standard unit of this level, the equivalent circuit model of the standard unit of this level and the external load capacitance of the standard unit of this level to obtain the output transition time of the signal output to the standard unit of this level.

[0096] Optionally, the preset aging conditions include: process voltage temperature PVT, excitation signal, and aging time.

[0097] Thirdly, Figure 8 As shown, an embodiment of the present invention further provides an electronic device, comprising: a housing 100, a processor 110, a memory 120, a circuit board 130 and a power supply circuit 140, wherein the circuit board 130 is arranged inside the space enclosed by the housing 100, and the processor 110 and the memory 120 are arranged on the circuit board 130; the power supply circuit 140 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 120 is used to store executable program codes; the processor 110 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 120, so as to execute any one of the transmission delay determination methods of the standard unit provided in the aforementioned embodiments.

[0098] The specific execution process of the above steps by the processor 110 and the steps further performed by the processor 110 by running the executable program code can be found in the description of the above embodiments, which will not be repeated here.

[0099] In the fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the transmission delay determination method of any standard unit provided by the embodiment of the present invention, thereby also being able to achieve corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0100] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0101] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0102] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0103] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0104] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0105] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for determining the transmission delay of a standard cell, It is characterized in that The method comprises: Determine the capacitance of the input pin of the standard cell in the standard cell library under the preset aging condition according to the preset standard cell aging model, and obtain the aging pin capacitance; wherein the preset aging condition includes: process voltage temperature PVT, excitation signal, aging time; the aging pin capacitance includes the interface trap capacitance of the metal oxide semiconductor MOS device in the standard cell; When a circuit is constructed using the standard cells in the standard cell library, the transmission delay of the standard cell at this level is determined according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level.

2. The method according to claim 1, It is characterized in that Before determining the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level, the method further comprises: determining the capacitance of the interconnect line after aging under the preset aging conditions according to a preset interconnect line aging model to obtain an aged interconnect line capacitance; Determining the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level includes: determining the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level, the aged interconnect capacitance and the aged pin capacitance.

3. The method according to claim 1, It is characterized in that Determining the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level includes: According to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level, searching the transmission delay of the standard cell of the current level in a preset transmission delay lookup table; or According to the input transition time of the signal input to the standard cell of the current level, the equivalent circuit model of the standard cell of the current level and the external load capacitance of the standard cell of the current level, simulation is performed to obtain the transmission delay of the standard cell of the current level.

4. The method according to any one of claims 1 to 3, It is characterized in that Also includes: Determining an output transition time of a signal outputted from the standard cell of the current level according to an input transition time of a signal inputted into the standard cell of the current level and an external load capacitance of the standard cell of the current level; According to the output transition time of the signal output from the standard cell of the current level, the input transition time of the signal input to the standard cell of the next level is determined, so as to determine the transmission delay of the standard cell of the next level according to the input transition time of the signal input to the standard cell of the next level and the external load capacitance of the standard cell of the next level.

5. The method according to claim 4, It is characterized in that Determining the output transition time of the output signal of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level comprises: According to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level, searching the output transition time of the signal output from the standard cell of the current level in a preset output transition time lookup table; or According to the input transition time of the signal input to the standard cell of this level, the equivalent circuit model of the standard cell of this level and the external load capacitance of the standard cell of this level, simulation is performed to obtain the output transition time of the signal output to the standard cell of this level.

6. A transmission delay determination device for a standard cell, It is characterized in that The device comprises: A capacitance determination module is used to determine the capacitance of the input pin of the standard cell in the standard cell library under preset aging conditions according to a preset standard cell aging model, and obtain an aged pin capacitance; the preset aging conditions include: process voltage temperature PVT, excitation signal, and aging time; the aged pin capacitance includes the interface trap capacitance of the metal oxide semiconductor MOS device in the standard cell; A delay determination module is used to determine the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level and the external load capacitance of the standard cell at this level when a circuit is constructed using the standard cells in the standard cell library, wherein the external load capacitance includes: the aging pin capacitance of the next level standard cell connected to the output end of the standard cell at this level, and the capacitance of the interconnection line between the standard cell at this level and the standard cell at the next level.

7. The device according to claim 6, It is characterized in that The capacitance determination module is further used to determine the capacitance of the interconnect line after aging under the preset aging conditions according to a preset interconnect line aging model before determining the transmission delay of the standard unit of the current level according to the input transition time of the signal input to the standard unit of the current level and the external load capacitance of the standard unit of the current level, so as to obtain the aged interconnect line capacitance; The delay determination module is specifically used to determine the transmission delay of the standard cell at this level according to the input transition time of the signal input to the standard cell at this level, the aged interconnection line capacitance and the aged pin capacitance.

8. The device according to claim 6, It is characterized in that The delay determination module comprises: A first table lookup determination submodule, configured to look up the transmission delay of the standard cell of the current level in a preset transmission delay lookup table according to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level; or The first simulation determination submodule is used to perform simulation according to the input transition time of the signal input to the standard cell of this level, the equivalent circuit model of the standard cell of this level and the external load capacitance of the standard cell of this level to obtain the transmission delay of the standard cell of this level.

9. The device according to any one of claims 6 to 8, It is characterized in that Also includes: An output transition time determination module, used to determine an output transition time of a signal outputted from the standard cell of the current level according to an input transition time of a signal inputted into the standard cell of the current level and an external load capacitance of the standard cell of the current level; An input transition time determination module is used to determine the input transition time of the signal input to the next-level standard cell according to the output transition time of the signal output from the current-level standard cell, so as to determine the transmission delay of the next-level standard cell according to the input transition time of the signal input to the next-level standard cell and the external load capacitance of the next-level standard cell.

10. The device according to claim 9, It is characterized in that The output transition time determination module comprises: A second table lookup determination submodule is used to look up the output transition time of the signal output of the standard cell of the current level in a preset output transition time lookup table according to the input transition time of the signal input to the standard cell of the current level and the external load capacitance of the standard cell of the current level; or The second simulation determination submodule is used to perform simulation based on the input transition time of the signal input to the standard unit of this level, the equivalent circuit model of the standard unit of this level and the external load capacitance of the standard unit of this level to obtain the output transition time of the signal output to the standard unit of this level.

11. An electronic device, It is characterized in that include: A housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the transmission delay determination method of the standard unit described in any one of claims 1 to 5.

12. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the transmission delay determination method of the standard cell according to any one of claims 1 to 5.

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