Phase change memory device having a selector including defect reduction material and method of forming the same

Abstract

In some aspects, a memory device includes multiple bit lines, multiple word lines, and multiple memory cells. Each of the multiple memory cells is disposed at the intersection of a corresponding bit line and a corresponding word line among the multiple bit lines. Each of the multiple memory cells includes stacked phase-change memory (PCM) elements and a selector having defect-reducing material.

Description

Technical Field

[0001] The present disclosure relates to a phase change memory (PCM) device and a method of manufacturing the same. Background Art

[0002] Planar memory cells have been shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches a lower limit, planar processing and manufacturing techniques become more challenging and more expensive. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals transmitted to and from the memory array. For example, PCM can exploit the resistivity difference between amorphous and crystalline phases in a phase change material based on electrothermal heating and quenching of the phase change material. PCM array cells can be stacked vertically in three dimensions to form a 3D PCM. Summary of the invention

[0004] In one aspect, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of the plurality of memory cells is disposed at an intersection of a corresponding one of the plurality of bit lines and a corresponding one of the plurality of word lines. Each of the plurality of memory cells includes a stacked phase change memory (PCM) element and a selector having a defect reduction material.

[0005] In another aspect of the present disclosure, a phase change memory (PCM) cell includes a PCM element and a selector having a defect reduction material.

[0006] In yet another aspect of the present disclosure, a method for forming a memory device includes: depositing a selector using a deposition process and introducing a defect reduction material into the selector; and depositing a phase change memory (PCM) element on the selector. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and together with the description further serve to explain the principles of the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0008] Figure 1 A perspective view of an exemplary 3D cross-point (XPoint) memory device is shown in accordance with some aspects of the present disclosure.

[0009] Figure 2A side view of a cross section of a 3D XPoint memory device with an OTS selector is shown.

[0010] Figure 3 A side view of a cross section of an exemplary 3D PCM device with an OTS selector including defect reduction material according to aspects of the present disclosure is shown.

[0011] Figure 4A A schematic diagram showing defect distribution in an exemplary OTS selector according to aspects of the present disclosure is shown.

[0012] Figure 4B Schematic diagram showing defect distribution in an exemplary OTS selector with defect reduction material according to aspects of the present disclosure.

[0013] Figure 4C Measured IV characteristics of a 3D XPoint memory device with an exemplary OTS selector according to aspects of the present disclosure are shown.

[0014] Figure 4D Measured IV characteristics of another 3D XPoint memory device having an exemplary OTS selector including defect reduction material according to aspects of the present disclosure are shown.

[0015] Figure 4E Measured IV characteristics of yet another 3D XPoint memory device having an exemplary OTS selector including defect reduction material according to aspects of the present disclosure are shown.

[0016] Figure 4F A diagram showing a device speed test of a 3D XPoint memory device with an exemplary OTS selector including defect reduction material according to aspects of the present disclosure is shown.

[0017] Figure 5 A schematic diagram illustrating the operation of an exemplary array of PCM cells with OTS selectors according to aspects of the present disclosure.

[0018] Figures 6A-6C An exemplary fabrication process for forming a 3D PCM device having an OTS selector including defect reduction material according to some aspects of the present disclosure is shown.

[0019] Figure 7 A flow chart illustrating an exemplary method for forming a 3D PCM device having an OTS selector including defect reduction material according to aspects of the present disclosure.

[0020] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] Although specific configurations and arrangements are discussed, it should be understood that the discussion is only for the purpose of illustration. Those skilled in the art will appreciate that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be used in a variety of other applications.

[0022] It should be noted that references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. In addition, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly or not explicitly described.

[0023] Generally, terms should be understood based at least in part on the context of use. For example, depending at least in part on the context, the words "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words "one," "an," or "the" may also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, also depending at least in part on the context, the word "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may instead allow for the presence of other factors that may not be explicitly stated.

[0024] It should be easily understood that the terms “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only being directly on something, but also includes being on something with intervening features or layers therebetween, and such that “on” or “over” includes not only the meaning of being on or over something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0025] In addition, spatially relative terms, such as "below," "below," "beneath," "above," "above," etc., may be used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0026] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0027] As used herein, the term "layer" refers to a portion of a material including an area having a certain thickness. A layer may extend over the entire underlying structure or overlying structure, or may have a range smaller than the range of the underlying structure or overlying structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any paired horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers located thereon, above it and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (interconnect lines and / or via contacts are formed therein) and one or more dielectric layers.

[0028] As used herein, the term "3D memory device" refers to a semiconductor device having memory cells that can be arranged vertically on a horizontally oriented substrate, thereby increasing the number of memory cells in a vertical direction relative to the substrate. The term "vertical / vertically" as used herein refers to being nominally perpendicular to a lateral surface of a substrate.

[0029] PCM can exploit the resistivity difference between amorphous and crystalline phases in a phase change material (e.g., a chalcogenide alloy) based on electrothermal heating and quenching of the phase change material. The phase change material in a PCM cell can be located between two electrodes, and an electric current can be applied to cause the material (or at least a portion thereof that blocks the current path) to repeatedly switch between the two phases to store data. PCM cells can be stacked vertically in three dimensions to form a 3D PCM.

[0030] 3D PCM includes 3D cross-point (XPoint) memory, which stores data based on the resistance change of bulk material properties (e.g., in a high resistance state or a low resistance state), which is combined with a cross-point data access array that can be stacked to make the data bit-addressable. For example, Figure 1A perspective view of an exemplary 3D XPoint memory device 100 according to some embodiments of the present disclosure is shown. According to some embodiments, the 3D XPoint memory device 100 has a transistor-free crosspoint architecture that places memory cells at the intersection of mutually perpendicular conductors. The 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above the lower bit lines 102. The 3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane located between the lower bit lines 102 and the upper bit lines 104 in a vertical direction. Figure 1 As shown, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in a plan view (parallel to the wafer plane), and each word line 106 extends laterally along the word line direction in a plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

[0031] It should be pointed out that in Figure 1 The x-axis and y-axis are included to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction and the y-direction is the bit line direction. It should be noted that Figure 1 100. A z-axis is also included to further illustrate the spatial relationships of components in the 3D XPoint memory device 100. A substrate (not shown) of the 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the xy plane: a top surface at the front side of the wafer and a bottom surface at the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether a component (e.g., a layer or device) of a semiconductor device (e.g., a 3D XPoint memory device 100) is "on," "over," or "below" another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the z-direction when the substrate is in the lowest plane of the semiconductor device in the z-direction (a vertical direction perpendicular to the xy plane). The same concepts will be used throughout this disclosure to describe spatial relationships.

[0032] like Figure 1As shown, the 3D XPoint memory device 100 includes a plurality of memory cells 108, each of which is disposed at the intersection of a lower bit line 102 or an upper bit line 104 and a corresponding word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each memory cell 108 stores a single bit of data, and each memory cell 108 can be written or read by changing a voltage applied to a corresponding selector 112 (which replaces the need for a transistor). Each memory cell 108 can be individually accessed by applying a current through a top conductor and a bottom conductor (e.g., a corresponding word line 106 and a lower bit line 102 or an upper bit line 104) in contact with each memory cell 108. The memory cells 108 in the 3D XPoint memory device 100 are arranged in a memory array.

[0033] In the existing 3D XPoint memory, the material of the selector 112 is an omni-directional threshold switch (OTS) material, such as zinc telluride (ZnTe), which exhibits field-dependent volatile resistance switching behavior (known as the "OTS" phenomenon) when an external bias voltage (Va) higher than a threshold voltage (Vth) is applied. For example, Figure 2 A side view of a 3D XPoint memory device 200 with an OTS selector is shown. The 3D XPoint memory device 200 includes a plurality of parallel bit lines 204 located above a substrate 202 and a plurality of parallel word lines 216 located above the bit lines 204. The 3D XPoint memory device 200 also includes a plurality of memory cells 201, each memory cell 201 being disposed at an intersection of a corresponding pair of bit lines 204 and word lines 216. Adjacent memory cells 201 are separated by an insulating structure 203. Each memory cell 201 includes an OTS selector 208 and a PCM element 212 located above the OTS selector 208. Each memory cell 201 further includes three electrodes 206, 210, and 214 located in a vertical direction between the corresponding bit line 204, the OTS selector 208, the PCM element 212, and the corresponding word line 216, respectively.

[0034] The OTS selector 208 includes an OTS material, e.g., ZnTe. At a lower voltage (|Va| < Vth), the high resistance of the OTS selector 208 in its cutoff state keeps the cutoff state current (Ioff) at a low level. At a higher voltage (|Va| > Vth), the OTS selector 208 undergoes the OTS phenomenon and switches to a conducting state with low resistance; thus, the current (Ion) through the OTS selector 208 in the conducting state increases. As long as the high voltage is supplied, this volatile conducting state is maintained. However, the leakage current accumulated through all the unselected memory cells 201 limits the scalability of the array size. That is, the larger the array size, the greater the total leakage current. In addition, when the accumulated leakage current is too large and accidentally fails to set or reset the unselected devices, the leakage current problem will also degrade the read operation margin. The leakage current may also introduce a voltage related to parasitic resistance, which will limit the total memory cell array size. To overcome the challenges mentioned above, a unique selector composition and its manufacturing method are proposed to improve the undesired device leakage.

[0035] Figure 3 A side view of a cross-section of an exemplary 3D PCM device 300 having a selector including a defect reduction material in accordance with some embodiments of the present disclosure is shown. The 3D PCM device 300 (e.g., a 3D XPoint memory device) may include a plurality of bit lines 304 located above a substrate 302, which may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The bit lines 304 may be parallel to each other and located in the same plane. In some embodiments, each of the plurality of parallel bit lines 304 extends laterally along Figure 3 the y-direction (e.g., the bit line direction) in. The 3D PCM device 300 may further include a plurality of word lines 316 located above the bit lines 304. The word lines 316 may be parallel to each other and located in the same plane. In some embodiments, each of the plurality of parallel word lines 316 extends laterally along Figure 3 the x-direction (e.g., the word line direction) in. The word lines 316 and the bit lines 304 of the 3D PCM device 300 (e.g., a 3D Xpoint memory device) may be vertically arranged conductors in a cross-point architecture. The bit lines 304 and the word lines 316 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the bit lines 304 and the word lines 316 includes a metal such as tungsten.

[0036] In some embodiments, the 3D PCM device 300 includes a plurality of memory cells 301, each of which is disposed at an intersection of a corresponding one of the bit lines 304 and a corresponding one of the word lines 316. Each memory cell 301 can be individually accessed by applying a current through a corresponding word line 316 and a corresponding bit line 304 in contact with the memory cell 301. Figure 3 As shown in FIG. 3 , the 3DPCM device 300 may further include an insulating structure 303 laterally disposed between adjacent memory cells 301. In some embodiments, each memory cell 301 has a vertical columnar shape (eg, Figure 1 ), and the insulating structure 303 can extend laterally in both the x-direction and the y-direction to separate each pillar-shaped memory cell 301. In some embodiments, the insulating structure 303 includes one or more dielectric layers, such as an encapsulation layer (not shown) formed along the sidewalls of the memory cells 301 and the bit lines 304, and a cap layer (not shown) filling the remaining space between the memory cells 301. The dielectric layer of the insulating structure 303 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof. In some embodiments, the encapsulation layer and the cap layer include silicon nitride and silicon oxide, respectively.

[0037] Each memory cell 301 may include a stacked PCM element 312, a selector 308, a first electrode 306 located between a bit line 304 and the selector 308, a second electrode 310 located between the selector 308 and the PCM element 312, and a third electrode 314 located between the PCM element 312 and a word line 316. The PCM element 312 may utilize the resistivity difference between the amorphous phase and the crystalline phase in the phase change material based on electrothermal heating and quenching of the phase change material. The phase change material of the PCM element 312 (or at least the portion thereof that blocks the current path) may be repeatedly switched between the two phases by applying a current to store data. A single bit of data may be stored in each memory cell 301, and a single bit of data may be written or read by changing a voltage applied to a corresponding selector 308, which eliminates the need for transistors and replaces conventional OTS selectors (e.g., Figure 2 That is, the electrodes 310 and 314 may be arranged on opposite sides (eg, above and below) of the PCM element 312 to separate the PCM element 312 from direct contact with other components. It should be understood that the structure of the memory cell 301 is not limited to Figure 3In one example, the relative positions of the selector 308 and the PCM element 312 in other examples may be exchanged. In another example, the number and relative positions of the electrodes 310 and 314 in the memory cell 301 in other examples may also be changed.

[0038] According to some embodiments, the material of PCM element 312 includes a chalcogenide-based alloy (chalcogenide glass), for example, a germanium antimony telluride (GeSbTe or GST) alloy, or includes any other suitable phase change material. Electrodes 306, 310, and 314 may include a conductive material, including but not limited to W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of electrodes 306, 310, and 314 includes carbon, for example, amorphous carbon (aC).

[0039] like Figure 3 As shown in FIG. , the selector 308 includes Figure 4B In some embodiments, the thickness of the selector 308 is between 5 nm and 50 nm, for example, between 5 nm and 50 nm (e.g., 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, any range bounded by any of these values, or any range bounded by any two of these values). In some embodiments, the thickness of the selector 308 is 30 nm.

[0040] According to various embodiments of the present disclosure, a 3D PCM device (e.g., a 3D XPoint memory device) having an OTS selector including a defect reduction material and a method for manufacturing the same are provided. Figure 4A 208) compared to materials with reduced defects (e.g., Figure 4B 309) of the OTS selector (for example, Figure 4B 308 in ) can reduce leakage current and parasitic resistance-related voltage without significantly affecting other key material or electrical parameters, thereby improving read operation margin and enabling larger cell arrays. For example, an OTS selector (e.g., Figure 4A208 in the OTS selector) can have multiple highly distorted vacancy-type defects formed at grain boundaries, surfaces, and other mismatch regions caused by material deposition. These defects can have free carriers, such as electrons or holes, formed therein to provide additional leakage paths when a voltage is applied. The defect reduction materials disclosed herein can be used to repair these dangling bond defects, which will result in significant improvements in electronic properties, such as reduced leakage current without substantially changing the characteristics of the OTS selector. For example, an OTS selector (e.g., Figure 4B 308) may include an amorphous chalcogenide threshold switch material including Ge x Se y As z Si t Moreover, defect reduction materials (e.g. Figure 4B 309 in the graphene may include nitrogen (N), carbon (C), oxygen (O), boron (B), phosphorus (P), sulfur (S), or a combination thereof. For example, nitrogen ions may combine with dangling bond defects and fill those vacancies to form a more stable configuration in which the nitrogen ions are strongly bonded to Si atoms or Ge atoms. x Se y As z Si t In some embodiments, selector 308 includes Ge x Se y As z Si t N s, wherein x is 0.03 to 0.2 (e.g., 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20), y is 0.3 to 0.6 (e.g., 0.3, 0.4, 0.5, or 0.6), z is 0.15 to 0.45 (e.g., 0.15, 0.20, 0.25, 0.30, 0.35, 0.40, or 0.45), and t is 0.02 to 0.20 (e.g., 0.02, 0.03, 0.04 , 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20), and s is 0.005 to 0.1 (e.g., 0.005, 0.010, 0.015, 0.020, 0.025, 0.030, 0.035, 0.040, 0.045, 0.050, 0.055, 0.060, 0.065, 0.070, 0.075, 0.080, 0.085, 0.090, 0.095, or 0.100). In some embodiments, selector 308 includes Ge x Se y As z Si t C s, wherein x is 0.03 to 0.2 (e.g., 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20), y is 0.3 to 0.6 (e.g., 0.3, 0.4, 0.5, or 0.6), z is 0.15 to 0.45 (e.g., 0.15, 0.20, 0.25, 0.30, 0.35, 0.40, or 0.45), and t is 0.02 to 0.2 (e.g., 0.02, 0.03, 0.04, 0.05, 0.06 0.040, 0.045, 0.050, 0.055, 0.060, 0.065, 0.070, 0.075, 0.080, 0.085, 0.090, 0.095, or 0.100). Note that x, y, z, t, and s are the mole fractions of the corresponding elements, and the sum of all mole fractions is always equal to 1.

[0041] Figure 4C-4E The invention shows a method of forming a substrate having no or a defect reduction material (e.g., Figure 4B 309) of the OTS selector of the 3D XPoint memory device. For example, Figure 4C A reference 3D Xpoint memory device with an exemplary OTS selector that does not include defect reduction material is shown, and Figure 4D Another 3D XPoint memory device is shown with an exemplary OTS selector including defect reduction material, obtained, for example, by introducing a 4 standard cubic centimeter per minute (sccm) nitrogen (N2) gas flow during sputter deposition of the 30nm threshold switch material of the selector. Also, Figure 4E Still another 3D XPoint memory device is shown with an exemplary OTS selector including defect reduction material, obtained, for example, by introducing 8 sccm of N2 gas flow during sputter deposition of the 30 nm threshold switch material of the selector. Figure 4C-4E As shown, after introducing defect reduction materials into the selector, the threshold voltage (Vth) is reduced, and the leakage current is approximately reduced from 10 -6 to 10 -7 A between down to 10 -7 to 10-8 A (for example, 1×10 -8 , 2×10 -8 , 3×10 -8 , 4×10 -8 , 5×10 -8 , 6×10 -8 ,7×10 -8 , 8×10 -8 ,9×10 -8 or any range with a lower limit defined by any of these values, or within any range defined by any two of these values). The hold voltage (Vhold) also increases, and the set current remains at a similar level.

[0042] While it is important to reduce leakage current of the selector, it is also important to maintain the same or similar characteristics, especially when the memory device is used to replace dynamic random access memory (DRAM). That is, the switching speed must not be reduced due to the implementation of defect reduction materials.

[0043] Figure 4F Graphs of device speed testing of a 3D XPoint memory device having an exemplary OTS selector including defect reduction material according to some embodiments of the present disclosure are shown. The top three graphs are when the selector of the device is subjected to 4 sccm of N2 gas flow during sputter deposition of the 30 nm threshold switch material of the selector (e.g., Figure 4D The following three figures are graphs of device speed tests when an 8 sccm N2 gas flow is introduced into the selector of the device during the sputtering deposition of the 30 nm threshold switch material of the selector (as shown in FIG. Figure 4E A diagram of the device speed test mentioned in . Figure 4F It is shown in Figure 1 that after applying voltage to the device, the switching speed can be maintained. For example, the set (SET) speed of the memory device can be maintained at 96 to 110 ns. And the reset (RESET) speed of the memory device can be maintained at 12 to 14 ns, which means that it is highly desirable that the switching speed remains the same or similar after introducing defect reduction materials into the selector.

[0044] Figure 5 Schematic diagram showing the operation of an exemplary array of PCM cells having a selector including defect reduction material according to some embodiments of the present disclosure. Figure 5 As shown, PCM unit 502 (eg, corresponding to Figure 3 The array of memory cells 301 in FIG. 3 may be formed as word lines 504 (eg, corresponding to Figure 3 ) and bit lines 506 (eg, corresponding to Figure 3Each PCM cell 502 may include a selector (eg, corresponding to a bit line 304 in FIG. 1 ). Figure 3 The PCM element 508 (eg, corresponding to the selector 308 in FIG. 1 ) is connected in series with the PCM element 508 (eg, corresponding to Figure 3 312 in the PCM element 502). To operate the array of PCM cells 502, a word line voltage (Vw) having a value of either 0 or Vhh can be applied to each word line 504, and a bit line voltage (Vb) having a value of either 0 or Vll can be applied to each bit line 506. Therefore, the voltage (Va) applied to each PCM cell 502 (and its selector 510) can be Vhh, -Vll, 0, or Vhh-Vll. In some embodiments, Vhh and Vll can be set based on the inherent threshold voltage (Vth) of the selector 510, so that |Vhh-Vll|≥Vth>|Vhhl|, |Vll|, or 0. According to some embodiments, as Figure 5 As shown in FIG. 1 , only at one intersection of a word line 504 and a bit line 506 having a non-zero voltage is the voltage (Va) equal to or greater than the threshold voltage (Vth). Thus, only at the intersection of the pair of word lines 504 and bit lines 506 having a non-zero voltage is the PCM cell 502 ( Figure 5 The PCM cells 502 in the dashed circle in FIG. 5 can be selected (ie, are applied with a voltage Vhh-Vll and are in a conducting state). According to some embodiments, the other PCM cells 502 are not selected and are in a cut-off state.

[0045] Figures 6A-6C An exemplary fabrication process for forming a 3D PCM device having a selector including a defect reduction material according to some embodiments of the present disclosure is shown. Figure 7 A flow chart is shown of an exemplary method 700 for forming a 3DPCM device having a selector including a defect reduction material according to some embodiments of the present disclosure. Fig. 6A –6C and Figure 7 Examples of 3D PCM devices shown in include Figure 3 The 3D PCM device 300 shown in FIG. Fig. 6A –6C and Figure 7 Examples of selectors with defect reduction materials shown in include Figure 4B The selector 308 with defect reduction material 309 is shown in FIG. Fig. 6A –6C and Figure 7 It should be understood that the operations shown in method 700 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously or in different order. Figure 7 Executed in the order shown.

[0046] refer to Figure 7 , method 700 begins at operation 702, in which a bit line and a first electrode are sequentially deposited over a substrate. That is, the bit line is deposited on the substrate, and then the first electrode is deposited on the bit line. In some embodiments, the deposition may include using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

[0047] refer to Fig. 6A , forming a bit line 604 on the substrate 602, and forming a first electrode 606 on the bit line 604. In some embodiments, the bit line 604 may include W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the first electrode 606 may include W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the first electrode 606 includes carbon, for example, amorphous carbon (aC).

[0048] Method 700 proceeds to operation 704, such as Figure 7 As shown in, in this operation, a selector is deposited on a first electrode using sputtering deposition, and a defect reduction material is introduced into the selector by using a sputtering target having a defect reduction material or a reactive gas. In one example, a defect reduction material (e.g., N) is introduced into the selector by using a sputtering target having a defect reduction material (e.g., silicon nitride (SiN)). Specifically, during the sputtering deposition process, a first electrode (e.g., aC) is placed in a vacuum chamber containing one or more inert gases (e.g., Ar gas), and a negative charge is applied to the sputtering target (e.g., SiN) together with other co-sputtering targets composed of a threshold switching material (such as Ge, Se, As, or Si), which will be deposited onto the first electrode to produce a layer composed of (e.g.) Ge. x Se y As z Si t N sThe desired film is formed. Free electrons flow out of the negatively charged sputtering target in the plasma environment, thereby colliding with the outer electron shells of Ar gas atoms, and then driving these electrons away due to their similar charges. The inert gas atoms become positively charged ions, which are attracted to the negatively charged target material at very high speeds, thereby sputtering atomic-sized particles from the sputtering target due to the momentum of the collision. These particles across the vacuum deposition chamber are deposited on the surface of the first electrode as a thin film material. In another example, a defect reduction material (e.g., nitrogen (N)) is introduced into the selector by using a reactive gas (e.g., N2 gas flow) with a defect reduction material. Specifically, during the sputtering deposition process, the first electrode (e.g., aC) is placed in a vacuum chamber containing one or more inert gases (e.g., Ar gas) of the particles to be sputtered and one or more reactive gases (e.g., N2 gas) to be deposited, and a negative charge is applied to a sputtering target composed of a threshold switch material (e.g., Ge, Se, As or Si) to generate a film composed of (e.g.) Ge x Se y As z Si t N sThe expected film formed. Free electrons flow out from the negatively charged sputtering target in the plasma environment, thereby colliding with the outer electron shell of the Ar gas atoms, and then driving these electrons away due to their similar charges. The inert gas atoms become positively charged ions, which are attracted to the negatively charged target material at a very high speed, thereby sputtering atomic-sized particles from the sputtering target due to the collision momentum. These particles across the vacuum deposition chamber are accompanied by atoms or ions of the reaction gas and are deposited on the surface of the first electrode as a film of material. As mentioned above, atoms or ions N can be introduced and combined with dangling bonds of other materials of the selector, thereby reducing dangling bond defects. In another example, defect reduction materials (e.g., C) are introduced into the selector by using a sputtering target (e.g., C target or silicon carbide (SiC) target) with defect reduction materials. In some embodiments, the defect reduction material may include N, C, O, B, P, S or a combination thereof. In some embodiments, the sputtering target includes SiN, SiC, C or a combination thereof. In some embodiments, the reaction gas includes N2. In some embodiments, the selector is deposited onto the first electrode using chemical vapor deposition (CVD), and the defect reduction material is introduced into the selector by using a volatile precursor having the defect reduction material. In one example, the defect reduction material (e.g., N) is introduced into the selector by using a volatile precursor having the defect reduction material (e.g., N2 gas flow). Specifically, during the CVD process, the first electrode (e.g., aC) is exposed to one or more volatile precursors (e.g., N2) and other volatile precursors composed of threshold switch materials (e.g., Ge, Se, As, or Si), which react and / or decompose on the surface of the first electrode to generate a material composed of, for example, Ge. x Se y As z Si t N s The expected film consists of a film.

[0049] refer to Figure 6B , a selector 608 is formed on the first electrode 606 using sputtering deposition, and a defect reduction material (eg, Figure 4B 309) is introduced into selector 608.

[0050] Method 700 proceeds to operation 706, such as Figure 7As shown in , in this operation, the second electrode, the PCM element and the third electrode are sequentially deposited on the selector. In some embodiments, the deposition of the second electrode, the PCM element and the third electrode may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process or any combination thereof.

[0051] refer to Figure 6C , a second electrode 610, a PCM element 612, and a third electrode 614 are sequentially deposited on the selector 608. In some embodiments, the PCM element 612 may include a chalcogenide-based alloy. The second electrode 610 and the third electrode 614 may include W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof.

[0052] Method 700 proceeds to operation 708, such as Figure 7 As shown in FIG. 1 , in this operation, a word line is deposited on the third electrode, and thus a memory device (eg, Figure 3 300 in FIG. 300). Deposition of the word line on the third electrode may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

[0053] According to one aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of the plurality of memory cells is disposed at an intersection of a corresponding one of the plurality of bit lines and a corresponding one of the plurality of word lines. Each of the plurality of memory cells includes a stacked phase change memory (PCM) element and a selector having a defect reduction material.

[0054] In some embodiments, the defect reduction material includes at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.

[0055] In some embodiments, the selector includes a chalcogenide threshold switching material.

[0056] In some embodiments, the selector comprises Ge x Se y As z Si t N s , wherein x is from 0.03 to 0.20, y is from 0.30 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.005 to 0.10.

[0057] In some embodiments, the selector comprises Ge x Sey As z Si t C s , wherein x is from 0.03 to 0.20, y is from 0.30 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.002 to 0.10.

[0058] In some embodiments, the selector has a thickness between 10 nm and 50 nm.

[0059] In some embodiments, the defect reduction material is configured to fill dangling bond defects of the selector.

[0060] In some implementations, the memory device has a set speed of 96 to 110 ns.

[0061] In some embodiments, the memory device has a reset speed of 12 to 14 ns.

[0062] In some embodiments, the memory device has a leakage current of less than 10 -7 A.

[0063] In some implementations, the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

[0064] In some embodiments, each of the plurality of memory cells further includes a first electrode located in a vertical direction between the selector and a corresponding bit line, a second electrode located in a vertical direction between the PCM element and the selector, and a third electrode located in a vertical direction between the PCM element and a corresponding word line.

[0065] According to another aspect of the present disclosure, a phase change memory (PCM) cell includes a PCM element and a selector having a defect reduction material.

[0066] In some embodiments, the defect reduction material includes at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.

[0067] In some embodiments, the selector includes a chalcogenide threshold switching material.

[0068] In some embodiments, the selector comprises Ge x Se y As z Si t N s , wherein x is from 0.03 to 0.20, y is from 0.30 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.005 to 0.10.

[0069] In some embodiments, the selector comprises Ge x Se y As z Si t C s , wherein x is from 0.03 to 0.20, y is from 0.30 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.002 to 0.10.

[0070] In some embodiments, the selector has a thickness between 10 nm and 50 nm.

[0071] In some embodiments, the defect reduction material is configured to fill dangling bond defects of the selector.

[0072] According to yet another aspect of the present disclosure, a method for forming a memory device includes: depositing a selector using a deposition process and introducing a defect reduction material into the selector; and depositing a phase change memory (PCM) element on the selector.

[0073] In some embodiments, the deposition process includes physical vapor deposition (PVD), and introducing the defect reduction material includes using a sputtering target or a reactive gas with the defect reduction material.

[0074] In some embodiments, the sputtering target includes a silicon-based material having the defect reduction material.

[0075] In some embodiments, the sputtering target includes at least one of silicon nitride (SiN), silicon carbide (SiC), or carbon (C).

[0076] In some embodiments, the reaction gas includes nitrogen (N2).

[0077] In some embodiments, the deposition process includes chemical vapor deposition (CVD), and introducing the defect reduction material includes using a volatile precursor having the defect reduction material.

[0078] In some embodiments, the defect reduction material includes at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.

[0079] In some embodiments, the selector includes a chalcogenide threshold switching material.

[0080] In some embodiments, the selector comprises Ge x Se y As z Si t N s, wherein x is from 0.03 to 0.20, y is from 0.30 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.005 to 0.10.

[0081] In some embodiments, the selector includes a chalcogenide threshold switching material.

[0082] In some embodiments, the selector comprises Ge x Se y As z Si t C s , wherein x is from 0.03 to 0.20, y is from 0.30 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.002 to 0.10.

[0083] In some embodiments, the selector includes a chalcogenide threshold switching material.

[0084] In some embodiments, the method further comprises: depositing a bit line and a first electrode in sequence on a substrate; depositing a second electrode, the PCM element and a third electrode in sequence on the selector; and forming a word line on the third electrode. The selector is deposited on the first electrode.

[0085] The above description of the specific embodiments will reveal the general essence of the present disclosure, and those skilled in the art will be able to easily make modifications and / or adjustments to various applications of such specific embodiments by applying the knowledge in the art without excessive experiments, without departing from the general principles of the present disclosure. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed embodiments and the scope of equivalent schemes. It should be understood that the wording or terminology in the text is for the purpose of description rather than limitation, and therefore those skilled in the art should interpret the terms or wording of this specification according to the teachings and guidance.

[0086] The above describes the embodiments of the present disclosure by means of functional building blocks that illustrate the embodiments of the specified functions and their relationships. For the convenience of description, the boundaries of these functional building blocks are arbitrarily defined. Alternative boundaries can be defined as long as the specified functions and their relationships are appropriately performed.

[0087] The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0088] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, comprising: multiple bit lines; Multiple word lines; as well as a plurality of memory cells, each memory cell being disposed at an intersection of a corresponding one of the plurality of bit lines and a corresponding one of the plurality of word lines, wherein each of the plurality of memory cells comprises a stacked phase change memory (PCM) element and a selector having a defect reduction material, and Wherein, the selector includes Ge x Se y As z Si t N s , wherein x is 0.03 to 0.20, y is 0.40 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.08; or the selector comprises Ge x Se y As z Si t C s , wherein x is from 0.03 to 0.20, y is from 0.40 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.002 to 0.

01.

2. The memory device according to claim 1, wherein: The selector includes a chalcogenide threshold switching material.

3. The memory device according to any one of claims 1 to 2, wherein: The thickness of the selector is between 10 nm and 50 nm.

4. The memory device according to any one of claims 1 to 3, wherein: The defect reduction material is configured to fill dangling bond defects of the selector.

5. The memory device according to any one of claims 1 to 4, wherein: The memory device has a set speed of 96 to 110 ns.

6. The memory device according to any one of claims 1 to 5, wherein: The memory device has a reset speed of 12 to 14 ns.

7. The memory device according to any one of claims 1 to 6, wherein: The memory device has a leakage current lower than 10 -7 A.

8. The memory device according to any one of claims 1 to 7, wherein: The plurality of word lines and the plurality of bit lines are in a cross-point architecture.

9. The memory device according to any one of claims 1 to 8, wherein: Each of the plurality of memory cells further includes a first electrode located in a vertical direction between the selector and a corresponding bit line, a second electrode located in a vertical direction between the PCM element and the selector, and a third electrode located in a vertical direction between the PCM element and a corresponding word line.

10. A phase change memory (PCM) cell, comprising: PCM components; as well as Selector with defect reduction materials, Wherein, the selector includes Ge x Se y As z Si t N s , wherein x is 0.03 to 0.20, y is 0.40 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.08; or the selector comprises Ge x Se y As z Si t C s , wherein x is from 0.03 to 0.20, y is from 0.40 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.002 to 0.

01.

11. The PCM unit according to claim 10, wherein: The selector includes a chalcogenide threshold switching material.

12. The PCM unit according to any one of claims 10-11, wherein: The thickness of the selector is between 10 nm and 50 nm.

13. The PCM unit according to any one of claims 10 to 12, wherein: The defect reduction material is configured to fill dangling bond defects of the selector.

14. A method for forming a memory device, comprising: A selector is deposited using a deposition process and a defect reduction material is introduced into the selector, wherein the selector includes Ge x Se y As z Si t N s , wherein x is 0.03 to 0.20, y is 0.40 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.08; or the selector comprises Ge x Se y As z Si t C s , wherein x is from 0.03 to 0.20, y is from 0.40 to 0.60, z is from 0.15 to 0.45, t is from 0.02 to 0.20, and s is from 0.002 to 0.01; and A phase change memory (PCM) element is deposited on the selector.

15. The method according to claim 14, wherein: The deposition process includes physical vapor deposition (PVD), and introducing the defect reduction material includes using a sputtering target or a reactive gas having the defect reduction material.

16. The method according to claim 15, wherein: The sputtering target includes a silicon-based material having the defect reduction material.

17. The method according to claim 15 or 16, wherein: The sputtering target includes at least one of silicon nitride (SiN), silicon carbide (SiC), or carbon (C).

18. The method according to any one of claims 15 to 17, wherein: The reaction gas includes nitrogen (N2).

19. The method according to claim 14, wherein: The deposition process includes chemical vapor deposition (CVD), and introducing the defect reduction material includes using a volatile precursor having the defect reduction material.

20. The method according to any one of claims 14 to 19, wherein: The selector includes a chalcogenide threshold switching material.

21. The method according to any one of claims 14 to 20, further comprising: Depositing a bit line and a first electrode in sequence on a substrate, wherein the selector is deposited on the first electrode; depositing a second electrode, the PCM element and a third electrode in sequence on the selector; and A word line is formed on the third electrode.

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