Controller area network device

Abstract

A CAN bit stream sampling device for a controller area network (CAN) controller, the device configured to receive a bit stream from a CAN transceiver, the device configured to: detect a rising edge in the bit stream; separately detect a falling edge in the bit stream; and generate a recovered non-return-to-zero coded bit stream based on at least the detected falling edge and the detected rising edge.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a sampling device for use in a controller area network (CAN). In particular, the present disclosure relates to a sampling device for a CAN controller and a CAN node, comprising a CAN transceiver and the CAN controller. The present disclosure further relates to a CAN network and a method of operating the sampling device. BACKGROUND

[0002] A CAN network enables communication between nodes over a bus. Nodes connected to the bus can transmit data to and receive data from other nodes connected to the bus. A CAN node typically comprises a CAN controller for coupling to the CAN bus and a CAN transceiver. The CAN transceiver provides differential signaling to the bus based on digital transmission data from the CAN controller and receives differential signaling from the bus and provides a bit stream comprising the received data to the CAN controller. The CAN network implements a CAN protocol defining rules for communication between nodes. SUMMARY

[0003] According to a first aspect of the present disclosure, there is provided a CAN bit stream sampling device for a controller area network, CAN, controller, the device being configured to receive a bit stream from a CAN transceiver, the device being configured to:

[0004] detect a rising edge in the bit stream;

[0005] separately detect a falling edge in the bit stream; and

[0006] generate a recovered non-return-to-zero coded bit stream based on at least the detected falling edge and the detected rising edge.

[0007] In one or more examples, a first block is configured to provide the detection of the rising edge in the bit stream; a second block is configured to provide the detection of the falling edge in the bit stream; and a selector block is configured to generate the recovered non-return-to-zero coded bit stream based on the detection of the rising and falling edges in the bit stream by the first and second blocks;

[0008] wherein detection of a rising edge by the first block causes a first logic state bit to be generated in the recovered non-return-to-zero coded bit stream and detection of a falling edge by the second block causes a second logic state bit to be generated in the recovered non-return-to-zero coded bit stream.

[0009] It will be appreciated that the first logic state bit can comprise a logic high bit and the second logic state bit can comprise a logic low bit. However, the assignment between a transition and a logic state is an arbitrary assignment depending on the protocol.

[0010] In one or more examples, the first block is configured to generate another first logic state bit in the recovered non-return-to-zero encoded bit stream based on a predetermined bit time after the generation of the first logic state bit after the detection of the rising edge and before the detection of a subsequent edge; and

[0011] the second block is configured to generate another second logic bit in the recovered non-return-to-zero encoded bit stream based on the predetermined bit time after the generation of the second logic state bit after the detection of the falling edge and before the detection of a subsequent edge.

[0012] In one or more examples, the first block is configured to provide an edge detection signal to the selector block after detecting a rising edge to instruct the selector block to generate the first logic state bit in the recovered non-return-to-zero encoded bit stream, and the first block is configured to provide a bit passage signal after each predetermined bit time thereafter to enable the selector block to generate one or more subsequent first logic state bits in the recovered non-return-to-zero encoded bit stream; and

[0013] wherein the second block is configured to provide an edge detection signal to the selector block after detecting a falling edge to instruct the selector block to generate the second logic state bit in the recovered non-return-to-zero encoded bit stream, and the second block is configured to provide a bit passage signal after each predetermined bit time thereafter to enable the selector block to generate one or more subsequent second logic state bits in the recovered non-return-to-zero encoded bit stream.

[0014] In one or more examples, the first block and the second block are configured to determine a nominal bit time of the bit stream, the nominal bit time comprising a time for a bit to be transmitted by a transmitting node that transmits the bit stream, wherein the first block is configured to determine the nominal bit time based on a determined first block time between rising edges of the bit stream, and the second block is configured to determine the nominal bit time based on a determined second block time between falling edges of the bit stream, wherein the first block time and the second block time indicate integer multiples of the nominal bit time of the bit stream; and

[0015] the first block and / or the second block is configured to modify the predetermined bit time based on the determined nominal bit time.

[0016] In one or more examples, the first block time comprises a time between consecutive rising edges.

[0017] In one or more examples, the second block time comprises a time between consecutive falling edges.

[0018] In one or more examples, the first block and the second block are configured to receive a clock signal from an oscillator, and wherein the predetermined bit time is defined by a number of cycles of the oscillator. The number of cycles defining the predetermined bit time can be modified so that the predetermined bit time conforms to the determined nominal bit time.

[0019] In one or more examples, the device is configured to suppress noise in the bit stream by oversampling the bit stream and detecting a rising edge based on a logic state between two samples changing to a first logic state and being maintained in at least a third sample connected to the first and second samples, and

[0020] detecting a falling edge based on a logic state between two samples changing to a second logic and being maintained in at least a third sample connected to the first and second samples.

[0021] In one or more examples, the device is configured to use oversampling of the bit stream to suppress noise, the oversampling comprising sampling the bit stream using at least two consecutive samples, wherein a determined edge in the bit stream is suppressed as noise based on one of a rising edge or a falling edge determined from the first sample and a rising edge or a falling edge determined from the second sample, wherein the samples are taken at a time interval less than a predetermined bit time.

[0022] In one or more examples, the threshold is a time interval less than the bit time.

[0023] In one or more examples, the first block is configured to provide a synchronization signal to the second block upon detecting a rising edge to define a point in time from which the predetermined period of time is determined; and wherein the second block is configured to provide a synchronization signal to the first block upon detecting a falling edge to define a point in time from which the predetermined period of time is determined.

[0024] According to a second aspect of the disclosure, there is provided a CAN controller comprising the CAN bit stream sampling device of the first aspect. The CAN controller can be configured to be coupled to a CAN transceiver to receive a bit stream and to provide transmission data for transmission in a CAN bus. The CAN controller can comprise a CAN protocol controller implementing a CAN protocol.

[0025] According to a third aspect of the disclosure, there is provided a CAN network comprising a plurality of nodes, wherein at least one of the nodes comprises the CAN controller of the second aspect.

[0026] According to a fourth aspect of the disclosure, there is provided a method of sampling a bit stream in a CAN controller, the method comprising: receiving a bit stream from a CAN transceiver;

[0027] detecting rising edges in the bitstream;

[0028] separately detecting falling edges in the bitstream; and

[0029] generating a recovered non-return-to-zero encoded bitstream based at least on the detected falling edges and the detected rising edges.

[0030] In one or more examples, the detecting rising edges provides a first logic state in the generating the recovered non-return-to-zero encoded bitstream; and the detecting falling edges provides a second logic state in the generating the recovered non-return-to-zero encoded bitstream, and wherein the method includes determining a nominal bit time, the nominal bit time including a time for a bit to be transmitted by a transmitting node that transmits the bitstream, wherein the nominal bit time is used as a bit length for the recovered non-return-to-zero encoded bitstream, the determination of the nominal bit time is based on a determined time between successive rising edges of the bitstream and / or based on a determined time between successive falling edges of the bitstream.

[0031] In another aspect, a CAN sampling mechanism on an RXD path is provided, in particular a CAN XL sampling mechanism, which separately detects falling and rising edges and uses edge information to recover an NRZ encoded bitstream inside a CAN controller, in particular a CAN XL controller.

[0032] In another aspect or in one or more examples, a CAN sampling mechanism on an RXD path is provided, in particular a CAN XL sampling mechanism, which optionally uses some over-sampling (e.g. 2 samples in a line or more) to suppress noise of very fast edges in a line, the CAN sampling mechanism uses at least a single sample to detect an edge transition. The amount of edges can be programmable to define filter characteristics to suppress noise pulses.

[0033] In another aspect or in one or more examples, a CAN sampling mechanism on an RXD is provided, in particular a CAN XL sampling mechanism, which synchronizes two edge monitors based on detecting an edge on a single edge monitor. In effect, if a falling edge is detected, both edge detectors correct their bit timing by the same time shift amount to compensate for oscillator tolerance between a transmitting node and a receiving node.

[0034] In another aspect or in one or more examples, a CAN controller is provided that utilizes the same sampling mechanism on an RXD line during a fast data phase, in particular a CAN FD controller.

[0035] While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that other embodiments can be utilized without departing from the scope of the disclosure. All modifications and alternatives falling within the spirit and scope of the appended claims are intended to be encompassed.

[0036] The above discussion is not intended to represent every example embodiment or every implementation of the present or future claim set. The following drawings and detailed description further convey the various example embodiments. The following detailed description, when taken together with the drawings, can enable a fuller appreciation of the various example embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0037] One or more embodiments will now be described, by way of example only, with reference to the attached drawings in which:

[0038] Figure 1 An example embodiment of a CAN controller coupled with a CAN transceiver is shown;

[0039] Figure 2 An example CAN network is shown;

[0040] Figure 3 An example of asymmetry in an NRZ encoded CAN bit stream is shown;

[0041] Figure 4 An example sampling of an asymmetric signal in classic CAN and CAN FD as in the state of the art is shown;

[0042] Figure 5 Another example sampling of an asymmetric signal in classic CAN and CAN FD as in the state of the art is shown;

[0043] Figure 6 A state of the art implementation for determining bit values in a bit stream in classic CAN and CAN FD is shown;

[0044] Figure 7 An example embodiment of an apparatus providing two independent mechanisms for detecting edges and reconstructing bit stream order is shown;

[0045] Figure 8 An example embodiment of an edge-based bit pattern recovery mechanism for implementation in a CAN controller of a CAN node of a CAN network is shown;

[0046] Figure 9 A second example embodiment of an edge-based bit pattern recovery mechanism for implementation in a CAN controller of a CAN node of a CAN network is shown; and

[0047] Figure 10An example method performed by a device is shown. DETAILED DESCRIPTION

[0048] A controller area network, CAN, typically includes a plurality of nodes each connected to a two-wire CAN bus. The nodes can communicate with each other by sending and receiving signaling to and from the CAN bus.

[0049] Figure 1 An example node 100 is shown. Figure 2 An example controller area network 200 including a plurality of nodes including node 100 and other nodes 201, 202, 203 is shown. Network 200 can be part of an automobile or other device, and the CAN network can provide communication between systems of the automobile or other device. The network includes a two-wire CAN bus 202 to which nodes 100, 201, 202, 203 are coupled. It will be appreciated that network 200 can include any number of nodes, and can also include termination nodes at each end of bus 202 to provide a predetermined resistance between the bus wires.

[0050] Returning to Figure 1 , an example node 100 is shown. The node includes a CAN controller 101, such as a microcontroller. CAN controller 101 can be embedded with a CAN protocol, such as in an embedded protocol controller module. CAN controller 101 provides and receives signaling from CAN bus 202 using a CAN transceiver 103. Thus, CAN transceiver 103 typically provides signaling to CAN bus based on transmission data received from CAN controller 101, and provides receive data to CAN controller 101 based on signaling received by the CAN transceiver 103 from CAN bus 102. CAN transceiver 103 can be configured to provide signaling to CAN bus 102 based on transmission data with voltage levels appropriate for a logical high and a logical low, and with differential signaling appropriate for a two-wire CAN bus according to the CAN protocol. CAN transceiver 103 can be configured to produce receive data for the CAN controller by converting the differential signaling of the bus into a bit stream on a single receive line or RXD for the CAN controller.

[0051] References herein to a CAN transceiver or CAN controller can be understood as a controller and transceiver implementing at least in part all or part of the CAN protocol or all or part of the CAN FD protocol. The functionality described herein for a CAN transceiver or CAN controller can include increased functionality beyond that defined in the current CAN or CAN FD protocol specifications, such as in the proposed CAN XL protocol specification.

[0052] The CAN controller 101 is configured to provide transmission data at a transmission output 104 for receipt at a transmission input 105 of the CAN transceiver 103. The transmission output 104 and the transmission input 105 (also referred to as "TXD") can comprise integrated circuit pins. Thus, the transmission input pin 105 is configured to receive transmission data from the CAN controller 101. The CAN transceiver 103 is configured to receive signalling from the CAN bus 102 and provide received data based on the signalling to a reception output 106 for receipt at a reception input 107 at the CAN controller 101. The reception output 106 and the reception input 107 can comprise integrated circuit pins. The reception output 106 and the reception input 107 are also referred to as "RXD" in the art.

[0053] The CAN transceiver 103 comprises a transmitter arrangement 108 configured to transmit signalling on the CAN bus 102 based on the transmission data. The CAN transceiver 103 further comprises a receiver arrangement 111 configured to receive signalling from the CAN bus 102 and provide received data based on the signalling.

[0054] The transmitter arrangement 108 comprises at least one transmitter, and in this example two transmitters 109, 110. The at least one transmitter is configured to operate in a first transmission mode or a second transmission mode, wherein in the first transmission mode the transmitter arrangement is configured to transmit the signalling with a first property, and wherein in the second transmission mode the transmitter arrangement is configured to transmit the signalling with a second property. The first property and the second property can comprise one or more property types, such as a baud rate (e.g. a maximum baud rate, a minimum baud rate or an average baud rate), a voltage scheme, a coding scheme or others. However, for ease of explanation in this document, the first property and the second property can comprise a baud rate, such that the first property comprises a first baud rate and the second property comprises a second baud rate, wherein the second baud rate is higher than the first baud rate. Using a higher baud rate can increase the rate at which data can be transmitted on the CAN bus. However, it will be appreciated that the first property and the second property can alternatively, or in addition, be (in any example embodiment herein) a voltage scheme used to represent a logical 0 and a logical 1 on the CAN bus 102. For example, the first property can comprise using the first baud rate and a first voltage scheme, and the second property can comprise using the second baud rate and a different second voltage scheme.

[0055] Thus, further, and by way of example only, the first transmission mode can comprise a normal transmission mode, and the second transmission mode can comprise a fast transmission mode having a higher baud rate than the normal transmission mode. In one or more examples, the first transmitter 109 can provide the first transmission mode or normal transmission mode, and the second transmitter 110 can provide the second transmission mode or fast transmission mode.

[0056] In one or more examples, the second transmitter 110, or more generally the transmitter arrangement 108, can comprise a first transmitter element configured to increase a potential difference between at least two wires of the bus towards a first differential voltage state, and a second transmitter element configured to decrease the potential difference between the at least two wires of the bus towards a second differential voltage state. Thus, the transmitter elements are configured to actively drive the bus between the first differential voltage state and the second differential voltage state, and vice versa. In a conventional CAN implementation, energy can be drawn from the bus using a termination resistor to assume one of the differential voltage states, but in this example configuration the bus 202 can be driven to both the first differential voltage state and the second differential voltage state by the transmitter elements, which can be embodied as amplifiers.

[0057] It will be appreciated that in one or more examples, the transmitter arrangement 108 can comprise one transmitter, and that the first transmission mode and the second transmission mode can be provided by the single transmitter using one or more of a change in voltage applied to the transmitter, a bias voltage, and a cut-in and cut-out of additional circuitry. In other examples, more than two transmitters can be used to provide the first transmission mode and the second transmission mode.

[0058] The receiver arrangement 111 comprises at least one receiver, and in this example two receivers 112, 113. The at least one receiver can be configured to operate in a first reception mode or a second reception mode, where in the first reception mode the receiver arrangement 111 is configured to receive signalling from the bus 102 using the first property, and in the second reception mode the receiver arrangement 111 is configured to receive signalling from the bus 102 using the second property. As described above, the property can be any one or more of a baud rate, a voltage scheme, a coding scheme, or others.

[0059] Thus, further, and by way of example only, the first reception mode can comprise a normal reception mode, and the second reception mode can comprise a fast reception mode, where signalling having a higher baud rate is configured to be received from the bus.

[0060] As mentioned above and as shown in this example, the receiver arrangement 111 includes a first receiver 112 configured to receive signaling at the normal baud rate and a second receiver 113 configured to receive signaling at a higher baud rate. In one or more examples, the first receiver 112 is configured to receive the signaling from the CAN bus 102 with a first voltage scheme to determine a logic high and a logic low of the signaling, and the second receiver 113 is configured to receive the signaling from the CAN bus 102 with a second voltage scheme different from the first voltage scheme to determine a logic high and a logic low from the signaling. Thus, the first receiver 112 and the second receiver 113 can differ in one or more of the baud rate at which they are able to receive symbols on the CAN bus 102 and the voltage scheme used to signal on the CAN bus (to enable receiving the signaling with the first and second properties). Each of the receivers 112, 113 has two inputs for receiving signaling from the two-wire CAN bus 102, and a single output for enabling forward transmission of received data to the CAN controller 101 or any other component therebetween.

[0061] It should be appreciated that in one or more examples, the receiver arrangement 111 can include one receiver, and the fast and slow receive modes can be implemented by the single receiver using one or more of a change in voltage applied to the receiver, a bias voltage, and cut-in and cut-out additional circuitry. In other examples, more than two receivers can be used to provide the first and second receiver modes.

[0062] It can be determined by the CAN controller 101 whether the node 100 needs to operate in the first transmission mode instead of the second transmission mode.

[0063] Turning now to an example configuration of the CAN controller 101, the CAN controller 101 can include a controller module 123, which can include a CAN protocol controller, and is configured to output transmission data. The transmission data can be provided to the transmission output 104 of the CAN transceiver. The transmission data can include NRZ encoded transmission data (non-return-to-zero NRZ encoding) in at least one operating mode of the CAN controller 101. The signaling received by the receiver arrangement 111 can also be NRZ encoded signaling. The received data received by the CAN controller 101 at the receive input or RXD 107 can also include NRZ encoded signaling.

[0064] According to the CAN protocol, signaling on the CAN bus 102 can comprise a logic 0, i.e. the dominant of the CAN protocol according to the (typically) 2V provided between the wires of the bus, or a logic 1, i.e. the recessive of the CAN protocol according to the 0V provided between the wires of the bus. The CAN protocol defines a predetermined bit time for each bus level to be provided. In an ideal case, the dominant and recessive levels (and / or other differential voltage levels that can be provided between the CAN bus wires) can be provided for the predetermined bit time.

[0065] Reference Example Figure 3 shows signaling representing a CAN protocol message, which is provided by differential bus signaling and encoded on the bus wires with an NRZ signal scheme. This means that any bit is represented by a dedicated bus level. Since the beginning of the CAN protocol, which is referred to by those skilled in the art as conventional / classic CAN, and in CAN FD (Controller Area Network Flexible Data Rate), an NRZ bit encoding scheme has been used and is planned to be used for the next CAN type, also referred to as "CAN XL".

[0066] A general problem of NRZ encoded signals is that these signals suffer from signal distortions, especially in terms of bit length variations. Depending on all kinds of physical effects, the bus signaling representing a bit on the bus 102 can be lengthened on one level (e.g. one of the dominant or recessive level) and shortened on the other level (e.g. the other one of the dominant or recessive level), or shortened on one level and lengthened on the other level, respectively. Thus, the time length of a dominant or logic 0 can be increased with respect to the predetermined bit time defined by the CAN protocol and the time length of a recessive or logic 1 can be decreased with respect to the predetermined bit time defined by the CAN protocol. In one or more examples, the "duty cycle" or "asymmetry" of the bit stream can degrade after transmission in the bus 202 from a transmitting node, e.g. 201, 202, 203, towards a receiving node, e.g. 100. Each element on the path, i.e. the nodes 201, 202, 203 between the transmitting and receiving nodes on the bus 202, can add to this "asymmetry".

[0067] Figure 3A timing diagram 300 is shown that shows examples of asymmetry of a CAN bitstream that is NRZ encoded. Trace 301 shows the ideal bus signal as received by node 100 or any other node 201, 202, 203. The nominal bit length 304 of a logical low bit is the same as the nominal bit length 305 of a subsequent logical high bit. In trace 302, a first "extreme" is shown where the logical low bit is shorter in time and the logical high bit is longer in time. Thus, the bit time is asymmetric in the case where the logical high state dominates. In trace 303, a second "extreme" is shown where the logical high bit is shorter in time and the logical low bit is longer in time. Thus, the bit time is asymmetric in the case where the logical low state dominates.

[0068] As the nodes 100, 201, 202, 203 in a bus system of CAN do not have a common clock reference and there is no simple clock recovery possible from a bitstream that is NRZ encoded, as all CAN systems utilize re-synchronization based on edges. If an edge is detected, this is considered a bit change driven by the sending node and the receiving node can consider this as a reference time point to reconstruct the bits after knowing the baud rate used based on the local oscillator and by system configuration. As the local clock sources are never 100% identical, the receiving node will drift away from the sending node over time and will lose the correct bitstream. Thus, these detected edges can be used for re-synchronization.

[0069] In conventional CAN and CAN FD, this re-synchronization is done on a single falling edge (implicit to explicit bit transition, differential bus voltage 0V to typically 2V) and only this falling edge is used for re-synchronization. Based on this falling edge as a reference time point, all subsequent bits are detected, i.e. sampled.

[0070] In conventional CAN and CAN FD, the actual bit level sampling is configured for the system and allows filtering of disturbances and the like. To allow asymmetry in both directions, the sample point, the time during the bit time when the voltage to the bus is sampled to determine if a logical high state or a logical low state is present, has to be configured to be in the middle of the bit time relative to the last detected synchronization edge. Based on this, up to 50% of the bit time asymmetry in both directions can be allowed, but more than 50% of the bit time asymmetry cannot be allowed. If the asymmetry becomes larger than 50% of the bit time, the sampling does not yield the correct bit value and the communication stops, i.e. is negatively affected or invalid.

[0071] By the way: Since the signal of the NRZ encoding does not have a guaranteed bit edge in case of many zeros or many ones transmitted, for example, in a row, there are so-called "stuff bits" inserted into the bit stream at known positions. For regular CAN and CAN FD, this is done every five consecutive bits at the same level. From this, there is a synchronization edge in such a NRZ encoded scheme at the latest after 10 bit times.

[0072] Since in real systems and especially for further development of CAN, for example, the proposed CAN XL specification (as well as CAN FD and classic CAN), the structural asymmetry can become higher than the tolerable 50% of the bit time, and it is proposed to change the sampling mechanism of the incoming bit stream, i.e. the bit stream received at the receiving input 107, to the CAN controller 101 on RXD.

[0073] In one or more examples, the idea can also be transferred to CAN FD in a phase without arbitration.

[0074] Figure 4 The sampling of an asymmetric signal as performed in the state of the art, for example, in classic CAN and CAN FD, is shown. The sampling can be performed by an entity called bit timing logic block or BTL block.

[0075] The trace 401 shows an asymmetric bit stream (RXD). The asymmetric bit stream can comprise a "worst case single ended RXD". This can mean that this is the most asymmetric bit stream tolerable in classic CAN and CAN FD. The section 402 shows the operation of a regular "falling edge synchronized bit timing logic block" configured to determine the presence of a logical high and a logical low in the bit stream.

[0076] The section 402 shows the expected bit length synchronized to the last synchronization falling edge, wherein each bit time is divided into a section Tseg1 and Tseg2 (and SynchSeg, as will be known to the skilled person, but not shown for simplicity). The falling edge is shown at 403, and thus, the nominal bit length extends from this point. The falling edge 403 belongs to the SynchSeg section, which is not shown. The section 402 shows the timing of a regular "falling edge synchronized bit timing logic block", wherein the bit sample point 404 is set to about 50% of the nominal bit time from the expected start of the bit, wherein the expected start of the bit is synchronized based on the last falling edge 403. As can be seen, the sample point 404 is between the Tseg1 section and the Tseg2 section, and the sampling time is just within the asymmetric bit time 406.

[0077] If the bit sample point 404 is at 70% of the nominal bit time from the expected start of the bit, then the regular sampling mechanism can completely miss the asymmetric logical low bit 406, as shown at 405.

[0078] Figure 5 The sampling of an asymmetric signal as performed in the state of the art, e.g. in classic CAN and CAN FD, is shown.

[0079] Trace 501 shows an asymmetric bit stream. The asymmetric bit stream can comprise "worst case single ended RXD". This can mean that this is the most asymmetric bit stream that is tolerable in classic CAN and CAN FD. Section 502 shows the operation of a regular "falling edge synchronized bit timing logic block" configured to determine the presence of a logic high and a logic low in the bit stream.

[0080] Section 402 shows the expected bit length synchronized to the last sync bit, which is divided into sections Tseg1 and Tseg2 at each bit time. The falling edge is shown at 503, and thus, the nominal bit length should extend from this point. Section 502 shows the timing of a regular "falling edge synchronized bit timing logic block", where the bit sample point 504 is set to 50% of the nominal bit time from the expected start of the bit, which is based on the last falling edge synchronization. As can be seen, the sample point is between the Tseg1 section and the Tseg2 section, and the sampling time is within the asymmetric bit time 506.

[0081] With the bit sample point at 504, the bit timing logic block is able to correctly determine the state of the bit 506, since the bit 506 is longer due to the asymmetry. However, the next bit 507 is shorter, and the regular sampling mechanism can place the next bit sample point 508 at a point, e.g. 509, that can completely miss the shorter logic high bit 507 of the asymmetry.

[0082] Thus, by using the regular CAN / CAN FD sampling mechanism for each bit level based on a fixed bit sample point 404, 504, 508, at most 50% asymmetry of the bit time is tolerable. As Figure 4 and 5 As shown, based on the falling edge, the BTL is synchronized, and the actual bit level is determined after 50% of the bit time.

[0083] In case the asymmetry becomes larger than about 50%, the bit sample point is no longer correct and the received bit stream is impaired.

[0084] Figure 6An example is shown of how such a classical CAN and CAN FD approach can be implemented. There is a bit-true logic block (BTL) 601 that receives a bit stream from a receive input 107 (also referred to as RXD). Thus, the BTL 601 comprises part of the CAN controller 101 and the bit stream is received from the CAN transceiver 103. The BTL 601 is triggered on a single edge and provides a bit level of the bit stream based on a configured bit sample point. Thus, as shown in Figure 4 and 5 Before a bit of the bit stream is sampled, one of the falling edges starts a timer, which in the above example uses an oscillator 602 to measure a time comprising 50% of the bit time of each subsequent bit. The bit level resulting from this sampling is provided at a “derived bit level” output 603. In addition, the BTL 601 provides information about whether a next bit is provided at a “next bit trigger” output 604.

[0085] We will now describe example embodiments.

[0086] Instead of using only the implicit to explicit edge for resynchronization, it is proposed to use two edges in the CAN XL data phase, because in the CAN XL data phase the physical layer ensures that two bit transitions have equal performance (push-pull driver, see description of transmitter element above). In contrast, classical CAN does not have such a property. In the example of a CAN FD transceiver with signal improvement capability (SIC), CAN FD becomes very close to the property. It should be appreciated that SIC is defined by the CiA 601-4 specification in publicly available standards from CiA (CAN in Automation), and CAN FD is ISO standard: ISO 11898-1 (protocol) and ISO 11898-2 (transceiver). The push-pull driver and signal improvement capability can provide at least a transmitter arrangement 108, wherein the transmitter arrangement is configured to drive a bus in an active manner between a first differential voltage state and a second differential voltage state, and vice versa. As mentioned above, the transmitter arrangement 108 can comprise respective transmitter elements configured to drive the bus to the first differential state and the second differential state.

[0087] Further, it is proposed to use a post-processing of an observed RXD bit pattern to sample the RXD bus signal differently. In fact, the information of a bit change on the bus can be obtained by observing that the level on the RXD line, i.e. at the receive input 107, has changed from one level to another. If there is a signal change of reasonable time, e.g. for a reasonable threshold time to filter out noise spikes, there is a bit level change on the bus line. In case the receive input pin 107 switches back to the other level, this is already the information that there is another bit on the bus. For proper message reception, it does not matter at which absolute time the bit level change is found, but rather about the correct bit order to be reconstructed. Thus, the bit falling edge can occur at any time relative to the rising edge, and thus, the symmetry of the bits is no longer relevant.

[0088] Thus, by reading the edge information at a fixed time, e.g. at the point of time of 50% of the bit time from the start of the expected bit, the NRZ encoded bit pattern can be reconstructed by a “edge on edge” decision. In case there is no further edge within one nominal bit time, this means another bit with the same level.

[0089] Thus, a controller area network, CAN, controller is disclosed, the CAN controller configured to receive a bit stream at a receive input RXD, the receive input comprising a part of a receive path from a CAN transceiver coupled to a CAN bus to the CAN controller, the CAN controller comprising a CAN sampling mechanism, the CAN sampling mechanism can have an application in the proposed CAN XL standard, wherein the CAN sampling mechanism or “device” is configured to:

[0090] detect a falling edge in the bit stream

[0091] separately detect a rising edge in the bit stream; and

[0092] restore a non-return-to-zero encoded bit stream based on the detected falling edge and the detected rising edge.

[0093] The bit stream received at the receive input 107 can be subject to the asymmetry discussed above. Thus, in one or more examples, it is disclosed that the CAN sampling mechanism configured to restore the bit stream by accurately determining the presence of a logic high state or a logic low state based on detecting a rising edge for determining a logic high and a falling edge for determining a logic low. This technique can overcome problems associated with the conventional way of sampling the bit stream in classic CAN, where the falling edge defines the synchronization point and a predetermined fraction of the nominal bit time is used to determine the sampling point of time of the level of the captured bit. In classic CAN, at the sampling point of time, the level in the bit stream determines whether the bit is determined to be a logic high or a logic low.

[0094] In particular, the CAN controller can be configured to recover the bit stream in the sense of sampling the bit stream in a manner that overcomes the effects of asymmetry, and wherein the recovered bit stream can be provided for further processing by the controller module 123 of the CAN controller 101, e.g. by the CAN protocol controller.

[0095] In one or more examples, when using rising and falling edges to determine a logic high state / logic low state, signal spikes caused by noise can potentially falsely determine a logic high bit / logic low bit, as the spikes can appear as a falling edge after a rising edge, or a rising edge after a falling edge.

[0096] Accordingly, in one or more examples, alternatively or in addition, the CAN sampling mechanism can use oversampling (e.g., two samples in a row or more) to suppress very fast edge noise in a row, the CAN sampling mechanism using at least a single sample to detect an edge transition. The amount of edges can be programmable to define filter characteristics that suppress noise pulses. Accordingly, the CAN sampling mechanism can be configured to sample the bit stream at the receive input 107 at twice or more the rate of the nominal bit time. In other examples, the CAN sampling mechanism can be configured to sample the bit stream one or more additional times after detecting an edge to suppress noise. Accordingly, if a rising edge is detected, the sampling mechanism can be configured to sample the bit stream a predetermined number of times later within the nominal bit time, and if a logic high is detected, the rising edge can be determined to be noise. Alternatively, if a rising edge is detected, and a logic high is then determined by the one or more additional samples, the rising edge can be determined to be a valid bus state. Similarly, if a falling edge is detected, the sampling mechanism can be configured to sample the bit stream a predetermined number of times later within the nominal bit time, and if a logic low is detected, the falling edge can be determined to be noise. Alternatively, if a falling edge is detected, and a logic low is then determined by the one or more additional samples, the falling edge can be determined to be a valid bus state. As an example, the devices (BTL 703 and 704 in the figure below) are configured to "oversample" by taking individual level samples faster than the bit times 304, 305. A typical oversampling rate can include ten samples per bit, but 5 to 15 samples per bit or any other range is possible. This can be user configurable. Accordingly, the use of two samples in a row can be explained by the following example: the device can detect an edge in the case where the first of, for example, ten samples per bit time is high and the next is low. In this case, a noise pulse would immediately be considered an edge representing a bit, which can be too sharp / fast on a noisy bus. Accordingly, the device can be configured to use "n" samples in a row before an edge is considered to represent a bit. As an example, in the case of single sample edge detection, the sample stream 111101111 would be a logic level 101 bit pattern, as it is a single sample that is being judged. If the device uses 2 samples in a row to indicate a true signal edge, for example, the same sample pattern would not cause a bit change. Accordingly, the device can confirm that the edge is actually an edge and not noise by the subsequent oversampled samples. By way of example, if it is decided that two samples in a row with the same logic state are needed to confirm that an edge is not noise, this sample pattern would cause a bit detection 1111001111, but a single zero would now be considered "noise" and ignored.

[0097] Thus, in general, to have some noise filtering, proper edge determination can be based on a mechanism that accepts only two or more identical samples in a row. At least any different sample value is considered edge information (or optionally, multiple identical samples in a row). The number of samples in a row for edge detection can be configurable. The more samples taken, the longer the level change the detection bit needs to maintain, and thus, the range of asymmetry that can be tolerated becomes smaller. This is a balance point between noise rejection and asymmetry tolerance.

[0098] In one or more examples, the CAN sampling mechanism can include a first edge monitor or "BTL" configured to provide the detection of falling edges and a second edge monitor or "BTL" configured to provide the detection of rising edges.

[0099] In one or more examples, the CAN sampling mechanism receives a timing signal from a local oscillator. It should be appreciated that the timing signal from one node can differ from or drift away from the timing signal of another node 100, 201, 202, 203 in the network.

[0100] Thus, the CAN sampling mechanism can be configured to synchronize both the first edge monitor and the second edge monitor based on detecting a respective rising edge or falling edge on one of the first edge monitor and the second edge monitor. In effect, if a falling edge is detected, both edge detectors correct their bit timing by the same amount of time shift to compensate for the oscillator tolerance between the transmitting node and the receiving node.

[0101] Thus, if the first edge monitor detects a falling edge that occurs at a time that is not an integer multiple of the bit time as determined with reference to the local oscillator, the first edge monitor determines that the local oscillator is not synchronized with the transmitting node of the network. The first edge monitor can then synchronize both the first edge monitor and the second edge monitor by configuring the controller such that the time between the falling edges is an integer multiple of the bit time. This can be achieved in different ways. For example, the first edge monitor and the second edge monitor can be configured such that the number of oscillations of the local oscillator that includes the bit time can be adjusted. Alternatively, the frequency of the local oscillator can be adjusted. Those skilled in the art will appreciate ways of providing the synchronization.

[0102] It should be appreciated that the CAN controller can include a CAN FD controller, which includes a CAN controller that implements the CAN FD protocol. The CAN FD controller includes a phase referred to in the art as a "fast data phase". The CAN FD controller can implement the same sampling mechanism described herein on the bit stream at the receive input (i.e. on the RXD line) during the fast data phase.

[0103] Thus, to implement, oversampling of the incoming RXD bit stream is proposed compared to the sampling currently performed in classic CAN and CAN FD. The difference of the proposed sampling mechanism is that the found signal transition has been considered as a bit level change. Thus, the CAN controller uses the bit transition itself to determine the value of the bit instead of using the bit transition as a starting point for a timer which then leads to the sampling of the bit stream at predetermined bit sample points (which can be based on 50% of the nominal bit time).

[0104] Reference is also made to Figure 7 and 8 Example embodiments are described. An example CAN sampling mechanism or device 700 that can be implemented in the CAN controller 101 is presented.

[0105] The device 700 comprises an input node 701 to receive a bit stream from the RXD pin (i.e. the receive input 107) which receives the bit stream from the CAN transceiver 103. It will be appreciated that the CAN transceiver 103 is configured to receive a differential signal from the CAN bus 202 and to provide a single digital signal to the receive input 107. The CAN transceiver 103 is not configured to interpret the differential signaling and can be considered to act as a level shifter based on the differential signaling. Thus, any asymmetry of the signaling from the bus 202 will be present in the bit stream received at 107 and thus at the input node 701.

[0106] The device 700 comprises a first bit timing logic module (“BTL”) 703 and a second bit timing logic module 704. The first BTL 703 is configured to detect rising edges in the bit stream from the input 701. The second BTL 704 is configured to detect falling edges in the bit stream from the input 701. The first and second BTL further comprise clock inputs 705 and 706 to receive a timing signal from the local oscillator 702.

[0107] A bidirectional connection 707 is provided between the first BTL 703 and the second BTL 704 to provide synchronization information between the first BTL 703 and the second BTL 704 to synchronize the two BTLs based on a determination that synchronization through one of the two BTLs is required.

[0108] The device 700 further comprises a BTL selector 708 configured to receive an edge detection signal 711 from the first BTL 703 and an edge detection signal 712 from the second BTL 704. The edge detection signals 711, 712 can be used to determine a logical high or a logical low of the bit stream. The selector 708 is further configured to receive a bit elapsed signal 713 from the first BTL 703 and a bit elapsed signal 714 from the second BTL 704. The bit elapsed signals can be configured to signal the bit time elapsed since the last rising or falling edge or an integer multiple thereof.

[0109] The first block 703 and the second block 704 are configured to receive a clock signal from the oscillator 702, and wherein the predetermined bit time for determining when to provide a bit pass signal is defined by the number of cycles of the oscillator.

[0110] Thus, in this and other examples, signal transitions in the bit stream are monitored by the BTLs 703, 704 comprising independent hardware blocks. The BTLs are synchronized with the detected edges. One BTL is synchronized with falling edges and the other BTL is synchronized with rising edges. Whenever the BTLs 703, 704 find a time skew between, for example, two falling edges or two rising edges (it will be appreciated that each similar edge can only occur after a nominal bit time or an integer multiple of the nominal bit time, regardless of asymmetries in the bit stream), this is seen as an oscillator tolerance problem and the BTLs are resynchronized. Thereby, the accuracy of the device is doubled and budget can be used for higher clock tolerance in the protocol or less padding bits.

[0111] In the case that an edge is detected by one BTL 703, 704 (and confirmed as a valid edge by the optional multiple samples with the same level), this transition is determined to be a received bit and is seen as a valid protocol bit. From now on, the other BTL 703, 704 takes over and looks for a transition back to the other bit level. In the absence of a transition back to the other level within a reasonable time (in practice measured in the nominal expected bit length), a second bit with the same level is found in a row and the device sees this as another valid bit level. This process continues until the next edge is found.

[0112] By the mechanism, any asymmetry in the duty cycle can be decoded back to the original NRZ bit stream as long as edges can still be detected. This improves the allowable signal degradation on the path from the transmitting node to the receiving node, resulting in a much higher robustness overall for the tolerances in the system.

[0113] Accordingly, an asymmetric bit stream can be received at input 701. At the next edge in the bit stream, either the first BTL 703 will detect a rising edge or the second BTL 704 will detect a falling edge. Upon experiencing any additional sampling to remove noise, detection of a rising edge by the first BTL 703 will provide edge detection signaling 711 to the BTL selector 708 indicating that a logical high was received. Likewise, and upon experiencing any additional sampling to remove noise, detection of a falling edge by the second BTL 704 will provide edge detection signaling 712 to the BTL selector 708 indicating that a logical low was received. Either or both of the BTLs 703, 704 will also provide bit passage signaling 713, 714 to the selector 708 based on the timing signal from the oscillator 702 and synchronization information stored by the BTLs for converting the number of oscillations of the oscillator to bit time whenever an integer multiple of the nominal bit time has passed.

[0114] Additionally, each of the first BTL 703 and the second BTL 704 determines the time difference between successive rising edges with respect to the first BTL 703 and successive falling edges with respect to the second BTL 704. It will be appreciated that, assuming any asymmetry in the network will likely affect successive rising edges or successive falling edges in the same way, the time difference should be a multiple of the bit time defined by the protocol. If the first BTL 703 and the second BTL 704 determine that the time difference between successive rising edges or the time difference between successive falling edges is not an integer multiple of the bit time, it is determined that the local oscillator 702 has drifted, or at least operates with different timing than the local oscillators of the transmitting nodes 100, 201, 202, 203 of the network. Accordingly, the first BTL 703 and / or the second BTL 704 can determine a synchronization or correction to be applied so that the bit time determined using the local oscillator 702 matches the bit time of the incoming bit stream. For example, the BTLs can be configured to determine the bit time based on a predetermined number of oscillations of the oscillator. If it is determined that the bit time is slower than the transmitting node, the predetermined number of oscillations can be decreased. Alternatively, if it is determined that the bit time determined by the BTLs is faster than the transmitting node, the predetermined number of oscillations can be increased. In this way, the selector 708 receives signaling indicating the presence of a logical high or a logical low in the bit stream based on the edges detected by the respective first BTL 703 and second BTL 704 and the bit passage signaling indicating the bit time, which uses the time difference between rising edges and the time difference between falling edges to maintain synchronization with the transmitting node.

[0115] Accordingly, the selector 708 can be configured to reconstruct the NRZ bit stream without the asymmetry. Accordingly, the selector 708 can be configured to provide the resulting level comprising a logical high or a logical low at output 709 and to provide a next bit trigger signal at output 710, which provides information about the elapsed bit time. Accordingly, for the case that there are multiple bits with the same level in a row, the signal at output 709 does not change and the information that another bit with the same level is now received is provided by the signal at 710. Accordingly, output 710 can be configured to output a pulse, for example, whenever a bit time has been determined to be elapsed by the BTLs 703, 704; i.e. the first BTL 703 if the BTL is active or the second BTL 704 if the BTL is actively searching for an edge. Accordingly, in one or more examples, once one BTL detects an edge, the other BTL can become active to look for the next edge. The "active" state of the BTLs can be provided by exchanging the signaling at 707. Accordingly, the signal at 710 "triggers" a found bit with a pulse, for example, while the signal at output 709 provides information about whether the found bit is a logical 1 or a logical 0.

[0116] It should be appreciated that other example embodiments can be provided. For example, the first and second BTLs can be logical blocks of a signal processing element rather than separate hardware blocks.

[0117] For overview, in the proposed CAN XL specification, it is disclosed to split the BTL (see Figure 6 : 601) into two independent engines (see Figure 7 : 703, 704), each providing the next bit level based on its detected edge. It is proposed to use two BTL blocks 703, 704 configured to search for bit transitions. Thereby, the bit stream can be reconstructed even at asymmetries higher than 50%.

[0118] Further, the device 700 can provide information that a full nominal bit time has elapsed from the detected edges of the engines. After detecting an edge, a post-processing takes the information from the two BTL blocks 703, 704 and produces the respective bit pattern at outputs 709, 710. It should be appreciated that the output 709 as well as the trigger signal at output 710 are time-aligned with both rising and falling edges determined by the first and second BTLs. This selector 708 can comprise a multiplexer that selects the output of the respective BLT based on the detected edge and triggers the next bit based on the elapsed bit time, which is based on the bit elapsed signals from each respective first BTL 703 and second BTL 704.

[0119] It should be noted that the received bitstream does not provide the nominal bit length, and does not need to do so. The device 700 is able to implement a reconstruction of the correct bit order.

[0120] Depending on the time between the two similar edges determined by the first BTL block 703 and the second BTL block 704, it can be found whether there are multiple bits in a row with the same bit level, since a similar edge can only occur after a full bit period. If there are more full bit periods without a level change, a simple counter can be used to limit the number of found bits with similar levels. The bit pass signal between BTL 703 and BTL 704 and the selector 708 can provide this information.

[0121] By this method, the degree of asymmetry that can be tolerated can be as much as the degree of detection of the remaining level changes at the over-sampling rate.

[0122] Figure 8 A first asymmetric bitstream 801 is shown, which can be referred to as "worst case single ended RXD". At time 802, the second block 704 detects a falling edge and thus provides an edge detection signal of said falling edge at 803. The nominal bit length time or "length" 804 is determined based on the time between said "first" falling edge and the consecutive "second" falling edge shown at 805.

[0123] At time 806, the first block 703 detects a rising edge and thus provides an edge detection signal of said rising edge at 807. The nominal bit length 808 is determined between said "first" rising edge 806 and the consecutive "second" rising edge not visible in the figure. Figure 8

[0124] As mentioned above, the nominal bit length comprises an integer multiple of the time difference between 802 and 805 (i.e. 2 x nominal bit length). The calculated nominal bit time or length can then be used to calibrate the device 700, such that the predetermined bit time determined from the oscillator signal 702 corresponds to the calculated nominal bit length.

[0125] Trace 812 can be referred to as "falling edge synchronized BTL passing "level 1 bit", which shows the action of one of the BTLs 703, 704. Trace 813 can be referred to as "rising edge synchronized BTL passing "level 0 bit", which shows the action of the other one of the BTLs 703, 704. Trace 814 can be referred to as "correct received bitstream".

[0126] The bit pass signal 713 is shown in trace 810, and the bit pass signal 714 is shown in trace 811.

[0127] Figure 9 ​A second asymmetric bit stream 901 is shown. At time 902, the second block 704 detects a falling edge and thus provides an edge detection signal at 903 of the falling edge. A nominal bit time or "length" 904 is determined between the "first" falling edge 902 and the successive "second" falling edge shown at 905.

[0128] At time 906, the first block 703 detects a rising edge and thus provides an edge detection signal at 907 of the rising edge. A nominal bit time or length 908 is determined between the "first" rising edge 906 and the immediately successive "second" rising edge not visible in the figure. Figure 9

[0129] The bit pass signal 713 is shown in trace 910 and the bit pass signal 714 is shown in trace 911.

[0130] As mentioned above, the nominal bit length includes an integer multiple of the time difference between 902 and 905 (i.e., 2 x nominal bit length). The calculated nominal bit length can then be used to calibrate the device 700 so that a predetermined bit time determined from the oscillator signal 702 corresponds to the calculated nominal bit time or length.

[0131] Trace 912 can be referred to as "falling edge synchronized BTL passing "level 1 bit" which shows the action of one of the BTLs 703, 704. Trace 913 can be referred to as "rising edge synchronized BTL passing "level 0 bit" which shows the action of the other of the BTLs 703, 704. Trace 914 can be referred to as "correctly received bit stream".

[0132] Figure 10 An example method of generating a bit stream from a received, e.g., asymmetric bit stream in a CAN controller is shown. The method includes determining a logical low state of the bit stream based on detecting a falling edge 1001. The method includes determining a logical high state based on detecting a rising edge 1002. The method includes determining 1003 the time between successive rising edges and determining the time between successive falling edges to determine a nominal bit length of the received bit stream 1003, the determined nominal bit length used to update a predetermined bit time, e.g., stored in each BTL by the device 700. The predetermined bit time can be used to determine when there are successive logical highs in the bit stream or when there are successive logical lows in the bit stream. The predetermined bit time can be used to provide timing to the bits in a transmission mode.

[0133] Unless a specific order is required, the instructions and / or flowchart steps in the above figures can be performed in any order. Moreover, one skilled in the art will appreciate that the material in the present specification gives guidance regarding the exercises of the examples only and is not a limitation on the scope of the examples. A skilled artisan will further appreciate that modifications can be made to the material within the scope of the appended claims and the material of the examples described in this specification are for illustrative purposes only. Therefore, the scope of the examples is limited only by the following claims.​

[0134] It should be appreciated that the terms logic high and logic low are generally used to refer to different logic states represented by rising and falling edges of a bit stream, however, the logic states represented by the edges can be arbitrarily assigned. Thus, more generally, the terms first logic state and second logic state can be used.

[0135] In some example embodiments, the instruction sets / method steps described above are implemented as functional and software instructions embodied in an executable instruction set that is implemented on a computer or machine programmed and controlled with the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor can refer to a single component or multiple components.

[0136] In other examples, the instruction sets / methods shown herein, and the data and instructions associated therewith, are stored in respective storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are deemed to be part of an article (or article of manufacture). An article or article of manufacture can refer to one or more single components or multiple components. The non-transitory machine- or computer-readable media as defined herein excludes signals, but such media can receive and transmit information as a signal.

[0137] Example embodiments of the material discussed in this specification can be implemented in whole or in part via a network, cloud, computer or data-based device and / or service. These can include a cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, infrastructure, or other enabling devices and services. As can be used herein and in the claims, the following non-exclusive definitions are provided.

[0138] In one example, one or more of the instructions or steps discussed herein are automated. The term automated or automatically (and like variations thereof) means that the operation of the device, system, and / or process is controlled by a computer and / or mechanical / electrical devices without the need for human intervention, observation, effort, and / or decision making.

[0139] It should be appreciated that any components said to be coupled can be directly or indirectly coupled or connected. In the case of indirect coupling, additional components can be disposed between the two components said to be coupled.

[0140] In this specification, example embodiments have been presented in collections of selected details. However, a person of ordinary skill in the art will appreciate that many other example embodiments can be practiced that include different selected collections of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A CAN bit stream sampling device for a controller area network (CAN) controller, characterized by The device is configured to: receive a bit stream from a CAN transceiver; detect a rising edge in the bit stream; separately detect a falling edge in the bit stream; and generate a recovered non-return-to-zero encoded bit stream based at least on the detected falling edge and the detected rising edge; wherein generating a recovered non-return-to-zero encoded bit stream based at least on the detected falling edge and the detected rising edge comprises: in response to detecting a first rising edge in the bit stream, generating a first logic state bit in the recovered non-return-to-zero encoded bit stream; in response to detecting a first falling edge in the bit stream, generating a second logic state bit in the recovered non-return-to-zero encoded bit stream; after the detection of the rising edge and after generating the first logic bit in the recovered non-return-to-zero encoded bit stream, generating another first logic state bit in the recovered non-return-to-zero encoded bit stream based on a predetermined bit time elapsing; and after the detection of the falling edge and after generating the second logic state bit in the recovered non-return-to-zero encoded bit stream, generating another second logic bit in the recovered non-return-to-zero encoded bit stream based on the predetermined bit time elapsing.

2. The CAN bitstream sampling device of claim 1, wherein, comprises: a first block configured to provide the detection of the rising edge in the bit stream; a second block configured to provide the detection of the falling edge in the bit stream; and a selector block configured to generate the recovered non-return-to-zero encoded bit stream based on the detection of the rising and falling edges in the bit stream by the first and second blocks; wherein the detection of a rising edge by the first block causes the generation of a first logic state bit and another first logic state bit in the recovered non-return-to-zero encoded bit stream, and the detection of a falling edge by the second block causes the generation of a second logic state bit and another second logic state bit in the recovered non-return-to-zero encoded bit stream.

3. The CAN bitstream sampling device of claim 2, wherein, the first block is configured to provide an edge detection signal to the selector block upon detection of a rising edge to instruct the selector block to generate the first logic state bit in the recovered non-return-to-zero encoded bit stream, and the first block is configured to provide a bit elapsed signal after each predetermined bit time to enable the selector block to generate one or more subsequent first logic state bits in the recovered non-return-to-zero encoded bit stream; and wherein the second block is configured to provide an edge detection signal to the selector block upon detection of a falling edge to instruct the selector block to generate the second logic state bit in the recovered non-return-to-zero encoded bit stream, and the second block is configured to provide a bit elapsed signal after each predetermined bit time to enable the selector block to generate one or more subsequent second logic state bits in the recovered non-return-to-zero encoded bit stream.

4. The CAN bitstream sampling device of claim 2, wherein, the first block and the second block are configured to determine a nominal bit time of the bit stream, the nominal bit time comprising a time at which a bit is transmitted by a transmitting node transmitting the bit stream, wherein the first block is configured to determine the nominal bit time based on a determined first block time between rising edges of the bit stream, and the second block is configured to determine the nominal bit time based on a determined second block time between falling edges of the bit stream, wherein the first block time and the second block time indicate integer multiples of the nominal bit time of the bit stream; and the first block and / or the second block are configured to modify the predetermined bit time based on the determined nominal bit time.

5. The CAN bitstream sampling device of claim 4, wherein, the first block time comprises a time between consecutive rising edges.

6. The CAN bitstream sampling device of claim 4, wherein, the second block time comprises a time between consecutive falling edges.

7. A CAN controller, characterized by a CAN bit stream sampling device according to any of the preceding claims.

8. A CAN network comprising a plurality of nodes, characterized in that at least one of the nodes comprises a CAN controller according to claim 7.

9. A method of sampling a bit stream in a CAN controller, characterized by, the method comprises receiving a bit stream from a CAN transceiver; detecting a rising edge in the bit stream; separately detecting a falling edge in the bit stream; and generating a recovered non-return-to-zero coded bit stream based on at least the detected falling edge and the detected rising edge; wherein generating a recovered non-return-to-zero coded bit stream based on at least the detected falling edge and the detected rising edge comprises: in response to detecting a first rising edge in the bit stream, generating a first logic state bit in the recovered non-return-to-zero coded bit stream; in response to detecting a first falling edge in the bit stream, generating a second logic state bit in the recovered non-return-to-zero coded bit stream; after the detection of the rising edge and after generating the first logic bit before detection of a subsequent edge, generating another first logic state bit in the recovered non-return-to-zero coded bit stream based on a predetermined bit time elapsing; and after the detection of the falling edge and after generating the second logic bit before detection of a subsequent edge, generating another second logic bit in the recovered non-return-to-zero coded bit stream based on the predetermined bit time elapsing.

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