Memory module and method of operating the same

Abstract

A memory module includes: a first memory device; a second memory device; and a processing buffer circuit connected to the first memory device and the second memory device (independent of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host according to the DDR SDRAM standard.

Description

[0001] Priority claim

[0002] This application claims priority to Korean Patent Application No. 10-2020-0070658, filed on Jun. 11, 2020, the disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] Embodiments of the inventive concepts described herein relate to a memory module and an operating method thereof, and more particularly, to a memory module capable of performing an offloaded operation through a standard memory interface and an operating method thereof. Background Art

[0004] The memory device may store data input from an external host. In addition, the memory device may output the data stored therein in response to a request from the external host. A substrate on which one or more memory devices and one or more components associated with the memory device are mounted may be referred to as a "memory module". A memory module including a processor capable of processing data may perform operations on data stored in the memory module based on commands received from a host. In other words, the memory module may have a near data processing (NDP) structure. Summary of the invention

[0005] Embodiments of the inventive concept provide a memory module and an operating method thereof, the memory module including a processor that supports operations offloaded using a standard DDR memory interface and that can access data in the memory module without intervention of a host.

[0006] According to an exemplary embodiment, a memory module may include a first memory device, a second memory device, and a processing buffer circuit. The processing buffer circuit is connected to the first memory device and the second memory device (independent of each other) and is connected to a host. The processing buffer circuit may include: a processing circuit, which processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host; and a buffer, which stores data processed by the processing circuit. The processing buffer circuit can communicate with the host according to the DDR SDRAM standard.

[0007] According to an exemplary embodiment, an operation method for a memory module can be provided, the memory module includes a normal memory channel and a processing memory channel, and each of the normal memory channel and the processing memory channel shares a router of a processing buffer circuit, and includes a memory cell array. The method may include: setting the operation mode of the router to one of an extended mode or a mirror mode based on a mode register setting command received from a host. In addition, based on an address and command received from the host and the set operation mode of the router (i.e., extended mode or mirror mode), access data stored in the normal memory channel and the processing memory channel. Then, at a processing circuit included in the processing buffer circuit, the accessed data is processed based on a processing command received from the host. The mode register setting command, the address, the command, and the processing command can be transmitted from the host to the memory module according to the DDR SDRAM standard.

[0008] According to another exemplary embodiment, a memory module may include: a processing buffer chip; and one or more DRAM chips storing data. One or more DRAM chips may form a normal memory channel and a processing memory channel. The processing buffer chip may include: a physical layer that receives a command / address signal and a data signal from a host; and a first memory controller and a second memory controller that access the normal memory channel and the processing memory channel, respectively, based on the command / address signal. A processing circuit is also provided, and the processing circuit processes at least a portion of the data stored in the normal memory channel accessed by the first memory controller and the data stored in the processing memory channel accessed by the second memory controller based on the processing command included in the data signal. In addition, a buffer is also provided, and the buffer stores data processed by the processing circuit, and a router is provided, and the router receives the command / address signal and the data signal from the physical layer, and transmits the command / address signal and the data signal to the first memory controller and the buffer. The processing buffer circuit communicates with the host according to the DDR SDRAM standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present inventive concept will become apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0010] Figure 1 A memory system according to an embodiment of the inventive concept is shown.

[0011] Figure 2 Shown in detail Figure 1 Block diagram of the memory module.

[0012] Figure 3 It is shown Figure 1A flowchart of a method of operating a memory system.

[0013] Figure 4A Shows when Figure 2 When the router is in mirror mode Figure 1 The memory map of the memory controller.

[0014] Figure 4B Shows when Figure 2 When the router is in extension mode Figure 1 The memory map of the memory controller.

[0015] Figure 5 It shows that Figure 2 When the operation mode of the router is determined to be mirror mode Figure 1 A flowchart of a method of operating a memory system.

[0016] Figure 6 It shows that Figure 2 When the operation mode of the router is determined to be the extended mode Figure 1 A flowchart of a method of operating a memory system.

[0017] Figure 7 The embodiment according to the present invention is shown Figure 1 A flowchart of a method for operating a memory module.

[0018] Fig. 8A Shows that following Figure 7 The flowchart stores data Figure 2 a cell of a first memory device.

[0019] Figure 8B Shows that following Figure 7 The flowchart stores the data Figure 2 unit of a third memory device.

[0020] Fig.9A It shows that Figure 2 A flow chart of a portion of an operation method of a memory module when an operation mode of a router is determined to be a mirroring mode.

[0021] Fig. 9B It shows that Figure 2 A flow chart of a portion of an operation method of a memory module when an operation mode of a router is determined to be a mirroring mode.

[0022] Fig.10 It is shown Figure 1 A flowchart of a method for operating a memory module.

[0023] Fig.11 A block diagram of a memory module according to an embodiment of the inventive concept is shown.

[0024] Fig.12 It is shown that Fig.11 A flowchart of a method for operating a memory system of a memory module. DETAILED DESCRIPTION

[0025] Embodiments of the inventive concept are described in detail and clearly below to the extent that it is easy for a person of ordinary skill in the art to implement the inventive concept. Hereinafter, the best embodiment of the inventive concept will be described in detail with reference to the accompanying drawings. For the description of the inventive concept, similar components will be marked by similar reference numerals in the accompanying drawings to facilitate overall understanding, and thus additional descriptions will be omitted to avoid redundancy.

[0026] Figure 1 A memory system according to an embodiment of the inventive concept is shown. Figure 1 , the memory system 10 may include a memory module 100, a host 200, and a connection line 300. The memory module 100 may include a processing buffer circuit 110 and one or more memory devices 120. The processing buffer circuit 110 may be connected to the memory device 120. The processing buffer circuit 110 may access the storage space of the memory device 120. The processing buffer circuit 110 may process data stored in the memory device 120 or data received from the host 200 based on a request of the host 200. The operation of the processing buffer circuit 110 will be described more fully later. In an embodiment, the memory module 100 may include: a structure capable of performing near data processing (NDP). The memory module 100 may also be referred to as "processing-internal memory (PIM)" or "functional-internal memory (FIM)".

[0027] One embodiment is shown as the number of memory devices 120 being "n" (n being a positive integer greater than one). In other words, the memory module 100 may include a first memory device 121 to an nth memory device 12n. The number of memory devices 120 included in the memory module 100 is not limited by the illustrated embodiment. Each of the memory devices 120 may include: a memory cell array including a plurality of memory cells. In an embodiment, each of the first memory device 121 to the nth memory device 12n may be implemented using a dynamic random access memory (DRAM).

[0028] The host 200 may also be referred to as a “central processing unit (CPU)”. The host 200 may include a memory controller (MC) 210. The host 200 may issue or generate a signal for accessing the memory device 120. For example, the host 200 may generate data to be stored in the memory device 120, or a data signal DQ indicating an operation to be performed by the processing buffer circuit 110, a command signal CMD instructing the memory device 120 to perform a specific operation such as a read or write operation, and an address signal ADD indicating a physical address of a storage space of each of the memory devices 120. The command signal CMD and the address signal ADD may be collectively referred to as a “command / address signal CA”.

[0029] The memory controller 210 may transmit the data signal DQ, the command signal CMD, the address signal ADD, etc. generated by the host 200 to the memory module 100 through the connection line 300. The memory controller 210 may include an address mapping table (not shown). The address mapping table of the memory controller 210 may map the virtual address assigned by the host 200 to the memory module 100 and the physical address of the memory module 100. For example, the address mapping table may store the physical addresses corresponding to the first memory device 121 to the nth memory device 12n, respectively, and the virtual addresses corresponding to the physical addresses, respectively. The host 200 may generate the address signal ADD based on the address stored in the address mapping table of the memory controller 210.

[0030] The memory module 100 may communicate with the memory controller 210 of the host 200 through the connection line 300. For example, the memory controller 210 may transmit the data signal DQ, the command signal CMD, and the address signal ADD generated by the host 200 to the memory module 100 through the connection line 300. The connection line 300 may be implemented in accordance with the double data rate (DDR) standard. For example, the connection line 300 may meet the DDR synchronous DRAM (SDRAM) standard defined by JEDEC (Joint Electron Device Engineering Council).

[0031] In an embodiment, the processing buffer circuit 110 of the memory module 100 may execute: a processing command (eg, Figure 2 Therefore, the host 200 can offload the operation to be performed to the processing buffer circuit 110 of the memory module 100 through the connection line 300 that meets the DDR SDRAM standard. According to the above description, the memory module 100 can receive a request associated with performing an operation from the host 200 without a separate hardware change.

[0032] Figure 2 Shown in detail Figure 1 A block diagram of the memory module. Figure 1 and Figure 2 , the memory module 100 may include a processing buffer circuit 110 and first to fourth memory devices 121 to 124. Some components belonging to the memory module 100 may be included in a normal channel (or normal memory channel) C1, and other components may be included in a processing memory channel C2. Other components included in the memory module 100 may be included in an interface unit IF. The components of the normal memory channel C1, the processing memory channel C2, and the interface unit IF will be described more fully below in this document.

[0033] In an embodiment, at least one of the first to fourth memory devices 121 to 124 may be classified as (or assigned to) a normal memory channel C1, and the other memory devices may be classified as (or assigned to) a processing memory channel C2. An embodiment is shown as including the first memory device 121 and the second memory device 122 in the normal memory channel C1, and including the third memory device 123 and the fourth memory device 124 in the processing memory channel C2. However, the manner of classifying the first to fourth memory devices 121 to 124 is not limited thereto. For example, the first to fourth memory devices 121 to 124 may be classified by the mode register 113. The operation of the mode register 113 will be described more fully below in this document.

[0034] In an embodiment, each of the normal memory channel C1 and the processing memory channel C2 may include a memory cell array, and the normal memory channel C1 and the processing memory channel C2 may share some components (e.g., an interface unit IF) of the processing buffer circuit 110. In another embodiment, each of the normal memory channel C1 and the processing memory channel C2 may include: at least one or more memory devices and at least some components of the processing buffer circuit 110. For example, the processing memory channel C2 may include: a mode register 113, a buffer 114, a processing circuit 115, a main physical layer 116p, and a memory device 120p classified as the processing memory channel C2. As another example, the normal memory channel C1 may include: a main physical layer 116n and a memory device 120n classified as the normal memory channel C1. The memory devices 120n and 120p may be respectively disposed at the ends of the normal memory channel C1 and the processing memory channel C2.

[0035] The processing buffer circuit 110 may include: a slave physical layer 111, a router 112, a mode register 113, a buffer 114, and one or more master physical layers 116n and 116p. The master physical layers 116n and 116p may also be referred to as "memory controllers". The interface unit IF of the processing buffer circuit 110 may include: a slave physical layer 111 and a router 112.

[0036] The slave physical layer 111 may be connected to the memory controller 210 of the host 200 through the connection line 300. The slave physical layer 111 may receive a data signal DQ, a command signal CMD, and an address signal ADD from the memory controller 210 of the host 200. The slave physical layer 111 may remove signal noise included in the data signal DQ, the command signal CMD, and the address signal ADD thus received. For example, the slave physical layer 111 may perform retiming or sampling on the data signal DQ, the command signal CMD, and the address signal ADD thus received. The slave physical layer 111 may transmit noise-free signals to the router 112 and the mode register 113.

[0037] The router 112 may allow the host 200 to access the memory device 120n classified as the normal memory channel C1 and the memory device 120p classified as the processing memory channel C2 based on the address signal ADD whose noise is removed from the physical layer 111. For example, the router 112 may provide the host 200 with the storage space of the memory devices 120n and 120p and the storage space of the buffer 114 as access targets. The router 112 may determine whether to perform a normal operation such as a data read / write operation or whether to perform a separate operation (or data processing) using the processing circuit 115 for data stored in one of the memory devices 120.

[0038] In an embodiment, router 112 may operate in one of an extended mode or a mirror mode. The operating modes of router 112 are described more fully below.

[0039] The mode register 113 may store information related to the operating condition of the memory module 100 according to a request of the host 200. The host 200 may set the operating mode of the memory module 100 by issuing a command signal CMD including a mode register setting command MRS for setting the operation of the mode register 113. The mode register setting command MRS may be transmitted from the physical layer 111 to the mode register 113 in the form of a digital signal.

[0040] In an embodiment, the mode register 113 may further include a register circuit for storing information about a normal command (e.g., a burst length setting command) for controlling a memory module including a DRAM, and a register circuit for storing information about an operation mode of the processing circuit 115. In this case, the mode register setting command MRS may further include: a command for setting an operation mode of the router 112, a command for setting an operation mode of the processing circuit 115, or a command for permitting all or part of the operations of the processing circuit 115, etc.

[0041] The processing circuit 115 may read the operation signal OP stored in the mode register 113 through the mode register setting command MRS. The operation signal OP may be a signal associated with a command for setting the operation mode of the processing circuit 115. In an embodiment, the processing circuit 115 may activate or deactivate the entire processing circuit 115 or a portion of the processing circuit 115 in response to information stored in the mode register 113 through the mode register setting command MRS. The operation of the processing circuit 115 will be described more fully later.

[0042] The router 112 may operate in one of an extended mode or a mirror mode based on information stored in the mode register 113 through a mode register setting command MRS. For ease of explanation, an embodiment is shown as omitting the connection line between the router 112 and the mode register 113. In an embodiment, the router 112 may reconfigure (or change): the settings (or configurations) of the memory devices 120n and 120p that can be accessed by the host 200 according to the information stored in the mode register 113 through the mode register setting command MRS. For example, the router 112 may classify at least one of the first memory device 121 to the fourth memory device 124 as a normal memory channel C1 in response to the information stored in the mode register 113, and classify the remaining memory devices as a processing memory channel C2. According to the above description, the host 200 may change the configuration of the normal memory channel C1 and the processing memory channel C2 by issuing a mode register setting command MRS.

[0043] The buffer 114 may store information about operations to be performed by the processing circuit 115, data MDN stored in the memory device 120n classified as the normal memory channel C1, and data PMD processed by the processing circuit 115. For example, the buffer 114 may receive a processing command CMDP and data MDN from the router 112. And, in response, the buffer 114 may provide the processing circuit 115 with the processing command CMDP and data MDN thus received. In an embodiment, the processing command CMDP included in the data signal DQ may be transmitted from the host 200 to the memory module 100. This processing command CMDP may be included in a burst of the data signal DQ in the form of a sequence of packets following a given format.

[0044] For example, the processing command CMDP may include: an operation code (OP code) indicating the type of operation to be performed by the processing circuit 115; a code src indicating the address of a source; a destination code dest (or dst) indicating the address of a destination; etc. According to the above description, the host 200 can offload the operation to be performed by the processing circuit 115 to the processing circuit 115 by requesting an operation to write the processing command CMDP into the buffer 114 (or issuing a command signal CMD including a write command), without additionally transmitting a separate command signal to the memory module 100.

[0045] The processing circuit 115 may process at least one of the data received from the host 200 or the data stored in the memory devices 120n and 120p based on the processing command CMDP stored in the buffer 114. The processing circuit 115 may also be referred to as a “processor.” In some embodiments, the processing circuit 115 may include a decoder circuit DEC, a communication circuit CC, and a logic circuit LC.

[0046] The decoder circuit DEC may decode the processing command CMDP received from the host 200. The communication circuit CC may perform data (or signal) communication. For example, the communication circuit CC may receive data stored in the buffer 114 from the buffer 114. The communication circuit CC may receive data MDP stored in the memory device 120p. The communication circuit CC may transmit data PMD processed by the processing circuit 115 to the buffer 114 or the main physical layer 116p. The communication circuit CC may transmit data MDP received from the memory device 120p to the buffer 114.

[0047] The logic circuit LC may perform an operation based on the processing command CMDP. For example, the logic circuit LC may include a logic circuit such as a multiply-accumulate operation (MAC) unit, a rectified linear unit (ReLu), or an arithmetic logic unit (ALU). The logic circuit LC may perform an operation requested by the host 200 based on the result of decoding the processing command CMDP.

[0048] In an embodiment, the processing circuit 115 may access data MDN stored in the memory device 120n classified as the normal memory channel C1. For example, the router 112 may provide the processing circuit 115 with data MDN stored in the memory device 120n classified as the normal memory channel C1 based on the command signal CMD and the address signal ADD received from the host 200. Therefore, without any additional data processing by the host 200, the processing circuit 115 may perform operations on the data stored in the memory device 120n classified as the normal memory channel C1 and the data stored in the memory device 120p classified as the processing memory channel C2.

[0049] In another embodiment, the processing circuit 115 may erase the memory device 120. For example, the processing circuit 115 may erase the memory device 120 in response to the erase request 200 received from the host in a state included in the processing command CMDP. As another example, the processing circuit 115 may periodically erase the memory device 120. In this case, the cycle at which the processing circuit 115 erases the memory device 120 may be predetermined when the memory module 100 is manufactured or may be determined by the host 200.

[0050] The processing circuit 115 may transfer the data PMD processed by the logic circuit LC to the buffer 114. The host 200 may access the data PMD processed by the processing circuit 115 by transferring a read request for the processed data PMD stored in the buffer 114 to the memory module 100. The processed data PMD stored in the buffer 114 may be transferred to the router 112 in response to the read request of the host 200. The router 112 may provide the storage space of the buffer 114 as an access target for the host 200.

[0051] The master physical layers 116n and 116p may be connected to the memory devices 120n and 120p, respectively. The master physical layers 116n and 116p may receive data signals DQ, command signals CMD, and address signals ADD from the router 112 through the processing circuit 115 based on the operation mode of the router 112. The master physical layers 116n and 116p may transmit at least a portion of the digital signals used by the various components of the processing buffer circuit 110 to the memory devices 120n and 120p, respectively.

[0052] The main physical layers 116n and 116p may receive signals associated with data stored in the memory devices 120n and 120p, respectively, from the memory devices 120n and 120p. The main physical layers 116n and 116p may receive noise associated with the received signals. The main physical layers 116n and 116p may transmit noise-free signals to at least a portion of the components of the processing buffer circuit 110. Therefore, the host 200 and the processing circuit 115 may access the storage spaces of the memory devices 120n and 120p disposed at the ends of the normal memory channel C1 and the processing memory channel C2, respectively, through the main physical layers 116n and 116p.

[0053] Figure 3 It is shown Figure 1 Flow chart of a method of operating a memory system. Figures 1 to 3 , the host 200 of the memory system 10 may perform operations S100 and S300, and the memory module 100 of the memory system 10 may perform operations S200 and S400. In operation S100, the host 200 may transmit a mode register setting command MRS for setting the mode register 113 to the memory module 100. In an embodiment, operation S100 may be performed in an initialization operation after the host 200 is powered on.

[0054] In operation S200, the memory module 100 may set the operation modes of the processing circuit 115 and the router 112 of the processing buffer circuit 110. For example, the memory module 100 may store the mode register setting command MRS in the mode register 113. The processing circuit 115 may read the operation signal OP, which is stored in the mode register 113 by the mode register setting command MRS and is used to activate or deactivate a part of the processing circuit 115. The router 112 may operate in the extended mode or the mirror mode based on the activity state of the processing circuit 115 and the request of the host 200.

[0055] In operation S300, the host 200 may transmit a data signal DQ, a command signal CMD, and an address signal ADD to the memory module 100. In operation S400, the memory module 100 may operate the memory device 120. For example, the memory module 100 may access the memory device 120 based on the operation modes of the processing circuit 115 and the router 112 set in operation S200 and a request of the host 200. The memory module 100 may perform an operation requested by the host 200 on at least a portion of the memory device 120 based on the data signal DQ, the command signal CMD, and the address signal ADD received from the host 200.

[0056] Figure 4A Shows when Figure 2 When the router is in mirror mode Figure 1 The memory map of the memory controller. Figure 4B Shows when Figure 2 When the router is in extension mode Figure 1 In other words, Figure 4A and Figure 4B 1 and 2 show memory maps of the memory device 120 in the mirror mode and the extended mode as viewed from the host 200, respectively. Figures 1 to 3 To describe Figure 4A and Figure 4B .

[0057] When the router 112 operates in the mirroring mode, the router 112 can provide the host 200 with: the storage space of the memory device 120n classified as the normal memory channel C1 and the storage space of the buffer 114 as access targets. Therefore, the memory map stored in the memory controller 210 may include: the area 401a of the storage space for the buffer 114 and the area 402a of the storage space for the memory device 120n classified as the normal memory channel C1, as shown in FIG. Figure 4A Refer to Figure 5 and Figure 7 The operation of memory system 10 when router 112 operates in mirroring mode is described more fully.

[0058] When the router 112 operates in the extended mode, the router 112 can provide the host 200 with: the storage space of at least a portion (e.g., 123) of the memory device 120p classified as processing the memory channel C2 and the storage space of the buffer 114 as access targets, and the storage space of the memory device 120n classified as the normal memory channel C1. Therefore, the memory map stored in the memory controller 210 may include: the area 401b for the storage space of the buffer 114, the area 402b for the storage space of the memory device 120n classified as the normal memory channel C1, and the area 403b for the storage space of the memory device 120p classified as processing the memory channel C2, as shown in FIG. Figure 4B Refer to Figure 6 The operation of memory system 10 when router 112 operates in the expansion mode is described more fully.

[0059] Figure 5 It shows that Figure 2 When the operation mode of the router is determined to be mirror mode Figure 1 Flow chart of a method of operating a memory system. Figures 1 to 3 as well as Figure 6, the host 200 may perform operations S100a and S310a, and the memory module 100 may perform operations S200a, S320a, S411a, S412a, S420a, and S430a. In the mirroring mode, the same data as the data stored in the storage space of the memory device 120n classified as the normal memory channel C1 may be stored in the storage space of the memory device 120p classified as the processing memory channel C2. The data corresponding to the data stored in the memory device 120n classified as the normal memory channel C1 and stored in the memory device 120p classified as the processing memory channel C2 may also be referred to as "mirrored data".

[0060] In operation S100a, the host 200 may transmit a mode register setting command MRS directing the router 112 to operate in the mirror mode to the memory module 100. For example, the mode register setting command MRS may include a command that allows the router 112 to operate in the mirror mode and allows the memory device 120 to be classified as one of the normal memory channel C1 or the process memory channel C2.

[0061] In operation S200a, the memory module 100 may set the operation modes of the processing circuit 115 and the router 112 of the processing buffer circuit 110. The router 112 may operate in the mirror mode in response to the mode register setting command MRS. In other words, the router 112 may provide only the storage space of the memory device 120n classified as the normal memory channel C1 and the storage space of the buffer 114 as access targets for the host 200.

[0062] In operation S310a, the host 200 may generate a first data signal DQ1, a write command signal CMDW, and an address signal ADD, and may transmit the first data signal DQ1, the write command signal CMDW, and the address signal ADD to the memory module 100. For example, the write command signal CMDW may include a command directing writing of data included in the first data signal DQ1 to at least a portion of the memory device 120. In operation S320a, the memory module 100 may be configured to pass access by the host 200 to data stored in the memory device 120n classified as the normal memory channel C1 to the processing memory channel C2.

[0063] In an embodiment, the router 112 may receive a request for accessing a storage space of a memory device 120n classified as a normal memory channel C1 from the host 200. In this case, the router 112 may transmit the received request of the host 200 (e.g., the first data signal DQ1, the write command signal CMDW, and the address signal ADD) to the processing memory channel C2. The processing memory channel C2 may write the first data signal DQ1, the write command signal CMDW, and the address signal ADD into the buffer 114.

[0064] In operation S411a, the normal memory channel C1 may perform a write operation based on the first data signal DQ1, the write command signal CMDW, and the address signal ADD thus received. For example, data based on the first data signal DQ1 may be written into a storage space of the memory device 120n corresponding to the address signal ADD.

[0065] In operation S412, the processing memory channel C2 may perform a write operation based on the first data signal DQ1, the write command signal CMDW, and the address signal ADD thus received. For example, data based on the first data signal DQ1 may be written into a storage space of the memory device 120p corresponding to the address signal ADD. Therefore, data requested from the host 200 to be written may be stored in each of the normal memory channel C1 and the processing memory channel C2.

[0066] In operation S420a, the memory module 100 may perform an operation on the mirror data based on the processing command CMDP. For example, the processing circuit 115 may read, write, or process the mirror data stored in the memory device 120p based on the result of decoding the processing command CMDP of the write buffer 114. In addition, even if the host 200 accesses the storage space of the memory device 120n classified as the normal memory channel C1, the processing circuit 115 may access the mirror data at the same time. In other words, by using the bandwidth in the memory module 100 that is independent of the host 200, the processing circuit 115 may access the same data as the data accessed by the host 200, and may perform processing on the data.

[0067] In operation S430a, the memory module 100 may write the data processed in operation 420a to the buffer 114. For example, the processing circuit 115 may transmit the processed data PMD generated as a result of processing the mirror data to the buffer 114. The buffer 114 may store the processed data PMD received from the processing circuit 115, and may provide the stored processed data PMD to the host 200 in response to a read request for the processed data PMD. Therefore, the host 200 may read the data PMD processed by the processing circuit 115 by accessing a specific storage space of the buffer 114.

[0068] Figure 6 It shows that Figure 2 When the operation mode of the router is determined to be the extended mode Figure 1 Flow chart of a method of operating a memory system. Figures 1 to 3 as well as Figure 6 , the host 200 of the memory system 10 may perform operations S100b, S311b, and S312b, and the memory module 100 of the memory system 10 may perform operations S200b, S411b, and S412b.

[0069] In operation S100b, the host 200 may transmit a mode register setting command MRS instructing the router 112 to operate in the extended mode to the memory module 100. For example, the mode register setting command MRS may include a command that allows the router 112 to operate in the extended mode, allows the memory device 120 to be classified as one of the normal memory channel C1 or the processing memory channel C2, and is used to control the operation time and activity state of the logic circuit LC of the processing circuit 115.

[0070] In operation S200b, the memory module 100 may set the operation modes of the processing circuit 115 and the router 112 of the processing buffer circuit 110. The router 112 may operate in an extended mode in response to the mode register setting command MRS. The operation of the processing circuit 115 may be determined according to the amount of storage space of the memory device 120p exposed to the host 200 through the router 112. In an embodiment, the router 112 may provide the host 200 with the entire storage space of the memory device 120p as an access target. In other words, through the router 112, the first memory device 121 to the nth memory device 12n may be exposed to the host 200 or recognized by the host 200 as an integrated high-capacity memory. In this case, the host 200 may monopolize the first memory device 121 to the nth memory device 12n, or the host 200 may share the first memory device 121 to the nth memory device 12n with the processing circuit 115.

[0071] In the case where the first memory device 121 to the nth memory device 12n are exclusively occupied by the host 200, the mode register 113 can deactivate the logic circuit LC of the processing circuit 115. For example, the power supplied to the logic circuit LC of the processing circuit 115 can be blocked by the operation signal OP readable by the processing circuit 115. Therefore, the operation performed by the processing circuit 115 on the data stored in the memory device 120 can be prohibited. However, even in this case, the path (e.g., the communication circuit CC) for data communication of the processing circuit 115 can still be activated. Therefore, the data stored in the memory device 120p can be provided to the host 200 through the path for data communication of the processing circuit 115, the buffer 114, and the router 112.

[0072] In another embodiment, in the case where the memory device 120 is shared by the host 200 and the processing circuit 115, the time interval at which the logic circuit LC of the processing circuit 115 is activated may be determined based on the mode register setting command MRS. In this case, the processing circuit 115 may perform a pre-specified (or determined or stored) calculation on the data stored in the memory device 120. For example, the host 200 may provide the processing circuit 115 with: the mode register setting command MRS, including a command permitting the logic circuit LC of the processing circuit 115 and the host 200 to access the storage space of the memory device 120 at different times. Therefore, the processing circuit 115 may access the storage space of the memory device 120 only in the time interval permitted by the host 200.

[0073] The time interval during which the processing circuit 115 can access the storage space of the memory device 120 may be determined by the host 200 when the operation mode of the router 112 is determined. Alternatively, the host 200 may control the operation of the processing circuit 115 by issuing a command signal CMD including information about the time interval during which the processing circuit 115 can access the storage space of the first memory device 121 to the nth memory device 12n.

[0074] In another embodiment, the router 112 may provide the host 200 with the entire storage space of the memory device 120n and only a portion of the storage space of the memory device 120p as an access target. In this alternative case, the remaining storage space of the memory device 120p that is not provided to the host 200 as an access target may be accessed only by the processing circuit 115. The processing circuit 115 may access the remaining storage space of the memory device 120p that is not provided to the host 200 as an access target based on the processing command CMDP. In this case, the portion of the storage space of the memory device 120 accessed by the host 200 may be exclusively occupied by the host 200 or may be shared by the processing circuit 115 and the host 200.

[0075] In the case where a portion of the storage space of the memory device 120 that can be accessed by the host 200 is exclusively occupied by the host 200, the processing circuit 115 may restrictively access the storage space exclusively occupied by the host 200. For example, when the host 200 accesses the storage space exclusively occupied by the host 200, the processing circuit 115 may not access the exclusively occupied storage space at the same time as the host 200. In other words, the processing circuit 115 may access the storage space exclusively occupied by the host 200 only in the time interval permitted by the host 200. In this case, the host 200 may permit the use of the logic circuit LC of the processing circuit 115 by writing the processing command CMDP to the request buffer 114. Therefore, in the case where the use of the logic circuit LC of the processing circuit 115 is permitted by the host 200, the processing circuit 115 may access the storage space exclusively occupied by the host 200 based on the processing command CMDP written to the buffer 114.

[0076] In the case where a portion of the storage space of the memory device 120 accessible to the host 200 is shared by the processing circuit 115 and the host 200, the processing circuit 115 may access the portion of the storage space of the memory device 120 accessible to the host 200 in a scheme similar to the scheme in the case where the entire storage space of the memory device 120 is shared. For example, the processing circuit 115 may access the portion of the storage space of the memory device 120 accessible to the host 200 at a time different from that of the host 200. In other words, the processing circuit 115 may access the shared storage space in a time interval permitted by the host 200 so that the processing circuit 115 may perform a pre-specified calculation on the data stored in the shared storage space.

[0077] In operation S311b, the host 200 may generate a second data signal DQ2, a command signal CMD, and an address signal ADD, and may transmit the second data signal DQ2, the command signal CMD, and the address signal ADD to the memory module 100. The second data signal DQ2, the command signal CMD, and the address signal ADD received from the host 200 may be provided to the memory device 120n classified as the normal memory channel C1. In addition, in operation S312b, the host 200 may generate a third data signal DQ3, and may transmit the third data signal DQ3, the command signal CMD, and the address signal ADD to the memory module 100. The third data signal DQ3, the command signal CMD, and the address signal ADD received from the host 200 may be provided to the memory device 120p classified as the processing memory channel C2. In this case, the memory device to which the third data signal DQ3, the command signal CMD, and the address signal ADD received from the host 200 are provided may be included in the memory device accessed by the host 200. In an embodiment, operation S311b and operation S312b may be performed simultaneously.

[0078] In operation S411b, the memory module 100 may perform an operation on the memory device 120n classified as the normal memory channel C1 based on the second data signal DQ2, the command signal CMD, and the address signal ADD. For example, the memory module 100 may write the data included in the second data signal DQ2 to the storage space of the memory device 120n corresponding to the address signal ADD. As another example, the memory module 100 may read the data stored in the storage space of the memory device 120n corresponding to the address signal ADD.

[0079] In operation S412b, the memory module 100 may perform an operation on the memory device 120p classified as the processing memory channel C2 based on the third data signal DQ3, the command signal CMD, and the address signal ADD. For example, the memory module 100 may write the data included in the third data signal DQ3 to the storage space of the memory device 120p corresponding to the address signal ADD. As another example, the memory module 100 may read the data stored in the storage space of the memory device 120p corresponding to the address signal ADD.

[0080] As another example, the processing buffer circuit 110 of the memory module 100 may perform an operation on the data MDN / MDP stored in the memory module 100 or the data included in the third data signal DQ3 based on the processing command CMDP included in the command signal CMD.

[0081] In operation S412b, the memory space accessible by the processing circuit 115 may be expanded to the memory device 120n classified as the normal memory channel in addition to the memory device 120p classified as the processing memory channel. Therefore, the processing circuit 115 may perform an operation on a data set that is larger than when the memory space accessible by the processing circuit 115 is limited to the memory device 120p classified as the processing memory channel.

[0082] Figure 7 The embodiment according to the present invention is shown Figure 1 Specifically, according to an embodiment of the present invention, in Figure 7 , a flowchart of memory module 100 preprocessing data to accelerate the operation of convolutional neural network (CNN) is shown. Figures 1 to 3 as well as Figures 5 to 7 , the memory module 100 may perform operations S401c to S403c.

[0083] In operation S401c, the memory module 100 may store the data received from the host 200 in a memory device permitted to be accessed by the host 200. For example, in the case where the router 112 operates in the extension mode, the memory module 100 may store the data received from the host 200 in a storage space permitted to be accessed by the host 200. As another example, in the case where the router 112 operates in the mirroring mode, the memory module 100 may store the data received from the host 200 in the memory device 120n classified as the normal memory channel C1.

[0084] In operation S402c, the memory module 100 may transpose all or part of the data received from the host 200. For example, the processing circuit 115 may transpose the data determined by the host 200 to require pre-processing.

[0085] In operation S403c, the transposed data may be stored in the memory device 120p classified as the processing memory channel C2 or in the buffer 114. For example, when the router 112 operates in the extension mode, the entire storage space of the memory device 120 may be provided as an access target to the host 200 and the processing circuit 115. In this case, the processing circuit 115 may store the transposed data in any storage space of the memory device 120 or in the buffer 114.

[0086] Alternatively, when the router 112 operates in the extended mode, only a portion of the storage space of the memory device 120p classified as the processing memory channel C2 may be provided to the host 200 as an access target. In this case, the processing circuit 115 may store the transposed data in a storage space exclusively occupied by the processing circuit 115 in the storage space of the memory device 120p. In response to a read request for pre-processed data provided from the host 200, the transposed data stored in the storage space exclusively occupied by the processing circuit 115 may be stored in the buffer 114. The host 200 may read the transposed data by accessing the storage space of the buffer 114.

[0087] According to another embodiment, when the router 112 operates in the extended mode, the processing circuit 115 may store the transposed data in the buffer 114. The host 200 may read the transposed data by accessing the storage space of the buffer 114. In addition, when the router 112 operates in the mirror mode, only a portion of the storage space of the memory device 120n classified as the normal memory channel C1 may be provided to the host 200 as an access target. In this case, the processing circuit 115 may store the transposed data in the storage space of the memory device 120p classified as the processing memory channel C2. In response to a read request for the transposed data provided from the host 200, the pre-processed data stored in the storage space of the memory device 120p may be stored in the buffer 114. The host 200 may read the transposed data by accessing the storage space of the buffer 114. When the router 112 operates in the mirror mode, the data may be transposed by the processing circuit 115 regardless of whether the host 200 accesses the memory device 120n. Thus, the speed at which data is pre-processed may be increased relative to when router 112 operates in the extended mode.

[0088] Fig. 8A Shows that following Figure 7 The flowchart stores the data Figure 2 a cell of a first memory device. Figure 8B Shows that following Figure 7 The flowchart stores the data Figure 2 A cell of a third memory device. Figures 1 to 3 , Figures 5 to 7 , Fig. 8A and Figure 8B , the first memory device 121a may be one of the memory devices 120n classified as the normal memory channel C1. The third memory device 123a may be one of the memory devices 120p classified as the processing memory channel C2.

[0089] Data received from the host 200 can be Fig. 8AThe processing circuit 115 can transpose Fig. 8A The data is in matrix form as shown. That is, Fig. 8A The data unit D12 and the data unit D21 may be stored in the memory cell array of the third memory device 123a so that their positions are changed, such as Figure 8B Then, in response to a read request from the host 200 , the processing circuit 115 may provide the transposed data to the host 200 through the buffer 114 .

[0090] The data received from the host 200 may be in the form of a k×1 matrix, where k and 1 are positive integers. In this case, in order to perform a CNN operation on the data stored in the memory device, it may be necessary to access the p-th row data (p is a positive integer equal to or less than k) and the q-th column data (q is a positive integer equal to or less than 1). For the purpose of accessing the q-th column data, the host 200 may read the data a total of k times. In contrast, if Figure 8B As shown, when the data has been transposed, you can access the qth row of data belonging to the transposed data. Fig. 8A The qth column data is shown. Therefore, the host 200 can read the desired data by only one access. This can indicate that the performance of the CNN operation performed by the host 200 is improved by the memory module 100.

[0091] In an embodiment, the processing circuit 115 may perform a CNN operation by using transposed data. The processing circuit 115 may read: data MDN stored in a memory device 120n classified as a normal memory channel C1 and at least a portion of data MDP stored in a memory device 120p classified as a processing memory channel C2. The processing circuit 115 may perform a CNN operation on the read data and the transposed data. The processing circuit 115 may store the result of the CNN operation in the buffer 114. In response to a read request from the host 200, the memory module 100 may output the result of the CNN operation stored in the buffer 114. In the above example, the host 200 may transmit to the memory module 100 data targeted for the CNN operation and a processing command CMDP directing the execution of the CNN operation. Therefore, the host 200 may offload the CNN operation to the processing circuit 115.

[0092] Fig.9A It shows that Figure 2 A flowchart of a portion of an operation method of a memory module when the operation mode of a router is determined to be a mirroring mode. Figure 1 , Figure 2 and Fig.9A, the memory module 100 may perform operations S510a to S530a. In operation S510a, the memory module 100 may detect one or more faulty memory cells of the memory device 120n classified as the normal memory channel C1. For example, the memory module 100 may continuously receive read requests from the host 200, the number of which is given for any storage space. In this case, the read request for the storage space of the normal memory channel C1 received from the host 200 may be transferred to the processing memory channel C2. Therefore, the processing circuit 115 may also receive a read request provided from the host 200. The processing circuit 115 may detect whether the number of read requests associated with the same address repeatedly received from the host 200 is equal to or greater than a given number of times. Therefore, the processing circuit 115 may determine whether the faulty memory cell included in the memory cell array corresponding to the physical address of the corresponding storage space is one or more.

[0093] In operation S520a, the memory module 100 may read data from a storage space of a memory device 120p corresponding to a storage space of a memory device 120n including a failed memory cell. For example, in response to read requests continuously received from the host 200, the processing circuit 115 may access a storage space of a memory device 120p classified as a processing memory channel C2. In other words, the processing circuit 115 may access mirror data corresponding to data stored in a storage space including a failed memory cell. The processing circuit 115 may provide the mirror data to the buffer 114.

[0094] In operation S530a, the memory module 100 may transmit the mirror data to the host 200 to replace the data stored in the storage space including the failed memory cell. For example, in the case where the host 200 transmits the address signal ADD indicating the storage space of the memory device 120n including the failed memory cell to the memory module 100, the router 112 may provide the mirror data stored in the buffer 114 to the host 200. Therefore, the performance of the memory module 100 can be improved.

[0095] Fig. 9B It shows that Figure 2 Flow chart of a portion of a method for operating a memory module when the operation mode of a router is set to an operation mode of a mirroring mode. In an embodiment, the memory module 100 may include: a plurality of normal memory channels and a plurality of processing memory channels. Figure 1 , Figure 2 and Fig. 9B , the memory module 100 may perform operations S510b to S540b.

[0096] In operation S510b, the memory module 100 may copy data stored in a memory device classified as a first normal memory channel to memory devices classified as a first processing memory channel to an mth processing memory channel (m is a positive integer) among a plurality of processing memory channels. For example, the router 112 may transfer an access request for a memory device classified as a first normal memory channel to a memory device classified as a first processing memory channel to an mth processing memory channel. Therefore, data received from the host 200 may be stored in a memory device classified as a first processing memory channel to an mth processing memory channel. Therefore, Fig.9A In comparison, the number of copies of data received from the host 200 can be increased.

[0097] In operation S520b, the memory module 100 may detect the presence of a faulty memory cell included in a memory device classified as a first normal memory channel. In other words, the memory module 100 may detect a fault of the first normal memory channel. Fig.9A In the same manner as described in operation S510a, the memory module 100 may detect the presence of a failed memory cell.

[0098] In operation S530b, the memory module 100 may vote between memory devices classified as the first processing memory channel to the mth processing memory channel. For example, the memory module 100 may receive from the host 200: a read request for a storage space including a faulty memory cell. In response to the read request from the host 200, the processing circuit 115 may access the storage space of the first processing memory channel to the mth processing memory channel, which corresponds to the storage space including the faulty memory cell. The processing circuit 115 may read: the first candidate data to the mth candidate data respectively stored in the first processing memory channel to the mth processing memory channel.

[0099] The processing circuit 115 may compare the first candidate data to the mth candidate data with each other, and may determine the mirror data corresponding to the data stored in the storage space including the faulty memory cell according to the majority rule. In an embodiment, when m is 3, the processing circuit 115 may compare the first candidate data to the third candidate data with each other. In this case, the first candidate data and the second candidate data may be the same, and the first candidate data may be different from the third candidate data. The processing circuit 115 may determine or select the first candidate data as the mirror data based on the result of the comparison.

[0100] In operation S540b, the memory module 100 may transmit data associated with the result of the voting performed in operation S530b to the host 200. For example, the memory module 100 may store the mirror data determined in operation S530b in the buffer 114. The memory module 100 may transmit the mirror data stored in the buffer 114 in response to a read request for a storage space of a memory device including a failed memory cell provided from the host 200.

[0101] Fig.10 It is shown Figure 1 A flowchart of a method for operating a memory module. Figures 1 to 3 as well as Fig.10 , the memory module 100 may also perform operations S610 to S630. In operation S610, the memory module 100 may receive a mode register set command MRS including an access code ACCKEY from the host 200. In an embodiment, the access code ACCKEY may be a code predetermined when the host 200 or the memory module 100 is manufactured. The memory module 100 may store the received access code ACCKEY in the mode register 113.

[0102] In operation S620, the memory module 100 may compare the access code ACCKEY received from the host 200 with the access code ACCKEY_p pre-stored in the processing buffer circuit 110. For example, the processing circuit 115 may receive the access code ACCKEY from the router 112. The processing circuit 115 may compare the received access code ACCKEY with the pre-stored access code ACCKEY_p. When the received access code ACCKEY is the same as the pre-stored access code ACCKEY_p, the memory module 100 may perform operation S631. When the received access code ACCKEY is different from the pre-stored access code ACCKEY_p, the memory module 100 may perform operation S632.

[0103] In operation S631, based on the command signal CMD received from the host 200, the memory module 100 may perform an operation on the memory device 120. For example, based on the operation mode of the router 112, the router 112 may permit the host 200 to access the buffer 114 or the storage space of the memory device 120. Therefore, the host 200 may read the data 100 stored in the memory module, or may write the data 100 in the memory module. In step S632, the memory module 100 may ignore the command signal CMD received from the host 200. In other words, the access request for the memory device 120 received from the host 200 may be ignored by the memory module 100. Therefore, a memory module 100 with improved security may be provided.

[0104] Fig.11 FIG. 2 is a block diagram of a memory module according to an embodiment of the inventive concept. Figure 1 , Figure 2 and Fig.11 , the memory module 1000 may include: a first memory chip MD1 to an eighth memory chip MD8, a processing buffer chip PB, and a serial presence detection (SPD) chip. The first memory chip MD1 to the eighth memory chip MD8 may be DRAM chips, respectively. The first memory chip MD1 to the eighth memory chip MD8 may store data. The first memory chip MD1 to the eighth memory chip MD8 may be connected to the processing buffer chip PB. An embodiment is shown as that the memory module 1000 includes eight memory chips, but the number of memory chips that the memory module 1000 can include is not limited thereto.

[0105] The processing buffer chip PB may receive a data signal DQ, an address signal ADD, and a command signal CMD from the host 200 through a memory interface that complies with the DDR SDRAM standard. In an embodiment, the processing buffer chip PB may include Figure 2 The processing buffer circuit 110 of the processing buffer chip PB may perform operations on the first to eighth memory chips MD1 to MD8 based on the data signal DQ, the address signal ADD, and the command signal CMD thus received.

[0106] For example, the processing buffer chip PB may read data stored in the first to eighth memory chips MD1 to MD8, or may write data received from the host 200 to the first to eighth memory chips MD1 to MD8. The processing buffer chip PB may process a portion of the data stored in the first to eighth memory chips MD1 to MD8.

[0107] The SPD chip SPD may store information associated with the memory module 1000. The SPD chip SPD may transmit a module information signal INFO including information associated with the memory module 1000 to the host 200 through a memory interface complying with the DDR SDRAM standard. The operation of the SPD chip SPD will be described more fully below.

[0108] In an embodiment, the memory module 1000 may be implemented using a dual in-line memory module (DIMM) complying with the JEDEC standard. In this case, the memory chips included in the memory module 1000 may be classified into normal memory channels and / or process memory channels in different schemes.

[0109] For example, in the case of implementing the memory module 1000 using DIMM, memory chips disposed on one surface (e.g., the front side) of the memory module 1000 may be classified as normal memory channels, and memory chips disposed on another surface (e.g., the back side) of the memory module 1000 may be classified as processing memory channels.

[0110] As another example, in the case where the memory module 1000 is implemented using DIMM, the memory chips may form ranks. The memory chips included in some of the multiple memory banks included in the memory module 1000 may be classified as normal memory channels, and the memory chips included in the remaining memory banks may be classified as processing memory channels. For example, in the case where the memory chips form the first to fourth memory banks, the memory chips belonging to the first and second memory banks may be classified as normal memory channels, and the memory chips belonging to the third and fourth memory banks may be classified as processing memory channels. However, the manner in which the memory chips are classified is not limited to the above example.

[0111] Fig.12 It is shown that Fig.11 A flowchart of an operation method of a memory system including a memory module. Figure 1 , Figure 2 , Fig.11 and Fig.12 ,include Fig.11 The memory system 10 of the memory module 1000 may perform operations S110c to S130c, operation S200c, operation S300c, and operation 400c. In operation S11oc, the memory module 1000 of the memory system 10 may transmit a module information signal INFO to the host 200. In some embodiments, such a module information signal INFO may include various information about the memory module 1000, for example, information indicating that the memory module 1000 includes a processing buffer chip PB, the type of operation mode of the processing buffer chip PB, and the type of operation that can be performed by the processing buffer chip PB. The SPD chip SPD may transmit the module information signal INFO to the host 200 through a memory interface that complies with the DDR SDRAM standard.

[0112] In operation S120c, the host 200 of the memory system 10 may determine the operation mode of the processing buffer chip PB in the memory module 1000. For example, the host 200 may check that the memory module 1000 is able to receive a command for unloading through the DDR SDRAM standard interface based on the received module information signal INFO. The host 200 may determine how the components included in the processing buffer chip PB of the memory module 1000 operate. For example, the host 200 may determine the operation mode of the router 112 or the processing circuit 115 of the processing buffer circuit 110 included in the processing buffer chip PB.

[0113] In operation S130c, the host 200 of the memory system 10 may transmit a command signal CMD to the memory module 1000. For example, the host 200 may issue a command signal CMD including a mode register setting command MRS associated with the operation of the processing buffer chip PB based on the result of operation S120c. The host 200 may transmit the command signal CMD to the memory module 1000 through a memory interface complying with the DDR standard.

[0114] In operation S200c, the memory module 1000 of the memory system 10 may select an operation mode of the processing buffer chip PB. For example, the memory module 1000 may determine the operation mode of the router 112 and the processing circuit 115 and the storage space accessible by the host 200 based on the command signal CMD received in operation S130c.

[0115] In operation S300c, the host 200 of the memory system 10 may transmit the data signal DQ, the command signal CMD, and the address signal ADD to the memory module 1000. In operation S400c, the memory module 1000 of the memory system 10 may perform operations on the memory device according to the operation mode of the selected processing buffer chip PB. For example, the processing buffer chip PB may operate based on the operation mode of the router 112 and the processing circuit 115 determined in operation S200c and the storage space accessible by the host 200. The processing buffer chip PB may access at least a portion of the first memory chip MD1 to the eighth memory chip MD8 based on the data signal DQ, the command signal CMD, and the address signal ADD.

[0116] According to an embodiment of the present invention, a PIM or FIM is provided that can access data at the memory module level without additional intervention of a host or CPU. For example, a PIM or FIM with a separate bandwidth for processing data can be set in the memory module. Therefore, the performance of data processing of the memory module can be improved.

[0117] Due to the use of the memory module of the embodiment conceived according to the present invention, the performance of applications using machine learning or deep learning algorithms can be improved. For example, in the case of processing data based on algorithms such as recurrent neural networks (RNNs), multilayer perceptrons (MLPs), or CNNs with fully connected layer structures, the memory device may be frequently accessed because the amount of data to be processed is large. The memory module of the embodiment conceived according to the present invention can provide a separate internal bandwidth for data processing, so the processing volume of the above applications can be improved.

[0118] According to an embodiment of the present invention, a deep learning accelerator based on a DDR memory channel can be provided. According to another embodiment of the present invention, a memory module including a preprocessor for acceleration of CNN operations can be provided. For example, the memory module can transpose the data in the form of a matrix received from the host by using an internal processor. Because the memory module stores the transposed data, the speed of the CNN operation can be improved.

[0119] According to another embodiment of the present invention, a memory module is provided that improves the reliability of data stored therein by mirroring the data in the memory module. According to another embodiment of the present invention, a memory module is provided that can provide a dual security function for data by verifying an access code received from a host using an internal processor.

[0120] According to an embodiment of the present invention, data processing can be offloaded from a host to a memory module through a memory interface that complies with the DDR standard. A memory module according to another embodiment of the present invention may include a processor that can access storage spaces of different memory devices in the memory module without intervention by the host. Therefore, the performance of data processing and the compatibility of the memory module can be improved.

[0121] While the inventive concepts have been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concepts as described in the appended claims.

Claims

1. A memory module, comprising: A processing buffer circuit is electrically coupled to the first memory device and the second memory device and the host, the processing buffer circuit is configured to communicate with the host in accordance with the double data rate DDR synchronous dynamic random access memory SDRAM standard, and includes: a processing circuit configured to process at least one of data received from the host, data stored in the first memory device, and data stored in the second memory device in response to a processing command received from the host; a mode register configured to store information regarding operation of the processing buffer circuit in response to a mode register set command including a command permitting operation of all or a portion of the processing circuit; and The buffer is configured to store data processed by the processing circuit.

2. The memory module according to claim 1, wherein: The processing buffer circuit also includes a router configured to support access by the host to the first memory device and the second memory device.

3. The memory module according to claim 2, in, During the extended operation mode, the router provides the storage space of the first memory device, all or part of the storage space of the second memory device, and the storage space of the buffer as access targets to the host, and provides all or part of the storage space of the second memory device as access targets to the processing circuit; and Wherein, during the mirroring operation mode, the router provides to the processing circuit an access request for the first memory device received from the host.

4. The memory module according to claim 3, wherein: During the extended operating mode, the processing circuit: (i) processes at least one of data received from the host, data stored in the first memory device, and / or data stored in the second memory device based on the processing command; and, (ii) storing the processed data in the buffer.

5. The memory module according to claim 4, wherein: While the processing circuit is processing data, the storage space of the first memory device is accessed by the host.

6. The memory module according to claim 1, wherein: The processing circuit is configured to erase the second memory device periodically and / or in response to an erase request received from the host.

7. The memory module of claim 1 , further comprising a third memory device and a fourth memory device; and in, In response to the information stored in response to the mode register set command, the mode register classifies at least one of the first to fourth memory devices as a normal memory channel and classifies the remaining memory devices of the first to fourth memory devices as process memory channels; and wherein, during the extended operation mode, the processing circuit processes the data stored in each of the first to fourth memory devices based on the processing command, and stores the processed data in the buffer; and Wherein, during the mirroring operation mode, the processing circuit copies at least a portion of the data stored in the memory device of the normal memory channel to a corresponding one of the memory devices of the processing memory channel.

8. A method for operating a memory module, the memory module comprising a normal memory channel and a processing memory channel, each of the normal memory channel and the processing memory channel sharing a router of a processing buffer circuit and comprising a memory cell array, the method comprising: Based on a mode register setting command received from a host, setting an operation mode of the router to one of an extended mode or a mirror mode; accessing data stored in the normal memory channel and the processing memory channel based on an address and command received from the host and a set operation mode of the router; as well as processing, at a processing circuit included in the processing buffer circuit, the accessed data based on a processing command received from the host; The mode register setting command, the address, the command and the processing command are transmitted from the host to the memory module according to a double data rate DDR synchronous dynamic random access memory SDRAM standard.

9. The method according to claim 8, wherein: When the operation mode of the router is determined to be the extended mode, determining the operation mode of the router includes: in response to a permission request of the host, permitting the operation of a logic circuit that performs data processing in the processing circuit; and wherein the logic circuit performs an operation on the accessed data based on the processing command.

10. The method according to claim 8, wherein: When the operation mode of the router is determined to be the mirror mode, determining the operation mode of the router includes: permitting operation of the logic circuit of the processing circuit; and wherein accessing data stored in the normal memory channel and the processing memory channel includes: passing access to the storage space of the normal memory channel to the processing circuit.

11. The method according to claim 10, wherein: Processing of accessed data also includes: performing an operation on the accessed data at the processing circuit based on the processing command; storing a result of the operation in a buffer of the processing buffer circuit; and In response to a read request from the host, a result of the operation stored in the buffer is provided to the host.

12. The method according to claim 10, wherein: Processing of accessed data also includes: detecting a failure of a memory cell included in the normal memory channel; In response to a read request from the host regarding data stored in the normal memory channel, reading mirror data stored in the processing memory channel, the mirror data corresponding to data stored in the memory unit in which the failure is detected; and The mirror data is provided to the host.

13. The method according to claim 12, in, The processing memory channel includes: copying the data stored in the normal memory channel to the first mirror channel, the second mirror channel and the third mirror channel; Wherein, reading the mirror data includes: In response to the read request, reading first candidate data, second candidate data, and third candidate data corresponding to data stored in the memory cell in which a failure is detected from the first mirror channel, the second mirror channel, and the third mirror channel, respectively; and Based on majority voting, one of the first to third candidate data is determined as the mirror data.

14. The method according to claim 10, wherein: Accessing the data includes: comparing an access code included in the mode register setting command with a code pre-stored in the processing buffer circuit; wherein, when the access code is different from the pre-stored code, ignoring a command received from the host; and wherein, when the access code is the same as the pre-stored code, accessing the data stored in the normal memory channel based on the command.

15. A memory module, comprising: Processing buffer chip; as well as One or more DRAM chips to store data; wherein the one or more DRAM chips form a normal memory channel and a processing memory channel; Wherein, the processing buffer chip includes: A physical layer that receives command / address signals and data signals from a host; a first memory controller and a second memory controller, wherein the first memory controller and the second memory controller respectively access the normal memory channel and the processing memory channel based on the command / address signal; a processing circuit that processes at least a portion of the data stored in the normal memory channel accessed through the first memory controller and the data stored in the processing memory channel accessed through the second memory controller based on a processing command included in the data signal; a buffer storing data processed by the processing circuit; and a router that receives the command / address signal and the data signal from the physical layer and transmits the command / address signal and the data signal to the first memory controller and the buffer; and The processing buffer chip communicates with the host according to the double data rate DDR synchronous dynamic random access memory SDRAM standard.

16. The memory module according to claim 15, wherein: The memory module is a Dual Inline Memory Module DIMM.

17. The memory module of claim 15, further comprising: a serial presence detection (SPD) chip, the SPD chip transmitting a module information signal including information about the memory module to the host; and The processing buffer chip receives a mode register setting command generated based on the module information signal from the host, and permits the operation of the logic circuit of the processing circuit based on the mode register setting command.

18. The memory module of claim 15, further comprising: a mode register that receives a mode register setting command received from the host through the physical layer and stores information related to the operation of the processing buffer chip in response to the received mode register setting command; and wherein operation of logic circuitry of the processing circuitry is permitted in response to information stored in response to a received mode register set command.

19. The memory module according to claim 15, wherein: The router provides, to the cache, data accessed by the first memory controller and stored in the normal memory channel; and wherein the processing circuit performs an operation on the data stored in the normal memory channel and provided to the cache based on the processing command.

20. A memory module, comprising: A processing buffer circuit is electrically coupled to the first memory device and the second memory device and the host, the processing buffer circuit comprising: a processing circuit configured to process at least one of data received from the host, data stored in the first memory device, and data stored in the second memory device in response to a processing command received from the host; a mode register configured to store information regarding operation of the processing buffer circuit in response to a mode register set command including a command permitting operation of all or a portion of the processing circuit; a buffer configured to store data processed by the processing circuit; and A router extends between the host and the first memory device and the second memory device, and is configured so that data provided by the host to the first memory device or the second memory device, or data provided by the first memory device or the second memory device to the host passes through the router.

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