Signal processing circuit and signal processing method

Abstract

A signal processing circuit and signal processing method. The signal processing circuit includes: a drive control circuit; a signal acquisition circuit configured to acquire multiple input analog signals; a memristor array, wherein the memristor array is configured to perform K-order convolution processing on the multiple input analog signals, where K is an integer greater than 1; and an output circuit configured to, under the control of the drive control circuit, sequentially acquire K first analog accumulated signals after the memristor array performs the K-order convolution processing at a first time interval and sum the K first analog accumulated signals to obtain a first data fusion signal corresponding to the multiple input analog signals. The signal processing circuit can directly operate on the received analog signals without analog-to-digital conversion, avoiding the introduction of a digital conversion circuit. It achieves analog signal delay and temporary storage through post-sampling, and utilizes the memristor array to simultaneously improve computing power and energy efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a signal processing circuit and a signal processing method. Background Art

[0002] With the development of the Internet of Things (IoT) and intelligent sensing applications, the demand for rapid, real-time analysis of sensor data is increasing. For example, autonomous driving technology requires timely processing of image sensors and on-board radar signals to cope with complex traffic conditions. At the same time, the number of sensors is increasing to extract more information to improve system performance. For example, microphone arrays are used for voice enhancement, improving the recognition accuracy and robustness of voice interaction systems. This places higher demands on both the transmission of sensor data and the computing power of back-end processing. Consequently, a growing number of technologies are exploring data preprocessing at the sensor terminal to filter received signals, thereby reducing the amount of transmitted data and improving the overall system's responsiveness. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a signal processing circuit, comprising: a drive control circuit; a signal acquisition circuit configured to acquire multiple input analog signals; a memristor array, wherein the memristor array is configured to perform K-order convolution processing on the multiple input analog signals, where K is an integer greater than 1; and an output circuit configured to, under the control of the drive control circuit, sequentially acquire, at a first time interval, K first analog accumulated signals after the memristor array performs the K-order convolution processing, and sum the K first analog accumulated signals to obtain a first data fusion signal corresponding to the multiple input analog signals.

[0004] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the output circuit, under the control of the driving control circuit, obtains K first analog accumulated signals in sequence at a first time interval starting from a first moment. The output circuit is further configured to, under the control of the driving control circuit, obtain K second analog accumulated signals after the memristor array performs K-order convolution processing in sequence at the first time interval starting from a moment i*T after the first moment and sum the K second analog accumulated signals to obtain the i-th second data fusion signal corresponding to multiple input analog signals, wherein i is a positive integer less than or equal to m-1, and i takes values ​​1, 2, ...m-1 in chronological order, m is a positive integer greater than 1 and less than or equal to K, T represents the second time interval, and the ratio of the second time interval to the first time interval is N, N=K / m and is a positive integer.

[0005] For example, in the signal processing circuit provided by at least one embodiment of the present disclosure, the memristor array includes K column signal output terminals, and the K column signal output terminals are used to output K first analog accumulated signals corresponding to K-order convolution processing. The output circuit includes K switch sub-circuits and an accumulation circuit. The input terminals of the K switch sub-circuits are electrically connected one by one to the K column signal output terminals, and the output terminals of the K switch sub-circuits are electrically connected to the input terminal of the accumulation circuit. The K switch sub-circuits are configured to, under the control of the driving control circuit, sequentially turn on the connection between the corresponding column signal output terminals and the input terminal of the accumulation circuit according to a first time interval, and transmit the K first analog accumulated signals obtained after the convolution processing of the memristor array to the accumulation circuit. The accumulation circuit is configured to perform summation processing on the K first analog accumulated signals to obtain a first data fusion signal.

[0006] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the accumulator circuit is an integration circuit, and the drive control circuit is further configured to reset the integration circuit after obtaining the first data fusion signal.

[0007] For example, in the signal processing circuit provided by at least one embodiment of the present disclosure, the memristor array further includes K column signal output terminals, the K column signal output terminals are used to output K second analog accumulated signals or K first analog signals corresponding to the K-order convolution processing, the output circuit includes K switch sub-circuits and an accumulation circuit, each switch sub-circuit includes 1 first input terminal and m first output terminals, the accumulation circuit includes m accumulation sub-circuits, each of the m accumulation sub-circuits includes a second input terminal and a second output terminal, and the K column signal output terminals are respectively electrically connected to the K column signal output terminals in a one-to-one correspondence. Then, the m first output terminals of each switching sub-circuit are electrically connected to the m second input terminals of the m accumulating sub-circuits in a one-to-one correspondence, and each of the m accumulating sub-circuits is configured to perform an addition process to respectively obtain a first data fusion signal, a first second data fusion signal, a second second data fusion signal..., and an m-1th second data fusion signal, and output the first data fusion signal, the first second data fusion signal, the second second data fusion signal..., and the m-1th second data fusion signal through the m second output terminals of the m accumulating sub-circuits.

[0008] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, each switch sub-circuit is configured to: under the control of the drive control circuit, at the same time, make the column signal output terminal electrically connected to the switch sub-circuit only conductive with one of the m second input terminals of the accumulation circuit, and make the column signal output terminal electrically connected to the switch sub-circuit switched to different second input terminals in sequence at a second time interval.

[0009] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, under the control of the driving control circuit, starting from a first moment, the K switching sub-circuits are further configured to, at a first time interval, sequentially connect the K column signal output terminals to the second input terminal of the first accumulation sub-circuit, thereby sequentially outputting the K first analog accumulation signals to the first accumulation sub-circuit; and under the control of the driving control circuit, starting from the i*T moment after the first moment, at a first time interval, sequentially connect the K column signal output terminals to the second input terminal of the (i+1)th accumulation sub-circuit, thereby sequentially outputting the K second analog accumulation signals to the (i+1)th accumulation sub-circuit.

[0010] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the switch subcircuit includes a 1-to-m switch circuit, the 1-to-m switch circuit includes m channels, and the m channels are electrically connected to m first output terminals respectively.

[0011] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the accumulation sub-circuit is an integration circuit, and the drive control circuit is further configured to perform a reset operation on the integration circuit after the integration circuit outputs the first data fusion signal or the i-th second data fusion signal.

[0012] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the drive control circuit includes an array drive control circuit, which is coupled to the memristor array and is configured to set the memristor array, write data of the convolution parameter matrix corresponding to the K-order convolution processing into the memristor array, and control the operation of the memristor array to perform K-order convolution processing on multiple input analog signals.

[0013] For example, in the signal processing circuit provided in at least one embodiment of the present disclosure, the number of multiple input analog signals is J, and the memristor array includes J rows and K columns of memristor units arranged in an array, the J rows are respectively used to receive the multiple input analog signals, and the K columns correspond to K column signal output terminals.

[0014] At least one embodiment of the present disclosure provides a signal processing method, comprising: obtaining multiple input analog signals; performing K-order convolution processing on the multiple input analog signals using a memristor array, where K is an integer greater than 1; and sequentially obtaining, at a first time interval, K first analog accumulated signals after the memristor array performs the K-order convolution processing and summing the K first analog accumulated signals to obtain a first data fusion signal corresponding to the multiple input analog signals.

[0015] For example, in the signal processing method provided in at least one embodiment of the present disclosure, K first analog accumulated signals are obtained in sequence according to a first time interval starting from a first moment, and K second analog accumulated signals after the memristor array performs K-order convolution processing are obtained in sequence according to the first time interval, and the K second analog accumulated signals are summed to obtain the i-th second data fusion signal corresponding to multiple input analog signals, wherein i is a positive integer less than or equal to m-1, and i takes values ​​of 1, 2, ...m-1 in sequence, m is a positive integer greater than 1 and less than or equal to K, T represents the second time interval, and the ratio of the second time interval to the first time interval is N, N=K / m and is a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0017] Figure 1 A schematic diagram of the structure of discrete broadband beamforming is shown;

[0018] Figure 2A shows a schematic structure of a memristor array;

[0019] Figure 2B Schematic diagram of a 1T1R memristor unit;

[0020] Figure 2C Schematic diagram of a 2T2R memristor unit;

[0021] Figure 3A A schematic structural diagram of a signal processing circuit based on a memristor array according to at least one embodiment of the present disclosure;

[0022] Figure 3B A schematic structural diagram of an output circuit provided in at least one embodiment of the present disclosure;

[0023] Figure 3C A schematic diagram showing an exemplary signal processing circuit provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 3D A sampling schematic diagram of a signal processing circuit provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 4A A schematic structural diagram of a signal processing circuit provided in at least one embodiment of the present disclosure;

[0026] Figure 4BA schematic diagram showing another exemplary signal processing circuit provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 4C Shown Figure 4B The switch connection diagram of the signal processing circuit shown;

[0028] Figure 4D A schematic diagram illustrating a design process of a signal processing circuit provided by at least one embodiment of the present disclosure;

[0029] Figure 5A A schematic diagram showing a signal processing circuit provided by at least one embodiment of the present disclosure is shown;

[0030] Figure 5B Shown Figure 5A The switch connection diagram of the signal processing circuit shown;

[0031] Figure 6A A schematic structural diagram of a memristor array provided in at least one embodiment of the present disclosure;

[0032] Figure 6B A schematic diagram of another memristor array provided in at least one embodiment of the present disclosure;

[0033] Figure 6C A signal processing circuit constructed using a 2T2R structured memristor unit is shown;

[0034] Figure 6D Another signal processing circuit constructed using a 2T2R memristor unit is shown;

[0035] Figure 7 A schematic flowchart of a signal processing method provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] Data fusion technology refers to information processing techniques that use computers to automatically analyze and synthesize time-sequential observations based on specific criteria to complete required decision-making and evaluation tasks. Examples of data fusion techniques include wideband beamforming, which uses multiple FIR (Finite Impulse Response) filters to filter and superimpose signals from each channel, generating a specific response in time and space.

[0039] Figure 1 Figure 2 shows a schematic diagram of the structure of discrete broadband beamforming. Figure 1 As shown in the figure, J sensors Sen[0], Sen[1]...Sen[J-1] send the input signal Sen[i](t) (0≤i≤J-1, and i is a positive integer, t represents the time) to J groups of FIR filters for filtering, and then add up all the filtering results and output them to finally obtain a discrete beamforming result.

[0040] like Figure 1 As shown in Figure 1, each FIR filter has an order of K and consists of a delay unit and a weight multiplication unit. The calculation process of beamforming is as follows:

[0041] For the i-th sensor Sen[i], the i-th FIR filter delays the input signal Sen[i](t) of the i-th sensor Sen[i] multiple times. For example, the delayed signal can be represented by the vector a i =[Sen[i](t),Sen[i](t-τ),Sen[i](t-2τ),…,Sen[i](t-(K-1)τ)] TIndicates that τ represents the first time interval, that is, the sampling time interval of the input signal; and the delayed processing result and the corresponding weight w i =[w i，0 ,w i，1 ,w i，2 ,…,w i，K-1 ] T Multiply and add to get the output result Therefore, the final output of the beamforming system is

[0042] Analyzing the calculation process from another perspective, the delayed signals of each channel in the jth column (0≤j≤K-1, and j is a positive integer) at time t can be expressed by vector m j (t)=[Sen[0](t-jτ),Sen[1](t-jτ),Sen[2](t-jτ),…,Sen[J-1](t-jτ)] T Represents that the vector m j (t) and the column weight w j =[w 0,j ,w 1,j ,w 2,j ,…,w J-1,j ] T The result of multiplication and superposition is The final output can be expressed as:

[0043]

[0044] For example, for Figure 1 The wideband beamforming circuit shown is typically implemented using a DSP (Digital Signal Processor). This approach requires the integration of a large number of analog / digital conversion interface circuits to convert the received signal into a digital signal, which is then used by the DSP to perform logical operations. However, integrating a large number of analog / digital conversion interface circuits and DSPs within the sensor terminal undoubtedly conflicts with the terminal device's requirements for low power consumption and small size.

[0045] Memristors (such as resistive random access memory, phase-change memory, and conductive bridge memory) are a new type of micro-nanoelectronic device whose conductance state can be adjusted by applying external stimuli. As a two-terminal device, memristors have adjustable resistance and are non-volatile. According to Kirchhoff's current law and Ohm's law, an array of these devices can perform analog multiplication and addition calculations in parallel, directly processing the input analog signal. Both storage and calculation occur within the memristors of the array. Based on this computing architecture, integrated storage and computation can be achieved without requiring large amounts of data movement, reducing data transfer time, achieving high energy efficiency, low power consumption, and a small footprint. Due to the integrated and non-volatile nature of memristor devices and the efficient parallelization of memristor array operations, memristor arrays can be used to construct signal processing circuits.

[0046] At least one embodiment of the present disclosure provides a signal processing circuit, comprising: a drive control circuit; a signal acquisition circuit configured to acquire multiple input analog signals; a memristor array, wherein the memristor array is configured to perform K-order convolution processing on the multiple input analog signals, where K is an integer greater than 1; and an output circuit configured to, under the control of the drive control circuit, sequentially acquire, at a first time interval, K first analog accumulated signals after the memristor array performs the K-order convolution processing, and sum the K first analog accumulated signals to obtain a first data fusion signal corresponding to the multiple input analog signals.

[0047] The signal processing circuit provided in the above-mentioned embodiments of the present disclosure can directly operate on the received analog signal, avoid the introduction of digital-to-analog conversion circuits, reduce the area and circuit power consumption overhead caused by data interfaces and logic operation units, realize the delay and temporary storage of analog signals through post-sampling, and use memristor arrays to realize highly parallel multiplication and addition operations, thereby improving computing power and energy efficiency at the same time.

[0048] At least one embodiment of the present disclosure further provides an information processing method corresponding to the above-mentioned information processing circuit.

[0049] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0050] Figure 2A The schematic structure of a memristor array is shown. The memristor array is composed of a plurality of memristor units, which form an array of J rows and K columns, where J and K are both positive integers. Each memristor unit includes a switch element and one or more memristors. Figure 2A In, WL <1> 、WL <2> ...WL <k>BL represents the word lines of the first column, the second column, ... the Kth column, respectively. The control electrode (eg, the gate of the transistor) of the switch element in each row of the memristor unit is connected to the word line corresponding to the row; <1> BL <2> ...BL <j>They represent the bit lines of the first row, the second row, ... the Jth row, respectively. The memristors in the memristor units of each row are connected to the bit lines corresponding to the row; SL <1> , SL <2> ...SL <k>The source lines represent the first, second, …, Kth columns, respectively. The sources of the transistors in each column's memristor cells are connected to the corresponding source line. According to Kirchhoff's law, by setting the state (e.g., resistance) of the memristor cells and applying corresponding wordline and bitline signals to the wordlines and bitlines, the memristor array can perform multiplication and accumulation calculations in parallel.

[0051] Figure 2A The memristor cells in the memristor array may have, for example, a 1T1R structure or a 2T2R structure, wherein a 1T1R memristor cell includes one transistor and one memristor, and a 2T2R memristor cell includes two transistors and two memristors. For example, memristors include, but are not limited to, RRAM, PCRAM, ECRAM, Flash, etc. It should be noted that the present disclosure does not limit the structure of the memristor cell, and memristor cells of other structures that can implement multiplication and accumulation operations may also be used, such as 1S1F, 0T1R, and other structures.

[0052] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistors used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other pole is directly described as the second pole.

[0053] Figure 2B Schematic diagram of a 1T1R memristor unit. Figure 2B As shown, the 1T1R structured memristor unit includes a transistor M1 and a memristor R1.

[0054] The embodiments of the present disclosure do not limit the type of transistor used. For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line WL, for example, when the word line WL is input with a high level, the transistor M1 is turned on; the first electrode of the transistor M1 can be a source electrode and configured to be connected to the source line SL, for example, the transistor M1 can receive a reset voltage through the source line SL; the second electrode of the transistor M1 can be a drain electrode and configured to be connected to the second electrode (for example, the negative electrode) of the memristor R1, and the first electrode (for example, the positive electrode) of the memristor R1 is connected to the bit line BL, for example, the memristor R1 can receive a set voltage through the bit line BL. For example, when transistor M1 is a P-type transistor, its gate is connected to the word line WL. For example, when the word line WL input is low, transistor M1 is turned on. The first electrode of transistor M1 can be a drain and configured to be connected to the source line SL. For example, transistor M1 can receive a reset voltage through the source line SL. The second electrode of transistor M1 can be a source and configured to be connected to the second electrode (for example, the negative electrode) of memristor R1. The first electrode (for example, the positive electrode) of memristor R1 is connected to the bit line BL. For example, memristor R1 can receive a set voltage through the bit line BL. It should be noted that the memristor structure can also be implemented as other structures, such as a structure in which the second electrode of memristor R1 is connected to the source line SL, and the embodiments of the present disclosure are not limited to this.

[0055] The following embodiments are described by taking the transistor M1 as an N-type transistor as an example.

[0056] The function of the word line terminal WL is to apply a corresponding voltage to the gate of the transistor M1, thereby controlling whether the transistor M1 is turned on or off. When operating the memristor R1, such as performing a set operation or a reset operation, it is necessary to first turn on the transistor M1, that is, it is necessary to apply a turn-on voltage to the gate of the transistor M1 through the word line terminal WL. After the transistor M1 is turned on, for example, a voltage can be applied to the memristor R1 through the source line terminal SL and the bit line terminal BL to change the resistance state of the memristor R1. For example, a set voltage can be applied through the bit line terminal BL to put the memristor R1 in a low-resistance state; for another example, a reset voltage can be applied through the source line terminal SL to put the memristor R1 in a high-resistance state. For example, the resistance value of the high-resistance state is more than 100 times the resistance value of the low-resistance state, for example, more than 1000 times.

[0057] It should be noted that in the embodiments of the present disclosure, by applying voltage simultaneously to the word line terminal WL and the bit line terminal BL, the resistance value of the memristor R1 can be made smaller and smaller, that is, the memristor R1 changes from a high resistance state to a low resistance state. The operation of changing the memristor R1 from a high resistance state to a low resistance state is called a set operation; by applying voltage simultaneously to the word line terminal WL and the source line terminal SL, the resistance value of the memristor R1 can be made larger and larger, that is, the memristor R1 changes from a low resistance state to a high resistance state. The operation of changing the memristor R1 from a low resistance state to a high resistance state is called a reset operation. For example, the memristor R1 has a threshold voltage. When the input voltage amplitude is less than the threshold voltage of the memristor R1, the resistance value (or conductance value) of the memristor R1 will not change. In this case, the resistance value (or conductance value) of the memristor R1 can be used for calculation by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 can be changed by inputting a voltage greater than the threshold voltage.

[0058] Figure 2C Schematic diagram of a 2T2R memristor unit. Figure 2C As shown, the 2T2R structure memristor unit includes two transistors M1 and M2 and two memristors R1 and R2. The following description is based on an example in which both transistors M1 and M2 are N-type transistors.

[0059] The gate of the transistor M1 is connected to the word line terminal WL1. For example, when a high level is input to the word line terminal WL1 of M1, the transistor M1 is turned on. The gate of the transistor M2 is connected to the word line terminal WL2. For example, when a high level is input to the word line terminal WL2 of M2, the transistor M2 is turned on. The first electrode of the transistor M1 can be a source and is configured to be connected to the source line terminal SL. For example, the transistor M1 can receive a reset voltage through the source line terminal SL. The first electrode of the transistor M2 can be a source and is configured to be connected to the source line terminal SL. For example, the transistor M2 can receive a reset voltage through the source line terminal SL. The first electrode of the transistor M1 is connected to the first electrode of the transistor M2, and is connected together to the source line terminal SL. The second electrode of the transistor M1 can be a drain and is configured to be connected to the second electrode (for example, the negative electrode) of the memristor R1, and the first electrode (for example, the positive electrode) of the memristor R1 is connected to the bit line terminal BL1. For example, the memristor R1 can receive a set voltage through the bit line terminal BL1; the second electrode of the transistor M2 can be a drain and is configured to be connected to the second electrode (for example, the negative electrode) of the memristor R2, and the first electrode (for example, the positive electrode) of the memristor R2 is connected to the bit line terminal BL2. For example, the memristor R2 can receive a set voltage through the bit line terminal BL2.

[0060] It should be noted that the transistors M1 and M2 in the 2T2R structure memristor unit may also be P-type transistors, which will not be described in detail here.

[0061] Figure 3A A schematic structural diagram of a signal processing circuit based on a memristor array according to at least one embodiment of the present disclosure.

[0062] For example, the signal processing circuit can be located at the sensor end to complete part of the preprocessing operations in the data fusion to be processed, and realize direct real-time processing of the analog signal input by the sensor.

[0063] like Figure 3A As shown, some embodiments of the present disclosure provide a signal processing circuit 300 , including a memristor array 301 , a signal acquisition circuit 302 , a drive control circuit 303 , and an output circuit 304 .

[0064] For example, the signal acquisition circuit 302 is configured to acquire multiple input analog signals. For example, the signal acquisition circuit 302 includes multiple sensors, and the multiple input analog signals can be analog signals collected by the multiple sensors. The signal acquisition circuit 302 inputs the multiple input analog signals received and collected by the multiple sensors into corresponding bit lines in the memristor array 301 to perform K-order convolution processing.

[0065] For example, the output circuit 304 is configured to, under the control of the drive control circuit 303, sequentially obtain K first analog accumulated signals after the memristor array 301 performs K-order convolution processing at a first time interval and sum the K first analog accumulated signals to obtain a first data fusion signal corresponding to multiple input analog signals.

[0066] For example, the drive control circuit 303 includes an array drive control circuit, which is coupled to the memristor array 301 and is configured to set the memristor array 301, write data corresponding to the convolution parameter matrix of the K-order convolution processing into the memristor array 301, and control the operation of the memristor array 301 to perform K-order convolution processing on multiple input analog signals.

[0067] For example, the memristor array 301 may be configured as follows: Figure 2A In the structure shown, the memristor array 301 includes a plurality of memristor cells arranged in an array, and comprises J rows and K columns, i.e., each row has K memristor cells and each column has J memristor cells. The memristor array also includes K source lines, K word lines, and J bit lines. The K source lines correspond to the K columns, the K word lines correspond to the K columns, and the J bit lines correspond to the J rows, where J and K are positive integers.

[0068] For example, the memristor array 301 includes K column signal output terminals, that is, K source lines, and the K column signal output terminals are used to correspondingly output K first analog accumulated signals of the K-order convolution processing.

[0069] For example, the input analog signals are respectively input into the signal acquisition circuit 302 of the memristor array 301, and the drive control circuit 303 controls the operation of the memristor array 301 to perform convolution processing on the multiple input analog signals. According to Kirchhoff's law, the first analog accumulated signal output by the column signal output terminal is the output current of the memristor array 301. The first analog accumulated signal can be obtained according to the following formula: Where, j=1,…,J,k=1,…,K. In the above formula, V j Represents multiple j-th input analog signals, I k G represents the current signal output by the kth column signal output terminal among multiple column signal output terminals. jk represents the overall conductance of the memristor unit located at row j and column k. In this embodiment, the memristor conductance is used to represent the coefficient vector of the filter. According to Kirchhoff's law, a memristor array can perform multiplication and accumulation calculations in parallel.

[0070] Figure 3B A schematic structural diagram of an output circuit provided in at least one embodiment of the present disclosure. Figure 3B In the figure, arrows indicate the direction of signal flow.

[0071] like Figure 3B As shown, output circuit 304 includes K switch sub-circuits 305 and an accumulation circuit 306. The K switch sub-circuits 305 are switch sub-circuit 305_1, switch sub-circuit 305_2, ..., switch sub-circuit 305_K-1, and switch sub-circuit 305_K. The input ends of the K switch sub-circuits 305 are electrically connected to the K column signal output ends, that is, to the column signal output ends SL[0] to SL[K-1] of the memristor array. The output ends of the K switch sub-circuits 305 are all electrically connected to the input end of accumulation circuit 306. For example, the K switch sub-circuits 305 are all electrically connected to the drive control circuit 303 (not shown) to receive control signals from the drive control circuit 303 and perform corresponding operations based on the control signals.

[0072] For example, the K switching sub-circuits 305 are configured to, under the control of the driving control circuit 303, sequentially turn on the connection between the corresponding column signal output terminal and the input terminal of the accumulation circuit 306 according to the first time interval, and transmit the K first analog accumulation signals obtained after the convolution processing of the memristor array 301 to the accumulation circuit 306.

[0073] For example, the accumulation circuit 306 is configured to perform summing processing on the K first analog accumulation signals to obtain a first data fusion signal.

[0074] For example, the switch subcircuit 305 may be a circuit structure including a switch, which can be turned on and off under the control of the drive control circuit 303, thereby connecting and disconnecting the corresponding column signal output terminal and the input terminal of the accumulation circuit 306. Of course, the switch subcircuit can also be implemented as other circuit structures. The embodiments of the present disclosure do not limit the circuit structure of the switch subcircuit 305. It is only necessary that the switch subcircuit 305 can realize the function of connecting and disconnecting.

[0075] For example, the accumulation circuit 306 is an integration circuit and is configured to reset after outputting the first data fusion signal and restart the next round of accumulation operation.

[0076] For example, when the switch sub-circuit 305 is a circuit structure including one switch, the schematic diagram of the signal processing circuit is as follows: Figure 3C As shown below, Figure 3C An exemplary signal processing circuit in an embodiment of the present disclosure is described below.

[0077] like Figure 3C As shown, the signal processing circuit includes a memristor array 301. For example, the number of multiple input analog signals is J. The memristor array 301 includes J rows and K columns of memristor units arranged in an array, the J rows are respectively used to receive the multiple input analog signals, and the K columns correspond to K column signal output terminals. For example, the memristor array includes J bit lines (BL[0], BL[1]...BL[J-1]) and K source lines (SL[0], SL[1]...SL[K-1]), where J is an integer greater than 1 and K is an integer greater than 1.

[0078] For example, the signal acquisition circuit 302 is configured to acquire multiple input analog signals (not shown). The signal acquisition circuit 302 inputs the J input analog signals collected by the J sensors into the memristor array via corresponding bit lines. For example, one end of a memristor is connected to a source line of the memristor array, and the other end is connected to a bit line of the memristor array.

[0079] In this embodiment, Figure 3A The switch subcircuit 305 shown is a switch. Figure 3A The accumulator circuit 306 is an integrator circuit, which is not limited to the structure shown in the figure. The end of each of the K source lines in the memristor array, i.e., the K column signal output terminals, is electrically connected to the input terminal of the integrator circuit 306 through a switch.

[0080] For example, for the i-th column signal output terminal SL[i] of the memristor array, its end is electrically connected to the i-th switch Sk[i] (0≤i≤K-1, and i is a positive integer). When the switch Sk[i] is closed, the potential of the connected source line SL[i] (0≤i≤K-1, and i is a positive integer) is zero, thereby turning on the connection between the column signal output terminal SL[i] and the input terminal of the integration circuit, and transmitting the current signal output by the source line SL[i] to the input terminal of the integration circuit for accumulation calculation.

[0081] For example, in Figure 3A Under the control of the driving control circuit 303 shown, the connections between the K column signal output terminals and the input terminals of the integration circuit are sequentially turned on according to a first time interval τ (i.e., the time interval for closing adjacent switches is τ), and the K first analog accumulated signals obtained after the convolution processing of the memristor array are sequentially transmitted to the integration circuit.

[0082] For example, suppose that starting from time t, switches Sk[0] to Sk[K-1] are closed in sequence, only one switch is closed at the same time, and the closing time of each switch is Δτ in (called sampling and holding time). For example, at time t+i*τ, when the i-th switch Sk[i] is closed, the input analog signals v0(t), v1(t)...v J-1 (t) has been delayed by i*τ, so that the delayed signal of the memristor array bit line input can be obtained by vector c i =[v0(t-iτ),v1(t-iτ),v2(t-iτ),…,v J-1 (t-iτ)] T According to Kirchhoff's law, the current signal s output by the source line SL[i] in the memristor array i is the delayed signal and the conductivity matrix w corresponding to the delayed signal i =[G 0,i ,G 1,i ,G 2,i ,…,G J-1,i ] T The product of the first analog accumulated signal is obtained The first analog accumulated signal s i The signal is transmitted to the integration circuit via the turned-on switch Sk[i] for integration operation.

[0083] The above process is carried out in sequence. After the K switches are closed in sequence, that is, at the time t+Kτ, the integration result s of the integration circuit is out for:

[0084]

[0085] At this time, the integration result of the integration circuit is read and the integration circuit is reset, and the next round of sampling integration is performed again. That is, the period of sampling integration is Kτ.

[0086] According to formula (2) and formula (1), it can be seen that formula (2) and formula (1) have the same form. In formula (2), the conductance value of the memristor represents the coefficient vector of the filter, and the integration result represents a discrete filtering result.

[0087] Figure 3D FIG. 1 shows a sampling schematic diagram of a signal processing circuit provided by at least one embodiment of the present disclosure. Figure 3D As shown, (1) represents the discrete output signal output by the signal processing circuit, and (2) represents the continuous output signal. For example, the continuous output signal in (2) can be obtained by interpolating or performing digital-to-analog conversion on the discrete output signal in (1).

[0088] like Figure 3D As shown, the time interval between adjacent switch closures is τ. After Kτ time, the output result of the integration circuit is read and the integration circuit is reset to enter the next round of sampling integration. Therefore, the sampling time interval of the output signal is Kτ.

[0089] For example, in a process of processing an analog signal, it is usually necessary to first perform analog-to-digital conversion on the analog signal to convert the analog signal into a digital signal, and then process the digital signal to complete the processing of the analog signal.

[0090] The signal processing circuit provided by the embodiments of the present disclosure can directly process analog signals based on a memristor array, without having to convert the analog signals into digital signals before processing, thereby reducing the use of analog-to-digital converters and other hardware resources, reducing the power consumption of the circuit, and using memristors to perform parallel multiplication and addition operations, which can simultaneously improve computing power and energy efficiency.

[0091] However, if Figure 3D As shown, the output sampling interval of the signal processing circuit is Kτ. If the length of the FIR filter increases, the output sampling frequency will decrease linearly. To increase the output sampling frequency, at least one embodiment of the present disclosure further provides a signal processing circuit, wherein the output circuit of the signal processing circuit, under the control of the drive control circuit, sequentially obtains K first analog accumulated signals at a first time interval starting from a first moment. The output circuit is further configured to, under the control of the drive control circuit, sequentially obtain K second analog accumulated signals after the memristor array performs K-order convolution processing at the first time interval starting from a moment i*T after the first moment and sum the K second analog accumulated signals to obtain the i-th second data fusion signal corresponding to the multiple input analog signals, wherein i is a positive integer less than or equal to m-1, and i takes values ​​1, 2, ..., m-1 in chronological order, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and the ratio of the second time interval to the first time interval is N, N=K / m and is a positive integer.

[0092] For example, the sampling time intervals of the first data fusion signal, the first second data fusion signal, the second second data fusion signal, ... the m-1th second data fusion signal outputted in sequence by the signal processing circuit are the second time interval, i.e., Nτ. Since N=K / m, the output sampling frequency of the signal processing circuit is improved.

[0093] The schematic structure diagram of the signal processing circuit is as follows: Figure 4A As shown, in Figure 4A In the figure, arrows indicate the direction of signal flow.

[0094] like Figure 4A As shown, the output circuit 304 includes K switch sub-circuits 305 and an accumulation circuit 306. For example, the K switch sub-circuits 305 are switch sub-circuit 305_1, switch sub-circuit 305_2, ..., switch sub-circuit 305_K-1, and switch sub-circuit 305_K. Each switch sub-circuit 305 includes 1 first input terminal and m first output terminals. The first input terminals of the K switch sub-circuits 305 are electrically connected to the K column signal output terminals one by one, that is, they are electrically connected to the column signal output terminals SL[0] to the column signal output terminals SL[K-1] of the memristor array. For example, for the switch sub-circuit 305_1, its first input terminal is electrically connected to the column signal input terminal SL[0], and the m first output terminals are respectively Sm0[0], Sm0[1], ... Sm0[m-1]. For the switch sub-circuit 305_2, its first input terminal is electrically connected to the column signal input terminal SL[1], and the m first output terminals are respectively Sm1[0], Sm1[1], ... Sm1[m-1], and so on.

[0095] For example, the accumulation circuit 306 includes m accumulation sub-circuits, namely, accumulation sub-circuit 306_1, accumulation sub-circuit 306_2, ..., accumulation sub-circuit 306_m. Each accumulation sub-circuit includes a second input terminal and a second output terminal. For example, accumulation sub-circuit 306_1 includes a second input terminal In[0] and a second output terminal Out[0], accumulation sub-circuit 306_2 includes a second input terminal In[1] and a second output terminal Out[1], and so on.

[0096] For example, the m first output terminals of each switch sub-circuit 305 are electrically connected to the m second input terminals of the m accumulation sub-circuits in a one-to-one correspondence. For example, the m first output terminals Sm0[0], Sm0[1], ... Sm0[m-1] of the switch sub-circuit 305_1 are electrically connected to the second input terminal In[0] of the accumulation sub-circuit 306_1, the second input terminal In[1] of the accumulation sub-circuit 306_2, ... the second input terminal In[m-1] of the accumulation sub-circuit 306_m, respectively. The m first output terminals Sm1[0], Sm1[1], ... Sm1[m-1] of the switch sub-circuit 305_2 are electrically connected to the second input terminal In[0] of the accumulation sub-circuit 306_1, the second input terminal In[1] of the accumulation sub-circuit 306_2, ... the second input terminal In[m-1] of the accumulation sub-circuit 306_m, respectively, and so on.

[0097] For example, each of the m accumulation subcircuits is configured to perform summation processing to obtain a first data fusion signal, a first second data fusion signal, a second second data fusion signal, ..., and an m-1th second data fusion signal, respectively, and output the first data fusion signal, the first second data fusion signal, the second second data fusion signal, ..., and the m-1th second data fusion signal through the m second output terminals of the m accumulation subcircuits. For example, the second output terminal Out[0] of the accumulation subcircuit 306_1 outputs the first data fusion signal, the second output terminal Out[1] of the accumulation subcircuit 306_2 outputs the first second data fusion signal, ..., and the second output terminal Out[m-1] of the accumulation subcircuit 306_m outputs the m-1th data fusion signal. For example, the K switch subcircuits 305 are all electrically connected to the drive control circuit 303 (not shown) to receive control signals from the drive control circuit 303 and perform corresponding operations based on the control signals.

[0098] For example, each switch sub-circuit 305 is configured to, under the control of the drive control circuit 303, at the same time, make the column signal output terminal electrically connected to the switch sub-circuit 305 only conductive to one of the m second input terminals of the accumulation circuit 306, and make the column signal output terminal electrically connected to the switch sub-circuit 305 switched to different second input terminals in sequence at a second time interval.

[0099] For example, for the switch sub-circuit 305_1, the switch sub-circuit 305_1 is configured to, under the control of the drive control circuit 303, make the column signal output terminal SL[0] only conductive to the second input terminal In[0] at the first moment t, only conductive to the second input terminal In[1] at the moment t+T..., and only conductive to the second input terminal In[m-1] at the moment t+(m-1)*T.

[0100] For example, under the control of the drive control circuit 303, starting from a first moment t, the K switch sub-circuits 305 are configured to, at a first time interval, sequentially connect the first input terminals of the K switch sub-circuits 305 to the second input terminal of the first accumulator sub-circuit, thereby sequentially outputting K first analog accumulated signals to the first accumulator sub-circuit; and under the control of the drive control circuit 303, starting from a moment i*T after the first moment t, at the first time interval, sequentially connect the first input terminals of the K switch sub-circuits 305 to the second input terminal of the (i+1)th accumulator sub-circuit, thereby sequentially outputting K second analog accumulated signals to the (i+1)th accumulator sub-circuit, where i is a positive integer less than or equal to m-1, and i takes the values ​​1, 2, ..., m-1 in chronological order, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and the ratio of the second time interval to the first time interval is N, where N=K / m is a positive integer.

[0101] For example, under the control of the driving control circuit 303, at the first moment t, the first input terminal of the switch sub-circuit 305_1 is connected to the second input terminal In[0] of the accumulation sub-circuit 306_1, so that the first analog accumulation signal output by the column signal output terminal SL[0] is output to the accumulation sub-circuit 306_1 via the first output terminal Sm0[0]; at the moment t+τ, the first input terminal of the switch sub-circuit 305_2 is connected to the second input terminal In[0] of the accumulation sub-circuit 306_1, so that the first analog accumulation signal output by the column signal output terminal SL[1] is output to the accumulation sub-circuit 306_1 via the first output terminal Sm1[0]; ..., at the moment t+(K-1)τ, the first input terminal of the switch sub-circuit 305_K is connected to the second input terminal In[0] of the accumulation sub-circuit 306_1, so that the first analog accumulation signal output by the column signal output terminal SL[K-1] is output to the accumulation sub-circuit 306_1 via the first output terminal Sm1[0]. K-1 [0] is output to the accumulation sub-circuit 306_1.

[0102] For example, under the control of the driving control circuit 303, at a moment T after the first moment t, that is, at a moment t+T, the first input terminal of the switch sub-circuit 305_1 is connected to the second input terminal In[1] of the accumulation sub-circuit 306_2, so that the second analog accumulation signal output by the column signal output terminal SL[0] is output to the accumulation sub-circuit 306_2 via the first output terminal Sm0[1]; at a moment t+T+τ, the first input terminal of the switch sub-circuit 305_2 is connected to the second input terminal In[1] of the accumulation sub-circuit 306_2, so that the second analog accumulation signal output by the column signal output terminal SL[1] is output to the accumulation sub-circuit 306_2 via the first output terminal Sm1[1], ..., at a moment t+T+(K-1)τ, the first input terminal of the switch sub-circuit 305_K is connected to the second input terminal In[1] of the accumulation sub-circuit 306_2, so that the second analog accumulation signal output by the column signal output terminal SL[K-1] is output to the accumulation sub-circuit 306_2 via the first output terminal Sm1[1]. K-1 [1] is output to the accumulation sub-circuit 306_2.

[0103] For example, under the control of the driving control circuit 303, at time (m-1)T after the first time t, that is, at time t+(m-1)T, the first input terminal of the switch sub-circuit 305_1 is connected to the second input terminal In[m-1] of the accumulator sub-circuit 306_m, so that the second analog accumulated signal output by the column signal output terminal SL[0] is output to the accumulator sub-circuit 306_m via the first output terminal Sm0[m-1]; at time t+(m-1)T+τ, the first input terminal of the switch sub-circuit 305_2 is connected to the second input terminal In[m-1] of the accumulator sub-circuit 306_m. The second input terminal In[m-1] of the circuit 306_m is turned on, so that the second analog accumulated signal output by the column signal output terminal SL[1] is output to the accumulation sub-circuit 306_m via the first output terminal Sm1[m-1]. ..., at time t+(m-1)T+(K-1)τ, the first input terminal of the switch sub-circuit 305_K is turned on to the second input terminal In[m-1] of the accumulation sub-circuit 306_m, so that the second analog accumulated signal output by the column signal output terminal SL[K-1] is output to the accumulation sub-circuit 306_m via the first output terminal Sm1[m-1]. K-1 [m-1] is output to the accumulation sub-circuit 306_m.

[0104] For example, the closing time of each switch is Δτ in (called the sample and hold time).

[0105] like Figure 4B As shown, the signal processing circuit includes a memristor array 301 and a signal acquisition circuit 302. For the description of the memristor array 301 and the signal acquisition circuit 302, please refer to Figure 3C The relevant content will not be repeated any more.

[0106] In this embodiment, Figure 4A Each switching subcircuit 305 shown includes a 1-to-m switch, Figure 4A The accumulator circuit 306 shown includes m integrating circuits, that is, each accumulator sub-circuit is an integrating circuit, for example, Figure 4B As shown, the accumulation sub-circuit 306_1 is the integration circuit Int[0], the accumulation sub-circuit 306_m is the integration circuit Int[m-1], and so on. It should be noted that the integration circuit is not limited to the structure shown in the figure, and can also be other circuit structures that can achieve the accumulation function.

[0107] For example, the end of each of the K source lines in the memristor array 301, i.e., the K column signal output terminals, are connected to m integrating circuits via a 1-to-m switch. For example, the i-th column signal output terminal SL[i] is electrically connected to one input channel of a 1-to-m switch, and the m channels of the 1-to-m switch are respectively connected to the first output terminal Sm of the i-th switch sub-circuit. i [0], the first output terminal Sm i [1]... and the first output terminal Sm i [m-1], the first output terminal Sm i [0], first output terminal Sm i [1]... and the first output terminal Sm i [m-1] is electrically connected to the second input terminal In[0] of the integration circuit Int[0], the second input terminal In[1] of the integration circuit Int[1], ... the second input terminal In[m-1] of the integration circuit Int[m-1], respectively, where i is greater than or equal to 0 and less than m.

[0108] It should be noted that, in this embodiment, the number of source lines K and the number of integration circuits m satisfy K=Nm, where N represents the ratio of the sampling frequency of the input signal to the sampling frequency of the output signal, and both m and N are positive integers. For example, for a 1-to-m switch Sk[i] electrically connected to the i-th column signal output terminal SL[i] of the memristor array, the 1-to-m switch switches to the next adjacent channel every second time interval, i.e., Nτ. For example, the 1-to-m switch Sk[i] switches to the first output terminal Sm at time t0. i [0], thereby conducting the connection between the column signal output terminal SL[i] and the second input terminal In[0] of the integration circuit Int[0], so that the current signal output by the column signal output terminal SL[i] is transmitted to the integration circuit Int[0] for accumulation; the 1-to-m switch Sk[i] is switched to the first output terminal Sm at time t0+Nτ i [1], thereby conducting the connection between the column signal output terminal SL[i] and the second input terminal In[1] of the integration circuit Int[1], so that the current signal output by the column signal output terminal SL[i] is transmitted to the integration circuit Int[1] for accumulation; the 1-to-m switch Sk[i] is switched to the first output terminal Sm at time t0+2Nτ i [2], thereby turning on the connection between the column signal output terminal SL[i] and the second input terminal In[2] of the integration circuit Int[2], so that the current signal output by the column signal output terminal SL[i] is transmitted to the integration circuit Int[2] for accumulation. The subsequent process is similar and will not be repeated here.

[0109] For example, under the control of the drive control circuit 303, each integration circuit is connected to a different column signal input terminal at a first time interval τ. For example, at the first time t, the 1-to-m switch Sk[0] is switched to the first output terminal Sm0[0], thereby outputting the first analog accumulated signal output from the first column signal output terminal SL[0] to the integration circuit Int[0]. At the time t+τ, the 1-to-m switch Sk[1] is switched to the first output terminal Sm1[0], thereby outputting the first analog accumulated signal output from the second column signal output terminal SL[1] to the integration circuit Int[0]. And so on, until at the time t+(K-1)τ, the 1-to-m switch Sk[K-1] is switched to the first output terminal Sm K-1 [0], thereby outputting the first analog accumulated signal output by the K-th column signal output terminal SL[K-1] to the integration circuit Int[0], and resetting the integration circuit Int[0] after the integration circuit Int[0] outputs the first filtering result Out[0].

[0110] For the switching connection process of other 1-choose-m switches, refer to 1-choose-m switch Sk[0] and Figure 4A The relevant content will not be repeated any more.

[0111] For example, assume that, starting at a first time t, the signal processing circuit performs signal processing as described above. That is, any integration circuit receives a first analog signal or a second analog signal at a first time interval τ, and outputs an integration result, i.e., a filtering result, after K*τ, and resets. Because the time at which two adjacent integration circuits receive the first analog signal or the second analog signal differs by a second time interval Nτ, there is a delay of Nτ between each integration circuit. Therefore, the time at which each integration circuit outputs its filtering result differs by Nτ, resulting in an output sampling interval of Nτ.

[0112] For example, when the number of integrating circuits is K, that is, m=K, then N=K / m=1, the ratio of the input signal sampling frequency to the output signal sampling frequency is 1, and thus the output signal sampling time interval is also τ.

[0113] In this embodiment, by sequentially reading the output results of the integration circuit, the filtering results with the sampling interval shortened to Nτ can be continuously output, and by configuring the number K of the accumulation sub-circuits, the output sampling time interval can be shortened to the same as the input sampling time interval, thereby increasing the sampling frequency, and the sampling frequency is no longer restricted by the filter order K.

[0114] Figure 4C Shown Figure 4B The switch connection diagram of the signal processing circuit shown below is Figure 4C Describe the connection process of K 1-choose-m switches.

[0115] exist Figure 4C In, Sm mN-N [0] represents the first output terminal Sm of the mN-mth switch sub-circuit mN-N [0] connects the column signal output terminal SL[mN-N] to the integration circuit Int[0], that is, at time t0, the integration circuit Int[0] receives the first analog accumulation signal Sm from the column signal output terminal SL[mN-N]. mN-N+1 [0] represents the first output terminal Sm of the mN-m+1th switch sub-circuit mN-N+1 [0] connects the column signal output terminal SL[mN-N+1] to Int[0], that is, at time t0+τ, the integration circuit Int[0] receives the first analog accumulation signal from SL[mN-N+1], and so on.

[0116] It should be noted that although the integration circuit Int[0] outputs the integration result and performs a reset at the moment t0+(N-1)τ, it actually has already started the integration operation before the first moment t (not shown), that is, at t-(KN)τ, it is connected to the column signal output terminal SL[0] through the first output terminal Sm0[0] of the first switching sub-circuit, and the integration calculation starts from the first moment t.

[0117] Figure 4D A schematic diagram illustrating a design flow of a signal processing circuit provided by at least one embodiment of the present disclosure is shown.

[0118] For example, Figure 4D As shown, the design process of the signal processing circuit includes steps S401 to S404.

[0119] Step S401: Obtain the filter order K, the sampling frequency f1 of the input signal, the sampling frequency f2 of the output signal, and the filter coefficients.

[0120] For example, in some embodiments, the user determines the sampling frequency f1 of the input signal and the sampling frequency f2 of the output signal according to usage needs, and determines the FIR filter order K, filter coefficients, etc. according to filtering requirements.

[0121] Step S402: Calculate a frequency ratio N=f1 / f2 according to the sampling frequency f1 of the input signal and the sampling frequency f2 of the output signal.

[0122] That is, the sampling time interval of the output signal divided by the sampling time interval of the input signal is N.

[0123] Step S403: Calculate the number of accumulating sub-circuits m=K / N according to the filter order K and the frequency ratio N.

[0124] Step S404: setting the accumulation circuit to include m accumulation sub-circuits, setting the output circuit to include K switch sub-circuits, and setting each switch sub-circuit to include m first output terminals.

[0125] The specific connection method between the switch sub-circuit, the memristor array and the accumulation sub-circuit is referred to the above embodiment and will not be repeated here.

[0126] To better understand Figure 4B The signal processing circuit shown is described by taking K=6 and m=3 as an example.

[0127] Figure 5A A signal processing circuit provided by at least one embodiment of the present disclosure is shown.

[0128] According to the usage requirements, the filter order K is determined to be 6, the sampling time interval of the input signal is τ, and the sampling time interval of the output signal is 2τ, so N is determined to be 2, m is determined to be K / N is determined to be 3, that is, the accumulation circuit includes 3 accumulation sub-circuits, the output circuit includes 6 switch sub-circuits, and each switch sub-circuit includes 3 first output terminals.

[0129] like Figure 5A As shown, the signal processing circuit includes a memristor array 301, which includes 6 rows and 6 columns of memristor units arranged in an array, 6 source lines (SL[0], SL[1]...SL[5]), 6 word lines and 6 bit lines (word lines and bit lines are not shown), the 6 bit lines respectively receive input analog signals from 6 sensor channels (CH[0], CH[1]...CH[5]), and the output ends of the 6 source lines respectively correspond to the 6 column signal output ends (SL[0], SL[1]...SL[5]).

[0130] The signal acquisition circuit 302 (not shown) is used to acquire input analog signals. These input analog signals are input into the memristor array 301 from corresponding bit lines through six sensor channels.

[0131] In this embodiment, Figure 4A The switch subcircuit 305 shown includes a 1-to-3 switch. Figure 4A Accumulator circuit 306 shown includes three integration circuits, which are not limited to the structure shown in the figure. The output of each of the six source lines in memristor array 501, i.e., the six column signal outputs, is connected to the three integration circuits via a 1-to-3 switch. For example, each switch sub-circuit includes three first output terminals. For example, switch sub-circuit 305_1 includes a first output terminal Sm0[0], a first output terminal Sm0[1], and a first output terminal Sm0[2].

[0132] For example, the column signal output terminal SL[0] is connected to the integration circuit Int[0] through the first output terminal Sm0[0] of the switch sub-circuit 305_1, the column signal output terminal SL[0] is connected to the integration circuit Int[1] through the first output terminal Sm0[1] of the switch sub-circuit 305_1, and the column signal output terminal SL[0] is connected to the integration circuit Int[2] through the first output terminal Sm0[2] of the switch sub-circuit 305_1.

[0133] For example, for the column signal output terminal SL[0] of the memristor array, its end is electrically connected to the switch Sk[0] (respectively connected to the first output terminals Sm0[0], Sm0[1], and Sm0[2] of the switch sub-circuit 305_1), and the switch Sk[0] switches to a different first output terminal every 2τ, that is, at the first moment t, the 1-to-3 switch Sk[0] is switched to the first output terminal Sm0[0], thereby outputting the first analog accumulated signal output from the first column signal output terminal SL[0] to the second input terminal In[0] of the integration circuit Int[0]. At the moment t+2τ, the 1-to-3 switch Sk[0] is switched to the first output terminal Sm0[0]. Terminal Sm0[1], thereby outputting the first analog accumulated signal output by the first column signal output terminal SL[0] to the second input terminal In[1] of the integration circuit Int[1]. At time t+4τ, the 1-to-3 switch Sk[0] is switched to be connected to the first output terminal Sm0[2], thereby outputting the first analog accumulated signal output by the first column signal output terminal SL[0] to the second input terminal In[2] of the integration circuit Int[2]. When the connection between the column signal output terminal SL[0] and the second input terminal of the integration circuit is turned on, the current signal output by the column signal output terminal SL[0] is transmitted to the second input terminal of the integration circuit for accumulation calculation.

[0134] For example, in Figure 4A Under the control of the driving control circuit 303 shown, each integration circuit is connected to a different column signal input terminal at a first time interval τ. For example, at the first moment t, the 1-to-3 switch Sk[0] is switched to the first output terminal Sm0[0], thereby outputting the first analog accumulated signal output from the first column signal output terminal SL[0] to the integration circuit Int[0]. At the moment t+τ, the 1-to-3 switch Sk[1] is switched to the first output terminal Sm1[0], thereby outputting the first analog accumulated signal output from the second column signal output terminal SL[1] to the integration circuit Int[0]. At time t+2τ, the 1-to-3 switch Sk[2] is switched to the first output terminal Sm2[0], thereby outputting the first analog accumulated signal outputted by the third column signal output terminal SL[2] to the integration circuit Int[0]. This is analogous to the case until at time t+5τ, the 1-to-3 switch Sk[5] is switched to the first output terminal Sm5[0], thereby outputting the first analog accumulated signal outputted by the sixth column signal output terminal SL[5] to the integration circuit Int[0]. The integration circuit Int[0] outputs the first filtered result Out[0] and resets the integration circuit Int[0]. Since the multi-way selection switch switches once every 2τ, the output results of the multiple integration circuits are also separated by 2τ.

[0135] Figure 5B Shown Figure 5A The switch connection diagram of the signal processing circuit is shown.

[0136] like Figure 5B As shown, for example, the integration circuit Int[0] is connected to different signal input terminals at intervals of a first time interval τ. For example, as previously described, at the first moment t, the switch Sk[0] is switched to be connected to the first output terminal Sm0[0], thereby outputting the first analog accumulated signal outputted from the first column signal output terminal SL[0] to the integration circuit Int[0]. At the moment t+τ, the switch Sk[0] is switched to be connected to the first output terminal Sm1[0], thereby outputting the first analog accumulated signal outputted from the second column signal output terminal SL[1] to the integration circuit Int[0], and so on, until at the moment t+5τ, the 1-to-3 switch Sk[0] is switched to be connected to the first output terminal Sm5[0], thereby outputting the first analog accumulated signal outputted from the sixth column signal output terminal SL[5] to the integration circuit Int[0]. There is a delay of 2τ between the integration circuits Int[0], Int[1] and Int[2]. Therefore, at time t+2τ, the 1-to-3 switch Sk[1] is switched to be connected to the first output terminal Sm0[1], thereby outputting the second analog accumulated signal outputted from the first column signal output terminal SL[0] to the integration circuit Int[1]. At time t+3τ, the 1-to-3 switch Sk[2] is switched to be connected to the first output terminal Sm1[1], thereby outputting the second analog accumulated signal outputted from the second column signal output terminal SL[1] to the integration circuit Int[1]. And so on, until at time t+7τ, the 1-to-3 switch Sk[6] is switched to be connected to the first output terminal Sm5[1], thereby outputting the second analog accumulated signal outputted from the sixth column signal output terminal SL[5] to the integration circuit Int[1]. At time t+7τ, the 1-to-3 switch Sk[6] is switched to be connected to the first output terminal Sm5[1], thereby outputting the second analog accumulated signal outputted from the sixth column signal output terminal SL[5] to the integration circuit Int[1]. Take the value of Int[1] and reset Int[1]; at time t+4τ, the 1-to-3 switch Sk[3] is switched to the first output terminal Sm0[2], thereby outputting the second analog accumulated signal output by the first column signal output terminal SL[0] to the integration circuit Int[2]; at time t+5τ, the 1-to-3 switch Sk[4] is switched to the first output terminal Sm1[2], thereby outputting the second analog accumulated signal output by the second column signal output terminal SL[1] to the integration circuit Int[2], and so on, until at time t+9τ, the 1-to-3 switch Sk[6] is switched to the first output terminal Sm5[2], thereby outputting the second analog accumulated signal output by the sixth column signal output terminal SL[5] to the integration circuit Int[2]; at time t+9τ, the value of Int[2] is read and Int[2] is reset.

[0137] For example, the drive control circuit 303 includes an array drive control circuit, which is coupled to the memristor array and configured to set the memristor array, write data corresponding to the convolution parameter matrix of the K-order convolution processing into the memristor array, and control the operation of the memristor array to perform K-order convolution processing on multiple input analog signals.

[0138] For example, the driver control circuit 303 includes a source line driver circuit, a word line driver circuit, and a bit line driver circuit. For example, the source line driver circuit is configured to control the output signals of K source lines of the memristor array. For example, the word line driver circuit is configured to apply control signals to J word lines of the memristor array. For example, the bit line driver circuit is configured to apply input signals to J bit lines of the memristor array.

[0139] At least one embodiment of the present disclosure provides a signal processing circuit for broadband beamforming. This method uses multiple sets of integrator circuits to perform time-sharing sampling at the signal output terminals of multiple columns of a memristor array, eliminating the need for data conversion circuits and temporary data storage in traditional implementations (such as DSP). This effectively utilizes the multiplication and addition operations of the memristor array to achieve highly parallel beamforming filtering. The output analog signal can be fed through a simple signal conditioning circuit into a neural network computing unit based on the memristor array for back-end processing, facilitating the efficient construction of intelligent sensing terminals integrating sensors and data processing units.

[0140] For example, as described above, the conductance value of the memristor can be changed by applying a set voltage or a reset voltage to the memristor through the source line SL and the bit line BL, so that each memristor has a different conductance value, that is, by changing the conductance value of the memristor to map the coefficient vector of the filter to the corresponding memristor.

[0141] In some embodiments of the present disclosure, a first memristor pair consisting of two first memristors can be used to correspond to an element in a coefficient vector of a filter so that the coefficient vector includes a negative value, thereby realizing a richer and more complex filter using multiple first memristors.

[0142] For example, one element in a filter coefficient vector can be implemented by two memristors. For example, two memristor arrays can be used to form multiple memristor pairs, each memristor pair including two memristors. For example, the two memristors are positioned directly adjacent to each other in the memristor array. In another example, one memristor in each memristor pair is configured to receive an input analog signal, and the other memristor in the pair is configured to receive an inverted input analog signal corresponding to the input analog signal.

[0143] Accordingly, in this embodiment, the signal acquisition circuit 302 is further configured to respectively acquire a plurality of inverted input analog signals of the plurality of input analog signals.

[0144] Below through Figure 6A 、 Figure 6B Let's specifically illustrate an example of a memristor array that can realize negative-valued elements.

[0145] Figure 6A A schematic structural diagram of a memristor array provided in at least one embodiment of the present disclosure.

[0146] like Figure 6A As shown, memristor 701 and memristor 702 can form a memristor pair, and the conductance value of memristor 701 is expressed as G 11 , the conductance of the memristor 702 is expressed as G 12 . Since the memristor 702 is connected to an inverter, when the memristor 701 receives a positive input analog signal from the sensor channel CH[0], the inverter can flip the polarity of the voltage signal input from the sensor channel, so that the memristor 702 receives a negative input analog signal. For example, at time t, the input analog signal received by the memristor 701 is represented by v0(t), and the memristor 702 receives the inverted input analog signal of v0(t), that is, -v0(t). The memristor 701 and the memristor 702 are connected to two different SLs, and the input analog signal generates an output current through the memristor. Figure 3A At the end of SL, the output current through memristor 701 and the output current through memristor 702 are superimposed. Therefore, the result of the multiplication and accumulation calculation of memristor 701 and memristor 702 is v0(t)G 11 +(-v0(t))G 12 , that is, v0(t)(G 11 -G 12 ). Thus, the memristor pair composed of memristor 701 and memristor 702 can correspond to an element of the coefficient vector of the filter, and the element is G 11 -G 12 , by configuring G 11 -G 12 The numerical relationship can realize negative elements.

[0147] Figure 6B A schematic diagram of another memristor array provided according to at least one embodiment of the present disclosure.

[0148] like Figure 6B As shown, for example, memristor 701 and memristor 702 can form a memristor pair, and the conductance value of memristor 701 is expressed as G 11 , the conductance of the memristor 702 is expressed as G 12 .and Figure 6A The difference is that memristor 702 is not connected to the inverter, so when memristor 701 receives a positive input analog signal from sensor channel CH[0], memristor 702 also receives a positive input analog signal. For example, at time t, the input analog signal received by memristor 701 is represented by v0(t), and the input analog signal received by memristor 702 is also represented by v0(t). Memristor 701 and memristor 702 are connected to two different SLs, and at the end of the SL, the output current passing through memristor 701 and the output current passing through memristor 702 are subtracted. Therefore, the result of the multiplication and accumulation calculation of memristor 701 and memristor 702 is v0(t)G 11 -v0(t)G 12 , that is, v0(t)(G 11 -G 12 ). Therefore, the memristor pair composed of memristor 701 and memristor 702 can correspond to an element of the coefficient vector of the filter, and the element is G 11 -G 12 , by configuring G 11 -G 12 The numerical relationship can realize negative elements.

[0149] In addition, you can also use Figure 2C The 2T2R structured memristor unit shown corresponds to an element in the coefficient vector of the filter, so that the coefficient vector includes negative values, thereby being able to use the 2T2R structured memristor unit to implement a richer and more complex filter. Figure 6C 、 Figure 6D An example of constructing a signal processing circuit using a 2T2R structured memristor unit is described below.

[0150] Figure 6C A signal processing circuit constructed using a 2T2R structured memristor unit is shown.

[0151] like Figure 6C As shown, for example, a 2T2R structured memristor unit includes two memristors, namely memristor 701 and memristor 702, and the conductance value of memristor 701 is expressed as G 11 , the conductance of the memristor 702 is expressed as G 12 , the memristor 701 can be Figure 2C R1 in the figure, the memristor 702 can be Figure 2C R2 in . For example, since memristor 702 is connected to an inverter, when memristor 701 receives a positive input analog signal from sensor channel CH[0], the inverter can flip the polarity of the voltage signal input from the sensor channel, so that memristor 702 receives a negative input analog signal. For example, at time t, the input analog signal received by memristor 701 is represented by v0(t), and memristor 702 receives the inverted input analog signal of v0(t), that is, -v0(t). Memristor 701 and memristor 702 are connected to the same SL, and the output current passing through memristor 701 and the output current passing through memristor 702 are superimposed at the end of the SL. Therefore, the result of the multiplication and accumulation calculation of memristor 701 and memristor 702 is v0(t)G 11 +(-v0(t))G 12 , that is, v0(t)(G 11 -G 12 ). Therefore, the memristor unit of the 2T2R structure including the memristor 701 and the memristor 702 can correspond to an element of the coefficient vector of the filter, and the element is G 11 -G 12 , by configuring G 11 -G 12 The numerical relationship can realize negative elements.

[0152] Figure 6D Another signal processing circuit constructed using a 2T2R structured memristor unit is shown.

[0153] like Figure 6D As shown, for example, a 2T2R structured memristor unit includes two memristors, namely memristor 701 and memristor 702, and the conductance value of memristor 701 is expressed as G 11 , the conductance of the memristor 702 is expressed as G 12 .and Figure 6C The difference is that memristor 702 is not connected to the inverter, so when memristor 701 receives a positive input analog signal from sensor channel CH[0], memristor 702 also receives a positive input analog signal. For example, at time t, the input analog signal received by memristor 701 is represented by v0(t), and the input analog signal received by memristor 702 is also represented by v0(t). Memristor 701 and memristor 702 are connected to different SLs, and at the end of the SL, the output current passing through memristor 701 and the output current passing through memristor 702 are subtracted. Therefore, the result of the multiplication and accumulation calculation of memristor 701 and memristor 702 is v0(t)G 11 -v0(t)G 12 , that is, v0(t)(G 11 -G 12 ). Therefore, the memristor unit of the 2T2R structure including the memristor 701 and the memristor 702 can correspond to an element of the coefficient vector of the filter, and the element is G 11 -G 12 , by configuring G 11 -G 12 The numerical relationship can realize negative elements.

[0154] For example, the memristor array in the signal processing circuit provided in at least one embodiment of the present disclosure may adopt any of the structures provided in 6A to 6D to realize negative values ​​of elements in the filter vector, and the present disclosure does not impose any limitation on this.

[0155] For example, when this signal processing circuit is applied to a beamforming system, it can also be applied to adaptive beamforming. For example, after performing a filtering operation for a period of time, the updated value of the filter coefficient is calculated using methods such as the least mean square method (LMS) and the linearly constrained minimum variance (LCMV). The updated filter coefficient value is mapped to the corresponding memristor unit through the array drive control circuit, and the filtering operation continues. It should be noted that this signal processing circuit can also be used to build systems with multiple beamforming arrays, such as generalized sidelobe cancellation.

[0156] Figure 7 A schematic flowchart of a signal processing method provided by at least one embodiment of the present disclosure is shown.

[0157] For example, Figure 7 As shown, the signal processing method provided by the embodiment of the present disclosure includes steps S601 to S603.

[0158] Step S601: Acquire multiple input analog signals.

[0159] For example, the multiple input analog signals may be analog signals collected by multiple sensors.

[0160] Step S602: performing K-order convolution processing on a plurality of input analog signals using a memristor array, where K is an integer greater than 1.

[0161] For example, a memristor array can refer to Figure 2A Schematic diagram of the memristor array shown.

[0162] For example, step S602 may include: inputting multiple input analog signals into multiple column signal input terminals of the set memristor array, controlling the operation of the memristor array to perform convolution processing on the multiple analog signals, and obtaining multiple second analog accumulated signals or second analog accumulated signals after performing K-order convolution processing at multiple row signal output terminals of the memristor array.

[0163] Specifically, multiple input analog signals can be applied to multiple bit lines of the set memristor array respectively, and at the same time, an open signal can be applied to multiple word lines of the memristor array to detect and obtain multiple current signals, second analog accumulated signals or second analog accumulated signals at multiple column signal output ends of the memristor array.

[0164] Step S603: sequentially obtaining K first analog accumulated signals after the memristor array performs K-order convolution processing at a first time interval and summing the K first analog accumulated signals to obtain a first data fusion signal corresponding to the multiple input analog signals.

[0165] For example, the signal processing method can be applied to the above reference Figures 3A to 3C In step S601, for example, a plurality of input analog signals may be acquired by the signal acquisition circuit 302 in the signal processing circuit; in step S603, for example, Figures 3A to 3C The output circuit 304 in the signal processing circuit shown is used to obtain a first data fusion signal corresponding to multiple input analog signals.

[0166] The following combination Figures 3A to 3C , an embodiment of the signal processing method provided by at least one embodiment of the present disclosure is briefly described, and details can be found in the previous description.

[0167] For example, the memristor array 301 includes K column signal output terminals, each of which is configured to output K first analog accumulated signals subjected to a K-order convolution process. The output circuit 304 includes K switch sub-circuits 305 and an accumulation circuit 306. The input terminals of the K switch sub-circuits 305 are electrically connected to the K column signal output terminals, respectively, and the output terminals of the K switch sub-circuits 305 are electrically connected to the input terminals of the accumulation circuit 306. In this case, step S603 may include: utilizing the K switch sub-circuits to sequentially connect the corresponding column signal output terminals to the input terminals of the accumulation circuit at a first time interval, thereby transmitting the K first analog accumulated signals obtained after the convolution process on the memristor array to the accumulation circuit; and utilizing the accumulation circuit to sum the K first analog accumulated signals to obtain a first data fusion signal.

[0168] The signal processing method provided in the above embodiment directly performs analog operations on the received input analog signal through a memristor array, avoiding the introduction of a data conversion circuit, delaying and temporarily storing the input analog signal through a post-sampling method, and utilizing the memristor array to implement highly parallel multiplication and addition operations, thereby simultaneously improving computing power and energy efficiency.

[0169] For example, starting from a first moment t, K first analog accumulated signals are obtained in sequence according to a first time interval. The signal processing method provided by at least one embodiment of the present disclosure also includes step S604: starting from a moment i*T after the first moment t, K second analog accumulated signals after the memristor array performs K-order convolution processing are obtained in sequence according to the first time interval, and the K second analog accumulated signals are summed up to obtain the i-th second data fusion signal corresponding to multiple input analog signals, wherein i is a positive integer less than or equal to m-1, and i takes values ​​of 1, 2, ...m-1 in sequence, m is a positive integer greater than 1 and less than or equal to K, T represents the second time interval, and the ratio of the second time interval to the first time interval is N, N=K / m and is a positive integer.

[0170] For example, the signal processing method can be applied to the above reference Figures 4A to 4C The signal processing circuit described herein. In step S601, for example, the signal acquisition circuit 302 in the signal processing circuit may acquire multiple input analog signals. In step S603, for example, the output circuit 304 in the signal processing circuit may acquire a first data fusion signal, a first second data fusion signal, ..., and an m-1th second data fusion signal corresponding to the multiple input analog signals. Furthermore, the output sampling time intervals between the first data fusion signal, the first second data fusion signal, ..., and the m-1th second data fusion signal are the second time intervals.

[0171] The following combination Figures 4A to 4C , an embodiment of the signal processing method provided by at least one embodiment of the present disclosure is briefly described, and details can be found in the previous description.

[0172] For example, memristor array 301 includes K column signal output terminals, each of which is used to output K first analog accumulated signals subjected to a K-order convolution process. Output circuit 304 includes K switch subcircuits 305 and an accumulation circuit 306. Each switch subcircuit 305 includes a 1-to-m switch, and accumulation circuit 306 includes m integration circuits. Each switch subcircuit 305 includes a first input terminal and m first output terminals. The first input terminals of the K switch subcircuits 305 are electrically connected in a one-to-one correspondence with the K column signal output terminals, and the m first output terminals of each switch subcircuit 305 are electrically connected in a one-to-one correspondence with the m second input terminals of the m accumulation subcircuits. In this case, step S604 may include: starting from a first moment t, sequentially connecting the first input terminals of the K switch sub-circuits 305 to the second input terminal of the first accumulator sub-circuit at a first time interval, thereby sequentially outputting the K first analog accumulator signals to the first accumulator sub-circuit; and under the control of the drive control circuit 303, starting from a moment i*T after the first moment t, sequentially connecting the first input terminals of the K switch sub-circuits 305 to the second input terminal of the (i+1)th accumulator sub-circuit at a first time interval, thereby sequentially outputting the K second analog accumulator signals to the (i+1)th accumulator sub-circuit, where i is a positive integer less than or equal to m-1, and i takes the values ​​1, 2, ..., m-1 in chronological order, m is a positive integer greater than 1 and less than or equal to K, T represents a second time interval, and the ratio of the second time interval to the first time interval is N, and N=K / m is a positive integer.

[0173] The signal processing method provided by the above embodiment can continuously output the output results of the integration circuit by sequentially reading the output results. The sampling interval is shortened to Nτ, thereby increasing the sampling frequency.

[0174] Regarding this disclosure, the following points need to be explained:

[0175] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0176] (2) For the sake of clarity, the thickness and size of layers or structures in the drawings used to describe embodiments of the present invention are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly on" or "under" the other element, or intervening elements may be present.

[0177] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0178] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.< / k> < / j> < / k>

Claims

1. A signal processing circuit comprising: Drive control circuit; a signal acquisition circuit configured to acquire a plurality of input analog signals; A memristor array, wherein the memristor array is configured to perform K-order convolution processing on the multiple input analog signals, where K is an integer greater than 1; The output circuit is configured to, under the control of the drive control circuit, sequentially obtain, at a first time interval, K first analog accumulated signals after the memristor array performs the K-order convolution processing and sum the K first analog accumulated signals to obtain a first data fusion signal corresponding to the multiple input analog signals.

2. The signal processing circuit according to claim 1, wherein: The output circuit, under the control of the drive control circuit, sequentially obtains the K first analog accumulated signals at the first time interval starting from the first moment, The output circuit is further configured to, under the control of the drive control circuit, sequentially obtain, at the first time interval, K second analog accumulated signals after the memristor array performs the K-order convolution process, and sum the K second analog accumulated signals to obtain an i-th second data fusion signal corresponding to the multiple input analog signals, starting from the i*T time after the first time. Wherein, i is a positive integer less than or equal to m-1, and i takes the values ​​1, 2, ...m-1 in chronological order, m is a positive integer greater than 1 and less than or equal to K, T represents the second time interval, and the ratio of the second time interval to the first time interval is N, N = K / m and is a positive integer.

3. The signal processing circuit according to claim 1, wherein: The memristor array includes K column signal output terminals, and the K column signal output terminals are used to correspondingly output the K first analog accumulated signals of the K-order convolution processing. The output circuit includes K switch sub-circuits and an accumulation circuit. The input terminals of the K switch sub-circuits are electrically connected to the K column signal output terminals one by one, and the output terminals of the K switch sub-circuits are electrically connected to the input terminal of the accumulator circuit. The K switch sub-circuits are configured to, under the control of the drive control circuit, sequentially connect the corresponding column signal output terminals to the input terminals of the accumulator circuit at the first time interval, and transmit the K first analog accumulated signals obtained after the convolution processing of the memristor array to the accumulator circuit. The accumulation circuit is configured to perform summing processing on the K first analog accumulation signals to obtain the first data fusion signal.

4. The signal processing circuit according to claim 3, wherein: The accumulator circuit is an integration circuit, and the drive control circuit is further configured to reset the integration circuit after obtaining the first data fusion signal.

5. The signal processing circuit according to claim 2, wherein: The memristor array further includes K column signal output terminals, and the K column signal output terminals are used to correspondingly output the K second analog accumulated signals or the K first analog accumulated signals of the K-order convolution processing. The output circuit includes K switch sub-circuits and an accumulation circuit. Each switch sub-circuit includes 1 first input terminal and m first output terminals. The accumulation circuit includes m accumulation sub-circuits, each of the m accumulation sub-circuits includes a second input terminal and a second output terminal, The first input terminals of the K switch sub-circuits are electrically connected to the K column signal output terminals in a one-to-one correspondence. The m first output terminals of each switch sub-circuit are electrically connected to the m second input terminals of the m accumulation sub-circuits in a one-to-one correspondence. Each of the m accumulation sub-circuits is configured to perform addition processing to respectively obtain the first data fusion signal, the first second data fusion signal, the second second data fusion signal..., and the m-1th second data fusion signal, and output the first data fusion signal, the first second data fusion signal, the second second data fusion signal..., and the m-1th second data fusion signal through the m second output ends of the m accumulation sub-circuits. The signal processing circuit according to claim 5 , wherein: Each switching subcircuit is configured as: Under the control of the driving control circuit, at the same time, the column signal output terminal electrically connected to the switch sub-circuit is connected to only one of the m second input terminals of the accumulator circuit, and The column signal output terminal electrically connected to the switch sub-circuit is switched to be connected to different second input terminals in sequence according to the second time interval.

7. The signal processing circuit according to claim 5, wherein: Under the control of the drive control circuit, starting from the first moment, the K switch sub-circuits are further configured to, at the first time interval, sequentially connect the K column signal output terminals to the second input terminal of the first accumulation sub-circuit, thereby sequentially outputting K first analog accumulation signals to the first accumulation sub-circuit; as well as Under the control of the drive control circuit, starting from the moment i*T after the first moment, the K column signal output terminals are sequentially connected to the second input terminal of the (i+1)th accumulation sub-circuit according to the first time interval, so that the K second analog accumulation signals are sequentially output to the (i+1)th accumulation sub-circuit.

8. The signal processing circuit according to any one of claims 5 to 7, wherein: The switch subcircuit includes a 1-to-m switch circuit, The 1-to-m switch circuit includes m channels, and the m channels are electrically connected to the m first output terminals respectively.

9. The signal processing circuit according to any one of claims 5 to 7, wherein: The accumulator subcircuit is an integrating circuit, The driving control circuit is further configured to perform a reset operation on the integration circuit after the integration circuit outputs the first data fusion signal or the i-th second data fusion signal.

10. The signal processing circuit according to any one of claims 1 to 7, wherein: The drive control circuit includes an array drive control circuit, The array drive control circuit is coupled to the memristor array and is configured to set the memristor array, write data of a convolution parameter matrix corresponding to a K-order convolution process into the memristor array, and control the operation of the memristor array to perform the K-order convolution process on the multiple input analog signals.

11. The signal processing circuit according to claim 3 or 5, wherein: The number of the multiple input analog signals is J, The memristor array includes J rows and K columns of memristor units arranged in an array, the J rows are respectively used to receive the multiple input analog signals, and the K columns respectively correspond to the K column signal output terminals.

12. A signal processing method, comprising: Acquire multiple input analog signals; Performing K-order convolution processing on the multiple input analog signals using a memristor array, where K is an integer greater than 1; At a first time interval, K first analog accumulated signals after the memristor array performs the K-order convolution processing are sequentially obtained and summed up to obtain a first data fusion signal corresponding to the multiple input analog signals.

13. The signal processing method according to claim 12, wherein: Starting from the first moment, the K first analog accumulated signals are sequentially obtained at the first time interval. The method further comprises: Starting from a time i*T after the first time, according to the first time interval, sequentially obtaining K second analog accumulated signals after the memristor array performs the K-order convolution processing and summing the K second analog accumulated signals to obtain an i-th second data fusion signal corresponding to the multiple input analog signals, Where i is a positive integer less than or equal to m-1, and i takes the value of 1, 2, ...m-1 in sequence. m is a positive integer greater than 1 and less than or equal to K, T represents the second time interval, and the ratio of the second time interval to the first time interval is N, where N=K / m and is a positive integer.

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