Memory device for processing unassigned row addresses

Abstract

This application relates to the handling of unallocated row addresses in a memory. A semiconductor device is disclosed that includes circuitry for reducing unstable or metastable states in a logic circuit in response to receiving an unallocated row address. The semiconductor device may include one or more logic circuits configured to adjust a particular address-based control signal based on the unallocated row address to reduce processing. For example, the one or more logic circuits may override the handling of the unallocated row address to provide a control signal corresponding to an allocated row address, which may allow the semiconductor device to operate in a known state rather than performing operations based on the unallocated row address.

Description

Technical Field

[0001] The present disclosure relates to memories, and more particularly, to handling unallocated row addresses in a memory. Background Art

[0002] High data reliability, high-speed memory access, low power, and reduced chip size are characteristics required of semiconductor memories. As memory density increases, the number of address bits can be increased to accommodate additional addressable memory cells. However, in some memory systems, the width of the command and address buses can remain constant, so read addresses can be continuously provided over the command and address buses to multiple sub-components. A semiconductor device can perform a memory access operation based on the read address. Some specific combinations of read address bits can be unallocated or illegal (e.g., there is no memory cell or cells assigned to the read address). When a semiconductor device performs a memory access operation using an illegal read address, some downstream circuitry can enter an unknown or metastable state. When the circuitry of a semiconductor device enters a metastable state, the data provided from the semiconductor device can be unreliable or unpredictable, which can cause a memory system interruption. Summary of the Invention

[0003] One aspect of the present disclosure provides an apparatus including: an address decoder configured to receive a row address corresponding to a memory access operation, where the address decoder is configured to decode the row address to provide a decoded row address; and a section determination circuit configured to receive the decoded row address and determine a column segmentation address based on the decoded row address, where determination of column redundancy corresponding to the memory access operation is based on the column segmentation address, and where the section determination circuit further includes a logic circuit configured to cause the column segmentation address to be overwritten in response to determining that the decoded row address is an unallocated row address.

[0004] Another aspect of the present disclosure provides an apparatus including: an address decoder configured to receive a row address corresponding to a memory access operation, where the address decoder is configured to decode the row address to provide a decoded row address; a data buffer configured to synchronously store data at a first position indicated by an input pointer and output the stored data from a second position indicated by an output pointer; and a row logic circuit configured to cause the input pointer configured to control the data buffer to be adjusted in response to determining that the decoded row address is an unallocated row address.

[0005] Another aspect of the present disclosure provides a method, which includes: decoding a row address corresponding to a memory access operation received with an activation command at a semiconductor device to provide a decoded row address; determining whether the decoded row address is an unallocated row address based on a comparison between a first bit of the row address and a second bit of the row address; setting a column segment address to a first value based on the decoded row address in response to determining that the decoded row address is an allocated row address; setting the column segment address to a second value in response to determining that the decoded row address is an unallocated row address; and selecting a column address for a corresponding memory access operation based on the column segment address.

[0006] Another aspect of the present disclosure provides a method, which includes: decoding a row address corresponding to a memory access operation received with an activation command at a semiconductor device to provide a decoded row address; determining whether the decoded row address is an unallocated row address based on a comparison between a first bit of the row address and a second bit of the row address; adjusting an output pointer indicating an output from a data buffer of the semiconductor device in response to a memory access command; and adjusting an input pointer indicating a position for receiving data to be input at the data buffer in response to determining that the decoded row address is an unallocated row address. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic block diagram of a semiconductor device according to an embodiment of the present disclosure is shown.

[0008] Figure 2A A block diagram of a command decoder 200 according to an embodiment of the present disclosure is depicted.

[0009] Figure 2B Depicts an exemplary timing diagram 201 showing an ACT CMD signal provided from a command decoder 200 according to an embodiment of the present disclosure Figure 2A to

[0010] Figure 3 A block diagram of a portion of a semiconductor device 300 according to an embodiment of the present disclosure is depicted.

[0011] Figure 4 A block diagram of a column segment 0 decoder 400 according to an embodiment of the present disclosure is depicted.

[0012] Figure 5 A block diagram of a column segment 1 decoder 500 according to an embodiment of the present disclosure is depicted.

[0013] Figure 6 is a schematic block diagram of 600 according to an embodiment of the present disclosure.

[0014] Figure 7A block diagram depicting a memory cell array 700 and a portion of a logic circuit 704 of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 8A A block diagram depicting a portion of a semiconductor device 800 according to an embodiment of the present disclosure.

[0016] Figure 8B Depicts an exemplary timing diagram showing the control of input and output pointers associated with a DQ FIFO buffer for Figure 8A . Detailed Description

[0017] Certain details are set forth below to provide a sufficient understanding of embodiments of the present disclosure. However, it will be clear to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. Additionally, the specific embodiments of the present disclosure described herein are provided by way of example and should not be used to limit the scope of the present disclosure to these specific embodiments.

[0018] The present disclosure describes a semiconductor device that includes circuitry for reducing unstable or metastable states in a logic circuit in response to receiving an unassigned row address. An unassigned row address is a combination of address bit values of memory cells that are not assigned to a specific row in a memory array. The row address may be combined with a bank address and a column address to target a specific group of memory cells in the memory cell array. The row address (and bank address) may be received with an activation command ACT, and the column address may be received with a read or write command. In some memory systems, the ACT command may be a four-cycle command (e.g., received within 4 clock cycles), or may be considered two consecutive two-cycle commands (e.g., ACT-1 is received within the first 2 clock cycles and then ACT-2 is received within the subsequent 2 clock cycles). In some applications, a portion of the row address may be received with the ACT-1 command and a portion of the row address may be received with the ACT-2 command. Thus, the complete row address may not be available until the ACT-2 command is received.

[0019] Typically, when an ACT command and a row address are received, the row address can be decoded to provide the decoded row address along with the internal ACT command to the downstream circuitry. When an unassigned row address is received, the internal ACT command can be blocked to prevent the downstream circuitry from performing an operation based on the unassigned row address. However, in some instances, the detection of an unassigned row address can depend on the relative values of bits received with an ACT-1 command (e.g., RA16) and bits received with an ACT-2 command (e.g., RA17). In such cases, the internal ACT command can be provided before it is detected that the row address is unassigned. As a result, the semiconductor device may not be able to prevent some operations from being performed based on the unassigned row address. In some instances, the downstream circuitry performing an operation based on the unassigned row address can cause the downstream circuitry to enter an unknown state or a metastable state. When the circuitry of the semiconductor device enters a metastable state, the operation of the semiconductor device can be unreliable or unpredictable, which can cause an interruption in the operation of the semiconductor device or the installed memory system.

[0020] Accordingly, the semiconductor device can include one or more logic circuits configured to adjust a particular address-based control signal based on the unassigned row address to reduce processing. For example, the one or more logic circuits can override the processing of the unassigned row address to provide a control signal corresponding to an assigned row address, which can allow the semiconductor device to operate in a known state (e.g., as compared to performing an operation based on an unassigned row address). That is, the adjustment of the address-based control signal may not necessarily be intended to “correct” the unassigned row address to a particular target or assigned address. Instead, as an example, the intent can be to prevent the circuitry of the semiconductor device from attempting to determine whether a column address is redundant and / or to provide an unknown column address targeted at activating an undefined column in the memory cell array. Such operations can cause the semiconductor device to enter an unknown state or a metastable state. In some instances, an unassigned row address can be detected based on the relative values of two bits of the row address. In some instances, the two bits can include one bit received with an ACT-1 command and one bit received with an ACT-2 command. The one or more logic circuits can perform a bit-by-bit comparison between the two bits of the row address to provide an unassigned row address signal. In some instances, the two bits include row address bits RA16 and RA17.

[0021] In some instances, the one or more logic circuits may be included in an address logic circuitry configured to identify a target column and a target column section or segment, such as a section determination circuit and / or a column logic circuit. In response to detecting an unassigned row address, the one or more logic circuits may cause the address logic circuitry to override a column-based control signal. The column-based control signal may be provided to a column decoder circuitry. For example, typically, the section determination circuit may be configured to determine a target column section of a memory cell array based on specific bits of a row address (e.g., via one or more decoder circuits) and provide a column section address indicating the target column section of the memory array.

[0022] However, in the decoder logic of the section determination circuit, some bit combinations of the specific bits of the row address may be undefined or unassigned. Thus, when the section determination circuit attempts to determine a column section address based on an undefined bit combination, the output of the section determination may be unpredictable or metastable. Accordingly, the section determination circuit may further include the one or more logic circuits configured to determine whether the row address is an unassigned row address and, in response to determining that the row address is an unassigned row address, cause one or more decoder circuits in the decoder circuit to override corresponding bits of the column section address with a specific value corresponding to a valid or designated column section address. The one or more logic circuits may each perform a logical bit-by-bit (e.g., AND logic) comparison between two bits of the row address to detect whether the row address is unassigned. In some instances, the two bits include row address bits RA16 and RA17. As previously described, the two bits may be received at the semiconductor device at different times, such as the first bit received with an ACT-1 command and the second bit received with an ACT-2 command. Thus, the one or more logic circuits may prevent the semiconductor device from entering a metastable state by attempting to activate an undefined column.

[0023] As an additional precaution against performing operations based on an unassigned row address, the semiconductor device may include logic circuitry for disabling column selection operations on the memory cell array. For example, the memory array may be divided into portions or sides, and the portions or sides may be enabled independently by respective array side enable signals. A command decoder (e.g., via a mode register) may provide the array side enable signals to indicate whether one side (e.g., X8 configuration) or both sides (e.g., X16 configuration) of the memory cell array are enabled. The column logic circuitry may be configured to enable column selection operations to facilitate activating a column on one or both sides of the memory cell array based on the array side enable signals during a memory access operation. However, to reduce unpredictable behavior upon receipt of an unassigned row address, the column logic circuitry system may further include logic circuitry that overrides the array side enable signals to disable both sides of the memory array in response to detecting an illegal row address, thereby preventing activation of any column within the memory cell array. The logic circuitry may perform a logical bit-by-bit (e.g., AND logic) comparison between two bits of the row address to detect whether the row address is unassigned. In some instances, the two bits include row address bits RA16 and RA17. As previously described, the two bits may be received at the semiconductor device at different times, such as the first bit received with an ACT-1 command and the second bit received with an ACT-2 command. Thus, the one or more logic circuits may prevent the semiconductor device from entering a metastable state by attempting to activate an undefined column.

[0024] Additionally, for performing a read operation, a data terminal (DQ) first-in first-out (FIFO) buffer may be used to temporarily store the read data before transferring the read data to a data bus via the data terminal DQ. The operation of the DQ FIFO buffer may be controlled by an input pointer and an output pointer for respectively indicating a current input storage location and an output storage location. The DQ FIFO buffer may be a synchronous buffer configured to update both the input pointer and the output pointer simultaneously. Thus, during a normal read operation, both the input and output pointers are adjusted (e.g., incremented or decremented) simultaneously to remain synchronized for the next access operation when writing and reading data. The input pointer may be adjusted based on a column enable signal. The column enable signal may be set in response to an internal ACT signal and a row select signal.

[0025] However, when a row address is not allocated, the row select signal can remain cleared; preventing the column enable signal from being set, which can prevent the input pointer from being adjusted. The output pointer can be adjusted in response to a read command from the command decoder. Thus, the output pointer can be adjusted independently of the determination as to whether the row address is unallocated. When the output pointer is adjusted without adjusting the input pointer, the relationship between the input pointer and the output pointer may become out of sync, which can result in the inability to identify the appropriate location of data stored in the DQ FIFO buffer. Accordingly, the semiconductor device can further include logic circuitry configured to adjust the input pointer when an unallocated read address is detected by overriding the row select signal. The logic circuitry can perform a logical bitwise (e.g., AND logic) comparison between two bits of the row address to detect whether the row address is unallocated. In some instances, the two bits include row address bits RA16 and RA17. As previously described, the two bits can be received at the semiconductor device at different times, such as the first bit received with an ACT-1 command and the second bit received with an ACT-2 command.

[0026] Figure 1 FIG. 4 shows a schematic block diagram of a semiconductor device 100 in accordance with an embodiment of the present disclosure. The semiconductor device 100 includes a memory die. The memory die can include a command / address input circuit 102, an address decoder 104, a command decoder 106, a clock input circuit 112, an internal clock generator 114, a row logic circuit 130, a section determination circuit 140, a column address redundancy control circuit 142, a column logic circuit 144, a row decoder 108, a column decoder 110, a latency counter 150, a memory cell array 118, a read / write amplifier 120, an IO circuit 122, a DQ FIFO buffer 160, and a power circuit 190.

[0027] In some embodiments, the semiconductor device 100 may include, but is not limited to, for example, a dynamic random access memory (DRAM) device integrated into a single semiconductor chip, such as double data rate (DDR) DDR4, DDR5, low power (LP) DDR. The die may be mounted on an external substrate such as a memory module substrate, a motherboard, etc. The semiconductor device 100 may further include a memory cell array 118. The memory cell array 118 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL (e.g., digit lines, access lines, data I / O lines, etc.), and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word line WL is performed by the row decoder 108, while selection of the bit line BL (along with the column select signal CS) is performed by the column decoder 110. Sense amplifiers SAMP are positioned near their corresponding bit lines BL and are connected to at least one corresponding local I / O line based on the CS signal, and the I / O line is in turn coupled to a corresponding main I / O line pair of at least two main I / O line pairs through a transmission gate TG acting as a switch.

[0028] In some embodiments, the memory cell array 118 may include a memory array mat having corresponding digit lines and memory cells. The memory array mats may be separated by control circuitry that includes sense amplifiers SAMP connected to corresponding subsets (e.g., even or odd) of bit lines connecting adjacent memory array mats to perform read operations on the corresponding memory cells.

[0029] The semiconductor device 100 may employ a plurality of external terminals, the plurality of external terminals including address and command terminals coupled to a command / address (C / A) bus, clock terminals CK and / CK, data terminals DQ, DQS, and DM, power supply terminals VDD, VSS.

[0030] Address signals and bank address signals can be supplied externally to the command / address terminals via the command / address bus 110. The address signals and bank address signals supplied to the address terminals are transmitted to the address decoder 104 through the command / address input circuit 102. The address decoder 104 receives the address signals and decodes the address signals to provide decoded address signals ADD. The ADD signals include decoded row address RA signals and decoded column address CA signals. The decoded RA signals are provided to the row decoder 108 and the decoded CA signals are provided to the column decoder 110 through the control circuit 142 for column address redundancy. The address decoder 104 can be configured to determine whether a row address is allocated and can enable the row select signal RS in response to determining that a row address is allocated. Otherwise, the address decoder 104 can disable the RS signal. The address decoder 104 also receives the bank address signals and provides the bank address signals to the row decoder 108 and / or the column decoder 110.

[0031] Command signals can be further supplied externally, for example, from a memory controller, to the command / address terminals. The command signals can be provided to the command decoder 106 via the C / A bus through the command / address input circuit 102. The command decoder 106 decodes the command signals to generate various internal commands / signals, which include an ACT command signal (e.g., with a row address), a read command signal RD or a write command signal (e.g., with a column address) for selecting columns and / or word lines, and a column command signal Read / Write for selecting bit lines, such as a read command or a write command, etc. The row logic circuit 130 can receive the ACT command from the column decoder 106, as well as the decoded RA signals and the RS signal from the address decoder 104, and can provide a column enable signal CE and an ACT status signal IACT in response to the decoded RA signals and the RS signal.

[0032] The segment determination circuit 140 can determine a column segment address (e.g., the column segment 0 / 1 signal from the segment determination circuit 140), and the control circuit 142 for column address redundancy can determine whether the decoded CA signal has been replaced by the redundant CA RedCA based on the column segment 0 / 1 signal, the read command RD, and the CA fuse data CAFD signal. The column logic 144 can be configured to receive the memory array P and M side enable signals PEnD and MEnD (e.g., indicating whether one side (e.g., X8 configuration) or both sides (e.g., X16 configuration) of the memory cell array 118 have been enabled), the RD command, the CE signal, and the decoded RA signal. The PEn signal and the MEn signal can be provided from a mode register (not shown) of the command decoder 106. The column logic 144 can be configured to provide PEnD and MEnD to the column decoder 110 based on the RA signal and the PEn signal and the MEn signal, respectively. The column logic 144 can be further configured to provide the column select enable signal CYE and the column read activation up and down signals CRACTU / D to the column decoder 110 based on the RD signal and the CE signal.

[0033] Accordingly, when a read command is issued and the read command is timely supplied to RA and CA, the readout data is read from the memory cells specified by these row addresses and column addresses in the memory cell array 118. The read data DQ is output to the outside from the data terminals DQ (data), DQS (data strobe), and DM (data mask) through the read / write amplifier 120 and the IO circuit 122. Similarly, when a write command is issued and this command is timely supplied to the row address and the column address and then the write data is supplied to the data terminals DQ, DQS, DM, the write data is received by the data receiver in the IO circuit 122 and supplied to the memory cell array 118 through the IO circuit 122 and the read / write amplifier 120 and written into the memory cells specified by the row address and the column address.

[0034] In some instances, a memory access operation (e.g., read, write, refresh, etc.) can be initiated in response to receiving an activation command ACT along with a row address (e.g., and a bank address) via the C / A bus at the semiconductor device 100. The semiconductor device 100 can subsequently receive a column address with a corresponding read RD, write, etc. command. In some instances, the complete ACT command can be received over multiple clock cycles (e.g., via a combination of two two-cycle ACT-1 and ACT-2 commands), where a portion of the RA is received across the multiple clock cycles. For example, a first portion of the row address can be received with the ACT-1 command, while a second portion of the row address can be received with the ACT-2 command. The RA can be combined with a bank address (not shown) and the CA to target a specific group of memory cells in the memory cell array 118. In some instances, the RA can be set to an unassigned row address. An unassigned row address is a combination of address bit values that are not assigned to a particular row of memory cells in the memory cell array 118.

[0035] Typically, upon receiving the ACT command and the RA, the address decoder 104 can decode the RA and provide the RA to the downstream circuitry, and the command decoder 106 can provide an internal ACT command. When an unassigned row address is received, the internal ACT command can be blocked to prevent the downstream circuitry (e.g., row logic circuit 130, section determination circuit 140, control circuit 142 for column address redundancy, column logic 144, etc.) from performing operations based on the unassigned row address. However, in some instances, the detection of an unassigned row address can depend on the relative values of the bits received with the ACT-1 command (e.g., RA16) and the bits received with the ACT-2 command (e.g., RA17). In such cases, the internal ACT command from the command decoder can be provided before it is detected that the row address is unassigned and blocked. Thus, the semiconductor device 100 may not be able to prevent some operations from being performed based on an unassigned row address. In some instances, the downstream circuitry performing operations based on an unassigned row address may cause the downstream circuitry to enter an unknown state or a metastable state. When the circuitry of the semiconductor device 100 enters a metastable state, the operation of the semiconductor device may be unreliable or unpredictable, which may cause an interruption in the operation of the semiconductor device 100 or the installed memory system.

[0036] For example, an unassigned RA can be provided to the section determination circuit 140, and the decoder of the section determination circuit 140 can determine the column segmentation 0 / 1 signal based on an undefined combination of bit values from the unassigned RA. The undefined combination of bit values may cause the column segmentation 0 / 1 signal to be set to an undefined combination of bit values, which may cause the control circuit 142 for column address redundancy to operate in a metastable state. To prevent the metastable states of the section determination circuit 140 and the control circuit 142 for column address redundancy, the section determination circuit 140 can include one or more logic circuits configured to adjust the column segmentation 0 / 1 signal to indicate an assigned column segmentation in response to detecting an unassigned RA signal. Since the column segmentation 0 / 1 signal provided to the control circuit 142 for column address redundancy corresponds to an assigned column segmentation, the control circuit 142 for column address redundancy can avoid entering a metastable state. The assigned column segmentation 0 / 1 signal caused by the one or more logic circuits may not be intended to "correct" the unassigned column segmentation 0 / 1 signal to a specific assigned bit combination. Instead, the adjustment of the column segmentation 0 / 1 signal caused by the one or more logic circuits may be intended to allow the circuitry of the control circuit 142 for column address redundancy to remain in a known or predictable state. The logic circuit can be configured to detect whether the RA is an unassigned row address based on the relative values of two bits of the decoded RA signal. In some instances, the two bits can include one bit received with an ACT-1 command (e.g., RA16) and one bit received with an ACT-2 command (e.g., RA17). The one or more logic circuits can perform a bit-by-bit comparison between the two bits of the row address.

[0037] Additionally, column logic 144 can be configured to disable column selection operations on memory cell array 118 by disabling memory cell array 118. Memory cell array 118 can be divided into an M side and a P side, and the M side and the P side can be enabled independently by MEnD signal and PEnD signal. Column logic 144 can provide a signal that enables column selection operations performed on one or both of the M side and the P side through column decoder 110 based on whether the M side and / or the P side of memory cell array 118 is enabled. In some instances, column logic 144 can provide MEnD signal and PEnD signal based on MEn signal and PEn signal together with a logic circuit configured to override MEn signal and PEn signal when set to disable both sides of memory cell array 118 from performing column selection operations. The logic circuit can perform a logical bit-by-bit (e.g., AND logic) comparison between two bits of a row address to detect whether the row address is unassigned. In some instances, the two bits include row address bits RA16 and RA17. As previously described, the two bits can be received at the semiconductor device at different times, such as the first bit received with an ACT-1 command and the second bit received with an ACT-2 command.

[0038] Additionally, for a read operation, DQ FIFO buffer 160 can be used to temporarily store the read data before transferring the read data to the data bus through data terminal DQ. The operation of DQ FIFO buffer 160 can be controlled by an input IN pointer and an output OUT pointer for respectively indicating a current input storage location and an output storage location. DQ FIFO buffer 160 can be a synchronous buffer configured to update the IN pointer and the OUT pointer simultaneously. Thus, during a normal read operation, both the IN pointer and the OUT pointer are adjusted (e.g., incremented or decremented) simultaneously to maintain synchronization for the next access operation when writing and reading data. The IN pointer can be adjusted based on the CE signal from row logic circuit 130. The CE signal can be set in response to an ACT command and an RS signal.

[0039] However, when a row address is not allocated, the RS signal can remain cleared; preventing the CE signal from being set, which can prevent the IN pointer from being adjusted. The OUT pointer can be adjusted in response to an RD command from the command decoder, which is delayed according to the wait time counter 150. Thus, the OUT pointer can be adjusted independently of the determination as to whether the RA is unallocated. When the OUT pointer is adjusted without adjusting the IN pointer, the relationship between the IN pointer and the OUT pointer may become out of sync, which can result in the inability to identify the appropriate location of the data stored in the DQ FIFO buffer 160. Thus, the row logic circuit 130 can further include logic circuitry configured to cause the CE signal to be set (e.g., overriding the RS signal) when an unallocated RA is detected. Because the CE signal is set, the column logic 144 can be configured to adjust the IN pointer. The logic circuitry can perform a logical bit-by-bit (e.g., AND logic) comparison between two bits of the row address to detect whether the row address is unallocated. In some instances, the two bits include row address bits RA16 and RA17. As previously described, the two bits can be received at the semiconductor device at different times, such as the first bit received with an ACT-1 command and the second bit received with an ACT-2 command.

[0040] Turning to the external terminals included in the semiconductor device 100, an external clock signal and a complementary external clock signal are supplied to the clock terminals CK and / CK, respectively. The external clock signal (including the complementary external clock signal) can be supplied to the clock input circuit 112. The clock input circuit 112 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generator 114, and thus a phase-controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. Although not limited thereto, a delay locked loop (DLL) circuit, a duty cycle correction (DCC) circuit, or a combination thereof can be used as the internal clock generator 114. The phase-controlled internal clock signal LCLK can be used as a timing signal for determining the output timing of the read data.

[0041] Power supply potentials VDD and VSS are supplied to the power supply terminals. These power supply potentials VDD2 and VSS are supplied to the power circuit 190. The power circuit 190 generates various internal potentials VKK, VARY, VPERI, etc. based on the power supply potentials VDD2 and VSS. The internal potential VKK is mainly used in the row decoder 108, the internal potential VARY is mainly used in the sense amplifiers included in the memory cell array 118, and the internal potential VPERI is used in many other circuit blocks.

[0042] It is also possible to supply power potentials VDDQ and VSSQ to the power terminals. These power potentials VDDQ and VSSQ are supplied to the IO circuit 122. The power potentials VDDQ and VSSQ are typically the same potentials as the power potentials VDD2 and VSS, respectively. However, using dedicated power potentials VDDQ and VSSQ for the IO circuit 122 prevents the power noise generated by the IO circuit 122 from propagating to other circuit blocks.

[0043] Figure 2A A block diagram of a command decoder 200 in accordance with an embodiment of the present disclosure is depicted. Figure 2B Depicts an exemplary timing diagram 201 showing the ACT CMD signal provided from the Figure 2A command decoder 200 in accordance with an embodiment of the present disclosure. The command decoder may include an Act2 control circuit 210, an AND gate 220, a RA17 decoder circuit 230, a RA16 decoder circuit 240, and a NAND gate 250. Figure 1 The command decoder 106 of may implement the command decoder 200.

[0044] The Act2 control circuit 210 receives an Act1 signal based on an ACT-1 command received via a command and address bus (e.g., Figure 1 the CA bus of ). In response to the Act1 command, the RA16 decoder circuit 240 may receive row address bit 16RA16 from the CA bus and provide the row address bit to the NAND gate 250. In response to an internal clock signal ICLK, the Act2 control circuit 210 may provide Act2 based on a predetermined amount of time after receiving the Act1 command. The Act2 command may correspond to an ACT-2 command received via the command address. In response to the Act2 command, the RA17 decoder circuit 230 may receive row address bit 17RA17 from the CA bus and provide the row address bit to the NAND gate 250. The NAND gate 250 may be configured to detect whether the received row address is an unassigned row address based on the relative values of the RA16 bit and the RA17 bit of the row address. Thus, the NAND gate 250 may perform a logical NAND bitwise comparison between the RA16 signal and the RA17 signal to provide an active low ACT Block signal. For example, when both the RA16 bit and the RA17 bit have a first (e.g., high or set) logic value, the ACTBlockF signal may be set to a second (e.g., low or cleared) logic value. Otherwise, ACTBlockF may be set to the first logic value.

[0045] The AND gate 220 can provide the ACTCMD signal based on a bitwise logical AND comparison between the Act2 signal and the ACTBlockF signal. However, since the RA17 decoder circuit 230 is configured to determine the RA17 signal in response to the Act2 signal, the AND gate 220 can provide the ACT CMD at the output through the RA17 decoder circuit 230, the RA16 decoder circuit 240, and the NAND gate 250 before determining whether the row address is an unassigned row address. Thus, the ACT CMD corresponding to the unassigned row address can be output from the AND gate 220 before it may be blocked by the NAND gate 250.

[0046] As previously described, Figure 2B the timing diagram 201 depicts the operation of the command decoder 200 in response to receiving an unassigned row address, which can be indicated by both the RA16 signal and the RA17 signal having a first logic value. Refer to Figure 2A and 2B , before time T1, the NAND gate 250 is configured to set the ACTBlockF signal to a first logic value based on both the RA16 signal and the RA17 signal having a second logic value. Also before time T1, an external ACT-1 command can be received along with a portion of the row address including bit RA16. At time T1, the Act1 signal can transition to a first logic value in response to the ACT-1 command and the ICLK signal. At time T2, the RA16 decoder circuit 240 can transition the RA16 signal to a first logic value based on the received row address and in response to the Act1 signal.

[0047] Between time T2 and T3, an external ACT-2 command can be received along with a portion of the row address including bit RA17. At time T3, the Act2 control circuit 210 can cause the Act2 signal to transition to a first logic value in response to the ACT-2 command and the ICLK signal. At time T4, the AND gate 220 can provide the ACT CMD based on the Act2 signal having a first logic value and the ACTBlockF signal having a high logic value. At time T5, the RA17 decoder circuit 230 can transition the RA17 signal to a first logic value based on the received row address and in response to the Act2 signal. At time T6, in response to both the RA16 and RA17 signals having a first logic value, the NAND gate 250 can transition the ACTBlockF signal to a second logic value. In response to the ACTBlockF signal transitioning to the second logic value, the AND gate 220 can transition the ACT CMD signal to a second logic value. Thus, as shown in the timing diagram 201, the ACT CMD signal can be provided from the command decoder 200 before detecting an unassigned row address, which may cause downstream circuitry to operate in a metastable state.

[0048] The applicant notes that timing diagram 201 is exemplary and that the relative timing between signal transitions is not intended to be to scale. Different relative timing relationships may be implemented without departing from the scope of the present disclosure.

[0049] Figure 3 A block diagram of a portion of a semiconductor device 300 in accordance with an embodiment of the present disclosure is shown. The semiconductor device 300 includes a section determination circuit 340 coupled to a column redundancy detection circuit 342. Figure 1 The semiconductor device 100 may implement the semiconductor device 300.

[0050] The section determination circuit 340 may include a logic circuit 341 coupled to a decoder circuit 344. The logic circuit 341 may be configured to perform a bitwise AND logic comparison between row address RA signals RA16 and RA17 to provide an unassigned RA signal UARA. The UARA signal may be set (e.g., a first or high logic value) when both the RA16 and RA17 signals are set. Otherwise, the UARA signal may be cleared (e.g., a second or low logic value).

[0051] The decoder circuit 344 may be configured to receive the UARA signal, RA signals RA13, RA15, RA16, and RA17, and section bits SEC<6:0>. The SEC<6:0> bits may be based on the RA signals RA12 - RA0. The decoder circuit 344 may be configured to provide column segment 0 signals ColSeg0<1:0> and column segment 1 signals ColSeg1<6:0> based on the received signals. In some instances, the decoder circuit 344 may include respective decoder circuits for each of the ColSeg0<1:0> and ColSeg1<6:0> signals (e.g., nine decoder circuits).

[0052] The column redundancy detection circuit 342 may be configured to receive the ColSeg0<1:0> and ColSeg1<6:0> signals, column address fuse data CAFD, and column address CA. The column redundancy detection circuit 342 may be configured to determine whether the CA has been replaced by a redundant CA based on the ColSeg0<1:0> and ColSeg1<6:0> signals and the CAFD. In response to determining that the CA has been replaced by a redundant CA, the column redundancy detection circuit 342 may set a column redundancy hit signal. Otherwise, the column redundancy hit signal may be cleared. The redundant CA (e.g., Figure 1 RedCA) may be selected in response to the column redundancy hit signal being set.

[0053] In operation, during a memory access operation, a series of operations occur within semiconductor device 300, where subsequent operations sometimes depend on information from previous operations in the series. In some instances, a portion of RA can be received over multiple clock cycles with an ACT command. For example, in some instances, RA13, RA15, and RA16 can be received before RA17. In some instances, when both RA17 and RA16 are set, the entire RA can be unallocated RA. Thus, in response to RA17 and RA16 being set, logic circuit 341 can set UARA to indicate unallocated RA.

[0054] In the absence of the UARA signal, unallocated RA can cause decoder circuit 344 to clear all of the ColSeg0<1:0> and ColSeg1<6:0> signals, which would correspond to unallocated column segment addresses. Unallocated column segment addresses can cause decoder circuit 344 to enter a metastable state, which can cause column redundancy detection circuit 342 to provide unpredictable results. Thus, the UARA signal can be provided to at least one decoder for the ColSeg0<1:0> signal and to at least one decoder for the ColSeg1<6:0> signal of column redundancy detection circuit 342. In response to the UARA signal indicating unallocated RA, the at least one decoder for the ColSeg0<1:0> signal of decoder circuit 344 can force-set the corresponding signal in the ColSeg0<1:0> signal. For example, Figure 4 A block diagram of column segment 0 decoder 400 in accordance with an embodiment of the present disclosure is depicted. As Figure 4 shown, decoder 410 is configured to set the ColSeg0<1> signal in response to RA17 and RA13 being set or in response to RA16 being set. Decoder 412 is configured to set the ColSeg0<0> signal in response to both RA17 and RA16 being cleared or in response to RA17 being set and RA13 being cleared. Additionally, decoder 412 is configured to set the ColSeg0<0> signal in response to the UARA signal being set (e.g., detecting unallocated RA). The UARA signal can be set based on a bitwise AND comparison between the RA17 signal and the RA16 signal (e.g., via AND gate logic circuit 404). Applicants hereby solemnly state that the specific logic statements for each of decoder 410 and decoder 412 are exemplary, and other logical combinations of the RA signals can be applied without departing from the scope of the present disclosure. Applicants also note that logic circuit 404 can alternatively or additionally be coupled to decoder 412 to set the ColSeg0<1> signal in response to detecting an unallocated row address.

[0055] Similarly, in response to a UARA signal indicating an unassigned RA, at least one decoder of the decoder circuit 344 for the ColSeg1<6:0> signal may force-set the corresponding signal in the ColSeg1<6:0> signal. For example, Figure 5 FIG. depicts a block diagram of a column segment 1 decoder 500 according to an embodiment of the present disclosure. As Figure 5 shown, decoders 512(0)-(6) may be configured to set the corresponding ColSeg1<6:0> signals in response to the logical relationship between the RA17, RA16, RA13, and SEC<6:0> signals. It should be noted that for each corresponding individual logical statement depicted on the left side of the corresponding decoder in decoders 512(0)-(6), if the logical statement is TRUE, it represents a combination of signal values that causes the corresponding signal in the ColSeg1<6:0> signal to be set. When one of the logical statements in the corresponding set of logical statements is TRUE, each decoder in decoders 512(0)-(6) is configured to set the corresponding ColSeg1<6:0> signal. In addition to the corresponding logical statement, decoder 512(0) is also configured to set the ColSeg1<0> signal in response to the UARA signal being set (e.g., an unassigned RA is detected). The UARA signal may be set based on a bitwise AND comparison between the RA17 signal and the RA16 signal (e.g., via AND gate 304). The applicant solemnly submits that the specific logical statements for each decoder in decoders 512(0)-(6) are exemplary, and other logical combinations of the RA and Sec<6:0> signals may be applied without departing from the scope of the present disclosure. The applicant also notes that the logic circuit 504 may alternatively or additionally be coupled to one or more of the decoders 512(0)-(6) to set the corresponding ColSeg0<6:1> signals in response to detecting an unassigned row address.

[0056] Returning to Figure 3 , the column redundancy detection circuit 342 may detect whether a CA has been replaced by a redundant CA based on the ColSeg0<1:0> and ColSeg1<6:0> signals and the CAFD. For example, Figure 6 FIG. depicts a schematic block diagram of a column redundancy detection circuit 600 according to an embodiment of the present disclosure. As Figure 6As shown, the column redundancy detection circuit 600 includes corresponding fuse data decoders 610(0)-(6) configured to provide alternative CAs and 620 with 622 and a decoder, where 620 is configured to perform a bitwise exclusive-OR comparison between the alternative CA and the CA to determine whether the CA has been replaced by a redundant CA. In response to detecting a match between the CA and the alternative CA, 620 can set a column redundancy hit signal. Each fuse data decoder in the fuse data decoders 610 can include corresponding ColSeg0 decoder circuits 612(0)-(6) coupled to corresponding ColSeg1 decoder circuits 614(0)-(6). Each decoder circuit in the ColSeg0 decoder circuits 612(0)-(6) includes a corresponding inverter 613(0)-(6), which is enabled to invert the value of CAFD when any of the ColSeg0<1:0> signals is set. The output of each corresponding inverter 613(0)-(6) is provided to the corresponding ColSeg1 decoder circuit 614(0)-(6). Each decoder circuit in the ColSeg1 decoder circuits 614(0)-(6) includes a corresponding inverter 615(0)-(6), which is enabled to invert the output value of the corresponding inverter 613(0)-(6) when the corresponding ColSeg1<6:0> signal is set. As Figure 6 shown, if the ColSeg0<1:0> and ColSeg1<6:0> signals are not set, each corresponding inverter 613(0)-(6) and each corresponding inverter 615(0)-(6) can be disabled. Thus, the column redundancy detection circuit 600 can be configured to provide an alternative CA with an undetermined value. That is, the outputs of the fuse data decoders 610(0)-(6) will be in a metastable state. Returning to Figure 3 , using the logic circuit 341 to set the corresponding signals in the ColSeg0<1:0> signals and the corresponding signals in the ColSeg1<6:0> signals can reduce the possibility that the column redundancy detection circuit 342 is in a metastable state.

[0057] The applicant notes that Figures 3 - 6 the specific RA bits and bit combinations used by the circuit system of Figure 4 are exemplary. Additional or different RA bits can be used without departing from the scope of the present disclosure to determine column segmentation and detect whether a column has been replaced. When an unassigned row address is detected, using the logic circuit 341 (e.g., and / or Figure 5 the logic circuit 404 of

[0058] Figure 7 and Figure 5 the logic circuit 504 of

[0058] Figure 7 to override the logic of the decoder can prevent the circuit system of the semiconductor device 300 from entering a metastable state.FIG. 0 is a block diagram depicting a portion of a memory cell array 700 and a logic circuit 704 of a semiconductor device in accordance with an embodiment of the present disclosure. The memory cell array 700 includes an M-side memory array 720 sandwiched between an M-side far control signal line 710 and an M-side near control signal line 730, and a P-side memory array 722 sandwiched between a P-side far control signal line 712 and a P-side near control signal line 732. The memory cell array 700 further includes a 740 for providing control signals located between the M-side memory array 720 and the P-side memory array 722. Figure 1 The semiconductor device 100 of Figure 1 can implement the memory cell array 700 and the logic circuit 704.

[0059] The logic circuit 704 may include a near column selection control circuit 741 and a far column selection control circuit 742, each configured to receive control signals including an array side enable signal MEnD and PEnD, an upper activation signal CRACTU, a lower activation signal CRACTD, and a column enable signal CYE. The control signals may be received on a side of the memory cell array 700 close to the near column selection control circuit 741 and driven to the far column selection control circuit 742 through a driver circuit 750. The CYE signal may initially be routed directly to the driver circuit 750 (e.g., at a location approximately midway between the near column selection control circuit 741 and the far column selection control circuit 742), and then driven to the near column selection control circuit 741 and the far column selection control circuit 742 to align the activation times of column selection signals through the near column selection control circuit 741 and the far column selection control circuit 742. The near column selection control circuit 741 and the far column selection control circuit 742 may activate column selection within the M-side memory array 720 and / or the P-side memory array 722 based on the values of the control signals.

[0060] The logic circuit 704 may be configured to be based on commands received from a decoder (e.g., Figure 1The command decoder 106) sets the MEnD signal and the PEnD signal based on the received MEn signal, PEn signal, row address RA16 signal, and RA17 signal. For example, when one or both of the RA16 signal and the RA17 signal are cleared, the MEnD signal and the PEnD signal can be controlled based on the values of the MEn signal and the PEn signal respectively to enable or disable the near column selection control circuit 741 and the far column selection control circuit 742 to perform a column selection operation on any one of the M-side memory array 720 or the P-side memory array 722. When both the RA16 signal and the RA17 signal are set, the MEnD and PEnD signals can be cleared respectively (e.g., regardless of the values of the MEn signal and the PEn signal) to disable the column selection operation on the M-side memory array 720 and the P-side memory array 722.

[0061] Figure 8A FIG. depicts a block diagram of a portion of a semiconductor device 800 in accordance with an embodiment of the present disclosure. Figure 8B FIG. depicts, in accordance with an embodiment of the present disclosure, an exemplary timing diagram 801 showing the control of an input pointer and an output pointer associated with the DQ FIFO buffer 860. The semiconductor device 800 may include a row logic circuit 810, a column logic circuit 820, a latency counter 830, and a DQ FIFO buffer 860. Figure 8A The semiconductor device 100 may implement the semiconductor device 800. Figure 1

[0062] The row logic circuit 810 may include a latch circuit 811, a NOR gate 812, an OR gate 814, and an AND gate 816. The latch circuit 811 may be configured to receive an ACT command and latch an ACT status signal in response to the ACT command. The NOR gate 812 may be configured to receive an active-low RA16 signal RA16F and an RA17 signal RA17F, and perform a bitwise NOR logic comparison to provide a first input to the OR gate 814. The output of the NOR gate 812 may indicate whether the row address associated with the RA16F signal and the RA17F signal is an unassigned row address. The OR gate 814 may receive a row select signal RS at a second input, and may perform a bitwise OR logic comparison between the RS signal and the output of the NOR gate 812 to provide a first input to the AND gate 816. The RS signal may be set when the read address is an assigned address, and the RS signal may be cleared when the read address is an unassigned row address. The AND gate 816 may receive an ACT STATE signal at a second input and may perform a bitwise AND logic comparison between the ACT STATE signal and the output of the OR gate 814 to provide a column enable signal CE. Thus, when the ACT STATE signal is set, and the RS signal is set or both the RA16F signal and the RA17F signal are set, the row logic circuit 810 may set the CE signal. Otherwise, the row logic circuit 810 may clear the CE signal.

[0063] The column logic circuit 820 may be configured to receive a CE signal and a read command RD. When the CE signal is set, the column logic circuit 820 may adjust (e.g., increment or decrement) an input pointer IN provided to the DQ FIFO buffer 860 in response to the RD command. The latency counter 830 may receive the RD command and may adjust an output pointer OUT after a predetermined delay since receiving the RD command.

[0064] As previously described, Figure 8B the timing diagram 801 of depicts the operation of the semiconductor device 800 in response to receiving an assigned row address after receiving an unassigned row address. Referring to Figure 8A and 8B before time T1, an external ACT command may be received along with a corresponding row address. At time T1, the row logic circuit 810 may receive an ACT CMD signal in response to the external ACT command, which may transition to a first (e.g., high or set) logic value.

[0065] At time T2, in response to the ACT CMD signal transitioning to a first logic value, the latch circuit 811 may latch the ACT STATE signal at the first logic value. Also at time T2, both the RA16F signal and the RA17F signal may transition to a second (e.g., low or cleared) logic value, where the second logic value indicates the corresponding bit value of the received row address with an external ACT command. In response to the RA16F signal and the RA17F signal transitioning to the second logic value, the NOR gate 812 may transition its output to the first logic value. The transition of both the RA16F and the RA17F to the second logic value may correspond to an unassigned row address. Accordingly, the RS signal may remain at the second logic value. The OR gate 814 may set its output to the first logic value in response to the output of the NOR gate 812 having the first logic value.

[0066] At time T3, the AND gate 816 may transition the CE signal to the first logic value based on the ACT STATE signal having the first logic value and the output of the OR gate 814 having the first logic value. The CE signal may be provided to the column logic circuit 820.

[0067] Before time T4, an external RD command may be received along with a corresponding column address. At time T4, the RD command signal may transition to the first logic value in response to the external RD command signal. The RD command signal may be provided to the column logic circuit 820 and the wait time counter 830. At time T5, the IN pointer may be adjusted to the [0] value in response to the RD command signal and based on the CE signal having the first logic value. After the delay applied by the wait time counter 830 from time T5 to T6, the wait time counter 830 may adjust the OUT pointer to the [0] value at time T6. Accordingly, even though an unassigned row address is received, both the IN pointer and the OUT pointer may remain synchronized at the [0] value.

[0068] Before time T7, an allocated row address can be received. One or both of RA16F and RA17F can be set to a first logic value in response to the allocated row address. The RS signal can be set in response to the allocated row address. In response to a transition of the RA16F signal and the RA17F signal based on the allocated address, the NOR gate 812 can transition the output to a second logic value. The OR gate 814 can set the output to a first logic value in response to the RS signal having the first logic value. After receiving the allocated row address and before time T7, a second external RD command can be received along with the corresponding column address. At time T7, the RD command signal can transition to a first logic value in response to the second external RD command signal. At time T8, the IN pointer can be adjusted to a [1] value in response to the RD command signal and based on the CE signal having the first logic value. After the delay from time T8 to T9 applied by the wait time counter 830, the wait time counter 830 can adjust the OUT pointer to a [1] value at time T6. Thus, both the IN pointer and the OUT pointer can remain synchronized at the [1] value even though an unallocated row address is received.

[0069] Thus, the row logic circuit 810 can prevent the IN and OUT pointers from mismatching in response to an unallocated row address. The applicant notes that the timing diagram 801 is exemplary and that the relative timing between signal transitions is not intended to be to scale. Different relative timing relationships can be implemented without departing from the scope of the present disclosure.

[0070] The applicant notes that while the above describes that the determination as to whether the received row address is an unallocated row address is based on the respective values of the row address bits RA16 and RA17, it should be understood that different or additional row address bits can be used to indicate an unallocated row address without departing from the scope of the present disclosure.

[0071] In view of the foregoing, it should be understood that although specific embodiments of the present disclosure have been described for purposes of illustration, various modifications can be made without departing from the spirit or scope of the present disclosure. Accordingly, the present disclosure is not limited except as by the appended claims.

Claims

1. A memory device, which comprises: an address decoder configured to receive a row address corresponding to a memory access operation, wherein the address decoder is configured to decode the row address to provide a decoded row address; and a section determination circuit configured to receive the decoded row address and determine a column segmentation address based on the decoded row address, wherein determination of column redundancy corresponding to the memory access operation is based on the column segmentation address, and wherein the section determination circuit further includes a logic circuit configured to cause the column segmentation address to be overwritten in response to determining that the decoded row address is an unallocated row address.

2. The memory device according to claim 1, wherein the logic circuit is configured to compare a first bit of the row address with a second bit of the row address to determine whether the decoded row address is an unallocated row address.

3. The memory device according to claim 1, wherein the logic circuit is configured to perform a bitwise AND comparison between the first bit of the row address and the second bit of the row address to determine whether the decoded row address is an unallocated row address.

4. The memory device according to claim 1, further comprising a column address redundancy control circuit configured to receive a decoded column address corresponding to the memory access operation and determine whether the decoded column address is replaced by a redundant column address based on the column segmentation address to determine the column redundancy.

5. The memory device according to claim 1, further comprising a column logic circuit configured to disable column selection activation in response to determining that the decoded row address is an unallocated row address.

6. The memory device according to claim 5, wherein the column logic circuit is configured to disable an array side enable signal to disable the column selection activation in response to determining that the decoded row address is an unallocated row address, and the array side enable signal is configured to control whether a specific side of a memory array is enabled.

7. The memory device according to claim 5, wherein the column logic circuit is configured to determine whether the decoded row address is an unallocated row address based on a comparison between the first bit of the row address and the second bit of the row address.

8. The memory device according to claim 1, further comprising a row logic circuit configured to cause an input pointer configured to control a data buffer to be adjusted in response to determining that the decoded row address is an unallocated row address.

9. The memory device according to claim 8, wherein the row logic circuit is configured to determine whether the decoded row address is an unallocated row address based on a comparison between the first bit of the row address and the second bit of the row address.

10. The memory device according to claim 8, wherein the input pointer is adjusted in response to a read command and based on a column enable signal provided by the row logic circuit, and wherein the row logic circuit is configured to set the column enable signal in response to determining that the decoded row address is an unallocated row address.

Images