Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming a semiconductor structure, the structure comprising: a layer to be etched; a transition structure located on the layer to be etched, the transition structure containing diffusion-resistant ions; a sacrificial layer and a modified layer located on the transition structure, the sacrificial layer and the modified layer being adjacent to each other. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous improvement of the performance of very large-scale integrated circuits (VLSI), the gradual reduction of device size and the continuous increase in device density, the process nodes continue to shrink. Due to the insufficient light source power of the next-generation lithography technology, extreme ultraviolet lithography (EUV), its time to enter mass production has been delayed, so 193 nanometer (nm) deep ultraviolet (DUV) immersion lithography technology will inevitably continue to be used for a long time. However, the resolution of a single exposure of deep ultraviolet immersion lithography technology is approximately 38 nanometers (nm). To further reduce the process node, new process methods must be used. Therefore, a variety of pattern-forming materials have been introduced. The materials can be modified under appropriate conditions. Under certain conditions, the modified materials have a larger etching selectivity ratio with the original materials, thereby being able to form an ordered pattern of nanometer-sized structural units to form the pattern of the semiconductor structure to be formed.

[0003] However, as semiconductor technology nodes are further reduced, existing methods of using material modification as a method for patterning semiconductor structures need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the method for forming the semiconductor structure.

[0005] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a layer to be etched; a transition structure located on the layer to be etched, wherein the transition structure has anti-diffusion ions; a sacrificial layer and a modified layer located on the transition structure, wherein the sacrificial layer and the modified layer are adjacent to each other.

[0006] Optionally, the ionic radius of the anti-diffusion ions is larger than the ionic radius of the diffusing ions.

[0007] Optionally, the diffusing ions include hydrogen ions or boron ions.

[0008] Optionally, the transition structure includes a first transition layer and a hard mask layer located on the first transition layer.

[0009] Optionally, the transition structure further includes a second transition layer located on the hard mask layer.

[0010] Optionally, the anti-diffusion ions are located in any one or more layers of the first transition layer, the hard mask layer, and the second transition layer.

[0011] Optionally, the material of the first transition layer and the surface material of the layer to be etched have different etching selectivities.

[0012] Optionally, the material of the second transition layer and the material of the hard mask layer have different etching selectivities.

[0013] Optionally, the layer to be etched includes a substrate and an isolation material layer located on the substrate; the substrate includes a base and a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.

[0014] Optionally, the isolation material layer is made of a low dielectric constant material, and the dielectric constant of the low dielectric constant material is in the range of 2.5 to 3.5.

[0015] Optionally, it is characterized in that the material of the sacrificial layer includes an amorphous material.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming a transition structure on the layer to be etched, wherein the transition structure has anti-diffusion ions; forming a sacrificial layer on the transition structure; and modifying part of the sacrificial layer by ion implantation to form a modified layer.

[0017] Optionally, the ionic radius of the anti-diffusion ions is larger than the ionic radius of the diffusing ions.

[0018] Optionally, the diffusing ions include hydrogen ions or boron ions.

[0019] Optionally, the transition structure includes a first transition layer and a hard mask layer located on the first transition layer.

[0020] Optionally, the transition structure further includes a second transition layer located on the hard mask layer.

[0021] Optionally, the anti-diffusion ions are located in any one or more layers of the first transition layer, the hard mask layer, and the second transition layer.

[0022] Optionally, the material of the first transition layer and the surface material of the layer to be etched have different etching selectivities.

[0023] Optionally, the material of the second transition layer and the material of the hard mask layer have different etching selectivities.

[0024] Optionally, the process of doping anti-diffusion ions into the transition structure includes an ion implantation process or an in-situ doping process.

[0025] Optionally, the material of the sacrificial layer includes an amorphous material.

[0026] Optionally, the layer to be etched includes a substrate and an isolation material layer located on the substrate; the substrate includes a base and a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.

[0027] Optionally, the implanted ions used in the ion implantation into a portion of the sacrificial layer include boron ions, nitrogen ions or fluorine ions.

[0028] Optionally, the method of modifying part of the sacrificial layer by ion implantation includes: forming a mask structure on the sacrificial layer, wherein the mask structure exposes part of the surface of the sacrificial layer; and performing ion implantation on the sacrificial layer exposed by the mask structure to form the modified layer.

[0029] Optionally, the mask structure includes: a liner layer; an anti-reflection layer located on the liner layer; and a photoresist layer located on the anti-reflection layer.

[0030] Optionally, the method for forming the mask structure includes: forming a pad material layer on the sacrificial layer; forming an anti-reflective material layer on the pad material layer; forming a patterned photoresist layer on the anti-reflective material layer; etching the anti-reflective material layer and the pad material layer using the patterned photoresist layer as a mask until the surface of the sacrificial layer is exposed to form the mask structure.

[0031] Optionally, the process of etching the anti-reflection material layer and the liner material layer includes a dry etching process, and the etching gas of the dry etching process includes a mixed gas of hydrogen, nitrogen, carbon tetrafluoride and trifluoromethane.

[0032] Optionally, the method further includes: after forming the modified layer, removing the modified layer; after removing the modified layer, etching the transition structure and the layer to be etched using the sacrificial layer as a mask.

[0033] Optionally, the method further includes: forming a groove in the layer to be etched; and forming a conductive layer in the groove.

[0034] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0035] The semiconductor structure in the technical solution of the present invention has anti-diffusion ions in the transition structure, so that the anti-diffusion ions can block the diffusion ions in the process of modifying the sacrificial layer from diffusing into the layer to be etched, thereby avoiding the situation where the diffused ions diffuse into the layer to be etched and damage the structure of the layer to be etched, thereby affecting the performance of the semiconductor structure.

[0036] The method for forming a semiconductor structure in the technical solution of the present invention incorporates anti-diffusion ions into the transition structure, so that the anti-diffusion ions can block the diffusion ions in the process of modifying the sacrificial layer from diffusing into the layer to be etched, thereby avoiding the situation where the diffused ions diffuse into the layer to be etched and damage the structure of the layer to be etched, thereby affecting the performance of the semiconductor structure.

[0037] Furthermore, the ion radius of the anti-diffusion ions is larger than the ion radius of the diffusing ions, so that the anti-diffusion ions can prevent the diffusing ions from diffusing into the layer to be etched.

[0038] Furthermore, after forming the modified layer, the modified layer is removed; after removing the modified layer, the transition structure and the layer to be etched are etched using the sacrificial layer as a mask to form a groove in the layer to be etched; and a conductive layer is formed in the groove. Anti-diffusion ions are present in the transition structure, and the anti-diffusion ions can block the diffusion of diffusing ions into the layer to be etched during the modification of the sacrificial layer, thereby preventing the diffusion of the diffusing ions into the conductive layer when the diffusing ions diffuse into the layer to be etched, and simultaneously preventing ions of the conductive layer material from diffusing into the layer to be etched, thereby causing a short circuit in the conductive layer formed in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0040] Figures 4 to 8 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] As described in the background art, the existing method for forming patterns still needs to be improved.

[0042] Figures 1 to 3 It is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment.

[0043] Please refer to Figure 1, providing a layer to be etched, the layer to be etched comprising a substrate 100 and an isolation material layer 101 located on the substrate 100; forming a hard mask layer 102 and a transition layer 103 located on the hard mask layer 102 on the layer to be etched; forming an initial sacrificial layer (not shown) on the transition layer 103; forming a mask structure 105 on the initial sacrificial layer, the mask structure 105 exposing a portion of the surface of the initial sacrificial layer; modifying the initial sacrificial layer using the mask structure 105 as a mask to form a modified layer 106 and a sacrificial layer 104 adjacent to the modified layer 106.

[0044] Please refer to Figure 2 , remove the modified layer 106; after removing the modified layer 106, etch the transition layer 103, the hard mask layer 102 and the isolation material layer 101 using the sacrificial layer 104 as a mask to form an isolation structure 107 on the substrate 100; and form a conductive material layer 108 on the substrate 100 and the isolation structure 107.

[0045] Please refer to Figure 3 , planarizing the conductive material layer 108 until the surface of the isolation structure 107 is exposed, and forming a conductive layer 109 between the isolation structures 107 .

[0046] During the formation of the semiconductor structure, when forming the mask structure 105, it is necessary to first form a liner material layer (not shown) on the initial sacrificial layer, form an anti-reflective material layer (not shown) on the liner material layer, and then form a patterned photoresist layer on the anti-reflective material layer. The anti-reflective material layer and the liner material layer are then etched using the patterned photoresist layer as a mask until the surface of the initial sacrificial layer is exposed, thereby forming the mask structure 105 on the initial sacrificial layer. To obtain a mask structure 105 with a good and straight sidewall morphology, a dry etching process is typically used to etch the anti-reflective material layer and the liner material layer. The etching gas used in the dry etching process includes a mixed gas of hydrogen, nitrogen, carbon tetrafluoride, and trifluoromethane. After the mask structure 105 is formed, ions of the etching gas are also present on the exposed surface of the initial sacrificial layer. The subsequent process of modifying the initial sacrificial layer using the mask structure 105 as a mask includes an ion implantation process. During the ion implantation process, the ion bombardment will inject the ions of the etching gas present on the surface of the initial sacrificial layer into the underlying structure. Therefore, the ions of the etching gas exist in the isolation material layer 101. The ions of the etching gas include hydrogen ions, and the isolation structure 107 formed also contains hydrogen ions.

[0047] However, when subsequently forming the conductive layer 109 between the isolation structures 107, a seed layer (not shown) must first be formed on the substrate 100 and the isolation structures 107, and then a conductive material layer 108 is grown on the seed layer. The material of the seed layer and the conductive material layer 108 includes metal. At this time, hydrogen ions located in the isolation structure 107 can easily enter the metal material in contact with the isolation structure 107, thereby forming vacancies in the isolation structure 107. The ions of the metal material diffuse into the vacancies formed by the hydrogen ions through ion diffusion, resulting in metal ions in the surface layer of the isolation structure 107. After the conductive material layer 108 is subsequently flattened until the surface of the isolation structure 107 is exposed and the conductive layer 109 is formed between the isolation structures 107, the presence of metal ions in the surface layer of the isolation structure 107 weakens the electrical isolation effect of the isolation structure 107 on the conductive layer 109, making the conductive layers 109 located on both sides of the isolation structure 107 susceptible to short circuits, thereby affecting the performance of the formed semiconductor structure.

[0048] In addition, the boron ions in the ion implantation process of modifying the initial sacrificial layer using the mask structure 105 as a mask may also cause the above-mentioned problem.

[0049] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by doping anti-diffusion ions into the transition structure, so that the anti-diffusion ions can block the diffusion ions in the process of modifying the sacrificial layer from diffusing into the layer to be etched, thereby avoiding the situation where the diffusion ions diffuse into the layer to be etched and damage the structure of the layer to be etched, thereby affecting the performance of the semiconductor structure.

[0050] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] Figures 4 to 8 It is a schematic cross-sectional structural diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0052] Please refer to Figure 4 , providing a layer to be etched.

[0053] The layer to be etched includes a substrate 200 and an isolation material layer 201 located on the substrate 200; the substrate 200 includes a base (not shown) and a device layer (not shown) located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.

[0054] In this embodiment, the substrate is made of silicon.

[0055] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0056] The isolation material layer 201 is made of a low-k material, and the dielectric constant of the low-k material is in the range of 2.5 to 3.5.

[0057] Please refer to Figure 5 , forming a transition structure on the layer to be etched, wherein the transition structure contains anti-diffusion ions.

[0058] The transition structure includes a first transition layer 202 and a hard mask layer 203 located on the first transition layer 202 .

[0059] In this embodiment, the transition structure further includes a second transition layer 204 located on the hard mask layer 203 .

[0060] In other embodiments, the transition structure may not include the second transition layer.

[0061] In other embodiments, the transition structure further includes a plurality of second transition layers.

[0062] The material of the first transition layer 202 has a different etching selectivity from the surface material of the layer to be etched, that is, the material of the first transition layer 202 has a different etching selectivity from the material of the isolation material layer 201. Therefore, when the first transition layer 202 is subsequently etched to form a first transition structure, the etching process can stop at the surface of the isolation material layer 201, thereby enabling good graphic transfer.

[0063] The material of the first transition layer 202 includes a dielectric material, which includes one or more combinations of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the first transition layer 202 includes silicon oxycarbide.

[0064] The material of the second transition layer 203 and the material of the hard mask layer 204 have different etching selectivities, so that when the second transition layer 203 is subsequently etched to form a second transition structure, the etching process can stop at the surface of the second transition layer 203, thereby enabling good pattern transfer.

[0065] The material of the hard mask layer 204 and the material of the first transition layer 202 also have different etching selectivities, so that the pattern can be stably transferred to the first transition layer 202 .

[0066] The material of the second transition layer 203 includes a dielectric material, which includes one or more combinations of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbon nitride, and silicon carbon nitride. The material of the hard mask layer 204 includes one or more combinations of materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or titanium nitride.

[0067] In this embodiment, the material of the second transition layer 203 includes silicon oxide; the material of the hard mask layer 204 includes titanium nitride.

[0068] The process of doping the transition structure with anti-diffusion ions includes an ion implantation process or an in-situ doping process. By doping the transition structure with anti-diffusion ions, the anti-diffusion ions can block diffusing ions from subsequently diffusing into the layer to be etched during the modification of the sacrificial layer, thereby preventing the diffusing ions from damaging the structure of the layer to be etched, thereby affecting the performance of the semiconductor structure.

[0069] The anti-diffusion ions include N-type ions, P-type ions or other types of ions; the P-type ions include boron ions, boron fluoride ions or indium ions, etc., the N-type ions include phosphorus ions, arsenic ions or antimony ions, etc., and the other types of ions include nitrogen ions, germanium ions or silicon ions, etc.

[0070] In this embodiment, the anti-diffusion ions are located in any one of the first transition layer 202 , the hard mask layer 203 and the second transition layer 204 .

[0071] In other embodiments, the anti-diffusion ions are located in any two layers of the first transition layer, the hard mask layer, and the second transition layer.

[0072] In other embodiments, the anti-diffusion ions are located in the first transition layer, in the hard mask layer, and in the second transition layer.

[0073] Please refer to Figure 6 , forming a sacrificial layer 205 on the transition structure.

[0074] In this embodiment, the material of the sacrificial layer 205 includes an amorphous material, and the amorphous material includes amorphous silicon.

[0075] Please continue to refer to Figure 6 , a mask structure 206 is formed on the sacrificial layer 205 , wherein the mask structure 206 exposes a portion of the surface of the sacrificial layer 205 .

[0076] The mask structure 206 includes: a liner layer (not shown); an anti-reflection layer (not shown) located on the liner layer; and a photoresist layer (not shown) located on the anti-reflection layer.

[0077] The material of the liner layer includes amorphous silicon or amorphous carbon.

[0078] The material of the anti-reflection layer includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0079] The method for forming the mask structure 206 includes: forming a liner material layer (not shown) on the sacrificial layer; forming an anti-reflective material layer (not shown) on the liner material layer; forming a patterned photoresist layer (not shown) on the anti-reflective material layer; and etching the anti-reflective material layer and the liner material layer using the patterned photoresist layer as a mask until the surface of the sacrificial layer 205 is exposed to form the mask structure 206.

[0080] The process of etching the anti-reflective material layer and the liner material layer includes a dry etching process, and the etching gas of the dry etching process includes a mixed gas of hydrogen, nitrogen, carbon tetrafluoride and trifluoromethane. The etching gas etches the anti-reflective material layer and the liner material layer to obtain a mask structure with good and straight sidewall appearance, which is beneficial to improving the dimensional accuracy of the mask structure 206.

[0081] The ion radius of the diffusion-preventing ions is larger than the ion radius of the diffusion ions. In this embodiment, the diffusion ions include hydrogen ions or boron ions.

[0082] The etching gas of the dry etching process includes hydrogen, and the ion radius of the anti-diffusion ions is larger than the ion radius of the hydrogen ions, so that the anti-diffusion ions can block the hydrogen ions in the process of forming the mask structure from diffusing into the layer to be etched, thereby preventing the hydrogen ions from diffusing into the subsequently formed conductive layer when diffusing into the layer to be etched, and at the same time, the ions of the conductive layer material also diffuse into the layer to be etched, thereby causing a short circuit in the conductive layer formed in the groove.

[0083] Please refer to Figure 7 , the portion of the sacrificial layer 205 exposed by the mask structure 206 is modified by ion implantation to form a modified layer 207 .

[0084] The implanted ions used for ion implantation into a portion of the sacrificial layer 205 include boron ions, nitrogen ions, or fluorine ions.

[0085] The modified layer 207 is formed after ion implantation of part of the sacrificial layer 205. The sacrificial layer 205 and the modified layer 207 have a large etching selectivity ratio, so that the sacrificial layer 205 can be less damaged in the subsequent process of removing the modified layer 207, so that the sacrificial layer 205 can form a semiconductor pattern with good dimensional accuracy.

[0086] The ion radius of the diffusion-preventing ions is greater than the ion radius of the diffusion ions. In this embodiment, the diffusion ions include boron ions or hydrogen ions.

[0087] The implanted ions for ion implantation into part of the sacrificial layer 205 include boron ions, and the ion radius of the anti-diffusion ions is larger than the ion radius of the boron ions, so that the anti-diffusion ions can block the boron ions in the process of forming the mask structure from diffusing into the layer to be etched, thereby preventing the hydrogen ions from diffusing into the subsequently formed conductive layer when the boron ions diffuse into the layer to be etched, and at the same time, the ions of the conductive layer material also diffuse into the layer to be etched, thereby causing a short circuit in the conductive layer formed in the groove.

[0088] Please refer to Figure 8 After forming the modified layer 207, the modified layer 207 is removed.

[0089] The process of removing the modified layer 207 includes a dry etching process and a wet etching process or a combination thereof. The modified layer 207 has a large etching selectivity ratio with the sacrificial layer 205. During the process of removing the modified layer 207, the sacrificial layer 205 is less damaged.

[0090] Please continue to refer to Figure 8 After removing the modified layer 207 , the transition structure and the layer to be etched are etched using the sacrificial layer 205 as a mask.

[0091] In this embodiment, after etching the transition structure and the layer to be etched, a groove (not shown) is formed in the isolation material layer 201 ; and a conductive layer 209 is formed in the groove.

[0092] Since the transition structure contains anti-diffusion ions, the anti-diffusion ions can block the diffusion ions from diffusing into the layer to be etched during the modification of the sacrificial layer 205, thereby preventing the diffusion ions from diffusing into the conductive layer 209 when the diffusion ions diffuse into the layer to be etched. At the same time, the ions of the conductive layer material also diffuse into the layer to be etched, thereby causing a short circuit in the conductive layer 209 formed in the groove.

[0093] In other embodiments, after forming the modified layer, other mask structures are formed on the sacrificial layer and the modified layer, and other patterns are formed in the sacrificial layer and the modified layer. The specific process is common in the art and will not be described in detail here.

[0094] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 7 ,include:

[0095] layer to be etched;

[0096] A transition structure located on the layer to be etched, wherein the transition structure has diffusion-resistant ions;

[0097] The sacrificial layer 205 and the modified layer 207 are located on the transition structure, and the sacrificial layer 205 and the modified layer 207 are alternately arranged on the transition structure.

[0098] In this embodiment, the ion radius of the diffusion-preventing ions is larger than the ion radius of hydrogen ions.

[0099] In this embodiment, the anti-diffusion ions include N-type ions, P-type ions or other types of ions; the P-type ions include boron ions, boron fluoride ions or indium ions, etc., the N-type ions include phosphorus ions, arsenic ions or antimony ions, etc., and the other types of ions include nitrogen ions, germanium ions or silicon ions, etc.

[0100] In this embodiment, the transition structure includes a first transition layer 202 and a hard mask layer 203 located on the first transition layer 202 .

[0101] In this embodiment, the transition structure further includes a second transition layer 204 located on the hard mask layer 203 .

[0102] In this embodiment, the anti-diffusion ions are located in any one of the first transition layer 202 , the hard mask layer 203 and the second transition layer 204 .

[0103] In other embodiments, the anti-diffusion ions are located in any two layers of the first transition layer, the hard mask layer, and the second transition layer.

[0104] In other embodiments, the anti-diffusion ions are located in the first transition layer, the hard mask layer, and the second transition layer.

[0105] In this embodiment, the material of the first transition layer 202 and the surface material of the to-be-etched layer have different etching selectivities.

[0106] In this embodiment, the material of the first transition layer 202 includes a dielectric material, and the dielectric material includes one or more combinations of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbide nitride, and silicon oxycarbide nitride.

[0107] In this embodiment, the material of the second transition layer 204 and the material of the hard mask layer have different etching selectivities.

[0108] In this embodiment, the material of the second transition layer 204 includes a dielectric material, and the dielectric material includes one or more combinations of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbide nitride, and silicon oxycarbide nitride.

[0109] In this embodiment, the material of the hard mask layer 203 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or titanium nitride.

[0110] In this embodiment, the layer to be etched includes a substrate 200 and an isolation material layer 201 located on the substrate 200; the substrate includes a base (not shown) and a device layer (not shown) located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.

[0111] In this embodiment, the isolation material layer 201 is made of a low-k material, and the dielectric constant of the low-k material is in the range of 2.5 to 3.5.

[0112] In this embodiment, the material of the sacrificial layer 205 includes an amorphous material, and the amorphous material includes amorphous silicon.

[0113] In this embodiment, the material of the modified layer 207 is different from the material of the sacrificial layer 205. The modified layer 207 is a modified material obtained by ion implantation of the sacrificial layer material using the mask structure 206 as a mask. The implanted ions include boron ions, nitrogen ions or fluorine ions.

[0114] The semiconductor structure has anti-diffusion ions in the transition structure, so that the anti-diffusion ions can block the diffusion ions from diffusing into the layer to be etched during the modification of the sacrificial layer 205, thereby avoiding the situation where the diffused ions diffuse into the layer to be etched and damage the structure of the layer to be etched, thereby affecting the performance of the semiconductor structure.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: layer to be etched; a transition structure located on a layer to be etched, wherein the transition structure contains anti-diffusion ions, wherein the ion radius of the anti-diffusion ions is larger than the ion radius of the diffusing ions, the transition structure comprising a first transition layer and a hard mask layer located on the first transition layer, wherein the anti-diffusion ions are located in either or both of the first transition layer and the hard mask layer, wherein the material of the first transition layer has a different etching selectivity from the surface material of the layer to be etched, and wherein the material of the first transition layer has a different etching selectivity from the hard mask layer; A sacrificial layer and a modified layer are located on the transition structure, wherein the sacrificial layer and the modified layer are adjacent to each other.

2. The semiconductor structure according to claim 1, wherein The diffusing ions include hydrogen ions or boron ions.

3. The semiconductor structure according to claim 1, wherein: The transition structure further includes a second transition layer located on the hard mask layer.

4. The semiconductor structure according to claim 3, wherein: The anti-diffusion ions are located in any one or more layers of the first transition layer, the hard mask layer, and the second transition layer.

5. The semiconductor structure according to claim 3, wherein: The material of the second transition layer and the material of the hard mask layer have different etching selectivities.

6. The semiconductor structure according to claim 1, wherein The layer to be etched includes a substrate and an isolation material layer located on the substrate; the substrate includes a base and a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

7. The semiconductor structure according to claim 6, wherein: The isolation material layer is made of a low dielectric constant material, and the dielectric constant of the low dielectric constant material is in the range of 2.5 to 3.

5.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer includes an amorphous material.

9. A method for forming a semiconductor structure, characterized in that: include: providing a layer to be etched; forming a transition structure on the layer to be etched, wherein the transition structure contains anti-diffusion ions, wherein the ion radius of the anti-diffusion ions is larger than the ion radius of the diffusing ions, the transition structure comprising a first transition layer and a hard mask layer located on the first transition layer, wherein the anti-diffusion ions are located in either or both of the first transition layer and the hard mask layer, wherein the material of the first transition layer has a different etching selectivity from the surface material of the layer to be etched, and wherein the material of the first transition layer has a different etching selectivity from the hard mask layer; forming a sacrificial layer on the transition structure; Part of the sacrificial layer is modified by ion implantation to form a modified layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The diffusing ions include hydrogen ions or boron ions.

11. The method for forming a semiconductor structure according to claim 10, wherein: The transition structure further includes a second transition layer located on the hard mask layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The anti-diffusion ions are located in any one or more layers of the first transition layer, the hard mask layer, and the second transition layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: The material of the second transition layer and the material of the hard mask layer have different etching selectivities.

14. The method for forming a semiconductor structure according to claim 9, wherein: The process of doping the diffusion-preventing ions into the transition structure includes an ion implantation process or an in-situ doping process.

15. The method for forming a semiconductor structure according to claim 9, wherein: The material of the sacrificial layer includes an amorphous material.

16. The method for forming a semiconductor structure according to claim 9, wherein: The layer to be etched includes a substrate and an isolation material layer located on the substrate; the substrate includes a base and a device layer located on the base, the device layer includes an isolation structure and a device structure located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure.

17. The method for forming a semiconductor structure according to claim 9, wherein: The implanted ions used for ion implantation into a portion of the sacrificial layer include boron ions, nitrogen ions or fluorine ions.

18. The method for forming a semiconductor structure according to claim 9, wherein: The method for modifying part of the sacrificial layer by ion implantation includes: forming a mask structure on the sacrificial layer, wherein the mask structure exposes part of the surface of the sacrificial layer; and implanting ions into the sacrificial layer exposed by the mask structure to form the modified layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: The mask structure includes: a liner layer; an anti-reflection layer located on the liner layer; and a photoresist layer located on the anti-reflection layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: The method for forming the mask structure includes: forming a liner material layer on the sacrificial layer; forming an anti-reflective material layer on the liner material layer; forming a patterned photoresist layer on the anti-reflective material layer; etching the anti-reflective material layer and the liner material layer using the patterned photoresist layer as a mask until the surface of the sacrificial layer is exposed to form the mask structure.

21. The method for forming a semiconductor structure according to claim 20, wherein: The process of etching the anti-reflection material layer and the liner material layer includes a dry etching process, and the etching gas of the dry etching process includes a mixed gas of hydrogen, nitrogen, carbon tetrafluoride and trifluoromethane.

22. The method for forming a semiconductor structure according to claim 9, wherein: After forming the modified layer, the method further includes: removing the modified layer; and after removing the modified layer, etching the transition structure and the layer to be etched using the sacrificial layer as a mask.

23. The method for forming a semiconductor structure according to claim 22, wherein: Also includes: A groove is formed in the layer to be etched; and a conductive layer is formed in the groove.

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