Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same are provided. In an embodiment, the semiconductor structure includes: an epitaxial source component and an epitaxial drain component; a vertical stack of channel components disposed above a back dielectric layer, the vertical stack of channel components extending between the epitaxial source component and the epitaxial drain component along a direction; a gate structure wrapping each of the vertical stack of channel components; and a back source contact disposed in the back dielectric layer. The back source contact includes a top portion adjacent to the epitaxial source component and a bottom portion distal to the epitaxial source component. The top portion and the bottom portion include a step width variation along the direction.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having gate structures or portions thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and are promising candidates for high performance and low leakage applications. FinFETs have high-side channels wrapped by gates on more than one side (e.g., the top and sidewalls of the "fins" of the gate-wrapped semiconductor material extending from the substrate). MBC transistors have gate structures that can extend partially or entirely around the channel region to provide access to the channel region on two or more sides. Because the gate structure of the MBC transistor surrounds the channel region, the MBC transistor may also be referred to as a surround gate transistor (SGT) or a full ring gate (GAA) transistor. The channel region of the MBC transistor may be formed by nanowires, nanosheets, other nanostructures and / or other suitable structures. The shape of the channel region also gives the MBC transistor alternative names, such as nanosheet transistor or nanowire transistor.

[0004] As integrated circuit (IC) technology moves toward smaller technology nodes, some wiring structures have moved from the front side of the device structure to the back side of the device structure. For example, a backside power rail (BPR) or super power rail (SPR) has been proposed, in which a backside source / drain contact is formed through the substrate to contact the source / drain components, and a power rail is formed on the back side of the substrate to contact the backside source / drain contact. The formation of the backside source / drain contact is not without challenges. When the lithography mask overlap is not perfect, the backside source contact may short-circuit the gate structure. Therefore, although conventional backside source contacts and their formation are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor structure, including: an epitaxial source component and an epitaxial drain component; a vertical stack of channel components, arranged above a back dielectric layer, the vertical stack of channel components extending between the epitaxial source component and the epitaxial drain component along a direction; a gate structure, wrapping each of the vertical stack of channel components; and a back source contact, arranged in the back dielectric layer, wherein the back source contact includes a top adjacent to the epitaxial source component and a bottom away from the epitaxial source component, wherein the top and the bottom include a step width variation along the direction.

[0006] Other embodiments of the present application provide a semiconductor structure, including: a source component and a drain component; a plurality of channel components, arranged above a back dielectric layer, the plurality of channel components extending between the source component and the drain component along a first direction, the plurality of channel components being stacked along a second direction perpendicular to the first direction; a gate structure, wrapping each of the plurality of channel components; and a back source contact, arranged in the back dielectric layer, the back source contact including a first portion adjacent to the source component and a second portion away from the source component, wherein the first portion includes a first width along the first direction, and the second portion includes a second width along the first direction, wherein the first portion includes a first height along the second direction, and the second portion includes a second height along the second direction, wherein the first width is different from the second width, and wherein the first height is less than the second height.

[0007] Still other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a stack comprising a plurality of channel layers interlaced by a plurality of sacrificial layers above a substrate; patterning the stack and the substrate to form a fin-shaped structure; forming a source opening and a drain opening; depositing a dummy epitaxial component in the source opening and the drain opening; forming a source component in the source opening and a drain component in the drain opening, the source component and the drain component being arranged above the dummy epitaxial component; anisotropically etching the substrate to form a back contact opening of the dummy epitaxial component exposing the source component; selectively and isotropically etching the dummy epitaxial component; and forming a back source contact in the back contact opening to couple to the source component. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device having a backside contact according to one or more aspects of the present invention is shown.

[0010] FIG. 2A to FIG. 17A , Figures 2B to 17B and FIG. 10C to FIG. 17C According to one or more aspects of the present invention, Figure 1 A partial cross-sectional view of a workpiece during a manufacturing process of the method.

[0011] Fig.18A , Fig.18B and Fig.18C The use of one or more aspects of the present invention is shown Figure 1 An alternative semiconductor structure manufactured by the method.

[0012] Fig.19 and Fig. 20 The use of one or more aspects of the present invention is shown Figure 1 An alternative semiconductor structure manufactured by the method. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, when "about," "approximately," or the like is used to describe a value or a range of values, as understood by one of ordinary skill in the art, the term is intended to encompass values ​​within a reasonable range that takes into account inherent variations during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the values, the values ​​or ranges of values ​​encompass a reasonable range that includes the described values, such as within + / -10% of the described values. For example, a material layer having a thickness of "about 5 nm" may cover a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / -15%. Further, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] The present invention relates generally to methods of forming semiconductor devices having backside contacts, and more particularly to methods of forming backside contact openings using multiple etching steps.

[0017] Traditionally, source / drain contacts and gate contacts of transistors on a substrate connect the source / drain components of the transistor to an interconnect structure above the front side of the substrate. As IC device sizes shrink, the proximity between source contacts and gate contacts can reduce the process window for forming these contacts and can increase the parasitic capacitance between them. The backside power rail (BPR) structure is a modern solution for improving the performance of power delivery networks (PDNs) at advanced technology nodes. The implementation of the BPR structure can alleviate the crowding of contacts. In some conventional processes, backside contact openings are formed using photolithography and anisotropic dry etching. In these conventional processes, when the overlap is not perfect, the anisotropic dry etching can damage the adjacent gate structure, resulting in an electrical short between the gate structure and the backside contact.

[0018] The present invention provides a process for forming a backside contact that is self-aligned to a source / drain component. The process of the present invention forms a pseudo-epitaxial component in a source / drain opening extending into a substrate. The pseudo-epitaxial component is different from the component of the substrate to provide etching selectivity. After forming the source / drain component and the gate structure, the substrate is flipped. A backside contact opening is formed using a first etching process and a second etching process. In the first etching process, an anisotropic etching process is used to etch the substrate through a patterned mask layer. The first etching process etches through the substrate, but does not etch through the pseudo-epitaxial component. The pseudo-epitaxial component is then isotropically and selectively etched in the second etching process to expose the source / drain component. Because the second etching process is selective to the pseudo-epitaxial component relative to the substrate, the second etching process is self-aligned and is less likely to damage the gate structure. Therefore, the process of the present invention can reduce gate-source / drain shorts and improve yields.

[0019] Various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor device according to an embodiment of the present invention. The method 100 is merely an example and is not intended to limit the present invention to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. FIG. 2A to FIG. 16A , Figures 2B to 16B and FIG. 10C to FIG. 16C The method 100 is described. Because the workpiece 200 is manufactured into a semiconductor device 200 at the end of the manufacturing process, the workpiece 200 may be referred to as a semiconductor device 200 as the context requires. Throughout the present invention, the same reference numerals refer to the same components unless otherwise specified.

[0020] refer to Figure 1 , Figure 2A and Figure 2B The method 100 includes a block 102 in which a workpiece 200 is received. Figure 2A and Figure 2B As shown, workpiece 200 includes substrate 202 and stack 204 disposed on substrate 202. In one embodiment, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (GaInP), and indium gallium arsenide (InGaAs). Stack 204 may include a plurality of channel layers 208 interlaced by a plurality of sacrificial layers 206. Channel layers 208 and sacrificial layers 206 may have different semiconductor compositions. In some embodiments, channel layers 208 are formed of silicon (Si), and sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer 206 allows for the selective removal or recessing of the sacrificial layer 206 without causing substantial damage to the channel layer 208. In some embodiments, the sacrificial layer 206 and the channel layer 208 may be deposited using an epitaxial process. The stack 204 may be epitaxially deposited using a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The sacrificial layers 206 and the channel layers 208 are alternately deposited one after the other to form the stack 204. It should be noted that the three (3) layers of the sacrificial layer 206 and the three (3) layers of the channel layer 208 are alternately and vertically arranged, as shown in FIG. Figure 2A The number of layers depends on the desired number of channel components for semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0021] In preparation for the subsequent patterning process, a hard mask layer 210 is deposited over the stack 204. The hard mask layer 210 is used as an etch mask to pattern the stack 204 and even portions of the substrate 202 to form a fin structure 212 ( Figure 3B). In some embodiments, the hard mask layer 210 may be deposited using CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or a suitable deposition method. The hard mask layer 210 may be a single layer or multiple layers. When the hard mask layer 210 is multiple layers, it may include a first layer and a second layer disposed above the first layer. In one embodiment, the first layer may be a pad oxide and the second layer may be a pad nitride layer.

[0022] refer to Figure 1 , Figure 3A and Figure 3B , the method 100 includes block 104, where a fin structure 212 is formed. In some embodiments, at block 104, portions of the stack 204 and the substrate 202 are patterned to form the fin structure 212. Figure 3A and Figure 3B As shown, each of the fin structures 212 includes a base 212B formed by a portion of the substrate 202 and a top 212T formed by the stack 204. The top 212T is disposed above the base 212B. The fin structure 212 extends longitudinally from the substrate 202 in the X direction and vertically in the Z direction. The fin structure 212 can be patterned using a suitable process including a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the generation of patterns with, for example, a pitch smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a photolithography process. A spacer is formed next to the patterned material layer using a self-alignment process. The material layer is then removed, and by etching the stack 204 and the substrate 202, the remaining spacers or mandrels can then be used to pattern the hard mask layer 210, and the patterned hard mask layer 210 can then be used to pattern the fin structure 212. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. Although not explicitly shown in the figure, a semiconductor liner may be formed over the fin structure 212. The semiconductor liner may include silicon (Si) or silicon-rich silicon germanium (SiGe). In some embodiments, the semiconductor liner may be deposited using ALD, PEALD, VPE, MBE or a suitable method.

[0023] refer to Figure 1 , Figure 3A and Figure 3B The method 100 includes block 106, where an isolation feature 214 is formed. After forming the fin structures 212, a fin structure 214 is formed between adjacent fin structures 212. Figure 3BThe isolation feature 214 shown. The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. In an exemplary process, a dielectric material for the isolation feature 214 is first deposited over the fin structure 212, thereby filling the trenches between the fin structures 212 with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various instances, the dielectric material may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD (FCVD) process, an ALD process, spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric material is further recessed or etched back by a dry etching process, a wet etching process, and / or a combination thereof to form the isolation feature 214. As Figure 3B As shown, the top 212T of the fin structure 212 rises above the isolation feature 214, while the base 212B is surrounded by the isolation feature 214. It should be noted that because Figure 3A The cross section in FIG. 1 passes through the fin structure 212, so Figure 3A The isolation member 214 is not shown.

[0024] refer to Figure 1 , Figure 4A , Figure 4B , Figure 5A and Figure 5B , the method 100 includes a frame 108, in which a capping layer 216 and a dielectric fin 220 are formed. In some embodiments, the capping layer 216 may have a composition similar to that of the sacrificial layer 206. In one example, the capping layer 216 may be formed of silicon germanium (SiGe). This common composition allows the sacrificial layer 206 and the capping layer 216 to be selectively removed in a subsequent process. In some embodiments, the capping layer 216 may be conformally and epitaxially grown using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). The deposition process of the capping layer 216 is selected so that the capping layer 216 is amorphous and conformally deposits the capping layer 216 on the surface of the workpiece 200 (including the surface of the fin-shaped structure 212 and the isolation member 214). In some cases, the capping layer 216 may have a thickness between about 5 nm and about 10 nm. After the capping layer 216 is deposited above the workpiece 200, an etch-back process is performed on the workpiece 200 to recess the capping layer 216 until the capping layer 216 on the surface facing the top is removed. That is, after the etch-back process, top surfaces of the hard mask layer 210 and the isolation features 214 may be exposed.

[0025] Still reference Figure 4A and Figure 4B, block 108 also forms dielectric fins 220. In some embodiments, dielectric fins 220 may be formed in trenches formed after forming capping layer 216. In the depicted embodiment, each of dielectric fins 220 includes multiple layers. In an exemplary process, a liner 222 is conformally deposited over workpiece 200 (including over capping layer 216 and fin-shaped structure 212). The liner 222 may be deposited using PECVD, ALD, or a suitable method. Then, a fill layer 224 is deposited over the liner 222 on workpiece 200 using CVD, SACVD, FCVD, ALD, spin coating, and / or other suitable processes. The liner 222 may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. The fill layer 224 may include silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbonitride, or a suitable dielectric material. After the liner 222 and the fill layer 224 are deposited, the workpiece 200 is planarized using a planarization process such as a chemical mechanical polishing (CMP) process until the liner 222 and the fill layer 224 above the cap layer 216 are removed. After planarization, portions of the fill layer 224 and the liner 222 are selectively and partially recessed, and then a cap layer 226 is deposited over the workpiece 200. The cap layer 226 may include silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. Then, the workpiece 200 is planarized again using a CMP process to remove excess cap layer 226 on the cap layer 216. At this point, the dielectric fins 220 are substantially formed. Each of the dielectric fins 220 includes a cap layer 226 disposed above the fill layer 224 and the liner 222. In one embodiment, liner 222 includes silicon nitride or silicon carbonitride, fill layer 224 includes silicon oxide, and cap layer 226 includes silicon carbonitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, or hafnium oxide.

[0026] refer to Figure 5A and Figure 5BAfter forming the dielectric fins 220, the workpiece 200 is anisotropically etched to selectively remove portions of the capping layer 216 and the hard mask layer 210 to expose the topmost channel layer 208 without substantially damaging the cap layer 226. The anisotropic etching process may include a single-stage etching process or a multi-stage etching process. When the anisotropic etching process is a single-stage process, it is selective to semiconductor materials (e.g., silicon and silicon germanium) and silicon nitride. When the anisotropic etching process is a multi-stage process, the first stage may be selective to semiconductor materials (e.g., silicon and silicon germanium), and the second stage may be selective to silicon nitride. In some embodiments, the anisotropic etching process may include hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof.

[0027] refer to Figure 1 , Fig. 6A and Figure 6B , the method 100 includes a frame 110, wherein a dummy gate stack 230 is formed above the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or a gate-last process) is adopted, wherein the dummy gate stack 230 is used as a reserved position for a functional gate structure. Other processes and configurations are also possible. Although not explicitly shown, the dummy gate stack 230 may include a dummy dielectric layer and a dummy electrode disposed above the dummy dielectric layer. The region of the fin structure 212 located below the dummy gate stack 230 may be referred to as a channel region 212C. Each of the channel regions in the fin structure 212 is sandwiched between the source region 212S and the drain region 212D. In an exemplary process, a dummy dielectric layer is blanket deposited over the substrate 200 by CVD. Then a material layer for a dummy electrode is blanket deposited over the dummy dielectric layer. Then the dummy dielectric layer and the material layer for the dummy electrode are patterned using a photolithography process to form a dummy gate stack 230. In some embodiments, the dummy dielectric layer may include silicon oxide, and the dummy electrode may include polysilicon (poly silicon).

[0028] After forming the dummy gate stack 230, frame 110 also includes an operation for forming at least one gate spacer 232 along the sidewall of the dummy gate stack 230. The at least one gate spacer 232 may include two or more gate spacer layers. The dielectric material for the at least one gate spacer 232 may be selected to allow selective removal of the dummy gate stack 230 without substantially damaging the at least one gate spacer 232. Suitable dielectric materials may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, silicon oxynitride, and / or combinations thereof. In an exemplary process, at least one gate spacer 232 may be conformally deposited over the workpiece 200 using CVD, sub-atmospheric CVD (SACVD), or ALD. In one embodiment, the at least one gate spacer 232 includes two gate spacers, one of which is formed of silicon nitride and the other of which is formed of silicon carbonitride. Other combinations are fully contemplated. In some embodiments, after depositing the at least one gate spacer 232 , the at least one gate spacer 232 is etched back to expose the top surface of the fin structure 212 in the source region 212S and the drain region 212D.

[0029] refer to Figure 1 , Fig. 6A and Figure 6B , the method 100 includes block 112 , in which the source region 212S and the drain region 212D of the fin structure 212 are recessed to form a source opening 235S and a drain opening 235D. Fig. 6A A partial cross-sectional view of the fin-shaped structure 212 is shown when viewed from the side of the fin-shaped structure 212 . Figure 6B A partial cross-sectional view of the fin structure 212 at the drain region 212D along the longitudinal direction (X direction) of the fin structure 212 is shown. With the dummy gate stack 230 and the at least one gate spacer 232 used as an etching mask, the workpiece 200 is anisotropically etched in the source region 212S and the drain region 212D to form a source opening 235S and a drain opening 235D. Fig. 6A and Figure 6BAs shown, the source opening 235S and the drain opening 235D extend not only through the channel layer 208 and the sacrificial layer 206, but also extend through a portion of the substrate 202. The operation at box 112 can substantially remove the top 212T of the fin structure 212 in the source region 212S and the drain region 212D. The anisotropic etching at box 112 can include a dry etching process or a suitable etching process. For example, the dry etching process can be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As Fig. 6A and Figure 6B As shown, the dry etching process at box 120 may etch the cap layer 226 and the liner 222 at a slower rate and leave them substantially unetched. The sidewalls of the plurality of channel layers 208 , the plurality of sacrificial layers 206 , and the capping layer 216 are exposed in the source opening 235S and the drain opening 235D.

[0030] refer to Figure 1 , Fig. 7A and Figure 7B , the method 100 includes block 114, where an inner spacer member 236 is formed. Fig. 7A, at block 114, the sacrificial layer 206 exposed in the source opening 235S and the drain opening 235D is first selectively and partially recessed to form an internal spacer recess, while the exposed channel layer 208 is substantially not etched. Because the capping layer 216 and the sacrificial layer 206 share similar compositions, the capping layer 216 may also be etched at block 114. In embodiments where the channel layer 208 is substantially composed of silicon (Si), the sacrificial layer 206 is substantially composed of silicon germanium (SiGe), and the capping layer 216 is substantially composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 and the capping layer 216 may include a SiGe oxidation process followed by SiGe oxide removal. In those embodiments, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective recessing may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 and the capping layer 216 are recessed is controlled by the duration of the etching process. The selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include APM etching (e.g., a mixture of ammonium hydroxide-hydrogen peroxide-water). After forming the internal spacer recesses, a layer of internal spacer material is then conformally deposited over the workpiece 200 (including over and in the internal spacer recesses and the spaces left by the removed portions of the capping layer 216) using CVD or ALD. The internal spacer material may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbon, silicon carbide, or silicon oxynitride. After depositing the layer of internal spacer material, the layer of internal spacer material is etched back to form the internal spacer features 236, such as Fig. 7A shown.

[0031] refer to Figure 1 , Fig. 8A and Figure 8B, method 100 includes frame 116, wherein a dummy epitaxial component 238, a first epitaxial layer 240, and a second epitaxial layer 242 are deposited to form a source component 242S and a drain component 242D. In some embodiments, the dummy epitaxial component 238 may include silicon germanium (SiGe) or a semiconductor material different from the semiconductor material forming the substrate 202. In some cases, the dummy epitaxial component 238 may be doped with an n-type dopant (such as phosphorus (P) or arsenic (As)) or a p-type dopant (such as boron (B) or gallium (Ga)). The difference in composition provides etching selectivity in subsequent operations for self-aligned formation of backside contact openings. The first epitaxial layer 240 and the second epitaxial layer 242 are formed of doped semiconductor materials, and their composition depends on the conductivity type of the desired MBC transistor. When an n-type MBC transistor is desired, the first epitaxial layer 240 and the second epitaxial layer 242 may include silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). When a p-type MBC transistor is desired, the first epitaxial layer 240 and the second epitaxial layer 242 may include silicon germanium (Si) doped with a p-type dopant such as boron (B) or gallium (Ga). In some embodiments, the first epitaxial layer 240 and the second epitaxial layer 242 may share the same semiconductor material and the same doping substance, but they have different doping concentrations. For example, when an n-type MBC transistor is desired, the first epitaxial layer 240 may have a doping concentration of 5×10 20 Atom / cm 3 and about 1x10 21 Atom / cm 3 The phosphorus (P) doping concentration of the second epitaxial layer 242 may be between 1×10 21 Atom / cm 3 and about 5×10 21 Atom / cm 3 When a p-type MBC transistor is desired, the first epitaxial layer 240 may have a phosphorus (P) doping concentration between 3×10 20 Atom / cm 3 and about 8×10 20 Atom / cm 3 The boron (B) doping concentration of the second epitaxial layer 242 may be between 8×10 20 Atom / cm 3 and about 4×10 21 Atom / cm 3 The boron (B) doping concentration is between .

[0032] In some alternative embodiments, the first epitaxial layer 240 and the second epitaxial layer 242 may include different dopants of the same conductivity type. For example, when an n-type MBC transistor is desired, the first epitaxial layer 240 may be doped with arsenic (As) and the second epitaxial layer 242 may be doped with phosphorus (P). When a p-type MBC transistor is desired, the first epitaxial layer 240 may be doped with gallium (Ga) and the second epitaxial layer 242 may be doped with boron (B).

[0033] At block 114, first, a dummy epitaxial component 238 is deposited. Then, a first epitaxial layer 240 is deposited over the dummy epitaxial component 238. Thereafter, a second epitaxial layer 242 is deposited over the first epitaxial layer 240. Each of the dummy epitaxial component 238, the first epitaxial layer 240, and the second epitaxial layer 242 may be epitaxially deposited using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)) and / or other suitable epitaxial growth processes. In an exemplary process, silicon germanium is epitaxially deposited in the source opening 235S and the drain opening 235D over the exposed substrate 202. In some embodiments, in order to remove the dummy epitaxial component 238 from the surface of the channel layer 208, an etch back may be performed to recess the dummy epitaxial component 238. Then a first epitaxial layer 240 is deposited over the dummy epitaxial component 238 in the source opening 235S and the drain opening 235D. Similarly, in order to remove the first epitaxial layer 240 from the surface of the channel layer 208, in some embodiments, the deposited first epitaxial layer 240 may be subjected to an etch-back process to expose the sidewalls of the channel layer 208. After the first epitaxial layer 240 is deposited, the second epitaxial layer 242 is selectively deposited on the sidewalls of the channel layer 208 and the first epitaxial layer 240. In some embodiments, a pre-cleaning process may be performed after the dummy epitaxial component 238 is etched back or after the first epitaxial layer 240 is etched back to provide an oxide-free and debris-free surface for the next epitaxial layer. The pre-cleaning process may include the use of RCA SC-1 (a mixture of ammonium hydroxide, hydrogen peroxide, and water) and / or RCA SC-2 (a mixture of hydrochloric acid, hydrogen peroxide, and water). The second epitaxial layer 242 deposited in the source opening 235S may be referred to as a source component 242S, and the second epitaxial layer 242 deposited in the drain opening 235D may be referred to as a drain component 242D. It should be noted that in the depicted embodiment and with respect to one MBC transistor, the source feature 242S and the drain feature 242S are substantially identical in composition. They are referred to differently due to their location (ie, in the source opening 235S or in the drain opening 235D).

[0034] like Fig. 8A and Figure 8BAs shown, the dummy epitaxial feature 238 is disposed in the base 212B and is actually raised above the top surface of the isolation feature 214. The second epitaxial layer 242 (including the source feature 242S and the drain feature 242D) is substantially disposed above the top surface of the isolation feature 214. Fig. 8A As shown, the second epitaxial layer 242 contacts the sidewalls of the channel layer 208 and the inner spacer features 236. The first epitaxial layer 240 is disposed between the dummy epitaxial features 238 and the second epitaxial layer 242. Thus, the first epitaxial layer 240 is disposed around the level of the top surface of the isolation features 214. The second epitaxial layer 242 is also in contact with the adjacent dielectric fin 220, while the first epitaxial layer 240 and the dummy epitaxial features 238 are spaced apart from the dielectric fin 220.

[0035] refer to Figure 1 , Fig. 8A and Figure 8B , the method 100 includes block 118, where a contact etch stop layer (CESL) 246 and an interlayer dielectric (ILD) layer 248 are deposited. In an exemplary process, the CESL 246 is first conformally deposited over the workpiece 200, and then the ILD layer 248 is blanket deposited over the CESL 246. The CESL 246 may include silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The CESL 246 may be deposited using an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 248 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 248 may be deposited by spin coating, an FCVD process, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 248, the workpiece 200 may be annealed to improve the integrity of the ILD layer 248. To remove excess material and to expose the top surface of the dummy gate stack 230, a planarization process (such as a chemical mechanical polishing (CMP) process) may be performed on the workpiece 200 to provide a planar top surface. The top surface of the dummy gate stack 230 is exposed on the planar top surface.

[0036] refer to Figure 1 , Fig.9A and Fig. 9B, the method 100 includes box 120, in which the dummy gate stack 230 is removed and the channel member 2080 is released. After the dummy gate stack 230 is exposed by planarization at box 118, the dummy gate stack 230 is removed from the workpiece 200 by a selective etching process. The selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer and the dummy electrode in the dummy gate stack 230. Removal of the dummy gate stack 230 results in a gate trench 249 above the channel region 212C. After removal of the dummy gate stack 230, the channel layer 208, the sacrificial layer 206, and the capping layer 216 (at the gate trench 249) in the channel trench 212C are exposed. Fig.9A Due to their similar compositions, the exposed sacrificial layer 206 between the channel layer 208 and the capping layer 216 can be selectively removed to release the channel layer 208 to form the channel member 2080, as shown in FIG. Fig.9A As shown. Channel member 2080 is stacked vertically along the Z direction. The sacrificial layer 206 and the capping layer 216 can be selectively removed by selective dry etching, selective wet etching or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (for example, a mixture of ammonium hydroxide-hydrogen peroxide-water). In some optional embodiments, the selective removal includes the oxidation of silicon germanium followed by the removal of oxidized silicon germanium. For example, oxidation can be provided by ozone cleaning, and then the oxidized silicon germanium is removed by an etchant such as NH4OH. In the case of removing the sacrificial layer 206 and the capping layer 216 in the channel region, the top surface of the pad 222, the channel member 2080, the base 212B and the isolation component 214 are exposed in the gate trench 249.

[0037] refer to Figure 1 , Fig. 10A , Fig. 10B and Fig. 10C , method 100 includes frame 122, wherein gate structure 250 is formed to wrap each of channel member 2080. Gate structure 250 may include an interface layer, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. In some embodiments, the interface layer may include silicon oxide and may be formed due to a pre-cleaning process. An exemplary pre-cleaning process may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of channel member 2080 and substrate 202 to form an interface layer. A gate dielectric layer is then deposited over the interface layer using ALD, CVD, and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material. As used herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than the dielectric constant of thermal silicon oxide. In one embodiment, the gate dielectric layer may include hafnium oxide. Alternatively, the gate dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. After forming or depositing the gate dielectric layer, a gate electrode layer is deposited over the gate dielectric layer. The gate electrode layer may be a multilayer structure including at least one work function layer and a metal filling layer. For example, at least one work function layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN) or tantalum carbide (TaC). The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a planarization process such as a CMP process may be implemented to remove excess material to provide a substantially flat top surface of the gate structure. Reference Fig.11A , the gate structure 250 wraps around each of the channel members 2080 .

[0038] In some embodiments, the front side contacts and interconnect structures are formed before the workpiece 200 is flipped over to form the back side contacts and interconnect structures. Fig.18A , Fig.18B and Fig.18CIn some embodiments shown, a front side drain contact 280 may be formed through the ILD layer 248 and the CESL 246 to contact the drain feature 242D. The front side drain contact 280 includes a drain silicide feature 282 and a drain plug 284. In an exemplary process, a front side drain contact opening is formed through the ILD layer 248 and the CESL 246 to expose the drain feature 242D. To form the drain silicide feature 282, a metal layer is deposited over the exposed surface of the drain feature 242D, and an annealing process is performed to induce a silicide reaction between the metal layer and the drain feature 242D. Suitable metal layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The drain silicide feature 282 may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). Although not explicitly shown, excess metal layers that do not form drain silicide features 282 may be removed. After forming drain silicide features 282, a metal fill layer may be deposited in the front side drain contact opening to form a drain plug 284. The metal fill layer may include aluminum (Al), rhodium (Rh), ruthenium (Ru), copper (Cu), iridium (Ir), or tungsten (W). A planarization process such as a CMP process may subsequently remove excess material and provide a flat top surface. Front side drain contact 280 is electrically coupled to drain feature 242D.

[0039] Although not explicitly shown, a front-side interconnect structure may be formed above the workpiece 200 before the workpiece 200 is flipped. The front-side interconnect structure may include a plurality of intermetallic dielectric (IMD) layers and a plurality of metal lines or contact vias in each of the IMD layers. In some cases, the IMD layer and the ILD layer 248 may share similar compositions. The metal lines and contact vias in each of the IMD layers may be formed of metals such as aluminum (Al), tungsten (W), ruthenium (Ru), or copper (Cu). In some embodiments, the metal lines and contact vias may be lined with a barrier layer to isolate the metal lines and contact vias from the IMD layer and prevent electromigration.

[0040] refer to Figure 1 , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B and Fig. 14C, the method 100 includes a block 124, in which a second backside source contact opening 2620 is formed. In some embodiments, the operation at block 122 may include: turning the workpiece 200 upside down (eg, Fig.11A , Fig. 11B and Fig. 11C ); anisotropically etching the substrate 202 to expose the dummy epitaxial feature 238 (as shown); Fig. 12A , Fig. 12B and Fig. 12C isotropically and selectively etching the dummy epitaxial feature 238 to expose the first epitaxial layer 240 (as shown); Fig.13A , Fig. 13B and Fig. 13C and depositing a dielectric barrier layer 264 and etching back (as shown); Fig.14A , Fig. 14B and Fig. 14C ). In order to flip the workpiece 200 upside down, a carrier substrate (not explicitly shown) is bonded to the workpiece 200 (or the front-side interconnect structure). In some embodiments, the carrier substrate can be bonded to the workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some cases, the carrier substrate can be formed of a semiconductor material (such as silicon), sapphire, glass, a polymer material, or other suitable material. In an embodiment using fusion bonding, the carrier substrate includes a bottom oxide layer and the workpiece 200 includes a top oxide layer. After processing the bottom oxide layer and the top oxide layer, they are furred into contact with each other for direct bonding at room temperature or high temperature. Once the carrier substrate is bonded to the workpiece 200, the workpiece 200 is flipped, as shown. Fig.11A , Fig. 11B and Fig. 11C As shown. Fig. 12A , Fig. 12B and Fig. 12C Representatively shown, after the workpiece 200 is flipped, the back side of the workpiece 200 is planarized down to the isolation features (not explicitly shown).

[0041] Still reference Fig. 12A , Fig. 12B and Fig. 12C, a patterned hard mask 260 is formed over the back side of the workpiece 200. The patterned hard mask 260 selectively exposes the source region 212S while covering the drain region 212D. The substrate 202 is then anisotropically etched until the dummy epitaxial feature 238 is exposed in the first back side source contact opening 262. In some embodiments, the anisotropic etching at box 124 can be an isotropic dry etching process including the use of oxygen (O2), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In one embodiment, the anisotropic dry etching can include the use of a mixture of hydrogen bromide (HBr), oxygen (O2), and chlorine (Cl2). In some embodiments, the etchant flow rate can be between about 5 standard cubic centimeters per minute (SCCM) and about 200 SCCM, the chamber pressure can be between about 1 mTorr and about 100 mTorr, the process time can be between about 5 seconds and about 180 seconds, and the bias radio frequency (RF) power can be between about 50 W and about 250 W. The selective dry etching process is not selective to the substrate 202 and can also etch the dummy epitaxial features 238. After forming the first backside source contact opening 262, the patterned hard mask 260 can be removed by etching, ashing, or other suitable processes.

[0042] Reference now Fig.13A , Fig. 13B and Fig. 13C , the dummy epitaxial feature 238 exposed in the first backside source contact opening 262 is selectively and isotropically etched to expose the first epitaxial layer 240. As shown, the dummy epitaxial feature 240 is selectively removed to extend the first backside source contact opening 262 toward the source feature 242S to form a second backside source contact opening 2620. In some embodiments, the selective and isotropic etching at block 124 may be an isotropic dry etching including a fluorine-containing gas (e.g., fluorine (F2), NF3, CF4, SF6, CH2F2, CHF3, and / or C2F6) and hydrogen fluoride (HF). In one embodiment, the selective and isotropic dry etching may include using a mixture of fluorine (F2) and hydrogen fluoride (HF). In some embodiments, the etchant flow rate may be between about 5 SCCM and about 200 SCCM, the chamber pressure may be between about 1 mTorr and about 100 mTorr, the process time may be between about 5 seconds and about 180 seconds, and the plasma power may be between about 50 W and 250 W. It should be noted that because the isotropic etch is not directional, the plasma for the isotropic etch is generated by a remote plasma system (RPS). Fig.13A , Fig. 13B and Fig. 13CAs shown, because the formation of the first backside source contact opening 262 is anisotropic and the extension of the first backside source contact opening 262 is selective to the dummy epitaxial feature 238, the second backside source contact opening 2620 includes a step-type width variation. Here, the step-type width variation means that the second backside source contact opening 2620 includes a step-type variation along the X direction.

[0043] Reference now Fig.14A , Fig. 14B and Fig. 14C A dielectric barrier layer 264 is deposited over the workpiece 200 and then etched back. In some embodiments, the dielectric barrier layer 264 may include silicon nitride. The dielectric barrier layer 264 is then etched back or pulled back so that the sidewalls of the second backside source contact opening 2620 are covered by the dielectric barrier layer 264. Fig.14A , Fig. 14B and Fig. 14C As shown, the etch back not only removes the dielectric barrier layer 264 on the first epitaxial layer 240, but also removes the first epitaxial layer 240, thereby exposing the source component 242S. Here, the first epitaxial layer 240 serves as an epitaxial etch stop layer to prevent accidental damage to the source component 242S. In some embodiments, the dielectric barrier layer 264 can be deposited using CVD, ALD, or a suitable process, and the etch back can include using an anisotropic etching process, which can include using nitrogen, hydrogen, fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof.

[0044] refer to Figure 1 , Fig.15A , Fig. 15B and Fig. 15C, the method 100 includes a frame 126, in which a backside source contact 270 is formed. After the source component 242S is exposed in the second backside source contact opening 2620, a backside source contact 270 is formed in the second backside source contact opening 2620. The backside source contact 270 may include a source silicide component 266 and a source plug 268. To form the source silicide component 266, a metal layer is deposited over the exposed surface of the source component 242S, and an annealing process is performed to induce a silicide reaction between the metal layer and the source component 242S. Suitable metal layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The source silicide component 266 may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). Although not explicitly shown, excess metal layers that do not form source silicide features 266 may be removed. After forming source silicide features 266, a metal fill layer may be deposited in second backside source contact opening 2620 to form source plug 268. The metal fill layer may include tungsten (W), ruthenium (Ru), copper (Cu), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), titanium nitride (TaN), molybdenum (Mo), or nickel (Ni). A planarization process such as a CMP process may subsequently remove excess material and provide a flat top surface. Backside source contact 270 is electrically coupled to source feature 242S.

[0045] refer to Figure 1 , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B and Fig. 17C , the method 100 includes block 128, where the substrate 202 is replaced with the backside dielectric layer 278. Fig.15A , Fig. 15B and Fig. 15C As shown, at the end of the operation at block 126, the remaining substrate 202 is surrounded by features formed of different materials, including isolation features 214, dielectric barrier layer 264, and backside source contact 270. This arrangement allows for selective removal of the remaining substrate 202, such as Fig.16A , Fig. 16B and Fig. 16CAs shown. In some embodiments, selective removal of substrate 202 can be performed using selective wet etching or selective dry etching. An exemplary selective wet etching process may include a mixture of nitric acid and hydrofluoric acid or a solution of tetramethylammonium hydroxide (TMAH). An exemplary selective dry etching process may include a fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3, and / or C2F6) and a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3). Now referring to Fig.17A , Fig. 17B and Fig. 17C , after selectively removing the remaining substrate 202, a liner 276 is deposited over the back side of the workpiece 200 using CVD, ALD, or a suitable deposition technique. The liner 276 may include silicon nitride. A backside dielectric layer 278 is then deposited over the liner 276. The backside dielectric layer 278 may include silicon oxide and may be deposited using spin coating, CVD, or plasma enhanced CVD (PECVD). A planarization process such as a CMP process may be performed to remove excess material.

[0046] In the depicted embodiment, the stepped profile of the second backside source contact opening 2620 can result in a stepped profile of the backside source contact 270. Fig.17A As shown, the backside source contact 270 includes a first portion 270-1 adjacent to the source component 242S and a second portion 270-2 away from the source component 242S. The first portion 270-1 includes a first width W1 along the X direction and a first height H1 along the Z direction. The second portion 270-2 includes a second width W2 along the X direction and a second height H2 along the Z direction. In some embodiments, the second height H2 is equal to or greater than the first height H1, and the first width W1 is different from the second width W2. In some embodiments, the ratio of the second height H2 to the first height H1 is between about 1 and about 2. In these embodiments, the first height H1 can be between about 1nm and about 30nm, and the second height H2 can be between about 1nm and about 30nm. In some optional embodiments, the first height H1 is less than the second height H2. In the depicted embodiment, there is a step-like transition from the first width W1 to the second width W2. That is, the change from the first width W1 to the second width W2 is not gradual. This step-wise width change of the backside source contact 270 distinguishes it from a contact with a tapered profile where the width change is gradual and continuous. Fig.17A In the illustrated embodiment, the second width W2 is greater than the first width W1. In some cases, the ratio of the second width W2 to the first width W1 is between about 1.1 and about 2.5. In these cases, the second width W2 can be between about 6 nm and about 20 nm, and the first width W1 can be between about 5 nm and about 15 nm.

[0047] refer to Figure 1 , the method 100 includes a block 130, in which further processes are performed. Such further processes may include, for example, forming a backside power rail (not shown). In an exemplary process, an insulating layer having a composition similar to that of the ILD layer 248 may be deposited over the backside of the workpiece 200 (including over the backside dielectric layer 278, the isolation features 214, and the backside source contact 270). Then, a power rail trench may be patterned in the insulating layer. Then a barrier layer and a metal fill material are deposited in the power rail trench to form the backside power rail. In some embodiments, the barrier layer in the backside power rail may include titanium nitride, tantalum nitride, cobalt nitride, nickel nitride, or tungsten nitride, and the metal fill material in the backside power rail may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo). The barrier layer and the metal fill layer may be deposited using PVD, CVD, ALD, or electroless plating. A planarization process such as a CMP process may be performed to remove excess material over the insulating layer.

[0048] exist Fig.17A and Fig.18A In the illustrated embodiment, the first portion 270-1 and the second portion 270-2 are aligned along the Z direction. That is, the centerline of the first portion 270-1 coincides with the centerline of the second portion 270-2. Fig.19 In some optional embodiments shown, when forming the first backside source contact opening 262, imperfect mask overlap may result in an offset backside source contact 271. The offset backside source contact 271 includes a first portion 270-1 and an offset second portion 270-2'. Fig.19 As shown, the second portion 270-2' of the offset backside source contact 271 is not perfectly aligned with the first portion 270-1 along the Z-direction. That is, the centerline of the second portion 270-2' is offset from the centerline of the first portion 270-1. Fig.19 The offset shown demonstrates the advantages of the present invention. Even when the first backside source contact opening 262 is misaligned, it stops around the level of the dummy epitaxial feature 238 and does not extend all the way to the gate structure 250. If the first backside source contact opening 262 is allowed to cut into the gate structure 250, the gate structure 250 will short with the source feature 242S, causing the MBC transistor to be defective.

[0049] exist Fig.17A and Fig.18A In the illustrated embodiment, the second width W2 is greater than the first width W1. The second portion 270-2 is wider than the first portion 270-1 along the X direction. Fig. 20In some optional embodiments shown, when the first backside source contact opening 262 is narrower than the dummy epitaxial feature 238, an optional backside source contact 272 may be produced. Fig. 20 As shown, optional backside source contact 272 includes first portion 270 - 1 and optional second portion 270 - 2 ″. Optional second portion 270 - 2 ″ has a third width W3 that is less than first width W1 of first portion 270 - 1 . In some cases, third width W3 is between about 4 nm and about 13 nm.

[0050] exist Fig.17A , Fig.18A , Fig.19 , Fig. 20 In the workpiece 200 shown in FIG. 1 , the dummy epitaxial feature 238 and the first epitaxial layer 240 in the drain region 212D remain because no backside drain contact coupled to the drain feature 242D is formed. Fig.17A , Fig.18A , Fig.19 , Fig. 20 As shown, the first epitaxial layer 240 is in contact with the drain feature 242D and is disposed between the dummy epitaxial feature 238 and the drain feature 242D.

[0051] Embodiments of the present invention provide advantages. For example, the method of the present invention includes forming a pseudo-epitaxial component in a source opening extending into a substrate. When forming a backside source contact opening, the substrate is first anisotropically etched to form a first backside source contact opening to expose the pseudo-epitaxial component, and then the pseudo-epitaxial component is selectively and isotropically removed. Due to the two-step etching process, the resulting backside source contact includes a stepped width variation. In addition, when a backside drain contact is not formed, the pseudo-epitaxial component can be retained in the drain region. This two-step formation process of the backside source contact opening is beneficial for preventing a short circuit between the gate structure and the source component.

[0052] In one exemplary aspect, the invention is directed to a semiconductor structure. The semiconductor structure includes: an epitaxial source component and an epitaxial drain component; a vertical stack of channel components disposed above a back dielectric layer, the vertical stack of channel components extending between the epitaxial source component and the epitaxial drain component along a direction; a gate structure wrapping each of the vertical stack of channel components; and a back source contact disposed in the back dielectric layer. The back source contact includes a top portion adjacent to the epitaxial source component and a bottom portion distal to the epitaxial source component. The top portion and the bottom portion include a step width variation along a direction.

[0053] In some embodiments, the semiconductor structure further comprises: a front side drain contact located above the epitaxial drain component. In some embodiments, the width of the top is greater than the width of the bottom along the direction. In some cases, the width of the top is less than the width of the bottom along the direction. In some embodiments, the centerline of the bottom is offset from the centerline of the top. In some cases, the semiconductor structure further comprises: a pseudo-epitaxial component embedded in the back dielectric layer. In some embodiments, the epitaxial drain component comprises a first epitaxial layer in contact with the pseudo-epitaxial component and a second epitaxial layer above the first epitaxial layer. In some cases, the second epitaxial layer contacts the vertical stack of channel components, and the first epitaxial layer is spaced apart from the vertical stack of channel components.

[0054] In another exemplary aspect, the present invention is directed to a semiconductor structure. The semiconductor structure includes: a source component and a drain component; a plurality of channel components, disposed above a back dielectric layer, the plurality of channel components extending between the source component and the drain component along a first direction, and the plurality of channel components stacked along a second direction perpendicular to the first direction; a gate structure, wrapping each of the plurality of channel components; and a back source contact, disposed in the back dielectric layer, the back source contact including a first portion adjacent to the source component and a second portion away from the source component. The first portion includes a first width along the first direction, and the second portion includes a second width along the first direction. The first portion includes a first height along the second direction, and the second portion includes a second height along the second direction. The first width is different from the second width, and the first height is less than the second height.

[0055] In some embodiments, the ratio of the second height to the first height is between about 1.1 and about 2. In some embodiments, the centerline of the second portion is offset from the centerline of the first portion. In some embodiments, the semiconductor structure further comprises: a dummy epitaxial component embedded in the back dielectric layer. In some embodiments, the drain component comprises a first epitaxial layer in contact with the dummy epitaxial component and a second epitaxial layer above the first epitaxial layer. In some cases, the first epitaxial layer and the second epitaxial layer comprise a dopant, and the concentration of the dopant in the second epitaxial layer is greater than the concentration of the dopant in the first epitaxial layer. In some embodiments, the second epitaxial layer contacts a plurality of channel components, and the first epitaxial layer is spaced apart from the plurality of channel components.

[0056] In yet another exemplary aspect, the present invention is directed to a method. The method includes: forming a stack including a plurality of channel layers interleaved by a plurality of sacrificial layers over a substrate; patterning the stack and the substrate to form a fin-shaped structure; forming a source opening and a drain opening; depositing a dummy epitaxial component in the source opening and the drain opening; forming a source component in the source opening and a drain component in the drain opening, the source component and the drain component being disposed over the dummy epitaxial component; anisotropically etching the substrate to form a backside contact opening of the dummy epitaxial component exposing the source component; selectively and isotropically etching the dummy epitaxial component; and forming a backside source contact in the backside contact opening to couple to the source component. In some embodiments, the anisotropic etching includes using hydrogen bromide, oxygen, or chlorine. In some embodiments, the selective and isotropic etching includes using fluorine and hydrogen fluoride. In some cases, the method further includes: depositing an epitaxial layer over the dummy epitaxial component before forming the source component and the drain component. In some embodiments, the method further comprises: depositing a dielectric barrier layer over the source opening before forming the backside source contact; and etching back the dielectric barrier layer. The etching back also removes the epitaxial layer over the source feature.

[0057] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: an epitaxial source component and an epitaxial drain component; a vertical stack of channel components disposed above the backside dielectric layer, the vertical stack of channel components extending between the epitaxial source component and the epitaxial drain component in a direction from the epitaxial source component to the epitaxial drain component; a gate structure wrapping each of the vertical stack of channel members; a dummy epitaxial feature embedded in the backside dielectric layer; as well as a back side source contact disposed in the back side dielectric layer, The back side source contact comprises a top portion adjacent to the epitaxial source component and a bottom portion away from the epitaxial source component, Wherein, the top and the bottom include a step width variation along the direction.

2. The semiconductor structure according to claim 1, further comprising: A front drain contact is located above the epitaxial drain feature.

3. The semiconductor structure according to claim 1, wherein: The width of the top portion is greater than the width of the bottom portion along the direction.

4. The semiconductor structure according to claim 1, wherein: The width of the top portion is smaller than the width of the bottom portion along the direction.

5. The semiconductor structure according to claim 1, wherein: A centerline of the bottom portion is offset from a centerline of the top portion.

6. The semiconductor structure according to claim 1, further comprising: A silicide feature is disposed between the epitaxial source feature and the backside source contact.

7. The semiconductor structure according to claim 1, wherein: The epitaxial drain feature includes a first epitaxial layer contacting the dummy epitaxial feature and a second epitaxial layer over the first epitaxial layer.

8. The semiconductor structure according to claim 7, wherein: The second epitaxial layer is in contact with the vertical stack of channel members, and the first epitaxial layer is spaced apart from the vertical stack of channel members.

9. A semiconductor structure comprising: a source component and a drain component; a plurality of channel members disposed over the backside dielectric layer, the plurality of channel members extending between the source member and the drain member along a first direction from the source member to the drain member, the plurality of channel members being stacked along a second direction perpendicular to the first direction; a gate structure wrapping each of the plurality of channel members; a dummy epitaxial feature embedded in the backside dielectric layer; as well as a backside source contact disposed in the backside dielectric layer, the backside source contact comprising a first portion adjacent to the source feature and a second portion remote from the source feature, wherein the first portion comprises a first width along the first direction, and the second portion comprises a second width along the first direction, wherein the first portion comprises a first height along the second direction, and the second portion comprises a second height along the second direction, wherein the first width is different from the second width, Wherein, the first height is smaller than the second height.

10. The semiconductor structure according to claim 9, wherein: A ratio of the second height to the first height is between 1.1 and 2.

11. The semiconductor structure according to claim 9, wherein: A centerline of the second portion is offset from a centerline of the first portion.

12. The semiconductor structure according to claim 9, wherein: The gate structure is separated from the backside dielectric layer by a liner, and the backside dielectric layer and the liner are made of different materials.

13. The semiconductor structure according to claim 12, in, The drain feature includes a first epitaxial layer contacting the dummy epitaxial feature and a second epitaxial layer over the first epitaxial layer.

14. The semiconductor structure according to claim 13, in, The first epitaxial layer and the second epitaxial layer include a dopant, The concentration of the dopant in the second epitaxial layer is greater than the concentration of the dopant in the first epitaxial layer.

15. The semiconductor structure according to claim 13, wherein: The second epitaxial layer contacts the plurality of channel members, and the first epitaxial layer is spaced apart from the plurality of channel members.

16. A method of forming a semiconductor structure, comprising: forming a stack including a plurality of channel layers interleaved by a plurality of sacrificial layers over the substrate; patterning the stack and the substrate to form a fin structure; forming a source opening and a drain opening; depositing dummy epitaxial features in the source opening and the drain opening; forming a source feature in the source opening and a drain feature in the drain opening, the source feature and the drain feature being disposed above the dummy epitaxial feature; anisotropically etching the substrate to form a backside contact opening of the dummy epitaxial feature exposing the source feature; selectively and isotropically etching the dummy epitaxial feature; as well as A backside source contact is formed in the backside contact opening to couple to the source feature.

17. The method according to claim 16, wherein: The anisotropic etching includes using hydrogen bromide, oxygen or chlorine.

18. The method according to claim 16, wherein: The selective and isotropic etching includes the use of fluorine and hydrogen fluoride.

19. The method according to claim 16, further comprising: An epitaxial layer is deposited over the dummy epitaxial feature before forming the source feature and the drain feature.

20. The method according to claim 19, further comprising: before forming the backside source contact, depositing a dielectric barrier layer over the source opening; as well as etching back the dielectric barrier layer, The etch-back also removes the epitaxial layer above the source component.

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