Hybrid thin film transistor integrated electronic device and corresponding manufacturing method

Abstract

Provided are an electronic device and a manufacturing method integrating a silicon-based thin film transistor and a metal oxide thin film transistor. The electronic device includes a substrate, a stacked conductor layer, a silicon-based thin film transistor and a metal oxide thin film transistor arranged on the substrate. The silicon-based thin film transistor and the metal oxide thin film transistor each include a gate, a source, a drain and a semiconductor layer, and the semiconductor layer includes a source contact surface and a drain contact surface. The source and drain of the two thin film transistors are respectively formed by a first conductor layer and a second conductor layer arranged in a stacked manner. The first conductor layer and the second conductor layer are respectively in contact with the source contact surface and the drain contact surface of the semiconductor layer of the two types of thin film transistors. By using the present invention, the problems of semiconductor surface treatment and electrode material selection can be solved, and it is suitable for a metal oxide thin film transistor structure with a protective etching barrier layer, thereby realizing more convenient and lower-cost monolithic integration of hybrid TFTs.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to an electronic device integrated with a hybrid thin film transistor and a corresponding manufacturing method. Background Art

[0002] In the field of flat panel displays based on liquid crystal or organic light-emitting diodes, thin film transistors (TFTs) as driving elements are constantly innovating in technology. In addition, TFTs are also widely used in new optoelectronic systems outside the field of flat panel displays. Currently, TFTs mass-produced in the industrial system are generally based on silicon materials, and mostly exist in the form of amorphous silicon or low-temperature polycrystalline silicon (Low Temperature Poly-Silicon: LTPS), but silicon-based TFT technology is also limited by the characteristics of silicon materials. Compared with silicon-based TFTs, metal oxides (MO) as active layer materials for new semiconductors have made considerable progress in recent years. TFTs based on the above-mentioned LTPS have relatively high field effect mobility, while TFTs based on MO semiconductors exhibit relatively low leakage current.

[0003] Typically, only one semiconductor material is used to construct a TFT in a given system and application. If different semiconductor materials can be used according to actual conditions, the advantages of different types of TFTs can be combined to solve application requirements. However, the monolithic integration of devices of different materials is usually limited by process incompatibility issues, and this is also the case with the monolithic integration of LTPS and MO semiconductor TFTs. Electrical signals are exchanged between one TFT and other TFTs through metal interconnections of the conductor layer. In the construction of a TFT, before the deposition and patterning of the conductive layer, the semiconductor surfaces within the source contact surface and the drain contact surface exposed in the contact through hole need to be chemically treated or cleaned. One problem is that when different types of semiconductor TFTs are integrated on a single chip, the cleaning method used to treat one semiconductor may cause damage to another semiconductor. The second problem is that, considering the production of ohmic contacts, the electrodes used by different types of semiconductor TFTs usually need to be made of different conductive materials.

[0004] For process incompatibility issues, such as Figure 1A As shown, the most direct solution in the prior art is to achieve independent conductor layers by adding additional mask steps, that is, independently completing the patterning steps of the contact holes and conductive interconnection layers of the two types of TFTs, so as to achieve electrical contact between different types of semiconductor TFTs; such metallization requires at least four mask steps, and at least two mask steps are required for each type of TFT, thus increasing the complexity and cost of the process. Figure 1BAs shown, another solution of the prior art is not to chemically treat or clean the contact holes of the LTPS TFT before depositing and patterning the common conductive interconnect layer, such as wet treatment in dilute hydrofluoric acid; although the implementation of this metallization requires only two mask steps, it will reduce the electrical contact quality of the LTPS TFT, and it is impossible to use different conductive interconnect layers to contact two different types of TFTs, resulting in the contact electrode and TFT matching not being optimal. Figure 1C As shown, another solution of the prior art is to set a layer of conductive material on the MO semiconductor layer as a protective layer of the MO semiconductor before patterning the MO semiconductor layer to prevent the chemicals used in chemical treatment or cleaning of the contact holes of the LTPS TFT from damaging the MO semiconductor layer; although the implementation of this metallization only requires two mask steps, this solution is only applicable to the back channel etched (BCE) MO TFT structure.

[0005] Therefore, there is a need for a solution for monolithic integration of hybrid thin film transistors that can solve at least one or more of the above problems. Summary of the invention

[0006] The purpose of the present invention is to provide a solution for monolithic integration of hybrid thin film transistors to solve the above problems.

[0007] Specifically, according to a first aspect of the present invention, there is provided an electronic device integrating a silicon-based thin film transistor and a metal oxide thin film transistor, the electronic device comprising a substrate, a stacked conductor layer, a silicon-based thin film transistor and a metal oxide thin film transistor, wherein:

[0008] The stacked conductor layer, the silicon-based thin film transistor and the metal oxide thin film transistor are arranged on the substrate;

[0009] The stacked conductor layer comprises a first conductor layer and a second conductor layer arranged in a stacked manner;

[0010] The silicon-based thin film transistor comprises at least a first gate and a first semiconductor layer, wherein the first semiconductor layer comprises at least a first source contact surface and a first drain contact surface;

[0011] The metal oxide thin film transistor comprises at least a second gate electrode and a second semiconductor layer, wherein the second semiconductor layer comprises at least a second source contact surface and a second drain contact surface;

[0012] One of the first conductor layer and the second conductor layer is connected to the first source contact surface and the first drain contact surface of the first semiconductor layer of the silicon-based thin film transistor to respectively form a first source and a first drain of the silicon-based thin film transistor, and the other of the first conductor layer and the second conductor layer is connected to the second source contact surface and the second drain contact surface of the second semiconductor layer of the metal oxide thin film transistor to respectively form a second source and a second drain of the metal oxide thin film transistor.

[0013] In one embodiment, the first conductor layer and the second conductor layer have openings extending therethrough, the openings having aligned or non-aligned interior sidewalls.

[0014] In one embodiment, the first conductor layer and the second conductor layer are connected to the source contact surface and the drain contact surface of the corresponding semiconductor layer of the corresponding silicon-based thin film transistor or the metal oxide thin film transistor through contact vias or directly.

[0015] In one embodiment, the electronic device further comprises:

[0016] a buffer layer, the buffer layer being disposed above the substrate and below at least the first semiconductor layer;

[0017] a gate insulating layer disposed above at least the first semiconductor layer and below at least the first gate and below or above the second gate; and

[0018] An interlayer dielectric layer, at least a portion of which is disposed above the first gate and the second gate, and the interlayer dielectric layer is located below the first conductor layer.

[0019] In one embodiment, the silicon-based thin film transistor is a thin film transistor with a top gate structure, and the metal oxide thin film transistor is a thin film transistor with a bottom gate structure or a top gate structure, and for the metal oxide thin film transistor with a bottom gate structure, an etching barrier layer is arranged above the second semiconductor layer of the metal oxide thin film transistor.

[0020] In one embodiment, the semiconductor material of the second semiconductor layer of the metal oxide thin film transistor is selected from indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO), indium tin oxide (ITO) or any combination thereof.

[0021] In one embodiment, the conductive material of the stacked conductor layer is selected from metal, metal oxide, silicide or any combination thereof, wherein:

[0022] The metal is selected from molybdenum (Mo), aluminum (Al), tungsten (W), palladium (Pd), platinum (Pt), titanium (Ti), copper (Cu), silver (Ag), gold (Au), tungsten titanium (TiW), chromium (Cr) or any combination thereof;

[0023] The metal oxide is selected from indium tin oxide (ITO), indium zinc oxide (IZO), nickel oxide (NiO), copper aluminate (CuAlO2) or any combination thereof; and / or

[0024] The silicide is selected from nickel silicide, titanium silicide, tungsten silicide, molybdenum silicide or any combination thereof.

[0025] According to a second aspect of the present invention, there is provided a method for manufacturing an electronic device integrating a silicon-based thin film transistor and a metal oxide thin film transistor, the method comprising:

[0026] providing a substrate;

[0027] Patterning the gate and semiconductor layer of the silicon-based thin film transistor and the metal oxide thin film transistor on the substrate, respectively, wherein the semiconductor layer has a source contact surface and a drain contact surface;

[0028] forming an interlayer dielectric layer over the gates and semiconductor layers of the silicon-based thin film transistor and the metal oxide thin film transistor;

[0029] Patterning at least the interlayer dielectric layer to expose a source contact surface and a drain contact surface of a semiconductor layer of one of the silicon-based thin film transistor and the metal oxide thin film transistor;

[0030] Depositing a conductive material on the interlayer dielectric layer to form a first conductor layer, wherein the first conductor layer is connected to the exposed source contact surface and drain contact surface of the semiconductor layer of the thin film transistor;

[0031] Patterning at least the first conductor layer to expose a source contact surface and a drain contact surface of a semiconductor layer of the other thin film transistor of the silicon-based thin film transistor and the metal oxide thin film transistor; and

[0032] Depositing a conductive material on the first conductive layer to form a second conductive layer, wherein the second conductive layer is connected to the exposed source contact surface and drain contact surface of the semiconductor layer of the other thin film transistor;

[0033] The first conductor layer and the second conductor layer are patterned to form the source and drain of the silicon-based thin film transistor and the metal oxide thin film transistor, respectively.

[0034] In one embodiment, the first conductor layer and the second conductor layer have different conductive materials.

[0035] In one embodiment, the method further includes forming an opening extending through the first conductor layer and the second conductor layer, the opening having aligned or non-aligned interior sidewalls.

[0036] In one embodiment, the method further comprises:

[0037] Openings extending through the first conductor layer and the second conductor layer are formed above the gate and semiconductor layer of the silicon-based thin film transistor and above the gate and semiconductor layer of the metal oxide thin film transistor, respectively, and the openings have aligned or non-aligned inner sidewalls.

[0038] In one embodiment, either or both of the first conductor layer and the second conductor layer are connected to the source contact surface and the drain contact surface of the corresponding semiconductor layer of the corresponding silicon-based thin film transistor or the metal oxide thin film transistor through contact holes or directly, and the contact holes are formed during patterning of at least the interlayer dielectric layer or patterning of at least the first conductor layer to expose the source contact surface and the drain contact surface of the semiconductor layer of the corresponding thin film transistor.

[0039] In one embodiment, the method further comprises chemically treating the contact via after forming the contact via.

[0040] In one embodiment, the silicon-based thin film transistor is a thin film transistor with a top gate structure, and the metal oxide thin film transistor is a thin film transistor with a bottom gate structure or a top gate structure, wherein for the metal oxide thin film transistor with a bottom gate structure, an etching barrier layer is arranged above the semiconductor layer of the metal oxide thin film transistor.

[0041] According to the solution of the present invention, silicon-based thin film transistors and metal oxide thin film transistors are monolithically integrated on the same substrate, wherein the conductor interconnection layer connecting the above two types of thin film transistors is a stacked conductor layer comprising at least two materials. One conductor layer in the stacked conductor layer is connected to the source contact surface and the drain contact surface of the semiconductor layer of one type of thin film transistor, and the other conductor layer is connected to the source contact surface and the drain contact surface of the semiconductor layer of another type of thin film transistor. Therefore, it is possible to achieve the best adaptation of the contact between different conductive materials and different types of thin film transistors while using a relatively small number of masks, allowing the source and drain contact areas of the LTPS TFT to be chemically treated or cleaned without damaging the MO TFT, and being compatible with the use of the MO TFT with a protective etching barrier layer. Through the embodiments of the present invention, the problems of semiconductor surface treatment and electrode material selection can be solved at the same time, thereby realizing a more convenient and lower-cost monolithic integration of LTPS and MO TFT. In addition, by combining LTPS and MO semiconductors, a circuit consisting of complementary p-type and n-type TFTs composed of LTPS and MO semiconductors, respectively, can be constructed. Compared with circuits constructed with single polarity TFTs, complementary circuit design can improve circuit performance and reduce system power dissipation.

[0042] In general, compared with the above-mentioned prior art, the present invention has the following advantages: it can reduce the number of masks, while allowing the contact areas of the source and drain of different types of thin film transistors to be chemically treated or cleaned separately; and it can be applied to a thin film transistor structure including a protective etch stop (ES) layer. In addition, according to the embodiments of the present invention, the best adaptation of electrical contacts between different conductive materials and different types of thin film transistors can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Non-limiting and non-exhaustive embodiments of the present invention are described, by way of example, with reference to the following drawings, in which:

[0044] Figures 1A-1C is a cross-sectional schematic diagram showing a process of monolithically integrating an LTPS TFT and an MO TFT according to the prior art.

[0045] Figures 2A-2F is a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a bottom-gate MO TFT with a protective ES layer according to an embodiment of the present invention, wherein contacts of the MO TFT are formed first.

[0046] Figures 3A-3Eis a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a bottom-gate MO TFT with a protective ES layer according to an embodiment of the present invention, wherein contacts of the LTPS TFT are formed first.

[0047] Figures 4A-4F is a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a top-gate MO TFT according to an embodiment of the present invention, wherein the two TFTs share a gate electrode layer and contacts of the MO TFT are formed first.

[0048] Figures 5A-5E is a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a top-gate MO TFT according to an embodiment of the present invention, wherein the two TFTs share a gate electrode layer and the contact of the LTPS TFT is formed first.

[0049] Figures 6A-6F is a cross-sectional schematic diagram showing an example process of monolithically integrating a top-gate LTPS TFT and a top-gate MO TFT according to an embodiment of the present invention, wherein the two TFTs do not share a gate electrode layer and contacts of the MOTFT are formed first.

[0050] Figures 7A-7E 2 is a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a top-gate MO TFT according to an embodiment of the present invention, wherein the two TFTs do not share a gate electrode layer and contacts of the LTPS TFT are formed first. DETAILED DESCRIPTION

[0051] In order to make the above and other features and advantages of the present invention more clear, the present invention is further described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explaining to those skilled in the art and are only exemplary and not restrictive.

[0052] The features described herein may be embodied in different forms and should not be construed as being limited to the embodiments described herein. Rather, the embodiments described herein are provided only to illustrate some of the many possible ways of implementing the device and / or method described herein. In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that it is not necessary to practice the present invention using specific details. In some cases, well-known materials or methods are not described in detail to avoid blurring the present invention.

[0053] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more of the associated listed items. The term "one or more" refers to one or more than one of the referenced items.

[0054] Although terms such as "first" and "second" may be used herein to describe various components, parts, portions, or elements, these components, parts, portions, or elements are not limited by these terms. Instead, these terms are only used to distinguish one component, part, portion, or element from another component, part, portion, or element. Therefore, without departing from the teachings of the present invention, the first component, part, portion, or element mentioned in this article may also be referred to as the second component, part, portion, or element.

[0055] Spatial terms such as "upper", "lower", "left", "right", "above" and "below" may be used herein to facilitate description of the relative positional relationship between one member, component, part or element and another member, component, part or element as shown in the figures. In addition, the positions of the "source contact surface" and the "drain contact surface" mentioned herein may not only be arranged as exemplified below, i.e., the "source contact surface" is located on the left and the "drain contact surface" is located on the right, but also the positions of the "source contact surface" and the "drain contact surface" may be interchangeable.

[0056] The terms used in this article are only used to describe various embodiments and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, "one", "an" and "the" are intended to include plural forms. For example, the terms "one", "another", "another" and "another" can be broadly understood as "one", "two" and "more", and can also be understood as "a kind of" or "another" according to the context. The terms "include", "comprise" and "have" specify the existence of stated features, operations, components, elements and / or combinations thereof, but do not exclude the existence or addition of one or more other features, operations, components, elements and / or combinations thereof.

[0057] The overall concept of the present invention is as follows: by making one of the stacked conductor layers including at least two materials contact the source contact surface and the drain contact surface of the semiconductor layer of one type of thin film transistor and making another conductor layer contact the source contact surface and the drain contact surface of the semiconductor layer of another type of thin film transistor, the problems of semiconductor surface treatment and electrode material selection can be solved while using a relatively small number of masks, and it can be applicable to a thin film transistor structure including a protective etching stop layer, thereby realizing monolithic integration of hybrid thin film transistors with simpler, more convenient, lower cost and better electrical contact.

[0058] On the one hand, the present invention proposes an electronic device integrating a silicon-based thin film transistor and a metal oxide thin film transistor, and the electronic device may include a substrate, a silicon-based thin film transistor and a metal oxide thin film transistor. Specifically, the silicon-based thin film transistor and the metal oxide thin film transistor are arranged on the substrate; the silicon-based thin film transistor and the metal oxide thin film transistor may respectively include: a gate, a source, a drain and a semiconductor layer, wherein the semiconductor layer at least includes a source contact surface and a drain contact surface; and the source and drain of the silicon-based thin film transistor and the metal oxide thin film transistor are respectively formed by a first conductor layer and a second conductor layer arranged in a stacked manner, and the first conductor layer and the second conductor layer form a stacked conductor layer. Among them, one of the first conductor layer and the second conductor layer contacts the source contact surface and the drain contact surface of the semiconductor layer of the silicon-based thin film transistor; and the other of the first conductor layer and the second conductor layer contacts the source contact surface and the drain contact surface of the semiconductor layer of the metal oxide thin film transistor.

[0059] Specifically, four corresponding types of connection between the source contact surface and the drain contact surface and the conductor layer can be formed: the source contact surface and the drain contact surface of the semiconductor layer of the silicon-based thin film transistor are connected to the first conductor layer, and the source contact surface and the drain contact surface of the semiconductor layer of the metal oxide thin film transistor are connected to the second conductor layer; or, the source contact surface and the drain contact surface of the semiconductor layer of the silicon-based thin film transistor are connected to the second conductor layer, and the source contact surface and the drain contact surface of the semiconductor layer of the metal oxide thin film transistor are connected to the first conductor layer. The conductive material of the stacked conductor layer may include metal, metal oxide, silicide or any combination thereof, as will be described in detail below.

[0060] In one embodiment, the first conductor layer and the second conductor layer can contact the source contact surface and the drain contact surface of the semiconductor layer of the corresponding silicon-based thin film transistor or the metal oxide thin film transistor through contact holes or directly, thereby forming the source and drain of the corresponding thin film transistor.

[0061] In one embodiment, the first conductor layer and the second conductor layer may have openings extending therethrough, the openings having interior sidewalls that are aligned or misaligned.

[0062] Here, silicon-based thin film transistors and metal oxide thin film transistors may be referred to as hybrid thin film transistors. Silicon-based thin film transistors may include thin film transistors with top gate structures; metal oxide thin film transistors may include thin film transistors with bottom gate structures or top gate structures, wherein for metal oxide thin film transistors with bottom gate structures, an etching barrier layer is provided above the semiconductor layer thereof to protect the semiconductor layer. The semiconductor layer may be referred to as an active layer, and may optionally include a channel region. The semiconductor layer may include various suitable materials, and TFTs made of different semiconductor materials may have different characteristics, as will be described in detail below.

[0063] In one embodiment, the electronic device of the present invention may further include:

[0064] A buffer layer, the buffer layer is arranged above the substrate and below at least the first semiconductor layer; a gate insulating layer, the gate insulating layer is arranged above at least the first semiconductor layer and below at least the first gate; and an interlayer dielectric layer, at least a portion of the interlayer dielectric layer is arranged above the first gate and the second gate, and the interlayer dielectric layer is located below the first conductor layer.

[0065] On the other hand, the present invention provides a method for manufacturing the above electronic device, which may at least include:

[0066] providing a substrate;

[0067] Patterning the gate and semiconductor layer of the silicon-based thin film transistor and the metal oxide thin film transistor on the substrate, respectively, wherein the semiconductor layer has a source contact surface and a drain contact surface;

[0068] forming an interlayer dielectric layer over the gates and semiconductor layers of the silicon-based thin film transistor and the metal oxide thin film transistor;

[0069] Patterning at least the interlayer dielectric layer to expose a source contact surface and a drain contact surface of a semiconductor layer of one of the silicon-based thin film transistor and the metal oxide thin film transistor;

[0070] Depositing a conductive material on the interlayer dielectric layer to form a first conductor layer, wherein the first conductor layer is connected to the exposed source contact surface and drain contact surface of the semiconductor layer of the thin film transistor;

[0071] Patterning at least the first conductor layer to expose a source contact surface and a drain contact surface of a semiconductor layer of the other thin film transistor of the silicon-based thin film transistor and the metal oxide thin film transistor;

[0072] Depositing a conductive material on the first conductive layer to form a second conductive layer, wherein the second conductive layer is connected to the exposed source contact surface and drain contact surface of the semiconductor layer of the other thin film transistor;

[0073] The first conductor layer and the second conductor layer are patterned to form the source and drain of the silicon-based thin film transistor and the metal oxide thin film transistor, respectively.

[0074] In one embodiment, the method may further include: forming openings extending through the first conductor layer and the second conductor layer above the gate and semiconductor layer of the silicon-based thin-film transistor and above the gate and semiconductor layer of the metal oxide thin-film transistor, respectively, the openings having aligned or non-aligned internal side walls.

[0075] In one embodiment, either or both of the first conductor layer and the second conductor layer are connected to the source contact surface and the drain contact surface of the corresponding semiconductor layer of the corresponding silicon-based thin film transistor or the metal oxide thin film transistor through contact holes or directly, and the contact holes are formed during patterning of at least the interlayer dielectric layer or patterning of at least the first conductor layer to expose the source contact surface and the drain contact surface of the semiconductor layer of the corresponding thin film transistor.

[0076] In one embodiment, the method further comprises chemically treating the contact via after forming the contact via.

[0077] The metallization process of the present invention requires three masking steps, two of which are used to form contact vias and one of which is used to define the conductor interconnect layer. In addition, the details described above in conjunction with the electronic device of the present invention may be included or embodied in the manufacturing method of the present invention. The above method is exemplarily described below in conjunction with a specific embodiment.

[0078] Figures 2A-2F and Figures 3A-3E 1 is a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a bottom-gate MO TFT with a protective ES layer according to an embodiment of the present invention, wherein Figure 2B-2F The MO TFT contacts are first formed in Figures 3A-3E The contacts of the LTPS TFT are first formed.

[0079] In this embodiment, if Figure 2AAs shown, first, a buffer layer 102 is formed on a substrate 101, wherein the buffer layer 102 is insulating. Secondly, an island is formed by depositing a semiconductor material and patterning it to form an LTPS TFT semiconductor layer 103, and the LTPS TFT semiconductor layer 103 includes a channel region 103a, a source contact surface 103b (left side) and a drain contact surface 103b (right side). Then, a gate insulating layer 104 is provided on the LTPS TFT semiconductor layer 103. Next, a conductor material is deposited on the gate insulating layer 104 and patterned to form a top gate electrode 105a of the LTPS TFT and a bottom gate electrode 105b of the MO TFT. Next, an insulating layer 106 is formed on the top gate electrode 105a and the bottom gate electrode 105b, wherein the insulating layer 106 is a gate insulating layer (also referred to as a gate dielectric layer) of the MOTFT. Next, a MO TFT semiconductor material is deposited on the insulating layer 106 and patterned to form an island to form a MO TFT semiconductor layer 107. Then, a protective etch stop (ES) layer 108 formed of an insulating material is disposed on the MO TFT semiconductor layer 107, wherein the insulating layer 106 and the protective etch stop layer 108 form an interlayer dielectric layer 1001. The subsequent process steps of this embodiment may include the following two implementations:

[0080] According to this embodiment Figure 2B-2F In the first implementation shown in , the contacts of the MO TFT are first formed.

[0081] Specifically, first, the ES layer 108 is patterned by using a mask to expose a portion of the MO TFT semiconductor layer 107 (the portion corresponding to the source contact surface and the drain contact surface of the MO TFT semiconductor layer 107) ( Figure 2B ). Next, a first conductor layer 110 is deposited, wherein the first conductor layer 110 contacts the portion of the MO TFT semiconductor layer 107 that is not covered by the ES layer 108 (i.e., the source contact surface and the drain contact surface of the MO TFT semiconductor layer 107). Figure 2C Then, a contact hole 111 of the LTPS TFT is formed by using a mask, wherein the contact hole 111 passes through the first conductor layer 110, the interlayer dielectric layer 1001 and the gate insulating layer 104 in sequence from top to bottom ( Figure 2D Next, the contact hole 111 is chemically treated, and then the second conductor layer 112 is deposited. The second conductor layer 112 contacts the source contact surface 103b (left side) and the drain contact surface 103b (right side) of the LTPS TFT semiconductor layer through the contact hole 111 of the LTPS TFT. Figure 2EFinally, the stack of the first conductor layer 110 and the second conductor layer 112 is patterned by using a mask to form openings extending through the first conductor layer 110 and the second conductor layer 112 over the gate electrodes (105a and 105b) and the semiconductor layers (103 and 107) of the LTPS TFT and the MO TFT, respectively, the openings having aligned inner sidewalls 1010, thereby forming conductor interconnects ( Figure 2F ), or in other words, forming the source and drain of the LTPS TFT and the MO TFT respectively.

[0082] According to this embodiment Figures 3A-3E In the second implementation shown in , the contacts of the LTPS TFT are first formed.

[0083] Specifically, first, the ES layer 108 is patterned by using a mask to form a contact hole 113 of the LTPS TFT, so as to expose a portion of the LTPS TFT semiconductor layer 103, which corresponds to the source contact surface 103b (left side) and the drain contact surface 103b (right side) of the LTPS TFT semiconductor layer 103. The contact hole 113 of the LTPS TFT passes through the interlayer dielectric layer 1001 and the gate insulating layer 104 ( Figure 3A ). Secondly, the contact hole 113 is chemically treated, and then the first conductor layer 210 is deposited, wherein the first conductor layer 210 contacts the source contact surface 103b (left side) and the drain contact surface 103b (right side) of the LTPS TFT semiconductor layer 103 through the contact hole 113 ( Figure 3B Then, the first conductor layer 210 and the ES layer 108 are patterned by using a mask to expose a portion of the MO TFT semiconductor layer 107 (the portion corresponds to the source contact surface and the drain contact surface of the MO TFT semiconductor layer 107) ( Figure 3C Next, a second conductor layer 211 is deposited, and the second conductor layer 211 contacts the portion of the MO TFT semiconductor layer 107 that is not covered by the ES layer 108 (ie, the source contact surface and the drain contact surface of the MO TFT semiconductor layer 107). Figure 3D Finally, the stack of the first conductor layer 210 and the second conductor layer 211 is patterned by using a mask to form openings extending through the first conductor layer 210 and the second conductor layer 211 over the gate electrodes (105a and 105b) and the semiconductor layers (103 and 107) of the LTPS TFT and the MO TFT, respectively, the openings having aligned inner sidewalls 2010, thereby forming conductor interconnects ( Figure 3E), or in other words, forming the source and drain of the LTPS TFT and the MO TFT respectively.

[0084] Figures 4A-4F and Figures 5A-5E 1 is a cross-sectional schematic diagram showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a top-gate MO TFT according to an embodiment of the present invention, wherein the two TFTs share a gate electrode layer. Figures 4B-4F The MO TFT contacts are first formed in Figures 5A-5E The contacts of the LTPS TFT are first formed.

[0085] In this embodiment, if Figure 4A As shown, first, a buffer layer 302 is formed on a substrate 301, wherein the buffer layer 302 is insulating. Secondly, a semiconductor material is deposited and patterned to form an island to form an LTPS TFT semiconductor layer 303, wherein the LTPS TFT semiconductor layer 303 includes a channel region 303a, a source contact surface 303b (left side) and a drain contact surface 303b (right side). Then, a gate insulating layer 304 is provided on the LTPS TFT semiconductor layer 303. Next, a MO TFT semiconductor material is deposited on the gate insulating layer 304 and patterned to form an island to form an MO TFT semiconductor layer 305, wherein the MO TFT semiconductor layer 305 includes a channel region 305a, a source contact surface 305b (left side) and a drain contact surface 305b (right side). Next, an insulating layer 306 is deposited. Next, a conductor material is deposited on the insulating layer 306 and patterned to form a top gate electrode 307a of the LTPS TFT and a top gate electrode 307b of the MO TFT, wherein the gate dielectric layer of the LTPS TFT is composed of the gate insulating layer 304 and the insulating layer 306, and the gate dielectric layer of the MO TFT is the insulating layer 306. Then, an interlayer dielectric layer 308 is formed on the top gate electrode 307a and the top gate electrode 307b. The subsequent process steps of this embodiment may include the following two implementation methods:

[0086] According to this embodiment Figures 4B-4F In the first implementation shown in , the contacts of the MO TFT are first formed.

[0087] Specifically, first, the interlayer dielectric layer 308 is patterned by using a mask to form a contact hole 310b of the MO TFT, wherein the contact hole 310b passes through the interlayer dielectric layer 308 to expose a portion of the MO TFT semiconductor layer 305 (the portion corresponds to the source contact surface and the drain contact surface of the MO TFT semiconductor layer 305) ( Figure 4B). Next, a first conductor layer 311 is deposited, wherein the first conductor layer 311 contacts the exposed source contact surface 305b (left side) and drain contact surface 305b (right side) of the MO TFT semiconductor layer 305 through the contact through hole 310b ( Figure 4C ). Then, a contact hole 310a of the LTPS TFT is formed by using a mask, wherein the contact hole 310a passes through the first conductor layer 311, the interlayer dielectric layer 308 and the gate insulating layer 304 from top to bottom in order to expose the source contact surface 303b (left side) and the drain contact surface 303b (right side) of the LTPS TFT semiconductor layer 303 ( Figure 4D Next, the contact hole 310a is chemically treated, and then a second conductor layer 312 is deposited. The second conductor layer 312 contacts the source contact surface 303b (left side) and the drain contact surface 303b (right side) of the LTPS TFT semiconductor layer through the contact hole 310a of the LTPS TFT. Figure 4E Finally, the stack of the first conductor layer 311 and the second conductor layer 312 is patterned by using a mask to form openings extending through the first conductor layer 311 and the second conductor layer 312 over the gate electrodes (307a and 307b) and the semiconductor layers (303 and 305) of the LTPS TFT and the MO TFT, respectively, and the openings have aligned inner sidewalls 3010, thereby forming conductor interconnects of the LTPS TFT and the MO TFT, respectively, or in other words, forming source and drain electrodes ( Figure 4F ).

[0088] According to this embodiment Figures 5A-5E In the second implementation shown in , the contacts of the LTPS TFT are formed first.

[0089] Specifically, first, the interlayer dielectric layer 308 is patterned by using a mask to form a contact hole 313a of the LTPS TFT, wherein the contact hole 313a passes through the interlayer dielectric layer 308 and the gate insulating layer 304 to expose a portion of the LTPS TFT semiconductor layer 303 (the portion corresponds to the source contact surface and the drain contact surface of the LTPS TFT semiconductor layer 303) ( Figure 5A ). Next, the contact hole 313a is chemically treated, and then the first conductor layer 410 is deposited, wherein the first conductor layer 410 contacts the exposed source contact surface 303b (left side) and drain contact surface 303b (right side) of the LTPS TFT semiconductor layer 303 through the contact hole 313a ( Figure 5BThen, a contact hole 313b of the MO TFT is formed by using a mask, wherein the contact hole 313b passes through the first conductor layer 410 and the interlayer dielectric layer 308 from top to bottom in sequence to expose the source contact surface 305b (left side) and the drain contact surface 305b (right side) of the MOTFT semiconductor layer 305 ( Figure 5C ). Next, a second conductor layer 411 is deposited, and the second conductor layer 411 contacts the source contact surface 305b (left side) and the drain contact surface 305b (right side) of the MO TFT semiconductor layer through the contact through hole 313b of the MO TFT ( Figure 5D Finally, the stack of the first conductor layer 410 and the second conductor layer 411 is patterned by using a mask to form openings extending through the first conductor layer 410 and the second conductor layer 411 over the gate electrodes (307a and 307b) and the semiconductor layers (303 and 305) of the LTPS TFT and the MO TFT, respectively, the openings having aligned inner sidewalls 4010, thereby forming conductor interconnects ( Figure 5E ), or in other words, forming the source and drain of the LTPS TFT and the MO TFT respectively.

[0090] Figures 6A-6F and Figures 7A-7E 2 is a schematic cross-sectional view showing an exemplary process of monolithically integrating a top-gate LTPS TFT and a top-gate MO TFT according to an embodiment of the present invention, wherein the two TFTs do not share a gate electrode layer. Figure 6B-6F The MO TFT contacts are first formed in Figures 7A-7E The contacts of the LTPS TFT are first formed.

[0091] In this embodiment, if Fig. 6AAs shown, first, a buffer layer 502 is formed on a substrate 501, wherein the buffer layer 502 is insulating. Secondly, a semiconductor material is deposited and patterned to form an island to form an LTPS TFT semiconductor layer 503, and the LTPS TFT semiconductor layer 503 includes a channel region 503a, a source contact surface 503b (left side) and a drain contact surface 503b (right side). Then, a gate insulating layer 504 is provided on the LTPS TFT semiconductor layer 503. Next, a conductor material is deposited and patterned on the gate insulating layer 504 to form a top gate electrode 505 of the LTPS TFT. Next, an insulating layer 506 is deposited. MO TFT semiconductor material is deposited on the insulating layer 506 and patterned to form an island to form an MO TFT semiconductor layer 507, and the MOTFT semiconductor layer 507 includes a channel region 507a, a source contact surface 507b (left side) and a drain contact surface 507b (right side). Next, an insulating layer and a conductor layer are disposed on the MO TFT semiconductor layer 507 and patterned to form a MO TFT gate insulating layer 508 and a MO TFT top gate electrode 509. Then, an insulating layer 510 is formed. The insulating layer 506 and the insulating layer 510 form an interlayer dielectric layer 5001. The subsequent process steps of this embodiment may include the following two implementation methods:

[0092] According to this embodiment Figure 6B-6F In the first implementation shown in , the contacts of the MO TFT are first formed.

[0093] Specifically, first, the insulating layer 510 is patterned by using a mask to form a contact hole 511b of the MO TFT, wherein the contact hole 511b passes through the insulating layer 510 to expose a portion of the MO TFT semiconductor layer 507 (the portion corresponds to the source contact surface and the drain contact surface of the MO TFT semiconductor layer 507) ( Figure 6B ). Next, a first conductor layer 512 is deposited, wherein the first conductor layer 512 contacts the exposed source contact surface 507b (left side) and drain contact surface 507b (right side) of the MO TFT semiconductor layer 507 through the contact through hole 511b ( Figure 6C ). Then, a contact hole 511a of the LTPS TFT is formed by using a mask, wherein the contact hole 511a passes through the first conductor layer 512, the interlayer dielectric layer 5001 and the gate insulating layer 504 from top to bottom in order to expose the source contact surface 503b (left side) and the drain contact surface 503b (right side) of the LTPS TFT semiconductor layer 503 ( Fig.6DNext, the contact hole 511a is chemically treated, and then a second conductor layer 513 is deposited. The second conductor layer 513 contacts the source contact surface 503b (left side) and the drain contact surface 503b (right side) of the LTPS TFT semiconductor layer through the contact hole 511a of the LTPS TFT. Fig. 6E Finally, the stack of the first conductor layer 512 and the second conductor layer 513 is patterned by using a mask to form openings extending through the first conductor layer 512 and the second conductor layer 513 over the gates (505 and 509) and the semiconductor layers (503 and 507) of the LTPS TFT and the MO TFT, respectively, the openings having aligned inner sidewalls 5010, thereby forming conductor interconnects ( Fig. 6F ), or in other words, forming the source and drain of the LTPS TFT and the MO TFT respectively.

[0094] According to this embodiment Figures 7A-7E In the second implementation shown in , the contacts of the LTPS TFT are formed first.

[0095] Specifically, first, the interlayer dielectric layer 5001 is patterned by using a mask to form a contact hole 514a of the LTPS TFT, wherein the contact hole 514a passes through the interlayer dielectric layer 5001 and the gate insulating layer 504 to expose a portion of the LTPS TFT semiconductor layer 503 (the portion corresponds to the source contact surface and the drain contact surface of the LTPS TFT semiconductor layer 503) ( Fig. 7A ). Next, the contact hole 514a is chemically treated, and then the first conductor layer 610 is deposited, wherein the first conductor layer 610 contacts the exposed source contact surface 503b (left side) and drain contact surface 503b (right side) of the LTPS TFT semiconductor layer 503 through the contact hole 514a ( Figure 7B ). Then, the first conductor layer 610 and the insulating layer 510 are patterned by using a mask to form a contact hole 514b of the MO TFT, wherein the contact hole 514b passes through the first conductor layer 610 and the insulating layer 510 from top to bottom in sequence to expose the source contact surface 507b (left side) and the drain contact surface 507b (right side) of the MO TFT semiconductor layer 507 ( Figure 7C ). Next, a second conductor layer 611 is deposited, and the second conductor layer 611 contacts the source contact surface 507b (left side) and the drain contact surface 507b (right side) of the MO TFT semiconductor layer through the contact through hole 514b of the MO TFT ( Fig.7DFinally, the stack of the first conductor layer 610 and the second conductor layer 611 is patterned by using a mask to form openings extending through the first conductor layer 610 and the second conductor layer 611 over the gates (505 and 509) and the semiconductor layers (503 and 507) of the LTPS TFT and the MO TFT, respectively, and the openings have aligned inner sidewalls 6010, thereby forming conductor interconnects ( Fig. 7E ), or in other words, the source and drain of the LTPS TFT and the MO TFT are formed respectively. It should be understood that, although the above figures show aligned internal side walls, the internal side walls may be misaligned depending on circumstances. In addition, although the above figures do not describe chemical treatment of the contact through hole or the source contact surface and the drain contact surface of the MO TFT, according to circumstances, before the first conductor layer or the second conductor layer contacts the source contact surface and the drain contact surface of the semiconductor layer of the MO TFT, the contact through hole or the source contact surface and the drain contact surface of the MO TFT may also be chemically treated.

[0096] As required, the conductive material of the stacked conductor layer described herein may be, for example, but not limited to, selected from metals, metal oxides, silicides, or any combination thereof. Wherein, the above-mentioned metal may be, for example, but not limited to, selected from molybdenum (Mo), aluminum (Al), tungsten (W), palladium (Pd), platinum (Pt), titanium (Ti), copper (Cu), silver (Ag), gold (Au), tungsten titanium (TiW), chromium (Cr), or any combination thereof. The above-mentioned metal oxide may be, for example, but not limited to, selected from indium tin oxide (ITO), indium zinc oxide (IZO), nickel oxide (NiO), copper aluminate (CuAlO2), or any combination thereof. The above-mentioned silicide may be, for example, but not limited to, selected from nickel silicide, titanium silicide, tungsten silicide, molybdenum silicide, or any combination thereof. The first conductor layer and the second conductor layer may be made of suitable different or the same conductive materials according to the corresponding LTPSTFT and MO TFT. For example, the first conductor layer may be formed of molybdenum, and the second conductor layer may be formed of aluminum. For example, the first conductor layer and the second conductor layer can be formed by mixing or laminating multiple conductive materials, for example, the first conductor layer is a molybdenum / aluminum laminate, and the second conductor layer is an aluminum / molybdenum laminate. Preferably, the first conductor layer and the second conductor layer can have different types of conductive materials.

[0097] As needed, the metal oxide semiconductor material of the semiconductor layer of the MO TFT described in this article can be, for example, but not limited to, selected from indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO), indium tin oxide (ITO) and any combination thereof.

[0098] Finally, it should be noted that although the present invention is described in conjunction with the above embodiments and implementation schemes, they are only preferred embodiments of the present invention, rather than limiting the scope of protection of the present invention. Those skilled in the art should understand that any modification, equivalent replacement or improvement made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. An electronic device integrating a silicon-based thin film transistor and a metal oxide thin film transistor, the electronic device comprising a substrate, a stacked conductor layer, a silicon-based thin film transistor and a metal oxide thin film transistor, wherein: The stacked conductor layer, the silicon-based thin film transistor and the metal oxide thin film transistor are arranged on the substrate; The stacked conductor layer comprises a first conductor layer and a second conductor layer arranged in a stacked manner; The silicon-based thin film transistor comprises at least a first gate and a first semiconductor layer, wherein the first semiconductor layer comprises at least a first source contact surface and a first drain contact surface; The metal oxide thin film transistor comprises at least a second gate electrode and a second semiconductor layer, wherein the second semiconductor layer comprises at least a second source contact surface and a second drain contact surface; One of the first conductor layer and the second conductor layer is connected to the first source contact surface and the first drain contact surface of the first semiconductor layer of the silicon-based thin film transistor, and the other of the first conductor layer and the second conductor layer is connected to the second source contact surface and the second drain contact surface of the second semiconductor layer of the metal oxide thin film transistor, The second conductor layer is deposited above the first conductor layer so that the first conductor layer and the second conductor layer are in contact with each other in a direction perpendicular to the substrate, and the stacked conductor layer is configured to be patterned through a mask step to form the source and drain of the silicon-based thin film transistor and the source and drain of the metal oxide thin film transistor, or to form conductor interconnections between the silicon-based thin film transistor and the metal oxide thin film transistor.

2. The electronic device according to claim 1, wherein: The first conductor layer and the second conductor layer are connected to the source contact surface and the drain contact surface of the corresponding semiconductor layer of the corresponding silicon-based thin film transistor or the metal oxide thin film transistor through contact vias or directly.

3. The electronic device according to claim 1, further comprising: a buffer layer, the buffer layer being disposed above the substrate and below at least the first semiconductor layer; a gate insulating layer, the gate insulating layer being disposed above at least the first semiconductor layer and below at least the first gate; as well as An interlayer dielectric layer, at least a portion of which is disposed above the first gate and the second gate, and the interlayer dielectric layer is located below the first conductor layer.

4. The electronic device according to any one of claims 1 to 3, wherein: The silicon-based thin film transistor is a thin film transistor with a top gate structure, and the metal oxide thin film transistor is a thin film transistor with a bottom gate structure or a top gate structure, and for the metal oxide thin film transistor with a bottom gate structure, an etching barrier layer is arranged above the second semiconductor layer of the metal oxide thin film transistor.

5. The electronic device according to any one of claims 1 to 3, wherein: The semiconductor material of the second semiconductor layer of the metal oxide thin film transistor is selected from indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), indium tin zinc oxide (ITZO), indium tin oxide (ITO) or any combination thereof.

6. The electronic device according to any one of claims 1 to 3, wherein the conductive material of the stacked conductor layer is selected from metal, metal oxide, silicide or any combination thereof, wherein: The metal is selected from molybdenum (Mo), aluminum (Al), tungsten (W), palladium (Pd), platinum (Pt), titanium (Ti), copper (Cu), silver (Ag), gold (Au), tungsten titanium (TiW), chromium (Cr) or any combination thereof; The metal oxide is selected from indium tin oxide (ITO), indium zinc oxide (IZO), nickel oxide (NiO), copper aluminate (CuAlO2) or any combination thereof; and / or The silicide is selected from nickel silicide, titanium silicide, tungsten silicide, molybdenum silicide or any combination thereof.

7. A method for manufacturing an electronic device integrating a silicon-based thin film transistor and a metal oxide thin film transistor, the method comprising: providing a substrate; Patterning the gate and semiconductor layer of the silicon-based thin film transistor and the metal oxide thin film transistor on the substrate, respectively, wherein the semiconductor layer has a source contact surface and a drain contact surface; forming an interlayer dielectric layer over the gates and semiconductor layers of the silicon-based thin film transistor and the metal oxide thin film transistor; Patterning at least the interlayer dielectric layer to expose a source contact surface and a drain contact surface of a semiconductor layer of one of the silicon-based thin film transistor and the metal oxide thin film transistor; Depositing a conductive material on the interlayer dielectric layer to form a first conductor layer, wherein the first conductor layer is connected to the exposed source contact surface and drain contact surface of the semiconductor layer of the thin film transistor; Patterning at least the first conductor layer to expose a source contact surface and a drain contact surface of a semiconductor layer of the other thin film transistor of the silicon-based thin film transistor and the metal oxide thin film transistor; Depositing a conductive material over the first conductive layer to form a second conductive layer, so that the first conductive layer and the second conductive layer are in contact with each other in a direction perpendicular to the substrate, wherein the second conductive layer is connected to the exposed source contact surface and drain contact surface of the semiconductor layer of the other thin film transistor; and The first conductor layer and the second conductor layer are patterned in one mask step to form the source and drain of the silicon-based thin film transistor and the source and drain of the metal oxide thin film transistor, or to form conductor interconnections between the silicon-based thin film transistor and the metal oxide thin film transistor.

8. The method according to claim 7, wherein: Either or both of the first conductor layer and the second conductor layer are connected to the source contact surface and the drain contact surface of the corresponding semiconductor layer of the corresponding silicon-based thin film transistor or the metal oxide thin film transistor through contact holes or directly, and the contact holes are formed during patterning of at least the interlayer dielectric layer or patterning of at least the first conductor layer to expose the source contact surface and the drain contact surface of the semiconductor layer of the corresponding thin film transistor.

9. The method according to claim 8, wherein: The method further includes chemically treating the contact via after forming the contact via.

10. The method according to any one of claims 7 to 9, wherein: The silicon-based thin film transistor is a top-gate thin film transistor, and the metal oxide thin film transistor is a bottom-gate thin film transistor or a top-gate thin film transistor, wherein for the bottom-gate metal oxide thin film transistor, an etching barrier layer is provided above the semiconductor layer of the metal oxide thin film transistor.

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