Photodiode and / or PIN diode structures

Abstract

The present disclosure relates to semiconductor structures, and more particularly to photodiode and / or PIN diode structures and methods of manufacturing the same. The structure includes: at least one vertical pillar feature located within a trench; a photosensitive semiconductor material extending laterally from a sidewall of the at least one vertical pillar feature; and a contact electrically connected to the photosensitive semiconductor material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to photodiode and / or pin diode structures and methods of fabricating. Background Art

[0002] An avalanche photodiode (APD) is a highly sensitive semiconductor photodiode that uses the photoelectric effect to convert light into electricity. From a functional point of view, an avalanche photodiode can be considered the semiconductor analog of a photomultiplier tube. Typical applications of an avalanche photodiode are long-distance fiber-optic telecommunications and quantum sensing for control algorithms. Newer applications include positron emission tomography and particle physics.

[0003] The suitability and effectiveness of an avalanche photodiode depends on many parameters. Two of these factors, for example, are quantum efficiency and total leakage current. Quantum efficiency indicates to what extent incident photons are absorbed and then used to generate primary carriers; while total leakage current is the sum of dark current, photocurrent and noise.

[0004] The sensitivity of a photodiode depends on the path length of light through the photosensitive material and the ability of the generated carrier pairs to reach the electrode / contact / cathode. In conventional structures, carriers travel along a two-dimensional path (e.g., vertically or laterally), which results in a long path. Due to the long path of conventional avalanche photodiodes, the photon recombination frequency within the photosensitive material is high, resulting in signal loss or attenuation of the signal itself. In addition, the photosensitive material itself needs to be very thick, which makes growth expensive and time-consuming, and can make integration with other circuit elements more challenging. Summary of the invention

[0005] In one aspect of the disclosure, a structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from a sidewall of the at least one vertical pillar feature; and a contact electrically connected to the photosensitive semiconductor material.

[0006] In one aspect of the present disclosure, a structure includes: a trench located in a substrate material; a deep n-well implant region located below the trench; a shallow trench isolation region isolating the trench; at least one vertical column feature extending upward within the trench; an insulator material located at the bottom of the trench; and a photosensitive material located above the insulator material and embedding the at least one vertical column feature.

[0007] In one aspect of the present disclosure, a method includes: forming at least one vertical pillar feature within a trench; forming a photosensitive semiconductor material extending laterally from a sidewall of the at least one vertical pillar feature; forming a contact electrically connected to the photosensitive semiconductor material; and lining the photosensitive material with a semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0009] Figure 1A A cross-sectional view of a substrate having vertical pillar features and a corresponding fabrication process is shown, among other features, in accordance with aspects of the present disclosure.

[0010] Figure 1B Shows Figure 1A A top view of a substrate having vertical pillar features is shown.

[0011] Figure 2 A vertical pillar feature located within a trench and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0012] Figure 3 Photodetector material grown on vertical pillar features and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0013] Figure 4 Materials on a photodetector material and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0014] Figure 5 Contacts to a photodiode and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0015] Figure 6 A photodiode according to further aspects of the present disclosure is shown.

[0016] Figure 7 A photodiode according to a further additional aspect of the present disclosure is shown.

[0017] Figure 8 A photodiode according to additional aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0018] The present disclosure relates to semiconductor structures, and more particularly to photodiode and / or pin diode structures and methods of manufacturing. More particularly, the present disclosure relates to avalanche photodiodes (APDs) and / or pin diode structures having one or more vertical surfaces (e.g., vertical column features). Advantageously, the avalanche photodiodes described herein exhibit improved sensitivity due to a particular form factor (e.g., dome-shaped), while also reducing the growth time of the photodiode material (e.g., Ge) by enabling the use of vertical column features (e.g., increasing the semiconductor area used for lateral growth of photodetector material). In addition, the photodiode can be integrated with existing technologies while also providing a reduced chance of defect regions resulting from growth fronts from different planes merging together.

[0019] In an embodiment, the photodiode and / or pin diode structure includes an intrinsic photodetector material (e.g., an intrinsic Ge material) grown around one or more vertical features (e.g., vertical column features) within a trench to allow integration with FETs and other devices. The photodetector material grows laterally from one or more vertical column features, resulting in semiconductor material embedded in the Ge region. In another embodiment, the vertical column features can be doped or undoped Si material. An oxide (dielectric) layer is disposed below the Ge material, within the trench and on the top surface of the column. The oxide material acts as a reflector and prevents the Ge material or other photoreactor material from growing in undesirable areas. In addition, p+ polysilicon or Si contacts can be disposed above the photodetector material, with the p and n+ regions located in the substrate. In addition, the n+ region can be reached through these contacts. Due to the focusing properties of the shape of the photoreactor material (e.g., a dome-shaped Ge material that improves sensitivity), the photodiode structure can also be used for front and back lighting.

[0020] The photodiode and / or pin diode structures of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the photodiode and / or pin diode structures of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material patterned by a photolithography process on top of the wafer. Specifically, the manufacture of the photodiode and / or pin diode structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film to the mask.

[0021] Figure 1A A cross-sectional view of a substrate having vertical pillar features and a corresponding fabrication process is shown, among other features, in accordance with aspects of the present disclosure. Figure 1BShows Figure 1A A top view of a substrate having vertical column features is shown. More specifically, Figure 1A and Figure 1B A structure 10 is shown that includes a substrate 12. In an embodiment, the substrate 12 can be any bulk semiconductor material. For example, the substrate 12 can include, but is not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The substrate material 12 is preferably a p-doped material.

[0022] Still refer to Figure 1A and Figure 1B , a shallow trench isolation structure 14 is formed within the substrate 12, surrounding a portion 16 of the substrate material 12. In an embodiment, the portion 16 of the substrate material is a vertical pillar feature, as described in more detail herein. Figure 1B As shown in more detail in FIG. 1 , the vertical pillar features 16 may be octagonal in shape; although other shapes are also contemplated herein. For example, the vertical pillar features 16 may be diamond-shaped, octagonal, circular, rectangular, square, or other shapes that facilitate the growth of photodetector materials. Although Figure 1A and Figure 1B A single vertical column feature 16 is shown in FIG. 1 , but it should be understood that multiple vertical column features 16 are also contemplated herein, such as, for example, Figure 6 and Figure 7 shown.

[0023] The shallow trench isolation structure 14 can be manufactured by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, a resist formed on the substrate material 12 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemical action (e.g., reactive ion etching (RIE)) is used to form one or more grooves in the substrate material 12 through the opening of the resist. The resist can then be removed by a conventional oxygen ashing process or other known stripping agent. After removing the resist, an insulator material, such as SiO2, can be deposited by any conventional deposition process, such as a chemical vapor deposition (CVD) process. Any residual material on the surface of the substrate 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0024] After forming the shallow trench isolation structure 14, a deep n-well implant 18 and a shallow n-well implant 20 are formed in the substrate 12. The shallow n-well implant 20 can be used to isolate a region from the substrate 12 (e.g., a p-type substrate). In an embodiment, the depth of the deep n-well implant 18 is about 0.6 microns, while the depth of the shallow n-well implant 20 is about 0.3 microns; although other implant depths are contemplated herein.

[0025] The deep n-well implant 18 and the shallow n-well implant 20 may be formed by introducing dopants, for example, by ion implantation that introduces a concentration of dopants into the substrate 12. The dopant may be an n-type dopant, such as arsenic (As), phosphorus (P), and antimony (Sb), among other suitable examples. During these implant processes, the vertical column feature 16 (and other areas) may be blocked from receiving any dopant by using an implantation mask. The implantation mask may include a layer of a photosensitive material (e.g., an organic photoresist) that is applied by a spin coating process, then pre-baked, then exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and blocking capability sufficient to block the masked areas from receiving a dose of implanted ions.

[0026] Figure 2 A cross-sectional view of a vertical column feature 16 located within a trench 22 and a corresponding manufacturing process is shown, among other features. In an embodiment, the trench 22 is formed by removing the oxide material of the shallow trench isolation structure 14 surrounding the vertical column feature 16. The insulator material can be removed by using a selective etching chemistry. It should be understood by those skilled in the art that the selective chemistry only removes the oxide material of the shallow trench isolation structure 14 and does not attack (e.g., etch) the vertical column feature 16 and the underlying deep n-well implant 18, both of which are composed of the substrate material 12. The resist 28 will protect the device 24 and the rest of the shallow trench isolation structure 14. In an embodiment, the removal of the oxide material will result in the formation of a vertical column feature 16 within the trench 22, which is located above and connected to the deep n-well implant 18.

[0027] Before or after the trench is formed, one or more active or passive devices 24 may be formed on the substrate 12. In an embodiment, the device 24 (e.g., a gate structure of a transistor) may be formed in any known manner, so no further explanation is required to fully understand the present disclosure. After the device 24 is formed, a protective film 26 may be formed over the device 24, followed by deposition of a resist (masking material) that facilitates the formation of the trench 22.

[0028] Figure 3A photodetector material 32 grown on the vertical pillar structure 16 and a corresponding manufacturing process are shown, among other features. The photodetector material 32 is an intrinsically photosensitive semiconductor material. In a more specific embodiment, the photodetector material 32 is preferably a Ge material that provides excellent responsiveness. In alternative embodiments, the photodetector material 32 can be Si, SiGe, etc. As further described herein, the photodetector material 32 grows from the laterally exposed sides of the vertical pillar structure 16 to form a dimensional structure, such as a dome shape. The dimensional structure (e.g., dome shape) can be used as a focusing feature (e.g., to increase sensitivity).

[0029] Prior to the growth of the photodetector material 32, a blocking material 30, such as an insulator material, is deposited on the exposed surfaces of the trenches 22 and on the top surfaces of the pillar features 16. The insulator material 30, which may be an oxide material, is deposited to about 10% of the depth of the trenches 22. After the oxide deposition, an epitaxial material 32, such as a photodetector material, is grown on the exposed sidewall surfaces of the vertical pillar features 16. It should be understood that the insulator material 30 (e.g., oxide) will prevent the vertical growth of the photodetector material 32, and therefore, the photodetector material 32 will grow laterally from the sidewalls of the exposed semiconductor surfaces of the vertical pillar features 16. This lateral growth will reduce defects caused by growth fronts merging from different planes.

[0030] exist Figure 4 In the embodiment of the present invention, polysilicon or single crystal silicon material 34 is grown or deposited on the photodetector material 32, and then subjected to silicidation. The polysilicon material 34 is preferably deposited to about or greater thickness of p+ material; but other dimensions are also contemplated herein. The polysilicon material 34 will act as a contact to the top of the photodiode 33. In an embodiment, the insulator material 30, in addition to acting as a reflector for reflecting light back into the photodiode 33, will also prevent shorting between the deep n-well implant 18 and the p+ doped polysilicon material 34. In a preferred embodiment, the polysilicon material 34 will only grow on the exposed photodetector material 32 (e.g., semiconductor material). For example, the protective film 26 will prevent the polysilicon material 34 from growing in other areas of the device. Alternatively, any excess polysilicon material 34 grown or deposited on structures outside the trenches can be removed by conventional photolithography and etching processes.

[0031] Still refer to Figure 4In an alternative embodiment, a film 36 (e.g., a nitride or other hard mask material) will cover or isolate the polysilicon material 34 to prevent silicide from forming on top of the photodiode 33. The unsilicided top surface will provide the best performance under front illumination of the photodiode 33. Also, the film 36 (e.g., a nitride layer) can be used as a reflector for back illumination. Alternatively, for back illumination, the polysilicon material 34 can be silicided to form a contact.

[0032] Those skilled in the art will appreciate that the silicidation process begins by depositing a thin transition metal layer (e.g., nickel, cobalt, or titanium) over a fully formed and patterned semiconductor device (e.g., the corresponding device 24 and / or polysilicon material). After the material is deposited, the structure is heated so that the transition metal reacts with the exposed silicon (or other semiconductor materials described herein) in the active regions (e.g., source regions, drain regions, gate contact regions) of the semiconductor device to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device. Those skilled in the art will appreciate that when the gate structure is composed of a metal material, no silicide contacts will be required on the device.

[0033] Figure 5 The contact formation to the photodiode 33 and the corresponding manufacturing process are shown, among other features. Figure 5 , an inter-level dielectric material (e.g., oxide) 38 is deposited over the structure. A plurality of trenches are formed in the inter-level dielectric material (e.g., oxide) 38 that are aligned with the photodiode 33, the shallow n-well implant 20, the source / drain regions 42 of the device 24, and the device 24 itself. The trenches are formed by conventional photolithography and etching processes, as already described herein. The trenches are filled with a metallic material (e.g., tungsten) to form corresponding contacts 40a, 40b, 40c, 40d. It will be appreciated by those skilled in the art that the contact 40a is used to detect the current generated by photons striking the photodiode 33 (e.g., the semiconductor material 32 of the photodiode 33).

[0034] It will be appreciated by those of ordinary skill in the art that contacts 40a and 40b may be sensing electrodes when deep n-well implant 18 and shallow n-well implant 20 are doped with a different dopant than the substrate. In addition, some detectors may even use contacts 40a, 40b for differential sensing, as long as deep n-well implant 18 and shallow n-well implant 20 are doped opposite to the substrate. If deep n-well implant 18 and shallow n-well implant 20 are doped identically to the substrate, only contact 40a is used for sensing. For example, if contact 40b is an n-well contact and the substrate is P-type, either contact 40a or 40b or both may be used for sensing. On the other hand, if contact 40b is a substrate contact, only contact 40a is used for sensing.

[0035] Figure 6 A photodiode structure 10a according to further aspects of the present disclosure is shown. In this embodiment, the photodiode structure 10a includes a plurality of photodiodes 33a, 33b fabricated around a plurality of vertical pillar features 16. In this embodiment, the plurality of vertical pillar features 16 are spaced apart so that the photodetector material 32 does not fuse together during its lateral growth. Also, in this embodiment, each of the photodiodes 33a, 33b includes its own contact 40a, 40a'.

[0036] Figure 7 A photodiode structure 10b according to a further additional aspect of the present disclosure is shown. Figure 7 The photodiode structure 10b includes a plurality of vertical pillar features 16 that are spaced apart so that the photodetector material 32 grown from each vertical pillar feature 16 fuses together during the lateral growth process. In this way, a single photodiode 33c having a plurality of vertical pillar features 16 can be fabricated. Also, in this embodiment, a single photodiode 33c having a plurality of vertical pillar features 16 requires only a single contact 40a.

[0037] Figure 8 A photodiode 10c is shown according to additional aspects of the present disclosure. In this embodiment, the vertical column feature 16a can be an n-doped semiconductor material. For example, in this embodiment, as an example, during the formation of the shallow n-well implant 20, an n-doped material can be implanted into the vertical column feature 16a. In this case, the n-doped vertical column feature 16a will be connected to the deep n-well implant 18. In order to form the n-doped vertical column feature 16a, the mask used above the vertical column feature is now eliminated. It should also be understood by those of ordinary skill in the art that the photodiode structures 10a, 10b can also be implemented with vertical column features having n-doped implants. In this way, each different structure can include a pipn avalanche photodiode structure.

[0038] Photodiode and / or pin diode structures can be utilized in system-on-chip (SoC) technology. It should be understood by those skilled in the art that an SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with the same functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0039] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0040] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or process improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A photodetector structure, comprising: at least one vertical post feature positioned within the trench; a barrier material located on a bottom surface of the trench and on a top of the at least one vertical post feature and in contact with the top of the at least one vertical post feature, the barrier material being a reflective insulator material; a photosensitive semiconductor material extending laterally from a sidewall of the at least one vertical pillar feature; as well as A contact is electrically connected to the photosensitive semiconductor material.

2. The structure according to claim 1, wherein: The at least one vertical column is comprised of a substrate material.

3. The structure according to claim 2, wherein: The substrate material is Si material, and the photosensitive semiconductor material is undoped Ge material.

4. The structure according to claim 1, wherein: The at least one vertical pillar feature is embedded within the photosensitive semiconductor material.

5. The structure according to claim 4, wherein: The at least one vertical column feature is a plurality of vertical column features.

6. The structure according to claim 5, wherein: The photosensitive semiconductor material merges around the plurality of vertical pillar features.

7. The structure according to claim 5, wherein: The photosensitive semiconductor material embeds each of the plurality of vertical pillar features separately and without contacting each other.

8. The structure according to claim 1, wherein: The at least one vertical pillar feature is an n-doped material connected to an n-well implant beneath the trench.

9. The structure of claim 1, further comprising an active device or a passive device located outside the trench.

10. The structure of claim 1 further comprising a p+ polycrystalline material surrounding the photosensitive semiconductor material, and the contact is connected to the p+ polycrystalline material.

11. The structure according to claim 1, wherein: The photosensitive semiconductor material is domed over a surface of the trench.

12. A photodetector structure comprising: a groove in the substrate material; a deep n-well implantation region located below the trench; a shallow trench isolation region isolating the trench; at least one vertical post feature extending upwardly within said trench; an insulator material at the bottom of the trench; a photosensitive material overlying the insulator material and embedding the at least one vertical pillar feature; as well as A semiconductor material is provided to line the photosensitive material.

13. The structure according to claim 12, wherein: The at least one vertical pillar is a Si material, the photosensitive material is an undoped Ge material, the insulator material is a reflective material, and the semiconductor material is p+ polysilicon.

14. The structure according to claim 13, wherein: The at least one vertical pillar is an n-doped material connected to the deep n-well implant region below the trench.

15. The structure according to claim 14, wherein: The at least one vertical column feature is a plurality of vertical column features.

16. The structure according to claim 15, wherein: The photosensitive material is merged around the plurality of vertical pillar features.

17. The structure of claim 15, wherein: The photosensitive material embeds each of the plurality of vertical pillar features separately and without contact with each other.

18. The structure of claim 12, further comprising an active device or a passive device located outside the trench.

19. The structure of claim 12, wherein: The photosensitive material is in a dome shape.

20. A method of forming a photodetector structure, comprising: forming at least one vertical pillar feature within the trench; forming a barrier material on and in contact with a bottom surface of the trench and a top of the at least one vertical post feature, the barrier material being a reflective insulator material; forming a photosensitive semiconductor material extending laterally from a sidewall of the at least one vertical pillar feature; as well as Contacts are formed that are electrically connected to the photosensitive semiconductor material.

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