Semiconductor structure and method for manufacturing the same

Abstract

The present application provides a semiconductor structure and a method for preparing the same. The method for preparing the semiconductor structure includes: preparing a buffer layer on a substrate; preparing a mask layer on the buffer layer; patterning the mask layer to partially expose the buffer layer; preparing a first DBR structure on the portion of the buffer layer exposed by the mask layer; and preparing a light-emitting structure on the first DBR structure. The patterned mask layer can improve the growth quality of the first DBR structure and facilitate the preparation of subsequent light-emitting structures.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] As a typical representative of the third-generation semiconductor materials, wide bandgap semiconductor material Group III nitride has excellent characteristics such as wide bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructure. It is very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] Gallium nitride-based resonant cavity light-emitting devices, including resonant cavity light-emitting diodes and vertical cavity surface-emitting lasers, usually adopt a DBR (distributed Bragg reflector) structure. However, the stress generated by the first DBR structure of Al(Ga)N / GaN due to lattice mismatch can cause cracks and other problems. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, comprising: preparing a buffer layer on a substrate; preparing a mask layer on the buffer layer; patterning the mask layer to partially expose the buffer layer; preparing a first DBR structure on the portion of the buffer layer exposed by the mask layer; preparing a light-emitting structure on the first DBR structure; and preparing a second DBR structure on the light-emitting structure. By patterning the mask layer, a high-quality first DBR structure can be grown. In addition, the presence of the mask layer is also conducive to the selective preparation of the subsequent light-emitting structure on the first DBR structure.

[0005] Optionally, after patterning the mask layer to partially expose the buffer layer, the buffer layer exposed by the mask layer is partially etched to form a groove in the buffer layer, and then a first DBR structure is prepared on the portion of the buffer layer exposed by the mask layer. By continuing to etch the buffer layer, a thicker first DBR structure can be prepared, thereby increasing its reflectivity.

[0006] Optionally, after forming the groove in the buffer layer, a mask layer is first prepared on the sidewall of the groove, and then the first DBR structure is prepared on the portion of the buffer layer exposed by the mask layer. The mask layer can provide good protection for the sidewall of the groove to prevent parasitic growth on the sidewall of the groove when the first DBR structure is subsequently prepared.

[0007] Optionally, the substrate includes silicon, sapphire, gallium nitride, or silicon carbide.

[0008] Optionally, the mask layer includes silicon oxide or silicon nitride.

[0009] Optionally, the buffer layer, the first DBR structure, and the light-emitting structure include group III nitride materials.

[0010] The present application provides a semiconductor structure, comprising: a substrate; a buffer layer located on the substrate; a patterned mask layer located on the buffer layer; a first DBR structure located on the buffer layer and between the mask layers; a light-emitting structure located above the first DBR structure; and a second DBR structure located above the second DBR structure.

[0011] Optionally, the first DBR structure extends into the buffer layer.

[0012] Optionally, a mask layer is provided between a portion of the first DBR structure extending to the buffer layer and the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1a-1f It is a schematic diagram of a semiconductor structure according to the first embodiment of the present application.

[0014] Figure 2a-2c It is a schematic diagram of a semiconductor structure according to a second embodiment of the present application.

[0015] Figure 3a-Figure 3b It is a schematic diagram of a semiconductor structure according to a second embodiment of the present application. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] It should be noted that similar reference numerals and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. In the description of the embodiments of the present invention, it will be understood that when a layer (or film), region, pattern or structure is referred to as "on" or "under" another substrate, another layer (or film), another region, another pad or another pattern, it can be "directly" or "indirectly" on another substrate, layer (or film), region, pad or pattern, or one or more intermediate layers may also exist. This position of the layer has been described with reference to the accompanying drawings. For the purpose of convenience or clarity, the thickness and size of each layer shown in the drawings may be enlarged, omitted or schematically drawn. In addition, the size of the element does not fully reflect the actual size.

[0018] Figure 1a-Figure 1e The process flow of the method for manufacturing the semiconductor structure described in the first embodiment of the present application is shown.

[0019] Step S1, refer to Figure 1a As shown, a buffer layer 110 is prepared on a substrate 100 .

[0020] The substrate 100 includes silicon, sapphire, gallium nitride, silicon carbide, etc. The present application does not specifically limit the material type of the substrate 100. The buffer layer 110 includes a group III nitride material, such as GaN, AlGaN, etc.

[0021] Step S2, refer to Figure 1b As shown, a mask layer 120 is prepared on the buffer layer 110 .

[0022] The mask layer 130 includes silicon oxide, silicon nitride, or the like.

[0023] Step S3, refer to Figure 1c As shown, the mask layer 120 is patterned to partially expose the buffer layer 110 .

[0024] Step S4, refer to Figure 1d As shown, a first DBR structure 130 is formed on the exposed buffer layer 110. Preferably, the height of the first DBR structure 130 does not exceed the height of the mask layer 120.

[0025] The first DBR structure includes a group III nitride material, such as a periodic structure formed by alternating GaN and AlGaN.

[0026] Step S5, refer to Figure 1eAs shown, a light emitting structure 140 is prepared on the first DBR structure 130. The light emitting structure 140 includes a first doping layer 141, a quantum well layer 142, and a second doping layer 143. The first doping layer 141 of the light emitting structure 140 may be, for example, n-type doping, and the second doping layer 143 may be, for example, p-type doping.

[0027] Step S6, refer to Figure 1f As shown, the second DBR structure 150 continues to grow on the light emitting structure 140 .

[0028] The second DBR structure 150 includes a III-group nitride material, such as a periodic structure formed by alternating GaN and AlGaN, and may also include a dielectric material, such as a periodic structure formed by alternating Ta2O5 / SiO2.

[0029] The first DBR structure can be selectively grown through the patterned mask layer 120 , which can effectively release the pressure and grow a high-quality first DBR structure. In addition, the existence of the mask layer 120 is also conducive to the subsequent selective preparation of the light-emitting structure 140 on the first DBR structure 130 .

[0030] In the second embodiment of the present application, Figure 2a As shown, after step S3, the buffer layer 110 exposed by the mask layer 120 is partially etched to form a groove 111 in the buffer layer 110; then as shown in FIG. Figure 2b and Figure 2c As shown, a first DBR structure 130 is formed on the exposed buffer layer 110; a light emitting structure 140 is formed on the first DBR structure 130; and a second DBR structure 150 is formed on the light emitting structure 140. By continuing to etch the buffer layer, a thicker first DBR structure can be formed, thereby increasing its reflectivity.

[0031] In the third embodiment of the present application, Figure 3a-3b As shown, in the second embodiment described above, “partially etching the buffer layer 110 exposed by the mask layer 120, forming the groove 111 in the buffer layer 110, and then preparing the mask layer so that the mask layer 120 covers the side wall of the groove 111, and at the same time exposes the buffer layer 110 at the bottom of the groove 111. The mask layer can form a good protection for the side wall of the groove 111, and prevent the parasitic growth on the side wall of the groove 111 when the first DBR structure is subsequently prepared.

[0032] In one embodiment of the present application, a semiconductor structure is also disclosed, such as Figure 1eAs shown, the semiconductor structure includes a substrate 100, a buffer layer 110 on the substrate 100, a patterned mask layer 130 on the buffer layer 110, a first DBR structure 130 located on the buffer layer 110 and between the mask layers 130, a light emitting structure 140 located on the first DBR structure 130, and a second DBR structure 150 located on the light emitting structure 140. The light emitting structure 140 includes a first doping layer 141, a quantum well layer 142, and a second doping layer 143. Preferably, the height of the first DBR structure 130 does not exceed the height of the mask layer 120.

[0033] A high-quality first DBR structure can be grown by patterning the mask layer 120 . In addition, the existence of the mask layer 120 is also conducive to selectively preparing the subsequent light-emitting structure 140 on the first DBR structure 130 .

[0034] The substrate 100 includes silicon, sapphire, gallium nitride, silicon carbide, etc., and the present application does not specifically limit the material type of the substrate 100. The buffer layer 110 includes a group III nitride material, such as GaN, AlGaN, etc. The first DBR structure includes a periodic structure formed by alternating group III nitride materials, such as GaN and AlGaN. The second DBR structure 150 includes a periodic structure formed by alternating group III nitride materials, such as GaN and AlGaN, and may also include a dielectric material, such as a periodic structure formed by alternating Ta2O5 / SiO2.

[0035] In another embodiment of the present application, Figure 2c As shown, in the semiconductor structure, the first DBR structure 130 extends into the buffer layer 130. By continuing to etch the buffer layer, a thicker first DBR structure can be prepared, thereby increasing its reflectivity.

[0036] In another embodiment of the present application, Figure 3b As shown, in the semiconductor structure, a mask layer 120 is disposed between the portion of the first DBR structure 130 extending to the buffer layer 110 and the buffer layer 110. The mask layer can provide good protection for the sidewalls of the groove 111, preventing parasitic growth on the sidewalls of the groove 111 when the first DBR structure is subsequently prepared.

[0037] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: preparing a buffer layer on a substrate; preparing a mask layer on the buffer layer; Patterning the mask layer to partially expose the buffer layer; preparing a first DBR structure on a portion of the buffer layer exposed by the mask layer; preparing a light-emitting structure on the first DBR structure; as well as Preparing a second DBR structure on the light-emitting structure; Wherein, after patterning the mask layer to partially expose the buffer layer, and before preparing the first DBR structure on the portion of the buffer layer exposed by the mask layer, the method further comprises: Partially etching a portion of the buffer layer exposed by the mask layer to form a groove in the buffer layer; Wherein, preparing a first DBR structure on a portion of the buffer layer exposed by the mask layer comprises: Preparing the first DBR structure on the groove of the buffer layer so that the first DBR structure extends into the buffer layer to increase the thickness of the first DBR structure, thereby increasing its reflectivity; Among them, after forming the groove in the buffer layer and before preparing the first DBR structure on the portion of the buffer layer exposed by the mask layer, the method further includes: preparing a mask layer on the sidewall of the groove so that the mask layer is provided between the portion of the first DBR structure extending to the buffer layer and the buffer layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The substrate includes silicon, sapphire, gallium nitride, and silicon carbide.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The mask layer includes silicon oxide and silicon nitride.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The buffer layer, the first DBR structure and the light emitting structure include group III nitride materials, and the second DBR structure includes group III nitride materials and dielectric materials.

5. A semiconductor structure, characterized in that: include: substrate; a buffer layer located on the substrate; a patterned mask layer located on the buffer layer; a first DBR structure located on a portion of the buffer layer exposed by the mask layer; a light emitting structure located above the first DBR structure; as well as a second DBR structure located above the light emitting structure; The first DBR structure extends into the buffer layer to increase the thickness of the first DBR structure, thereby increasing its reflectivity, and the mask layer is provided between the portion of the first DBR structure extending into the buffer layer and the buffer layer.

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