Modulator circuit, corresponding device and method

Abstract

Modulator circuits, corresponding devices and methods are disclosed. An embodiment of a pulse width modulation (PWM) modulator circuit includes a first half-bridge stage having a first output node and a second half-bridge stage having a second output node. The first output node and the second output node are configured to have an electrical load coupled therebetween to apply a PWM modulated output signal to the electrical load. The circuit includes a differential stage having input nodes, the differential stage being configured to receive an input signal applied between the input nodes and to generate a differential control signal for the first half-bridge stage and the second half-bridge stage. A current comparator is arranged between the differential stage and the first half-bridge stage and the second half-bridge stage. The current comparator is configured to generate a PWM modulated drive signal to drive the half-bridge stage based on the input signal applied between the input nodes in the differential stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102020000014302, filed on June 16, 2020, which is incorporated herein by reference. Technical Field

[0003] The present specification relates to pulse width modulation (PWM) modulator circuits. For example, one or more embodiments may be applied in high frequency PWM modulators. One or more embodiments may be advantageously applied in class D audio power amplifiers. Background Art

[0004] Nowadays, there is a clear trend of increasing the switching frequency of class D power amplifiers.

[0005] The operation of a Class D (or switching) amplifier involves an electronic switch being alternately turned on and off (i.e., made conducting and non-conducting) via a modulator using pulse width modulation (PWM) or related techniques to encode the (audio) input signal into a train of pulses. The amplified signal is recovered (demodulated) via a low pass filter such as an LC filter for application to, for example, a loudspeaker.

[0006] A high switching frequency can help reduce the cost of the LC demodulation filter.

[0007] However, high switching frequencies have possible consequences, such as increased interference due to increased switching slopes, and the benefits of in-phase modulation over out-of-phase modulation are largely lost.

[0008] Therefore, an improved PWM modulator with enhanced robustness against disturbances and reduced area / current consumption is desirable for various applications. Summary of the invention

[0009] It is an aim of one or more embodiments to help provide such an improved solution.

[0010] According to one or more embodiments, such purpose can be achieved by a circuit having the features described in this disclosure.

[0011] One or more embodiments may be directed to corresponding devices.A class D power amplifier used in an audio system may be an example of such a device.

[0012] One or more embodiments may be directed to a corresponding method.

[0013] One or more embodiments may provide an improved fully differential PWM modulator that exhibits increased robustness to disturbances and reduced area / current specifications.

[0014] One or more embodiments may exhibit one or more of the following advantages: improved immunity to common-mode noise due to extended use of fully differential circuit arrangements; the possibility of acting on the input impedance of the comparator facilitates the creation of open-loop poles and zeros; peaks may be created at the top (vertices) of the reference signal, which are not necessarily "squared" and exhibit a finite slope, which facilitates control when approaching saturation; and the possible absence of common-mode control leads to a reduction in the number of components, which is advantageous in terms of both area occupied and power consumption.

[0015] One or more embodiments may be advantageously employed in consumer audio applications, such as in automobile audio systems.

[0016] One or more embodiments may be advantageously applied in a class D amplifier having a full-bridge final stage.

[0017] One or more embodiments may advantageously omit common-mode feedback: thus, in the presence of a common-mode load (eg, a load towards ground or a supply voltage at both outputs), the common-mode duty cycle of the two outputs does not change. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0019] Figure 1A is an exemplary circuit diagram of a full-bridge circuit driven by different drive signals;

[0020] Figure 1B is an exemplary circuit diagram of a full-bridge circuit driven by a common drive signal;

[0021] Figure 2 is an exemplary block diagram of a PWM modulator circuit according to the present disclosure and including a plurality of current comparators;

[0022] Figure 3 is an exemplary block diagram of a PWM modulator circuit according to the present disclosure and including a single current comparator;

[0023] Figure 4 is an exemplary circuit diagram of the operation of a current comparator; and

[0024] FIG. 5A to FIG. 5D is a time diagram illustrating possible time behavior of signals that may occur in embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] In the following description, one or more specific details are shown to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more specific details, or by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not described or described in detail so that some aspects of the embodiments are not obscured.

[0026] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more points of this specification do not necessarily refer to one and the same embodiment.

[0027] Furthermore, particular conformations, structures or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] The headings / references used herein are provided for convenience only and do not limit the degree or scope of protection of the embodiments.

[0029]

[0046] By way of introduction to the present detailed description, it may be noted that the advantage of in-phase modulation is less relevant in high frequency PWM modulators than in low frequency PWM modulators.

[0030] In fact: one advantage of in-phase modulation is related to the differential mode, as long as the switching occurs at double the frequency and the signal swing is halved; this leads to a reduction in the ripple coupled to the load of the modulator, which helps to avoid an undesirable increase in the size of the LC components for the same purpose: at high modulation frequencies, the size of the LC filter is reduced, which makes the possible size increase more tolerable; in-phase modulation reduces the transmission of PWM clock noise to the differential output: with high modulation frequencies, a regulation loop with very high gain in the audio band can be provided, which leads to a high suppression capability of this type of noise; in-phase modulation avoids discontinuities in the differential signal when the PWM signal is turned on / off, preventing pop noise: at high modulation frequencies, these discontinuities are moved to high frequencies outside the audible range.

[0031] In contrast, the advantages of out-of-phase modulation compared to in-phase modulation are related to the common mode, as long as the common mode harmonics are heavier than the differential mode harmonic components; this can be beneficial for emissions. Out-of-phase modulation provides a "robust" common mode, and as the modulation frequency increases, the insignificant modulation of the common mode is still significant, and the common mode is generally considered to be less of a concern than the differential mode.

[0032] Figure 1A and Figure 1Bis an example of the possibility (which may be considered conventional in the art) of creating an essentially differential final stage, where the half-bridges are (always) driven with opposite phases (anti-phase operation).

[0033] Figure 1A and Figure 1B Two half-bridges are shown, which include electronic switches, such as transistors (field effect transistors, such as metal oxide semiconductor (MOSFET) transistors may be examples of these switches), arranged between a power supply node or line VCC and ground GND.

[0034] A load LD is shown as a dotted line, coupled between the output nodes OUTP and OUTM, between the two transistors in each half-bridge.

[0035] exist Figure 1A and Figure 1B In a rather general representation of , the load LD can represent a rather complex network.

[0036] For example, in the Figure 1A and Figure 1B In the illustrated case of a final stage class D audio amplifier, the load LD may comprise, for example, an LC demodulator filter, an output damping network and a suitable load, such as a loudspeaker system which may include a crossover network.

[0037] Figure 1A and Figure 1B The switches in the half-bridge shown are configured to be switched on and off alternately in PWM operation by a driver stage with complementary outputs ( Figure 1A and Figure 1B As shown, for simplicity, no number is given), the driver stage receives different drive signals DrvInP and DrvInM ( Figure 1A ) or the same common drive signal DrvIn( Figure 1B ).

[0038] exist Figure 1B In this case, the two half-bridges receive only one input signal, DrvIn, dedicated to controlling the differential mode. Such a common operating mode cannot be controlled externally and is essentially (nominally) fixed at VCC / 2.

[0039] As mentioned earlier, Figure 1A and Figure 1B The switches (MOSFET transistors) in each half-bridge are shown driven in opposite phase (anti-phase operation) in order to avoid cross conduction.

[0040] In such Figure 1AIn the illustrated arrangement, each of the two half-bridges can be driven with a respective drive signal DrvInP, DrvInM (eg, a logic signal having a value of "0" or "1").

[0041] This signal can be generated in a manner known to a person skilled in the art via a comparator supplied with a modulation signal and a carrier signal (eg a triangular wave).

[0042] The carrier used to drive the "P" half-bridge has a certain phase relationship with the carrier used to drive the "M" half-bridge: in the case of in-phase modulation, the two carriers used to generate DrvInP and DrvInM are in phase, that is, they have a mutual shift of 0°, while in the case of out-of-phase modulation, the two carriers used to generate DrvInP and DrvInM are anti-phase, that is, they have a mutual shift of 180°.

[0043] The phase relationship between these carrier signals is mirrored by the corresponding phase relationship between the drive signals DrvInP and DrvInM (as discussed, these can be binary signals having voltage levels 0 and VCC, corresponding to logic signals having values ​​“0” or “1”), which also applies to the output signals at nodes OUTP and OUTM.

[0044] If (only) out-of-phase modulation is desired, then one can modify Figure 1A The arrangement shown, Figure 1B , where a single input signal DrvIn (derived from a single carrier) is used to drive two half-bridges, one in antiphase with the other: Figure 1B The "crossover" arrangement of the mid-drive stage, with Figure 1A The "symmetrical" arrangement of the driver stages is reversed, with the driver stages having complementary outputs.

[0045] Figure 1B The solution is better than Figure 1A The solution is simpler than the latter, which involves two different carriers (and two associated comparators). Figure 1A The shown solution comprising two different inputs DrvInP, DrvInM may involve separate regulation of the common mode.

[0046] Still by way of introduction to this detailed description, document US2015 / 0207498A1 (corresponding to US 2017 / 0155381A1, US2018 / 0323774A1, US 9 595 946 B2, US10 027315B2 and US10 615 784 B2) discloses a method for reducing pulse jumps from the characteristics of a modulation signal affecting an integrator input to a pulse width modulation (PWM) modulator, and a square wave carrier signal for generating a triangular waveform of the PWM modulator. This method may include generating a wide synchronous peak at the vertex of the triangular waveform output by the integrator.

[0047] As discussed in these references, it was found that adding a peak at the apex of the carrier signal can improve the behavior of the amplifier when it is approaching saturation.

[0048] Providing such peaks at high modulation frequencies using feedback circuits almost inevitably involves the use of amplifiers with (very) fast response and high slew rates.

[0049] The circuit as exemplified herein may comprise a fully differential PWM modulator which may benefit from the advantages derived from the characteristics of the aforementioned final stage on the one hand while overcoming certain limitations of the prior art.

[0050] The circuits as illustrated herein can be applied to both open-loop and closed-loop PWM modulators.

[0051] In the latter case, the regulation loop may or may not include an LC demodulation filter, and / or may include one or more nested loops.

[0052] Figure 2 is a block diagram of an exemplary architecture of a PWM modulator circuit, generally designated 100 .

[0053] Figure 2 is an example of the possibility of applying the underlying concept of the embodiments discussed herein (ie, using a current comparator instead of a voltage comparator) in an otherwise conventional PWM modulator circuit.

[0054] Figure 2 The circuit 100 shown can be configured to receive a differential input signal (eg, an audio signal) provided by a signal source S applied between two input nodes InP, InM, and to generate a corresponding PWM modulated (differential) signal between two output nodes OUTP, OUTM to be applied to a load LD.

[0055] The source S and the load LD are both shown with dashed lines, as long as one or both of them may be elements different from the circuit 100 of the embodiment.

[0056] As discussed earlier Figure 1A and Figure 1B In the case of Figure 2 (and Figure 3 ) can actually represent a rather complex network (e.g., an LC demodulator filter, an output damping network, a speaker system in the case of a Class-D audio amplifier including circuit 100 as illustrated herein).

[0057] Furthermore, throughout the description, for the sake of brevity, the same reference numerals may be used to refer to certain nodes or lines in a circuit and the signals appearing at the nodes or lines. This may apply, for example, to input nodes InP, InM that receive differential input signals from a source S.

[0058] like Figure 2 As shown, such a differential input signal (abbreviated as InP, InM) is applied to the input of a differential stage 10 (e.g., a fully differential amplifier), which generates two control signals VcP and VcM starting from the differential input signal (e.g., InP-InM) so as to be forwarded to the half bridges 121, 122 in the final stage of the circuit.

[0059] Otherwise, those skilled in the art will appreciate that a fully differential amplifier is only one exemplary possible implementation of the differential stage 10 contemplated herein.

[0060] By way of another possible exemplary embodiment, the differential stage 10 may include two single-ended amplifiers: a first amplifier receiving the signal InP and forwarding the control signal VcP to the half bridge 121 , and a second amplifier receiving the signal InM and forwarding the control signal VcM to the half bridge 122 .

[0061] Here again (as Figure 1A and Figure 1B In the case of ), the two half bridges 121, 122 may include electronic switches, such as transistors. Field effect transistors such as MOSFET transistors may be examples of these switches.

[0062] A load LD is shown as a dotted line and is coupled between the output nodes OUTP and OUTM between the two transistors in each half-bridge.

[0063] Here again, the switches in the half-bridge are configured to be alternately switched on and off via complementary driver stages 121A, 122A with complementary outputs, which are controlled by different drive signals DrvInP and DrvInM.

[0064] As shown, the drive signals DrvInP and DrvInM are provided as outputs from respective current comparators 141, 142. These comparators are sensitive to the carrier signals VrefP, VrefM (triangular waveforms, as described below) and the control signals VcP and VcM from the differential stage 10 (e.g., a fully differential amplifier or a pair of complementary single-ended amplifiers). This may occur through the intermediate voltage-to-current converter impedances ZmuxP, ZmuxM and ZcP, ZcM.

[0065] In order to generate carrier signals VrefP and VrefM, Figure 2 The exemplary circuit shown comprises two reference generators 161 , 162 which are configured to be clocked by respective clock signals ClockP, ClockM from a clock source which is not visible for simplicity.

[0066] The clock source may comprise any type of clock circuitry known to those skilled in the art for this purpose.

[0067] For example, where circuit 100 is included in a class D audio amplifier, such a clock source may already be provided to facilitate operation of the amplifier: such an amplifier may conventionally include digital blocks clocked with a clock signal, from which the clock discussed herein may be derived, for example, via a clock divider.

[0068] Figure 2 The reference generators 161 , 162 in the exemplary circuit of may include single-ended amplifiers.

[0069] For example, the reference generator 161 , 162 may comprise a single-ended amplifier in an integrator configuration which, starting from the clock signals ClockP, ClockM, generates a (carrier) signal VrefP, VrefM, for example having a triangular shape.

[0070] The reference carrier signals VrefP, VrefM are intended to be applied (for example, converted into current signals via intermediate voltage-to-current converter impedances ZmuxP and ZmuxM, respectively) to current comparators 141, 142 for comparison with differential control signals VcP, VcM (for example, also converted into current signals via intermediate voltage-to-current converter impedances ZcP and ZcM, respectively), thereby generating PWM modulated drive signals DrvInP, DrvInN for driving the first half-bridge stage 121 and the second half-bridge stage 122 as a result of the comparison in the current comparators 141, 142.

[0071] In general, this type of operation (generation of a PWM modulated signal) is otherwise conventional in the art, which makes it unnecessary to provide a more detailed description here. As described below, the modulator 100 described herein is characterized in that the comparison that results in the generation of a PWM modulated signal is performed as a comparison of currents rather than as a comparison of voltages.

[0072] exist Figure 2 In the exemplary circuit 100, the reference signals VrefP, VrefM are sent to the comparators 141, 142 via two multiplexers (MUX) 181, 182 to be compared with the control signals VcP, VcM, and the multiplexers are configured to receive the signals VrefP, VrefM and the threshold signals VpeakP, VpeakM from the reference threshold source and the clock signals ClockPpeak, ClockMpeak from the clock source. For simplicity, these threshold / clock sources (which may include any type of circuit device known to those skilled in the art for this purpose) are not visible.

[0073] For example, Figure 2 The two multiplexers 181, 182 in the exemplary circuit 100 may include analog multiplexers that can switch (force) their outputs to fixed levels (potentials) based on timing signals ClockPpeak, ClockMpeak that switch around the vertices of a "carrier" signal such as VrefP, VrefM in order to produce peaks.

[0074] For example, a corresponding arrangement is disclosed in US 2019 / 0123731 A1 (corresponding to US 10 560 082 B2).

[0075] In short, the PWM modulation circuit disclosed in these documents includes: a first circuit block, configured to receive a square wave input signal and generate a triangular wave signal from the square wave input signal; a second circuit block, configured to receive a modulation signal and generate a PWM signal by comparing the modulation signal with a carrier signal; a switching circuit block, coupled between the first circuit block and the second circuit block, and sensitive to a reference signal having an upper reference value and a lower reference value, and selectively switchable between a carrier transmission setting and one or more carrier forcing settings, in which the switching circuit block couples the first circuit block to the second circuit block to transmit the triangular wave signal as a carrier signal, and the carrier forcing setting is used to optimize or suppress pulse skipping in the PWM signal, wherein the switching circuit block forces the carrier signal to the upper reference value and the lower reference value, respectively.

[0076] The outputs from the multiplexers 181 , 182 (eg, via intermediate voltage-to-current converter impedances ZmuxP and ZmuxM, respectively) are provided to current comparators 141 , 142 , which are configured to generate drive signals DrvInP, DrvInM for the half-bridges 121 , 122 in a final stage.

[0077] Figure 2 The exemplary circuit also includes a common-mode feedback line FeedCM (shown in dotted lines) coupled to the generators 161, 162 to act on the baseline of the carrier signals VrefP, VrefM, and differential-mode feedback lines FeedP and FeedM (also shown in dotted lines) acting on the differential stage 10 (e.g., a fully differential amplifier or a pair of complementary single-ended amplifiers) that generates the control signals VcP, VcM.

[0078] Such feedback arrangements and associated operating principles are otherwise conventional in the art, such that it is not necessary to provide a more detailed description here.

[0079] Figure 2 An advantageous feature of the exemplary circuit is that the comparators 141, 142 comprise (differential) current comparators 141, 142, instead of voltage comparators, which receive at their inputs the current signals to be compared provided via voltage-to-current converter impedances ZcP, ZcM and ZmuxP, ZmuxM, respectively.

[0080] Note that voltage comparators are known to exhibit an expected high input impedance (e.g., provided by the gate terminal of a field effect transistor such as a MOSFET transistor). This is in contrast to current comparators, which are known to exhibit an expected low input impedance (e.g., provided by the source terminal of a field effect transistor such as a MOSFET transistor).

[0081] In a circuit as illustrated herein (using current comparators instead of voltage comparators), a logic value representing the sign of the difference in current into the two inputs of the comparators 141 , 142 may be used to drive the half-bridges 121 , 122 .

[0082] exist Figure 3 This concept is further illustrated in the figures of , in which entities, elements or components similar to those already discussed in conjunction with the previous figures are indicated by like reference symbols; for the sake of brevity, the corresponding detailed description will not be repeated.

[0083] As pointed out, Figure 2 FIG. 1 is an example of a modulator circuit 100, in which the half bridges 121, 122 in the final (power) stage are controlled by corresponding drive signals DrvInP, DrvInM, similar to Figure 1AThe solution shown is the case.

[0084] On the contrary, Figure 3 FIG. 1 is an example of a modulator circuit 100 in which the switches in the half-bridge are configured to be alternately turned on and off via complementary driver stages 121A, 122A with complementary outputs, which are controlled by a single drive signal DrvIn, similar to Figure 1B The solution shown is the case.

[0085] In addition, it should be understood that for the sake of simplicity, Figure 3 Certain features of the architecture can be applied to Figure 2 The architecture of the invention comprises a single current comparator designated as 14, the Figure 2 The architecture of includes two current comparators 141, 142. Figure 2 The dual comparator architecture illustrates certain features that can be applied to Figure 3 Single comparator architecture.

[0086] exist Figure 3 In the exemplary circuit of , the single drive signal DrvIn for driving the half-bridges 121 , 122 is again obtained via the current comparator 14 instead of the voltage comparator.

[0087] In this way, the half-bridges 121 , 122 may be driven with a logic value that represents the sign of the difference between the currents entering the two input terminals of the comparator 14 (ie, iP−iM).

[0088] It is important to note that current comparators such as 14 (and 141, 142) ideally present zero input impedance, so different pairs of signals can be connected to their inputs with all signals decoupled from each other.

[0089] The first pair of input signals may correspond to a differential control signal derived from control voltages VcP and VcM, which is coupled to an impedance via a voltage-to-current converter such as ZcP, ZcM (see, e.g. Figure 3 The iP-iM) applied to the current comparator 14 is converted into a current.

[0090] The second pair of input signals may correspond to carrier reference signals VrefM, VrefP, which are derived from a (single) clock signal Clock (see Figure 2 The differential reference generation (differential reference generation) of the timing (ClockP and ClockM) is achieved by voltage-to-current converter impedances such as ZrefM, ZrefP (see e.g. Figure 3The differential output voltage VrefP-VrefM) from the generator 16 having impedances ZrefM, ZrefP coupled at its output is converted again into a current.

[0091] The third pair of input signals may correspond to the peak values ​​applied at the apex of the carrier signals VrefM, VrefP: see the previous discussion Figure 2 The architecture shown is based on various patent documents cited.

[0092] These peak values ​​can be generated by a differential peak generator 20 in operation, which is generated by a (single) differential clock signal ClockPeak (see Figure 2 ClockPpeak and ClockMpeak in and below Figure 4 and FIG. 5A to FIG. 5D Discussion) Timing.

[0093] The differential peak generator 20 can be configured to generate a differential voltage, which is then converted into a current by a voltage-to-current converter accessing impedances ZpeakM, ZpeakP. Alternatively, the differential peak generator 20 can be configured to directly generate a corresponding differential current (for this purpose, impedances ZpeakM, ZpeakP are shown in dashed lines).

[0094] Other signal pairs may be connected to the inputs of current comparator 14 as may be desired, taking advantage of the mutual decoupling features discussed previously.

[0095] Matching the paired impedances (i.e., ZcP = ZcM, ZrefP = ZrefM, ZpeakP = ZpeakM) was found to be beneficial for promoting Figure 3 The fully differential architecture shown works adequately. A very tight matching is not mandatory as long as mismatches can cause a (small) common-mode signal to be generated by the differential signal. The downstream circuits are differential, making it difficult to transmit such a small common-mode signal.

[0096] Polysilicon resistors were found to provide adequate matching for the purposes herein, with the advantages of good linear behavior and reduced sensitivity to perturbations from the substrate.

[0097] Furthermore, employing a current comparator architecture as disclosed by G. Palmisano and G. Palumbo, "An offset-compensated full differential CMOS current comparator", 38th Midwest Symposium on Circuits and Systems. Proceedings, Rio de Janeiro, Brazila, 1995, Vol. 2, pp. 1038-1041, doi: 10.1109 / MWSCAS.1995.510271 was found to be advantageous for comparators such as 14, 141, 142 shown herein.

[0098] The use of a current comparison instead of a voltage comparison can be advantageous, for example, if only because the associated circuit arrangement is simpler and more flexible (particularly when using Figure 3 ), it can facilitate providing peaks at the vertices of the triangular carrier.

[0099] Figure 4 Yes Figure 3 An example of a differential current comparator 14 is shown, which is provided with a differential peak voltage Vpeakdiff=VpeakP-VpeakM, which is used to charge capacitor C via impedances (resistors) R1P, R1M. As shown, the voltage across capacitor C is passed to the differential (current) input of comparator 14 through further impedances (resistors) R2P, R2M, causing current ipeakdiff to circulate through the comparator input.

[0100] Assuming the matching conditions discussed above, i.e., R1P=R1M=R1 and R2P=R2M=R2, the possible temporal behaviors of VpeakP and VpeakM can be expressed as Figure 5A and Figure 5B That is, VpeakP and VpeakM may include pulse signals with the same peak value V0P=V0M and pulse width (duration) Tpeak; then Vpeakdiff and ipeakdiff may be for Figure 5A and Figure 5B The same common (horizontal axis) time scale is shown as Figure 5C and Figure 5D The temporal behavior illustrated.

[0101] In mathematical terms, this can be expressed as:

[0102] ipeakdiff / Vpeakdiff= 1 / (R1+R2).1 / 1+[sC(2R1.R2) / (R1+R2)] = k / (1+sτ)

[0103] The peak current amplitude (see Figure 5D ) is expressed as:

[0104] i0P=i0M=V0 . k(1-e- Tpeak / τ ).

[0105] The (PWM modulator) circuit (e.g., 100) as exemplified herein may include: a first half-bridge stage (e.g., 121) having a first output node (e.g., OUTP) and a second half-bridge stage (e.g., 122) having a second output node (e.g., OUTM), the first output node and the second output node being configured to have an electrical load (e.g., LD) coupled therebetween to apply a PWM modulated output signal thereto, a differential stage (e.g., 10: this may be a fully differential amplifier or a pair of complementary single-ended amplifiers) having input nodes (e.g., InP, InM), and at least one current ratio comparator (e.g., 14; 141, 142); the differential stage is configured to receive an input signal applied between the input nodes and generate a differential control signal (e.g., VcP, VcM) for the first half-bridge stage and the second half-bridge stage; the at least one current comparator is located between the differential stage and the first half-bridge stage and the second half-bridge stage, and the at least one current comparator is configured to generate at least one PWM modulated drive signal (e.g., DrvIn; DrvInP, DrvInN) to drive the first half-bridge stage and the second half-bridge stage according to the input signal between the input nodes applied in the differential stage.

[0106] As discussed repeatedly, the differential stage 10 considered herein is suitable for being implemented in different ways. For example, a possible alternative to a fully differential amplifier may involve "splitting" the differential stage 10 into two single-ended amplifiers: the first amplifier receives the signal InP and forwards the control signal VcP to the half-bridge 121, and the second amplifier receives the signal InM and forwards the control signal VcM to the half-bridge 122.

[0107] The circuit as illustrated herein may include a current comparator located between the differential stage and the first half-bridge stage and the second half-bridge stage, the current comparator being configured to generate a common PWM modulated drive signal (e.g., DrvIn) applied to both the first half-bridge stage and the second half-bridge stage based on an input signal applied between input nodes in the differential stage.

[0108] The circuit as illustrated herein may include: a first current comparator (e.g., 141) between the differential stage and the first half-bridge stage, the first current comparator being configured to generate a first PWM modulated drive signal (e.g., DrvInP) applied to the first half-bridge stage based on an input signal applied between input nodes in the differential stage, and a second current comparator (e.g., 142) between the differential stage and the second half-bridge stage, the second current comparator being configured to generate a second PWM modulated drive signal (e.g., DrvInM) applied to the second half-bridge stage based on an input signal applied between input nodes in the differential stage (10).

[0109] Circuits as illustrated herein may include at least one pair of matched impedances (e.g., ZcP, ZcM; ZmuxP, ZmuxM; R1P, R1M, R2P, R2M) coupled to the input of at least one current comparator to provide voltage-to-current conversion of a signal applied to the at least one current comparator.

[0110] The circuit as illustrated herein may include at least one reference signal generator (e.g., 16, 161, 162) coupled (e.g., ZmuxP, ZmuxM; ZrefP, ZrefM) to at least one current comparator, wherein the at least one reference signal generator is configured to generate at least one carrier signal (e.g., VrefP, VrefM) for comparison with a differential control signal at the current comparator, wherein at least one PWM modulated drive signal for driving the first half-bridge stage and the second half-bridge stage is a result of the (current) comparison.

[0111] Circuits as exemplified herein may include peak generating circuitry (e.g., Figure 3 20, ZpeakP, ZpeakM or Figure 2 181, 182, VpeakP, VpeakM or Figure 4 VpeakP, VpeakM, R1P, R1M, C, R2P, R2M, 14), the peak generating circuit device is configured to force the peak of the at least one carrier signal to a fixed value (e.g., VpeakP, VpeakM).

[0112] In the circuit as exemplified herein, the peak generating circuit means may include a current peak generator circuit means configured to generate a current peak value (see Figure 4 14 and ipeakdiff) are injected into at least one current comparator.

[0113] As discussed, such a peak generator circuit arrangement (see, for example, Figure 320) can be configured to directly generate current as needed, rather than a voltage to be converted into current (e.g., see Figure 3 ZpeakM and ZpeakP shown by the dashed lines in the middle).

[0114] In the circuit as illustrated herein, the first half-bridge stage may include a first pair of electronic switches having a first output node between the first pair of electronic switches, and the second half-bridge stage may include a second pair of electronic switches having a second output node between the second pair of electronic switches; the electronic switches in the pairs may be configured to be alternately turned on and off via a driver stage (e.g., 121A, 122A) having complementary outputs.

[0115] The device as illustrated in this document may include: a circuit as illustrated in this document (e.g., 100), a signal source (e.g., S) coupled to input nodes (e.g., InP, InM) of a differential stage and configured to apply an input signal between the input nodes, and an electrical load (e.g., LD), the electrical load being coupled between a first output node of the first half-bridge stage and a second output node of the second half-bridge stage to apply a PWM modulated output signal thereto.

[0116] An apparatus as exemplified herein may include a Class-D (eg, audio) amplifier.

[0117] For example, the modulator circuit illustrated herein may be advantageously used in a Class D amplifier implementing an output voltage control strategy, as compared to a Class D amplifier implementing an output current control strategy (e.g., via a flip-flop that is set at each clock cycle and reset as a result of the output inductor current reaching a threshold level).

[0118] A method of driving a circuit or device as illustrated herein may include applying an input signal between input nodes (InP, InM) of a differential stage, and collecting a PWM modulated output signal between a first output node in a first half-bridge stage and a second output node in a second half-bridge stage, the output signal being a function of the input signal applied between the input nodes in the differential stage (10).

[0119] The details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without prejudice to the underlying principle and without departing from the scope of protection.

[0120] The scope of protection is determined by the appended claims.

Claims

1. A modulator circuit comprising: a first half-bridge stage having a first output node; a second half-bridge stage having a second output node, the first output node and the second output node being configured to: provide a pulse width modulation (PWM) modulated output signal to an electrical load coupled between the first output node and the second output node; a differential stage having input nodes, the differential stage being configured to receive an input signal applied between the input nodes and to generate a differential control signal; as well as at least one current comparator located between the differential stage and the first half-bridge stage and the second half-bridge stage, the at least one current comparator being configured to receive the differential control signal and generate at least one PWM modulated drive signal according to the input signal applied between the input nodes in the differential stage to drive the first half-bridge stage and the second half-bridge stage; as well as At least one pair of matched impedances is coupled to the input of the at least one current comparator to provide a voltage-to-current conversion of a signal applied to the at least one current comparator.

2. The circuit of claim 1 , wherein the at least one current comparator is configured to generate a common PWM modulated drive signal applied to both the first half-bridge stage and the second half-bridge stage based on the input signal applied between the input nodes in the differential stage.

3. The circuit of claim 1 , wherein the at least one current comparator comprises: A first current comparator is located between the differential stage and the first half-bridge stage, and the first current comparator is configured to: generate a first PWM modulated drive signal applied to the first half-bridge stage according to the input signal applied between the input nodes in the differential stage; as well as The second current comparator is located between the differential stage and the second half-bridge stage, and the second current comparator is configured to generate a second PWM modulated drive signal applied to the second half-bridge stage according to the input signal between the input nodes applied in the differential stage.

4. The circuit according to claim 1, further comprising: At least one reference signal generator is coupled to the at least one current comparator, and the at least one reference signal generator is configured to generate at least one carrier signal to be compared with the differential control signal, wherein the at least one PWM modulated drive signal is a result of the comparison.

5. The circuit according to claim 4, further comprising: The peak generating circuit device is configured to force the peak of the at least one carrier signal to a fixed value.

6. The circuit of claim 5, wherein the peak generating circuit means comprises: A current peak generator circuit device is configured to inject a current peak at the vertex of the at least one carrier signal into the at least one current comparator.

7. The circuit of claim 1 , wherein the first half-bridge stage comprises a first pair of electronic switches having the first output node therebetween, and the second half-bridge stage comprises a second pair of electronic switches having the second output node therebetween, wherein the electronic switches in the pairs are configured to be alternately switched on and off via a driver stage having complementary outputs.

8. An electronic device comprising: A circuit, the circuit comprising: a first half-bridge stage having a first output node; a second half-bridge stage having a second output node, the first output node and the second output node being configured to provide a pulse width modulation (PWM) modulated output signal; a differential stage having input nodes, the differential stage being configured to receive an input signal applied between the input nodes and to generate a differential control signal; and at least one current comparator located between the differential stage and the first half-bridge stage and the second half-bridge stage, the at least one current comparator being configured to receive the differential control signal and generate at least one PWM modulated drive signal according to the input signal applied between the input nodes in the differential stage to drive the first half-bridge stage and the second half-bridge stage; at least one pair of matched impedances coupled to the input of the at least one current comparator to provide voltage-to-current conversion of a signal applied to the at least one current comparator; a signal source coupled to the input nodes of the differential stage and configured to apply the input signal between the input nodes; An electrical load is coupled between the first output node and the second output node and is configured to receive the PWM modulated output signal.

9. The device of claim 8, wherein the device comprises a class D amplifier.

10. The device of claim 8, wherein the at least one current comparator is configured to generate a common PWM modulated drive signal applied to both the first half-bridge stage and the second half-bridge stage based on the input signal applied between the input nodes in the differential stage.

11. The apparatus of claim 8, wherein the at least one current comparator comprises: A first current comparator is located between the differential stage and the first half-bridge stage, and the first current comparator is configured to: generate a first PWM modulated drive signal applied to the first half-bridge stage according to the input signal applied between the input nodes in the differential stage; as well as The second current comparator is located between the differential stage and the second half-bridge stage, and the second current comparator is configured to generate a second PWM modulated drive signal applied to the second half-bridge stage according to the input signal between the input nodes applied in the differential stage.

12. The apparatus of claim 8, wherein the circuit further comprises: At least one reference signal generator is coupled to the at least one current comparator, the at least one reference signal generator being configured to generate at least one carrier signal to be compared with the differential control signal, wherein the at least one PWM modulated drive signal is a result of the comparison.

13. The device of claim 12, wherein the circuit further comprises: The peak generating circuit device is configured to force the peak of the at least one carrier signal to a fixed value.

14. The apparatus of claim 13, wherein the peak generating circuit means comprises: A current peak generator circuit device is configured to inject a current peak at the vertex of the at least one carrier signal into the at least one current comparator.

15. The apparatus of claim 8, wherein the first half-bridge stage comprises a first pair of electronic switches having the first output node therebetween, and the second half-bridge stage comprises a second pair of electronic switches having the second output node therebetween, wherein the electronic switches in the pairs are configured to be alternately switched on and off via a driver stage having complementary outputs.

16. A method for driving a circuit, the circuit comprising: a first half-bridge stage having a first output node; a second half-bridge stage having a second output node; A differential stage, having input nodes; and at least one current comparator located between the differential stage and the first half-bridge stage and the second half-bridge stage, the method comprising: receiving an input signal between the input nodes of the differential stage; generating a differential control signal by the differential stage; receiving, by the at least one current comparator, the differential control signal; providing voltage-to-current conversion of a signal applied to the at least one current comparator by at least one pair of matched impedances coupled to inputs of the at least one current comparator; The first half-bridge stage and the second half-bridge stage are driven by the at least one current comparator using at least one pulse width modulation (PWM) modulated driving signal according to the input signal; and A PWM modulated output signal is provided to an electrical load coupled between the first output node and the second output node, the PWM modulated output signal being a function of the input signal.

17. The method according to claim 16, further comprising: A common PWM modulated drive signal applied to both the first half-bridge stage and the second half-bridge stage is generated by the at least one current comparator in accordance with the input signal applied between the input nodes in the differential stage.

18. The method of claim 16, wherein the at least one current comparator comprises: a first current comparator, located between the differential stage and the first half-bridge stage; and a second current comparator located between the differential stage and the second half-bridge stage, and the method further comprises: generating, by the first current comparator, a first PWM modulated drive signal applied to the first half-bridge stage according to the input signal applied between the input nodes in the differential stage; as well as A second PWM modulated driving signal applied to the second half-bridge stage is generated by the second current comparator according to the input signal applied between the input nodes in the differential stage.

19. The method according to claim 16, further comprising: At least one carrier signal is generated by at least one reference signal generator coupled to the at least one current comparator to be compared with the differential control signal, and the at least one PWM modulated drive signal is a result of the comparison.

20. The method according to claim 19, further comprising: The peak value of the at least one carrier signal is forced to a fixed value by a peak generating circuit means.

21. The method according to claim 20, further comprising: A current peak value at a vertex of the at least one carrier signal is injected into the at least one current comparator by a current peak value generator circuit device in the peak value generating circuit device.

22. The method of claim 16, wherein the first half-bridge stage comprises: a first pair of electronic switches having the first output node between the first pair of electronic switches, and the second half-bridge stage comprises: a second pair of electronic switches having the second output node between the second pair of electronic switches, and the method further comprises: The electronic switches in the pair are alternately switched on and off by a driver stage having complementary outputs.

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