A fast automatic frequency calibration device and method

Abstract

The present invention discloses a fast automatic frequency calibration device and method, which adopts an integer cycle calculation unit and a fractional cycle calculation unit to count the integer cycle number and fractional cycle number of a VCO frequency signal within a reference frequency signal cycle respectively, wherein the VCO frequency signal is subjected to multiple inversion delay processing by an inversion delay sampling circuit, the reference frequency signal samples the inversion delay signal, the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto is calculated based on the sampling signal, and the fractional cycle number of the VCO frequency signal within the reference frequency signal cycle is determined based on the difference; the integer cycle number and the fractional cycle number are added, so as to quickly and accurately obtain the complete cycle number of the VCO frequency signal within the reference frequency signal cycle, and further generate a control logic word to control the output frequency of the calibrated voltage-controlled oscillator. The calibration time is effectively reduced, and the application requirements of a high-performance fast frequency calibration system can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fast automatic frequency calibration device and method. Background Art

[0002] Frequency synthesizer (FS) is a very important module in modern wireless transceivers, such as Figure 1A The figure shows a basic structural diagram of FS, including a phase-locked loop (PLL) structure 1, a capacitor array 2 and a frequency calibration module 3. The PLL structure 1 is mainly composed of a phase frequency detector (PFD) 11, a charge pump (CP) 12, a loop filter (LPF) 13, a divider (Divider) 14 and a voltage controlled oscillator (VCO) 15.

[0003] In order to ensure strong robustness when the power supply voltage temperature (PVT) changes, the FS is usually required to output a wider frequency range, which means that the on-chip VCO needs to have a wider tuning range. The broadband tuning range of the VCO is generally obtained by adjusting the capacitor array 2 with a fixed inductor, such as using a capacitor array in the form of binary weights, and obtaining a broadband tuning range by adjusting the size of the connected capacitor. In this way, the tuning characteristic curve of the VCO will have multiple sub-bands.

[0004] In fast frequency hopping communication systems, such as military radars, when FS switches frequency, it is necessary to quickly find a suitable sub-band to meet the locking time requirements of the communication system. At the same time, there is generally a certain proportion of overlap between VCO sub-bands, and due to the nonlinearity of VCO tuning gain and CP output voltage, when FS is locked at both ends of the VCO sub-band, the phase noise is generally poor, so it is best to lock FS in the middle of the sub-band. In order to quickly and accurately select the appropriate sub-band, an automatic frequency calibration (AFC) circuit is required. Existing frequency calibration schemes can generally be divided into two types, one is a closed-loop calibration scheme based on control voltage, and the other is an open-loop calibration scheme based on counting form.

[0005] A closed-loop calibration scheme based on control voltage is used, such as Figure 1BThe circuit structure shown in the figure sets the VCO control word and determines whether the VCO control voltage falls within the set range in the closed loop state to determine whether the set VCO control word is appropriate. Since this solution works in the closed loop mode, it takes a long time for each loop lock. This time depends on the loop bandwidth, usually tens of us or even hundreds of us. If there are many VCO sub-bands, the calibration time of the entire AFC will be very long, possibly reaching the ms level, which is unacceptable in a fast frequency hopping system.

[0006] The open-loop calibration scheme based on counting form adopts Figure 1C The circuit structure shown in the figure is used to measure the reference frequency signal F in a fixed time window. REF and the VCO output frequency signal F VCO At the same time, counting is performed, and the current VCO output frequency is determined based on the counting result, so the VCO output frequency band is adjusted. This solution is based on an open-loop structure when counting, so the stabilization time is relatively fast. This method is generally used in FS now. However, since the counter can only count integer cycles, and the frequency interval between VCO frequency bands is sometimes very small, the corresponding integer division ratio may differ by less than 1. Therefore, in order to correctly distinguish the sub-bands, the accuracy can only be ensured by increasing the counting window time. Counting needs to be performed for a longer time, which increases the calibration time of AFC, which is also unacceptable in fast frequency hopping systems. Summary of the invention

[0007] The present invention aims at the technical problem that the automatic frequency calibration scheme in the prior art has a long calibration time (tens or hundreds of microseconds) and cannot meet the application requirements of a high-performance fast calibration system, and provides a new technology to improve the frequency calibration speed and reduce the calibration time.

[0008] In one aspect, the present invention provides a fast automatic frequency calibration device, comprising:

[0009] A global clock generating circuit comprises: a first input terminal and a second input terminal; the first input terminal is connected to a voltage controlled oscillator for inputting a VCO frequency signal; the second input terminal is connected to a reference signal source for inputting a reference frequency signal; the global clock signal is obtained by controlling the VCO frequency signal to oversample the reference frequency signal;

[0010] The integer cycle calculation unit comprises: a third input terminal and a fourth input terminal; the third input terminal is connected to the voltage controlled oscillator for inputting a VCO frequency signal; the fourth input terminal is connected to the global clock generating circuit for inputting the global clock signal; by processing the VCO frequency signal and the global clock signal, the number of integer cycles of the VCO frequency signal within the reference frequency signal cycle is obtained;

[0011] The inverted delay sampling circuit comprises: a fifth input terminal and a sixth input terminal; the fifth input terminal is connected to a voltage-controlled oscillator for inputting a VCO frequency signal; the sixth input terminal is connected to a reference signal source for inputting a reference frequency signal; an inverted delay signal is obtained by performing multiple inverted delay processes on the VCO frequency signal, and the inverted delay signal is sampled by the reference frequency signal to obtain a sampling signal;

[0012] A fractional cycle calculation unit is connected to the output end of the inverting delay sampling circuit, and is used to calculate the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto based on the sampling signal, and determine the number of fractional cycles of the VCO frequency signal within the reference frequency signal period based on the difference;

[0013] an adder connected to the output ends of the integer cycle calculation unit and the fractional cycle calculation unit, and used for adding the number of integer cycles and the number of fractional cycles to obtain the number of complete cycles of the VCO frequency signal within the reference frequency signal period;

[0014] A digital control logic circuit is connected to the adder and is used to generate a control logic word based on the number of complete cycles to control the output frequency of the calibration voltage controlled oscillator.

[0015] Optionally, the integer period calculation unit further includes:

[0016] A first counter is used to perform cumulative counting within a reference frequency signal period and under the triggering of a rising edge of the VCO frequency signal to obtain a plurality of first count values;

[0017] A first counting output unit, configured to output a plurality of first counting values ​​under the control of the global clock signal;

[0018] The first calculation unit is used to calculate the number of integer cycles of the VCO frequency signal within the reference frequency signal cycle based on a plurality of first count values.

[0019] Optionally, the operating frequency of the first counter is at GHz level, and the first counter includes a multi-stage asynchronous counter and a multi-stage synchronous counter.

[0020] Optionally, the inverting delayed sampling circuit further includes:

[0021] The inversion delay unit is used to perform multiple inversion delay processes on the VCO frequency signal to obtain an inversion delay signal;

[0022] The sampling unit is used to control the reference frequency signal to sample the inverted delayed signal to obtain a sampling signal.

[0023] Optionally, the inverting delay unit includes M inverters, M is a positive integer, and M≥Tvco / Tinv;

[0024] Wherein, Tvco is the VCO frequency signal cycle time, and Tinv is the delay time of the inverter.

[0025] Optionally, the fractional period calculation unit includes:

[0026] A second counter is used to perform cumulative counting within a VCO frequency signal period and under the triggering of a rising edge of a reference frequency signal to obtain a plurality of second count values;

[0027] The second calculation unit is used to obtain multiple groups of sampling signals corresponding to multiple second count values ​​respectively, and calculate the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent to it based on the multiple groups of sampling signals, and determine the number of fractional periods of the VCO frequency signal within the reference frequency signal period based on the difference.

[0028] Optionally, the global clock signal is used to synchronize counters in the integer cycle calculation unit and the fractional cycle calculation unit.

[0029] On the other hand, the present invention also provides a fast automatic frequency calibration method, comprising the following steps:

[0030] The global clock signal is obtained by controlling the VCO frequency signal to oversample the reference frequency signal;

[0031] By processing the VCO frequency signal and the global clock signal, the number of integer cycles of the VCO frequency signal within the reference frequency signal cycle is obtained;

[0032] An inverted delayed signal is obtained by performing multiple inverted delay processes on the VCO frequency signal, and the inverted delayed signal is sampled by the reference frequency signal to obtain a sampled signal;

[0033] Calculating the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto based on the sampling signal, and determining the number of fractional cycles of the VCO frequency signal within the reference frequency signal cycle based on the difference;

[0034] Adding the integer cycle number and the fractional cycle number to obtain the number of complete cycles of the VCO frequency signal within the reference frequency signal cycle;

[0035] A control logic word is generated based on the number of complete cycles to control the output frequency of the calibrated voltage controlled oscillator.

[0036] Optionally, the inverted delayed signal is obtained by performing multiple inverted delay processes on the VCO frequency signal, specifically:

[0037] By performing M times of inversion delay processing on the VCO frequency signal, an inversion delay signal is obtained; wherein M is a positive integer, M≥Tvco / Tinv; wherein Tvco is the VCO frequency signal cycle time, and Tinv is the delay time of the inverter.

[0038] Optionally, the step of calculating the difference between the reference frequency signal and a rising edge of a VCO frequency signal adjacent thereto based on the sampled signal, and determining the number of fractional periods of the VCO frequency signal within a period of the reference frequency signal based on the difference, specifically includes:

[0039] Perform cumulative counting within the VCO frequency signal period and under the triggering of the rising edge of the reference frequency signal to obtain a plurality of second count values;

[0040] A plurality of groups of sampling signals corresponding to the plurality of second count values ​​are obtained, and the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto is calculated based on the plurality of groups of sampling signals, and the number of fractional periods of the VCO frequency signal within the reference frequency signal period is determined based on the difference.

[0041] One or more technical solutions provided in the present invention have at least the following technical effects or advantages:

[0042] The fast automatic frequency calibration scheme of the present invention adopts an integer cycle calculation unit and a fractional cycle calculation unit to count the integer cycle number and fractional cycle number of the VCO frequency signal within the reference frequency signal cycle respectively, wherein when counting fractional cycles, the VCO frequency signal is subjected to multiple inversion delay processing by an inversion delay sampling circuit, and the inversion delay signal is sampled by the reference frequency signal to obtain a sampling signal, and then the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto is calculated based on the sampling signal, and the fractional cycle number of the VCO frequency signal within the reference frequency signal cycle is determined based on the difference; the integer cycle number and the fractional cycle number are added, so that the complete cycle number of the VCO frequency signal within the reference frequency signal cycle can be quickly and accurately obtained, that is, the current output frequency of the VCO frequency signal can be accurately and quickly obtained, so as to accurately generate a control logic word to control the output frequency of the calibration voltage-controlled oscillator. The calibration time is effectively reduced to within 2us, which has a very obvious improvement effect and can meet the application requirements of a high-performance fast calibration system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0044] Figure 1A A basic structural diagram of an existing frequency synthesizer provided as the background technology of the present invention;

[0045] Figure 1B A schematic diagram of the structure of a closed-loop calibration solution based on control voltage provided as the background technology of the present invention;

[0046] Figure 1C A schematic diagram of the structure of an open-loop calibration solution based on counting form provided as the background technology of the present invention;

[0047] Figure 2A A schematic diagram of the structure of a fast automatic frequency calibration device provided by an embodiment of the present invention;

[0048] Figure 2B A schematic diagram of the structure of another fast automatic frequency calibration device provided by an embodiment of the present invention;

[0049] Figure 3A A hardware implementation diagram of a global clock generation circuit provided by an embodiment of the present invention;

[0050] Figure 3B A waveform diagram of a global clock generated by a global clock generating circuit provided in an embodiment of the present invention;

[0051] Figure 4 A transient timing relationship diagram of a voltage-controlled oscillator output frequency signal, a reference frequency signal and a global clock signal provided in an embodiment of the present invention;

[0052] Figure 5A The reference frequency signal F provided by the embodiment of the present invention REF The rising edge and the previous VCO output frequency F VCO Error diagram when the rising edge of is approaching;

[0053] Figure 5B The reference frequency signal F provided by the embodiment of the present invention REF The rising edge and the previous VCO output frequency F VCO Error diagram when the falling edge of is approaching;

[0054] Figure 6 The VCO output frequency F provided by the embodiment of the present invention is VCOTiming diagram of the time data converter delay processing after the delay chain structure;

[0055] Figure 7 An overall scheme diagram of a fast automatic frequency calibration device provided by an embodiment of the present invention applied to a frequency synthesizer;

[0056] Figure 8 A calibration time simulation diagram of a fast automatic frequency calibration device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0058] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0059] The technical solution of the present invention is described in detail below with specific embodiments.

[0060] Embodiment 1

[0061] Please refer to Figure 2A , a fast automatic frequency calibration device 2 provided in an embodiment of the present application includes:

[0062] The global clock generating circuit 21 comprises: a first input terminal and a second input terminal; the first input terminal is connected to the voltage controlled oscillator VCO for inputting the VCO frequency signal Fvco; the second input terminal is connected to the reference signal source REF_SIG_S for inputting the reference frequency signal F REF ; By controlling the VCO frequency signal Fvco to the reference frequency signal F REF Sampling is performed to obtain a global clock signal CKR; wherein the global clock signal CKR is used to synchronize the counters in the integer cycle calculation unit 22 and the fractional cycle calculation unit 24.

[0063] The integer cycle calculation unit 22 includes: a third input terminal and a fourth input terminal; the third input terminal is connected to the voltage controlled oscillator VCO and is used to input the VCO frequency signal Fvco; the fourth input terminal is connected to the global clock generating circuit 21 and is used to input the global clock signal CKR; by processing the VCO frequency signal Fvco and the global clock signal CKR, a reference frequency signal F is obtained. REF The number of integer cycles of the VCO frequency signal Fvco within the cycle;

[0064] The inverting delay sampling circuit 23 includes: a fifth input terminal and a sixth input terminal; the fifth input terminal is connected to the voltage controlled oscillator VCO for inputting the VCO frequency signal Fvco; the sixth input terminal is connected to the reference signal source REF_SIG_S for inputting the reference frequency signal F REF ; By performing multiple inversion delay processing on the VCO frequency signal Fvco, an inversion delay signal is obtained, and the reference frequency signal F REF Sampling the inverted delayed signal to obtain a sampled signal;

[0065] The fractional cycle calculation unit 24 is connected to the output end of the inverting delay sampling circuit 23 and is used to calculate the reference frequency signal F based on the sampling signal. REF The difference between the rising edge of the VCO frequency signal Fvco and the next adjacent rising edge thereof is used to determine the reference frequency signal F REF The number of fractional cycles of the VCO frequency signal Fvco within the cycle;

[0066] The adder 25 is connected to the output ends of the integer cycle calculation unit 22 and the fractional cycle calculation unit 24, and is used to add the integer cycle number and the fractional cycle number to obtain a reference frequency signal F REF The number of complete cycles of the VCO frequency signal Fvco within the cycle;

[0067] The digital control logic circuit 26 is connected to the adder 25 and is used to generate a control logic word based on the number of complete cycles to control the output frequency of the calibration voltage controlled oscillator VCO.

[0068] In this embodiment, please refer to Figure 2A The fast automatic frequency calibration device is used to quickly calibrate the output frequency of the voltage controlled oscillator VCO in the frequency synthesizer FS, and the output frequency of the VCO after calibration is used as the final output frequency of the FS.

[0069] This solution applies the idea of ​​digital circuit to FS analog circuit. Converting numbers into time by counting is the key of this solution. Counters are respectively provided in the integer cycle calculation unit 22 and the fractional cycle calculation unit 24. Since the clocks of the two counters are not synchronized, the calculation results may be inaccurate, so it is necessary to synchronize the clocks to form a global clock. The global clock generation circuit 21 is as shown in FIG. Figure 3A and Figure 3B As shown, the VCO output frequency signal Fvco is used to control the reference frequency signal F REF Oversampling obtained.

[0070] The principle of calculating the number of integer cycles is as follows: at the moment when each VCO output frequency signal Fvco rises, the counter of the integer cycle calculation unit 22 is incremented by 1, and the counting result is output when the global clock signal CKR rises, represented by N, as shown in FIG. Figure 4 The difference between the two counts before and after is expressed in an F REF The integer number of cycles output by Fvco within a period.

[0071] In the specific implementation process, please refer to Figure 2B , the integer cycle calculation unit 22 comprises:

[0072] The first counter 221 is used to REF During the period, cumulative counting is performed under the triggering of the rising edge of the VCO frequency signal Fvco to obtain a plurality of first count values;

[0073] A first counting output unit 222, configured to output a plurality of first counting values ​​under the control of a global clock signal CKR;

[0074] The first calculation unit 223 is used to calculate the reference frequency signal F based on the multiple first count values. REF The integer number of cycles of the VCO frequency signal Fvco within the cycle.

[0075] In the specific implementation process, the integer cycle calculation is realized by a high-speed counter. REF The number of integer cycles output by Fvco in a cycle, the operating frequency of the first counter 221 is at the GHz level. The first counter 221 includes a multi-stage asynchronous counter and a multi-stage synchronous counter. Specifically, nine-stage counting is adopted, the first three-stage counters use asynchronous counters, and the last six stages use synchronous counters. The integer counting is mainly an analog D-flip-flop link, which will not be described one by one here.

[0076] The reference frequency signal F is obtained by calculation REFAt the same time as the integer number of cycles of the VCO frequency signal Fvco within the cycle, the number of fractional cycles needs to be calculated. The number of fractional cycles needs to be calculated based on the sampling signal output by the inverting delay sampling circuit 23. Please refer to Figure 2B , the inverting delay sampling circuit 23 comprises:

[0077] The inversion delay unit 231 is used to perform multiple inversion delay processes on the VCO frequency signal Fvco to obtain an inversion delay signal;

[0078] Sampling unit 232, used to control the reference frequency signal F REF The inverted delayed signal is sampled to obtain a sampled signal.

[0079] Specifically, the inverting delay unit 231 includes M inverters:

[0080] M≥Tvco / Tinv (I)

[0081] Wherein, M is a positive integer, Tvco is the cycle time of the VCO frequency signal Fvco, and Tinv is the delay time of the inverter.

[0082] Please still refer to Figure 2B , the fractional period calculation unit 24 comprises:

[0083] The second counter 241 is used to generate a counter within the period of the VCO frequency signal Fvco and within the period of the reference frequency signal F REF Accumulate counting under the triggering of the rising edge of to obtain multiple second counting values;

[0084] The second calculation unit 242 is used to obtain multiple groups of sampling signals corresponding to multiple second count values, and calculate the reference frequency signal F based on the multiple groups of sampling signals. REF The difference between the rising edge of the VCO frequency signal Fvco and the next adjacent rising edge thereof is used to determine the reference frequency signal F REF The number of fractional cycles of the VCO frequency signal Fvco within a cycle.

[0085] Specifically, Figure 4 As shown, after retiming, CKR and F REF There will be a certain error between them, and since CKR is Fvco oversampling F REF Therefore, CKR and F REF The error between them is F REF The error ε between the rising edge of Fvco and the next rising edge of Fvco needs to be accurately calculated to estimate the current frequency division ratio. Figure 5A-5B As shown, Figure 5A is the reference frequency signal F REFWhen the rising edge is close to the rising edge of the previous VCO output frequency Fvco, Figure 5B is the reference frequency signal F REF The rising edge is close to the falling edge of the previous VCO output frequency Fvco.

[0086] First, we need to estimate F REF The delay difference Δt between the rising edge and the previous Fvco rising edge and falling edge r and Δt f , and then calculate the error using formula (II):

[0087] ε=1-Δt r / T V (II)

[0088] Where T V =2|Δt r -Δt f |. The VCO frequency signal Fvco passes through a series of inverter delay chains and is then REF Signal sampling, through the 1-0 and 0-1 jump position in the sampling result, we can get Δt r and Δt f , and then calculate the error using the above formula.

[0089] In a specific implementation process, the inverting delay sampling circuit 23 can be implemented by a time data converter (TDC, Time to Digital Converter), such as Figure 6 As shown in FIG. 1 , it is a timing diagram of a TDC with a delay chain structure, where D(1) to D(8) are multiple delayed signals of Fvco. For example, in the case of a reference frequency signal (F REF ), the sampling result is 10000111, then the signal jumps from 1 to 0 at the first bit, and from 0 to 1 at the fifth bit, so the reference frequency signal F can be obtained. REF It lags behind the Fvco rising edge in front of it by one inverter delay T inv , and the frequency period of VCO is 2*(5-1)=8 inverter delays (8*T inv ), so the calculated phase error ε

[10] =1-T inv / (8*T inv )=7 / 8. By combining TDC with a counter, the accurate value of the current frequency can be obtained within one cycle, so automatic frequency calibration can be performed quickly. At the same time, the number M of inverters is required to meet the constraint of formula (I).

[0090] Furthermore, by combining the number of integer cycles and the number of fractional cycles, we can get a reference cycle (FREF ) is the number of VCO cycles within .

[0091] Combination Figure 4 and Table 1, for a counting example, F REF The period is 2.6, F VCO and F REF There is an initial phase difference ε. After the first retiming, F REF With F VCO There is a phase error of 0.7 between them. The output count value C = 1 at the first CKR rising edge. The second retiming, F REF With F VCO There is a phase error of 0.1, and the output C=3 at the second CKR rising edge. By calculation:

[0092] F REF [K]=C[K]-C[K-1]+ε[K-1]-ε[K] (III)

[0093] That is, the transient frequency division ratio can be obtained. The output results of each time are shown in Table 1. In other words, only two reference signal cycles are needed at most to accurately calculate the F at this time. REF With F VCO Frequency division ratio and F VCO Output frequency.

[0094] Table 1 The values ​​of each parameter when the CKR rising edge arrives

[0095] K ε[K] C[K] <![CDATA[F REF [K]]]> 1 0.7 1 2 0.1 3 2.6 3 0.5 6 2.6 4 0.9 9 2.6 5 0.3 11 2.6 6 0.7 14 2.6

[0096] The overall solution of the automatic frequency calibration device of this scheme being applied to the frequency synthesizer is as follows Figure 7 As shown, the frequency synthesizer includes a phase-locked loop (composed of a phase frequency detector PFD, a charge pump CP, a low-pass filter LPF, a voltage-controlled oscillator VCO, and a frequency divider DIV) and an automatic frequency calibration device 2 of the present scheme. When calibrating, the loop is disconnected and the output frequency signal F of the VCO is VCO and the reference frequency signal F REF It is sent to the automatic frequency calibration device 2, and after calculation and comparison, the control logic adjustment word BN4<5:0> is output to calibrate the VCO. The output frequency of the calibrated VCO is output by the post-synthesizer as the local oscillator signal LO, which is the current final output frequency of FS. Each comparison and calculation takes a total of 10 reference clock cycles, and a total of 7 comparisons are performed, so the AFC calibration time can be greatly reduced. The simulation results are as follows Figure 8 As shown, it can be seen that from the start to the end of the automatic frequency calibration, a total of 7 comparisons were performed, which took 1.4us.

[0097] The technical effect of this solution is mainly to greatly reduce the AFC calibration time. Traditional open-loop or closed-loop calibration requires tens or hundreds of microseconds, but the TDC-based AFC solution proposed in this solution can reduce the calibration time to less than 2us, which has a very obvious improvement effect.

[0098] Embodiment 2

[0099] Based on the same inventive concept, an embodiment of the present invention further provides a fast automatic frequency calibration method, comprising the following steps:

[0100] By controlling the VCO frequency signal Fvco to the reference frequency signal F REF Oversampling, obtaining the global clock signal CKR;

[0101] By processing the VCO frequency signal Fvco and the global clock signal CKR, a reference frequency signal F is obtained. REF The number of integer cycles of the VCO frequency signal Fvco within the cycle;

[0102] The VCO frequency signal Fvco is subjected to multiple inversion delay processes to obtain an inversion delay signal, and the inversion delay signal is obtained by using the reference frequency signal F REF Sampling the inverted delayed signal to obtain a sampled signal;

[0103] The reference frequency signal F is calculated based on the sampling signal REF The difference between the rising edge of the VCO frequency signal Fvco and the next adjacent rising edge thereof is used to determine the reference frequency signal F REF The number of fractional cycles of the VCO frequency signal Fvco within the cycle;

[0104] The number of integer cycles and the number of fractional cycles are added together to obtain a reference frequency signal F REF The number of complete cycles of the VCO frequency signal Fvco within the cycle;

[0105] A control logic word is generated based on the number of complete cycles to control the output frequency of the calibrated voltage controlled oscillator VCO.

[0106] Further, the inverted delayed signal is obtained by performing multiple inverted delay processing on the VCO frequency signal Fvco, specifically:

[0107] By performing M times of inversion delay processing on the VCO frequency signal Fvco, an inversion delay signal is obtained; wherein M is a positive integer, M≥Tvco / Tinv; wherein Tvco is the cycle time of the VCO frequency signal Fvco, and Tinv is the delay time of the inverter.

[0108] In a specific implementation process, the reference frequency signal F is calculated based on the sampling signal. REF The difference between the rising edge of the VCO frequency signal Fvco and the next adjacent rising edge thereof is used to determine the reference frequency signal F REF The number of fractional cycles of the VCO frequency signal Fvco within a cycle, specifically including:

[0109] During the VCO frequency signal Fvco period, at the reference frequency signal F REF Accumulate counting under the triggering of the rising edge of to obtain multiple second counting values;

[0110] Acquire multiple groups of sampling signals corresponding to multiple second count values, and calculate the reference frequency signal F based on the multiple groups of sampling signals REF The difference between the rising edge of the VCO frequency signal Fvco and the next adjacent rising edge thereof is used to determine the reference frequency signal F REF The number of fractional cycles of the VCO frequency signal Fvco within a cycle.

[0111] According to the above description, the above-mentioned fast automatic frequency calibration method is applied to the above-mentioned fast automatic frequency calibration device, so the method is consistent with one or more embodiments of the above-mentioned device, and will not be described one by one here.

[0112] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0113] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A fast automatic frequency calibration device, characterized in that: include: A global clock generating circuit comprises: a first input terminal and a second input terminal; the first input terminal is connected to a voltage controlled oscillator for inputting a VCO frequency signal; the second input terminal is connected to a reference signal source for inputting a reference frequency signal; the global clock signal is obtained by controlling the VCO frequency signal to oversample the reference frequency signal; The integer cycle calculation unit comprises: a third input terminal and a fourth input terminal; the third input terminal is connected to the voltage controlled oscillator for inputting a VCO frequency signal; the fourth input terminal is connected to the global clock generating circuit for inputting the global clock signal; by processing the VCO frequency signal and the global clock signal, the number of integer cycles of the VCO frequency signal within the reference frequency signal cycle is obtained; The inverted delay sampling circuit comprises: a fifth input terminal and a sixth input terminal; the fifth input terminal is connected to a voltage-controlled oscillator for inputting a VCO frequency signal; the sixth input terminal is connected to a reference signal source for inputting a reference frequency signal; an inverted delay signal is obtained by performing multiple inverted delay processes on the VCO frequency signal, and the inverted delay signal is sampled by the reference frequency signal to obtain a sampling signal; A fractional cycle calculation unit is connected to the output end of the inverting delay sampling circuit, and is used to calculate the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto based on the sampling signal, and determine the number of fractional cycles of the VCO frequency signal within the reference frequency signal period based on the difference; an adder connected to the output ends of the integer cycle calculation unit and the fractional cycle calculation unit, and used for adding the number of integer cycles and the number of fractional cycles to obtain the number of complete cycles of the VCO frequency signal within the reference frequency signal period; A digital control logic circuit is connected to the adder and is used to generate a control logic word based on the number of complete cycles to control the output frequency of the calibration voltage controlled oscillator.

2. The fast automatic frequency calibration device according to claim 1, characterized in that: The integer cycle calculation unit further includes: A first counter is used to perform cumulative counting within a reference frequency signal period and under the triggering of a rising edge of the VCO frequency signal to obtain a plurality of first count values; A first counting output unit, configured to output a plurality of first counting values ​​under the control of the global clock signal; The first calculation unit is used to calculate the number of integer cycles of the VCO frequency signal within the reference frequency signal cycle based on a plurality of first count values.

3. The fast automatic frequency calibration device according to claim 2, characterized in that: The operating frequency of the first counter is at GHz level, and the first counter includes a multi-stage asynchronous counter and a multi-stage synchronous counter.

4. The fast automatic frequency calibration device according to claim 1, characterized in that: The inverting delayed sampling circuit further includes: The inversion delay unit is used to perform multiple inversion delay processes on the VCO frequency signal to obtain an inversion delay signal; The sampling unit is used to control the reference frequency signal to sample the inverted delayed signal to obtain a sampling signal.

5. The fast automatic frequency calibration device according to claim 4, characterized in that: The inverting delay unit comprises M inverters, where M is a positive integer, and M≥Tvco / Tinv; Wherein, Tvco is the VCO frequency signal cycle time, and Tinv is the delay time of the inverter.

6. The fast automatic frequency calibration device according to claim 1, characterized in that: The fractional period calculation unit comprises: A second counter is used to perform cumulative counting within a VCO frequency signal period and under the triggering of a rising edge of a reference frequency signal to obtain a plurality of second count values; The second calculation unit is used to obtain multiple groups of sampling signals corresponding to multiple second count values ​​respectively, and calculate the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent to it based on the multiple groups of sampling signals, and determine the number of fractional periods of the VCO frequency signal within the reference frequency signal period based on the difference.

7. The fast automatic frequency calibration device according to claim 1, characterized in that: The global clock signal is used to synchronize the counters in the integer cycle calculation unit and the fractional cycle calculation unit.

8. A fast automatic frequency calibration method, characterized in that: The steps include: The global clock signal is obtained by controlling the VCO frequency signal to oversample the reference frequency signal; By processing the VCO frequency signal and the global clock signal, the number of integer cycles of the VCO frequency signal within the reference frequency signal cycle is obtained; An inverted delayed signal is obtained by performing multiple inverted delay processes on the VCO frequency signal, and the inverted delayed signal is sampled by the reference frequency signal to obtain a sampled signal; Calculating the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto based on the sampling signal, and determining the number of fractional cycles of the VCO frequency signal within the reference frequency signal cycle based on the difference; Adding the integer cycle number and the fractional cycle number to obtain the number of complete cycles of the VCO frequency signal within the reference frequency signal cycle; A control logic word is generated based on the number of complete cycles to control the output frequency of the calibrated voltage controlled oscillator.

9. The fast automatic frequency calibration method according to claim 8, characterized in that: The inverted delayed signal is obtained by performing multiple inverted delay processes on the VCO frequency signal, specifically: By performing M times of inversion delay processing on the VCO frequency signal, an inversion delay signal is obtained; wherein M is a positive integer, M≥Tvco / Tinv; wherein Tvco is the VCO frequency signal cycle time, and Tinv is the delay time of the inverter.

10. The fast automatic frequency calibration method according to claim 8, characterized in that: The step of calculating the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto based on the sampling signal, and determining the number of fractional cycles of the VCO frequency signal within the reference frequency signal cycle based on the difference, specifically includes: Perform cumulative counting within the VCO frequency signal period and under the triggering of the rising edge of the reference frequency signal to obtain a plurality of second count values; A plurality of groups of sampling signals corresponding to the plurality of second count values ​​are obtained, and the difference between the reference frequency signal and the rising edge of the VCO frequency signal adjacent thereto is calculated based on the plurality of groups of sampling signals, and the number of fractional periods of the VCO frequency signal within the reference frequency signal period is determined based on the difference.

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