Testing circuits and display panels

Abstract

The present invention relates to the field of display technology, and discloses a test circuit and a display panel, wherein the display panel comprises the test circuit, the test circuit comprises a test control line and a plurality of test lines, and a plurality of switch units arranged in columns, the switch units connect the plurality of test lines with data lines, and provide the test signals on the plurality of test lines to the corresponding data lines in the test phase to realize the lighting test of the display panel, and in the display phase, the plurality of switch units conduct the electrical path from the corresponding data lines to the test lines, and release the electrostatic charge on the data lines to the common electrode lines via the plurality of test lines. The test circuit and display panel provided by the present invention integrate the functional circuits of electrostatic protection and the lighting test of the display panel into one, effectively reducing the additional occupation of the frame space of the display panel by the electrostatic protection circuit, and providing convenience for the narrow frame design of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a test circuit and a display panel. Background Art

[0002] Liquid Crystal Display (LCD) has an important position in the field of flat panel display due to its advantages of lightness, thinness, low power consumption, high brightness and high image quality. Among them, the array substrate in the liquid crystal display panel of the LCD includes pixel units and data lines. The data lines are connected to the pixel units and the operation of the pixel units is controlled by the data lines. When the display panel is working normally, there will also be electrostatic discharge (ESD for short). Electrostatic discharge is the main factor causing most electronic components or electronic systems to be damaged by excessive electrical stress, which can easily cause permanent damage to semiconductor devices, thereby causing the failure of integrated circuit functions. For display panels, electrostatic discharge can cause damage to the microelectronic structure of the pixel units of the array substrate, which in turn causes display abnormalities. Therefore, it is necessary to release the charge on the data line through an anti-static circuit.

[0003] The existing electrostatic protection circuit includes a discharge transistor and a switch signal line. The gate of the discharge transistor is connected to the switch signal line, one of its source and drain is connected to the data line, and the other is connected to the common electrode on the array substrate through a transistor (the common electrode is connected through the common electrode line). The discharge transistor is controlled by the switch signal line to release the charge on the data line to the common electrode. Figure 1 A partial structural schematic diagram of a display panel according to the prior art is shown. Figure 1 In the display panel 100 of the prior art, an opening 101 is provided at one end thereof for placing a camera. Near the opening 101, the pixel units 111 are arranged in a stepped manner, and the wiring 121 corresponding to the non-display area is arranged obliquely, that is, there is no space for placing the electrostatic protection circuit at the position where the opening is provided, and the electrostatic protection circuit 10 needs to be provided at the other end, and the electrostatic protection circuit 10 generally needs to occupy a space of 200 to 300 microns in width of the lower frame, which is not conducive to the design of a narrow frame. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide a test circuit and a display panel, so as to reduce the occupancy of the electrostatic protection circuit on the frame and facilitate the design of a narrow frame.

[0005] According to one aspect of the present invention, there is provided a test circuit with an electrostatic protection function, which is arranged on a display panel, and the test circuit comprises:

[0006] Test control lines;

[0007] Multiple test lines;

[0008] A plurality of switch units arranged in columns, wherein the first ends of the plurality of switch units are connected to the plurality of data lines on the display panel in a one-to-one correspondence, the control end of each of the switch units is connected to the test control line, and the second end of each of the switch units is connected to the plurality of test lines,

[0009] Among them, each of the switching units is suitable for providing the test signals on the multiple test lines to the corresponding data lines among the multiple data lines in the test phase to realize the lighting test of the display panel, and in the display phase, each of the switching units turns on the electrical path from the corresponding data line to the test line, and releases the electrostatic charge on the data line to the common electrode line via the multiple test lines.

[0010] Optionally, it also includes:

[0011] At least one electrostatic release unit, a first end of the at least one electrostatic release unit is connected to the common electrode line, and a second end of the at least one electrostatic release unit is connected to the test line, and is suitable for providing an electrical path from the multiple test lines to the common electrode line in the display stage.

[0012] Optionally, the switch unit comprises a third transistor and a fourth transistor, wherein a drain of each of the third transistor and the fourth transistor is connected to a source of the other transistor,

[0013] The gate of the fourth transistor is connected to the corresponding data line, and the gate of the fourth transistor is connected to the drain.

[0014] A gate of the third transistor is connected to the test control line, and a drain of the third transistor is connected to a corresponding test line among the plurality of test lines.

[0015] Optionally, the electrostatic discharge unit comprises a first transistor and a second transistor, wherein a source of each of the first transistor and the second transistor is connected to a drain of the other transistor.

[0016] The drain of the first transistor is connected to the gate, and the gate of the first transistor is connected to the plurality of test lines.

[0017] A drain of the second transistor is connected to a gate, and a gate of the second transistor is connected to the common electrode line.

[0018] Optionally, it also includes:

[0019] A regulating transistor is connected in series between the plurality of test lines and the test control line, and connects the plurality of test lines to the test control line when the regulating transistor is turned on.

[0020] Optionally, a gate of the regulating transistor is connected to the plurality of test lines.

[0021] Optionally, the test circuit further comprises an auxiliary control line, wherein the auxiliary control line is connected to the gate of the regulating transistor.

[0022] In the test phase, the auxiliary control line provides a low level to turn off the regulating transistor, and

[0023] In the display stage, the auxiliary control line provides a high level to turn on the regulating transistor.

[0024] Optionally, in the test phase, the test control line provides a high level to turn on each of the switch units, and

[0025] In the display stage, the test control line and the plurality of test lines are all suspended.

[0026] Optionally, the test circuit is arranged at at least one of a tail end of a data line, a side where a data line enters, and a blank position inside the IC.

[0027] According to another aspect of the present invention, there is provided a display panel, comprising:

[0028] A test circuit is provided according to the present invention.

[0029] The test circuit provided by the present invention includes a test control line and multiple test lines, and multiple switch units arranged in columns, the switch units connect the multiple test lines with data lines, and provide the test signals on the multiple test lines to the corresponding data lines in the test phase to realize the lighting test of the display panel, and in the display phase, the multiple switch units turn on the electrical path from the corresponding data line to the test line, and release the electrostatic charge on the data line to the common electrode line via the multiple test lines, and use the multiple test lines for data input during testing and electrostatic charge release during electrostatic protection in a time-sharing manner, integrating the functional circuits of electrostatic protection and display panel lighting test into one, effectively reducing the additional occupation of the border space of the display panel by the electrostatic protection circuit, and providing convenience for the narrow border design of the display panel.

[0030] The display panel provided by the present invention includes the test circuit provided by the present invention, which integrates the test circuit with the lighting test circuit of the display panel, effectively reducing the additional occupation of the frame space of the display panel by the electrostatic protection circuit, and providing convenience for narrow frame design. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 A partial structural schematic diagram of a display panel according to the prior art is shown;

[0033] Figure 2 A schematic diagram of the structure of an electrostatic protection circuit according to the prior art is shown; Figure 3 A schematic diagram of the structure of a test circuit according to an embodiment of the present invention is shown;

[0034] Figure 4 A structural schematic diagram of a test circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0036] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0037] Figure 2 FIG. 4 shows a schematic diagram of a structure of an electrostatic protection circuit according to the prior art. Figure 2 As shown, the electrostatic protection circuit 10 of the prior art includes a plurality of switch units, each of which includes a transistor T11 and a transistor T12, a gate G1 of the transistor T11 is connected to a drain D1, a gate G2 of the transistor T12 is connected to a drain D2, a drain D1 of the transistor T11 is connected to a source S2 of the transistor T12, a drain D2 of the transistor T12 is connected to a source S1 of the transistor T11, gates of the transistors T11 in the plurality of switch units are connected to a switch signal line 11, a portion of the plurality of switch units corresponds one to one with data lines (S1, S2 to S5760, S5761), and wherein The source of the transistor T11 is connected to the corresponding data line, and the gate G2 of the transistor T12 in another part of the multiple switch units is connected to the common electrode Vcom. When a large static charge appears on any data line, the transistor T12 of the corresponding switch unit is turned on, and the static charge is transferred to the switch signal line 11 through the path from D2, S2, D1, G1 to the switch signal line 11, and the transistor T11 of another part of the multiple switch units is turned on, and the static charge is released to the common electrode through the path from G1, D1, S1, D2, G2 to the common electrode Vcom, thereby realizing the static discharge on the data line.

[0038] Figure 3 FIG. 1 shows a schematic diagram of a test circuit according to an embodiment of the present invention. Figure 3In the test circuit of this embodiment, it mainly includes an electrostatic release unit 21, a switch unit 22, a fifth transistor T5 (control transistor), a sixth transistor T6 (control transistor, two in this embodiment, but the present invention does not specifically limit the number of control transistors), a test control line ADD, a first test line D1, and a second test line D2. Among them, the electrostatic release unit 21 and the switch unit 22 are arranged side by side to avoid occupying additional width space.

[0039] In this embodiment, each transistor is an N-type transistor.

[0040] The electrostatic release unit 21 includes a first transistor T1 and a second transistor T2, the drain D1 of the first transistor T1 is connected to the source S2 of the second transistor T2, the source S1 of the first transistor T1 is connected to the drain D2 of the second transistor T2, the drain D1 of the first transistor T1 is connected to the gate G1, the drain D2 of the second transistor T2 is connected to the gate G2, the gate of the first transistor T1 is connected to the first test line D1, and the gate of the second transistor T2 is connected to the common electrode Vcom. When a large electrostatic charge appears on the first test line D1, the first transistor T1 is turned on, and the electrostatic charge is transmitted from the drain D1 of the first transistor T1 to the source S1, and then transmitted to the common electrode Vcom through the external wiring from the drain D2 of the second transistor T2 to the gate G2, providing a release path for the electrostatic charge.

[0041] In this embodiment, two electrostatic discharge units 21 are provided, and the gate of the first transistor T1 is connected to the first test line D1 and the second test line D2 respectively, providing electrostatic charge release paths for the first test line D1 and the second test line D2 respectively. In an optional embodiment, multiple electrostatic discharge units 21 are provided to increase the electrostatic charge release speed.

[0042] The switch unit 22 includes a third transistor T3 and a fourth transistor T4, the source of the third transistor T3 and the fourth transistor T4 are connected to the drain of the other, the drain and gate of the fourth transistor T4 are connected, the gate of the third transistor T3 is connected to the test control line ADD, the drain of the third transistor T3 is connected to the first test line D1 or the second test line D2 (in this embodiment, there are two test lines, the drain of the third transistor T3 in each switch unit 22 is connected to one of the two test lines, and alternately connected to different test lines), and the gate of the fourth transistor T4 is connected to the data line (S1 to S5761). When a large electrostatic current appears on the data line, the fourth transistor T4 is turned on, and the electrostatic charge is transferred to the source of the fourth transistor T4, and then transferred to the first test line D1 or the second test line D2. When the charge release path of the electrostatic release unit 21 connected to the first test line D1 or the second test line D2 is turned on, the electrostatic charge is released to the common electrode Vcom, thereby realizing the release of the electrostatic charge on the data line.

[0043] The test circuit of this embodiment is used for electrostatic protection when no other signal is input to the test control line ADD, the first test line D1 and the second test line D2.

[0044] In the test phase, a switch control signal (high level is valid) is applied to the test control line ADD, and a test signal (for lighting drive of the pixel unit) is applied to the first test line D1 and the second test line D2 for lighting test of the pixel unit of the display panel. After the lighting test of the pixel unit of the display panel is completed, in the display phase, no external signal is input to the test control line ADD, the first test line D1 and the second test line D2 for electrostatic protection.

[0045] Among them, the test control line ADD applies a switch control signal to drive the third transistor T3 of each switch unit 22 to turn on, thereby turning on the electrical path from the drain of the third transistor T3 to the gate of the fourth transistor T4. A test signal is applied to the first test line D1 and the second test line D2, and a drive signal can be provided to the data line to test the effectiveness of each pixel unit of the display panel.

[0046] In this embodiment, the drain of the fifth transistor T5 is connected to the first test line D1, the source is connected to the test control line ADD, and the gate is connected to the drain. The drain of the sixth transistor T6 is connected to the second test line D2, the source is connected to the test control line ADD, and the gate is connected to the drain. When the electrostatic charge on the data line is transferred to the first test line D1 and the second test line D2, the fifth transistor T5 and the sixth transistor T6 are also turned on, so that the potential of the first test line D1 and the second test line D2 are also synchronized to the test control line ADD, and the third transistor T3 of the switch unit 22 is turned on, so that the electrical path from the drain of the third transistor T3 of the switch unit to the gate of the fourth transistor T4 is turned on, so that the potential of the first test line D1 and the second test line D2 maintains the conduction of the fourth transistor T4, further ensuring the conduction of the switch unit 22 during electrostatic discharge, maintaining the effective opening of the electrostatic release path of the data line, improving the reliability of electrostatic discharge, and improving the electrostatic protection capability.

[0047] The test circuit of the embodiment of the present invention can simultaneously realize the functions of the lighting test circuit and the electrostatic protection circuit of the display panel, integrating the space occupied by the lighting test circuit and the electrostatic protection circuit in the non-display area of ​​the display panel into one, reducing the space occupied by the lighting test and electrostatic protection function realization circuits in the non-display area, and providing convenience for the narrow bezel design of the display panel.

[0048] In this embodiment, the test circuit is arranged at the lower frame position of the display panel 100, that is, at the tail end of the data line (matching the row scanning sequence). In an optional embodiment, the test circuit can also be arranged on the data line entry side (data signal input side), or in a blank position inside the control chip (IC), both of which can effectively reduce the total space occupied by the lighting test and electrostatic protection function circuits in the non-display area.

[0049] Figure 4 FIG. 1 is a schematic diagram showing a structure of a test circuit according to an embodiment of the present invention. Figure 3 The main structures of the test circuits shown are the same, and the same parts will not be described in detail here.

[0050] Reference Figure 4 In this embodiment, an auxiliary control line F is additionally provided, and the on and off control of the fifth transistor T5 and the sixth transistor T6 is controlled by the input signal of the auxiliary control line F, and the other parts are Figure 3 The embodiments shown are the same and will not be described in detail here.

[0051] It provides a low level during the lighting test of the pixel unit of the display panel to control the fifth transistor T5 and the sixth transistor T6 to be turned off. When the display panel works normally, the auxiliary control line F provides a high level to control the fifth transistor T5 and the sixth transistor T6 to be turned on, thereby improving the electrostatic protection effect.

[0052] The test circuit provided by the present invention includes a test control line and multiple test lines, and multiple switch units arranged in columns, the switch units connect the multiple test lines with data lines, and provide the test signals on the multiple test lines to the corresponding data lines in the test phase to realize the lighting test of the display panel, and in the display phase, the multiple switch units turn on the electrical path from the corresponding data line to the test line, and release the electrostatic charge on the data line to the common electrode line via the multiple test lines, and use the multiple test lines for data input during testing and electrostatic charge release during electrostatic protection in a time-sharing manner, integrating the functional circuits of electrostatic protection and display panel lighting test into one, effectively reducing the additional occupation of the border space of the display panel by the electrostatic protection circuit, and providing convenience for the narrow border design of the display panel.

[0053] The display panel provided by the present invention includes the test circuit provided by the present invention, which integrates the electrostatic protection circuit with the lighting test circuit of the display panel, effectively reducing the additional occupation of the frame space of the display panel by the electrostatic protection circuit, and providing convenience for narrow frame design.

[0054] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A test circuit with electrostatic protection function, arranged on a display panel, characterized in that: The test circuit comprises: Test control lines; Multiple test lines; A plurality of switch units arranged in columns, wherein the first ends of the plurality of switch units are connected to the plurality of data lines on the display panel in a one-to-one correspondence, the control end of each of the switch units is connected to the test control line, and the second end of each of the switch units is connected to the plurality of test lines, Each of the switch units is adapted to provide the test signals on the multiple test lines to the corresponding data lines among the multiple data lines in the test phase to implement the lighting test of the display panel, and in the display phase, each of the switch units conducts the electrical path from the corresponding data line to the test line, and releases the electrostatic charge on the data line to the common electrode line via the multiple test lines. The test circuit further comprises: at least one electrostatic discharge unit, wherein a first end of the at least one electrostatic discharge unit is connected to the common electrode line, and a second end of the at least one electrostatic discharge unit is connected to the test line, and is suitable for providing an electrical path from the plurality of test lines to the common electrode line in the display stage, The electrostatic discharge unit includes a first transistor and a second transistor, a source of each of the first transistor and the second transistor is connected to a drain of the other, The drain of the first transistor is connected to the gate, and the gate of the first transistor is connected to the plurality of test lines. The drain of the second transistor is connected to the gate, and the gate of the second transistor is connected to the common electrode line. The test circuit further includes a regulating transistor, which is connected in series between the plurality of test lines and the test control line, and connects the plurality of test lines to the test control line when the regulating transistor is turned on.

2. The test circuit according to claim 1, characterized in that: The switch unit includes a third transistor and a fourth transistor, a drain of each of the third transistor and the fourth transistor is connected to a source of the other, The gate of the fourth transistor is connected to the corresponding data line, and the gate of the fourth transistor is connected to the drain. A gate of the third transistor is connected to the test control line, and a drain of the third transistor is connected to a corresponding test line among the plurality of test lines.

3. The test circuit according to claim 1, characterized in that: The gate of the control transistor is connected to the plurality of test lines.

4. The test circuit according to claim 1, characterized in that: The test circuit further comprises an auxiliary control line connected to the gate of the regulating transistor. In the test phase, the auxiliary control line provides a low level to turn off the regulating transistor, and In the display stage, the auxiliary control line provides a high level to turn on the regulating transistor.

5. The test circuit according to claim 1, characterized in that: In the test phase, the test control line provides a high level to turn on each of the switch units, and In the display stage, the test control line and the plurality of test lines are all suspended.

6. The test circuit according to claim 1, characterized in that: The test circuit is arranged at least one of the tail end of the data line, the side where the data line enters, and a blank position inside the IC.

7. A display panel, characterized in that: include: A test circuit according to any one of claims 1 to 6.

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