Device, System, and Method for Error Correction

Abstract

The present disclosure discloses an apparatus, a system, and a method for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a masked write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit, and write data may be received along a data terminal by the write portion of the ECC circuit. The write portion of the ECC circuit may generate corrected write data based on the write data and the read data, and may generate corrected parity based on the read parity and the corrected write data. The corrected write data and the corrected parity may be written back to the memory array along the write bus.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices, such as semiconductor memory devices. Background Art

[0002] A semiconductor memory device may include a plurality of memory cells for storing information. The stored information may be encoded as binary data, and each memory cell may store a single bit of the information. Due to various different errors, the information may decay or change in the memory cells, which may result in reading one or more incorrect information bits (e.g., bits having a state different from the originally written bits) from the memory device.

[0003] There are many applications where it is useful to ensure a high fidelity of the information read from the memory. The memory device may include an error correction circuit, which may be used to determine whether the information read from the memory cells contains any errors compared to the data written into the memory cells, and may correct the detected errors. Summary of the Invention

[0004] In one aspect, the present application provides an apparatus, comprising: a bank; a data terminal; a write bus; a read bus; a write portion of an error correction code (ECC) circuit, configured to receive write data from the data terminal, generate parity bits based on the write data, and provide the write data and parity data to the bank along the write bus; and a read portion of the ECC circuit, configured to receive read data and read parity along the read bus from the bank, and generate read syndrome information based on the read data and the read parity.

[0005] In another aspect, the present application provides an apparatus, comprising: a read syndrome tree, configured to receive read data along a read bus and provide syndrome information based on the read data; a latch, configured to store the read data from the read bus; a multiplexer, configured to receive the read data from the latch and write data from a data terminal, and provide corrected write data along a write bus based on the read data and the write data; and a write syndrome tree, configured to receive the corrected write data and generate write parity based on the corrected write data, wherein the read syndrome tree operates in a timing based on a first clock signal, the latch operates in a timing based on a second clock signal, and the multiplexer and the write syndrome tree operate in a timing based on a third clock signal.

[0006] In another aspect, the present application provides a method, which includes: in response to a mask write command, reading read data from a memory array of a memory along a read bus; generating read syndrome information based on the read data by using a read syndrome tree; receiving write data along a data terminal of the memory; generating corrected write data based on the write data and the read data; generating corrected syndrome information based on the corrected write data and the read syndrome information by using a write syndrome tree; and writing the corrected write data and the corrected syndrome information to the memory array along a write bus of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. is a block diagram of a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2 FIG. is a block diagram of a read and write path of a memory according to some embodiments of the present disclosure.

[0009] Figure 3 A part of a memory device used in a mask write operation according to some embodiments of the present disclosure.

[0010] Figure 4 FIG. is a timing diagram of operations in a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 FIG. is a timing diagram of operations in multiple banks according to some embodiments of the present disclosure.

[0012] Figures 6A to 6C FIG. is a schematic diagram of a logic tree according to some embodiments of the present disclosure.

[0013] Figure 7 FIG. is a flowchart depicting a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part hereof, and which illustrate, by way of example, specific embodiments in which the described system and method may be practiced. The embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed system and method, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Additionally, for clarity purposes, when the detailed description of certain features would be apparent to those skilled in the art such that it would not obscure the description of the embodiments of the present disclosure, the detailed description of certain features will not be set forth. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0015] A memory device may include a memory array having a plurality of memory cells, each memory cell located at the intersection of a word line (row) and a digit line (column). During a read or write operation, a row and a column may be activated, and data may be read from or written to a memory cell at the intersection of the activated row and column. Data stored in the memory array may include a plurality of data bits and a plurality of parity bits, which may be used to check the integrity of the data bits. The information encoded in the parity bits may be used to correct a maximum number of errors. For example, a set of data may include i data bits and k parity bits, which may be used to correct up to j data bits. The parity bits may be generated by an error correction code circuit based on the data written to the memory cells of the memory array. During a read operation, the error correction code circuit may use the parity bits to determine whether the read data bits are correct and may correct any errors found.

[0016] The memory device may also perform a masked write operation, in which a data set is read from the memory array and a portion of the read data is replaced with new data (e.g., from a data terminal of the memory) before the corrected data set is written back to the memory array (e.g., the same memory cells that were read). As part of the masked write operation, a parity bit may also be generated and written to the memory array. For example, as part of the masked write operation, an error correction code (ECC) circuit may receive the data read from the memory array and the new write data, correct the read data by replacing a portion of the bits with the new write data, generate a parity bit based on the corrected data set (e.g., by correcting the parity bit based on the read data to reflect the corrected data), and then write the corrected data and the corrected parity back to the memory array. The masked write operation can create a bottleneck in the timing of the memory because the masked write operation requires both a read operation and a write operation in the memory. For example, the above scenario can cause problems if a new command that will use the ECC is received while the ECC is still processing a previous masked write operation. Accordingly, there is a need to simplify the timing of the ECC component and other parts of the read and write paths.

[0017] The present disclosure is directed to apparatuses, systems, and methods for error correction. A memory device may include a data terminal and a plurality of banks. Write data from the data terminal may be coupled to the banks along a write bus by a write portion of an ECC circuit. Read data may be coupled from the banks to a read portion of the ECC circuit along a read bus and then output to the data terminal. During a masked write operation, a plurality of timing domains may be used (e.g., a first domain for a first set of components, a second domain for a second set of components, etc.). The plurality of timing domains may allow data from different commands (e.g., a first masked write command and a second masked write command) to move through the ECC circuit without interfering with each other.

[0018] In an example masked write operation, a first clock domain may be used to manage reading data from the memory array. A second clock domain may be used to manage transferring the read data along the read bus to the read ECC circuit. A third clock domain may be used to manage checking for parity errors and transferring corrected parity information to the write ECC circuit. A fourth clock domain may manage receiving write data from the data terminal, thereby updating the parity information and correcting the read data and parity, and thus writing it back along the write bus for writing to the banks. By splitting the masked write operation between different buses and different clock domains, multiple commands may be processed even if the masked write operation takes longer than the timing between commands.

[0019] Figure 1Block diagram of a semiconductor device according to some embodiments of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0020] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of banks. In Figure 1 the embodiment, the memory array 118 is shown as including eight banks BANK0 to BANK7. More or fewer banks may be included in the memory array 118 of other embodiments. Each bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by the row decoder 108, and the selection of the bit lines BL is performed by the column decoder 110. In Figure 1 the embodiment, the row decoder 108 includes a corresponding row decoder for each bank, and the column decoder 110 includes a corresponding column decoder for each bank. The bit lines BL are coupled to corresponding sense amplifiers (SAMP). The read data from the bit lines BL is amplified by the sense amplifiers SAMP and transmitted to the read / write amplifier 120 through complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B), and the complementary main data lines are coupled to the read error correction code (ECC) control circuit 120 along the read bus through a data amplifier (DA). Conversely, the write data output from the write ECC control circuit 120 is transmitted to the sense amplifiers SAMP through a write buffer (WB) to the complementary main data line MIOT / B through the write bus through the transfer gate TG and the complementary local data line LIOT / B, and is written in the memory cells MC coupled to the bit lines BL.

[0021] The semiconductor device 100 may employ a plurality of external terminals, the external terminals including command and address (C / A) terminals coupled to command and address buses to receive commands and addresses, clock terminals for receiving clocks CK and / CK, data terminals DQ for providing data, and power terminals for receiving power potentials VDD, VSS, VDDQ, and VSSQ.

[0022] The clock terminals are supplied with external clocks CK and / CK, and the external clocks CK and / CK are provided to the input circuit 112. The external clocks can be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks can be used for the timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operations of the circuits included in the input / output circuit 122. For example, it is provided to the data receiver to time the reception of write data. In some embodiments, a data strobe signal (DQS) can be used to time the operations of the IO circuit 122.

[0023] Memory addresses can be provided to the C / A terminals. The memory addresses supplied to the C / A terminals are transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and the decoded column address YADD to the column decoder 110. The address decoder 104 can also supply a decoded bank address BADD, which can indicate the bank of the memory array 118 containing the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminals. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0024] Commands can be provided as internal command signals to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 can provide a row command signal for selecting word lines and a column command signal for selecting bit lines.

[0025] Device 100 can receive an access command as a read command. When a read command is received and the read command is timely supplied to the bank address, row address, and column address, read data is read from the memory cells corresponding to the row address and column address in the memory array 118. The read command is received by the command decoder 106, which provides an internal command to cause the read data from the memory array 118 to be supplied to the read portion of the ECC control circuit 120 along the read bus (RBus). The read command can also cause one or more parity bits associated with the read data to be supplied to the ECC control circuit 120 along the read bus. The ECC control circuit 120 can use the parity bits to determine whether the read data contains any errors, and if any errors are detected, it can correct them to generate corrected read data. The corrected read data is output from the data terminal DQ to the outside of the device 100 via the input / output circuit 122.

[0026] Device 100 can receive an access command as a write command. When a write command is received, and the write command is timely supplied with the bank address, row address, and column address, and write data is supplied to the ECC control circuit 120 through the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cells in the memory array 118 corresponding to the row address and column address. The write command is received by the command decoder 106, which provides an internal command to cause the write data to be received by the data receiver in the input / output circuit 122. A write clock can also be supplied to the external clock terminal to time-sequence the data receiver in the input / output circuit 122 to receive the write data. The write data is supplied to the ECC control circuit 120 via the input / output circuit 122. The write portion of the ECC control circuit 120 can generate a plurality of parity bits based on the write data, and can supply the write data and the parity bits to the memory array 118 along the write bus (WBus) to write them into the memory cells MC.

[0027] Device 100 may receive an access command that is a masked write command. A non-masked write command may expect to write a certain amount (e.g., a certain number of bits) of data to a memory array. When less than the amount of data is transmitted across the DQ terminals, a masked write command may be used. As part of a masked write operation, device 100 may receive a mask command, as well as a bank address, a row address, and a column address, and write data. Device 100 may also receive mask information (e.g., a mask signal DM), which may indicate which portions of the supplied address should not be written. As part of a masked write operation, device 100 may first read information (e.g., read data and read parity) from the row, column, and bank of memory array 118 specified by the respective row, column, and bank addresses. This information may be read out along a read bus to a read portion of ECC circuit 120. The write data may be loaded from the data terminals DQ into a write portion of ECC circuit 120 via IO circuit 122. ECC circuit 120 may generate modified write data by replacing certain bits of the read information with the write data from the DQ terminals as specified by the mask signal. ECC circuit 120 may generate modified parity information based on the modified write data, and may then provide the modified data and parity along a write bus to write them back to the row, column, and bank specified by the address.

[0028] Device 100 may operate based on a specification that may define certain timings for various operations. For example, access operations (reads, writes, and masked writes) may have a minimum timing tCCD. In other words, if an access command is received, then a time tCCD must elapse before device 100 may receive the next access command. The minimum command timing tCCD may be measured in terms of the period of the system clock CK (and / or an internal clock ICLK, as described herein). For example, the timing tCCD may be 8 clock cycles. In other example embodiments, longer or shorter tCCD durations (e.g., 4, 6, 10, or 12 clock cycles) may be used. The length of tCCD may be based on the time lengths of the respective components that occupy the read and write paths during read and / or write operations.

[0029] Since the mask write operation requires both reads and writes, the mask write may take a longer fraction of the read and write paths than tCCD. For example, the mask write may take 4*tCCD (e.g., 32 clock cycles) to execute. Since the ECC circuit 120 is shared among multiple banks, if a first bank receives a first mask write command at a first time and a second bank receives a second command at a second time, which is tCCD after the first time, there may be overlapping demands on various components of the ECC circuit 120 and / or other components of the read / write path. For example, one bank may be reading data out to the ECC circuit 120 along a bus while data is being sent back to another bank from the ECC circuit 120 along the bus.

[0030] Each ECC circuit 120 may include some components that are shared between the read path and the write path, and some components that are not shared. For example, each ECC circuit may include a logic tree, which may be a set of logic circuits coupled together to receive a first number of data bits and provide a second number of encoded bits, where the number of encoded bits is less than the number of data bits and the state of the encoded bits is based on the state of the data bits. There may be a write logic tree and a read logic tree such that an operation that requires both a read operation and a write operation (e.g., a write mask operation) does not become a bottleneck because both need to use the same logic tree. Similarly, separate read buses (RBus) and write buses (WBus) may be used to prevent bottlenecks. Thus, data may be read out to the read portion of the ECC circuit 120 along the read bus RBus while the write portion of the ECC circuit 120 provides write data along the write bus WBus.

[0031] The ECC control circuit 120 may receive a certain number of data bits (from the IO circuit 122 or the memory array 118), and may use a certain number of parity bits based on the number of data bits to correct potential errors in the data bits. For example, as part of a write operation, the ECC control circuit 120 may receive 128 bits of data from the IO circuit 122, and may generate 8 parity bits based on those 128 data bits. The 128 data bits and 8 parity bits (e.g., a total of 136 bits) may be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 may receive 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 may use the 8 parity bits to determine whether any errors exist in the 128 read data bits, and if any errors are found, it may correct them. For example, the ECC control circuit 120 may be able to locate and correct up to one error in the 128 data bits based on the 8 parity bits. In a masked write operation, the ECC control circuit 120 may receive 128 read bits and 8 parity bits from the memory array, replace a certain number of those bits with new data from the data terminal DQ, revise the parity bits, and write back the 128 write bits and 8 parity bits. Although various embodiments may be described with reference to an ECC circuit that uses 8 parity bits to detect one error in 128 data bits, it should be understood that these are for illustrative purposes only, and in other example embodiments, other numbers of data bits, error bits, and parity bits may be used.

[0032] The apparatus 100 may also receive a command that causes it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be issued to the memory device 100 from an external source. In some embodiments, the self-refresh mode command may be periodically generated by components of the device. In some embodiments, when an external signal indicates a self-refresh entry command, the refresh signal AREF may also be activated. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated once immediately after the command input, and may thereafter be periodically activated at a desired internal timing. The refresh signal AREF may be used to control the timing of the refresh operations during the self-refresh mode. Thus, the refresh operations may continue automatically. A self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state. The refresh signal AREF is supplied to the refresh control circuit 116. The refresh control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which may refresh one or more word lines WL indicated by the refresh row address RXADD.

[0033] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potentials VOD and VARY are mainly used in the sense amplifiers SAMP included in the memory array 118, and the internal potential VPERI is used in many peripheral circuit blocks.

[0034] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0035] Figure 2 A block diagram of the read and write paths of a memory according to some embodiments of the present disclosure. The memory 200 is, for example Figure 1 a view of a part of the memory device of the device 100. The memory 200 is a simplified view that shows various components related to the read and write paths from the data terminals DQ. For the sake of simplicity, other components are omitted.

[0036] The memory 200 includes a plurality of banks 202. Each bank 202 has a data amplifier (DA) 204 and a write buffer (WB) 206. In some embodiments, the data amplifier 204 may represent Figure 1 the sense amplifier (SAMP). Although a single data amplifier 204 and a write buffer 206 are shown for each bank 202 in the Figure 2 example, it should be understood that any number of data amplifiers 204 and / or write buffers 206 may exist for each bank, and the number of data amplifiers and write buffers in a given bank may be different from each other.

[0037] When a given memory bank and the rows and columns of the memory bank are activated, data can be read out along the bit lines to the data amplifier 204, which can then provide that data along the shared read bus RBus. Each memory bank 202 also includes a write buffer 206 that receives data from the write bus and then provides it to the memory cells at the intersection of the activated rows and columns. Each of the memory banks 202 can be commonly coupled to the read bus RBus and the write bus WBus. In some embodiments, there can be multiple read buses and write buses, with each read bus and write bus coupled to multiple memory banks (in which case, the components of Figure 2 can be repeated for each pair of buses).

[0038] The data terminals DQ can be used to send and receive data to and from the memory 200. The data terminals DQ can serially receive a large amount of data, and the IO circuit 208 can be used to convert between the serial data format of the DQ terminals and the parallel data of the memory device 200. For example, as part of a write operation, a given DQ terminal can serially receive 8 bits as part of a burst, and the deserialization circuit of the IO circuit 208 can convert it to 8 parallel bits, which can then be provided to the write ECC circuit 210. Similarly, as part of a read operation, the read ECC circuit 212 can provide 8 bits parallel to the serializer of the IO circuit 208, which can serially combine them into 8 bits along the DQ terminal. During a (non-masked) write operation or read operation, several data terminals can each have a burst of multiple bits (e.g., 16 terminals, 8-bit bursts for each terminal, for a total of 128 bits). During a masked write operation, a burst can be provided along fewer than all of the data terminals (e.g., an 8-bit burst along 2 terminals, for a total of 16 bits).

[0039] The memory 200 also includes a clock generator circuit 220 (e.g., Figure 1 114 of Figure 1 ), which receives an external clock signal CK (and / or a buffered internal clock signal such as ICLK of

[0040] Different local clock signals may have different timings. For example, each local clock signal may have a pulse after a specified number of cycles of the system clock CK. Local clocks LCLK with different timings may be provided to different components to control their timings relative to each other. Other local clock signals may be oscillating signals whose frequencies are based on the system clock. Other local clock signals LCLK may have timings independent of the system clock CK. Figure 3 Different clock signals and their use in mask write operations are described in more detail in

[0041] Using separate read and write paths, such as a read path that includes a read portion of a read bus Rbus and an ECC circuit 212 and a write path that includes a write portion of a write bus WBus and an ECC circuit 210, means that data can travel simultaneously along both the read path and the write path. For example, if commands are received at the fastest possible timing (e.g., a new command is received every tCCD clock cycle), then during a mask write operation, there may be a time when data associated with a first access command is read out along the read bus RBus while data associated with a second access command is written along the write bus WBus. Similarly, during a mask write command, both portions of the ECC circuits 210 and 212 can be used simultaneously to process the parity for the read data and the new write data.

[0042] Figure 3 A portion of a memory device used in a mask write operation according to some embodiments of the present disclosure. In some embodiments, the memory 300 may be included in the Figure 1 memory 100 and / or Figure 2 memory 200. In the Figure 3 memory 300, certain components have been omitted. Memory 300 shows an ECC circuit 302 shared among multiple banks of the memory, while Figure 3 other components of the memory 300 shown in

[0043] Memory 300 includes a set of components that operate based on multiple different clock domains as part of a mask write operation. In Figure 3In an example, four different clock domains are shown, a mask read clock domain 310, a read bus domain 320, a syndrome domain 330, and a write domain 340. Each domain may be associated with a different clock signal (e.g., a mask read clock, a read bus clock, a syndrome clock, and a write domain clock, respectively). Different clock domains may represent a set of components that have timing based on a particular clock signal and / or based on a signal derived from the clock signal.

[0044] Each of the timing domains 310, 320, 330, and 340 may be based on a different clock signal, which may be used to manage the operation of components within the timing domain such that masked write commands issued to different banks may operate in different parts of the memory 300. For example, components of the first timing domain 310 may be processing a masked write command issued to a first bank while, at the same time, components of the second timing domain 320 may be processing a masked write command issued to a second bank. In some embodiments, different timing domains may be used to sequentially process different commands issued to the same bank.

[0045] Each timing domain may receive an active clock signal, and the clock signals may be separated by less than the minimum timing between commands (e.g., tCCD or less). For example, if the time tCCD is approximately 8 clock cycles long, then components of the second timing domain 320 may be activated approximately 6 clock cycles after activating components of the first timing domain 310, components of the third timing domain 330 may be activated approximately 8 clock cycles after activating the second timing domain 320, and components of the fourth timing domain 340 may be activated approximately 7 clock cycles after activating the third timing domain 330. In other examples, different operating time lengths of the timing domains may be used. Since masked write operations as well as both read and write components require a relatively long time to execute, the number of timing domains may be selected based on the length of the masked write command as compared to the speed at which new commands may be received. For example, the memory 300 is arranged based on a masked write operation that executes in 4*tCCD or fewer clock cycles. Since each timing domain is activated within tCCD or less time, there are four timing domains 310, 320, 330, and 340. In other examples, more or fewer timing domains may be used.

[0046] In this way, a first masked write command may be issued to a first bank, and components of the first time domain 310 may begin processing it. Assuming the fastest possible operation, at a later time tCCD, a second access command is received, and components of the first time domain 310 may begin processing it. However, by then, the second time domain 320 has taken over processing of the first masked write command. Figures 4 to 5 The timing of the various operations is described in more detail.

[0047] Memory 300 includes a data sense amplifier (DSA) 312. The DSA 312 can be part of a masked read clock domain 310. The DSA 312 can be coupled to a main input / output line MIO, and the main input / output line MIO can couple the DSA to the active bit lines of the memory array. The DSA 312 can receive information bits along the MIO and latch them in response to a column activation signal CDAE. Timing for the column activation signal CDAE can be provided based on a masked read clock signal of the masked read domain 310. The DSA 312 can amplify or otherwise modify the bit signals received from the MIO.

[0048] The DSA 312 provides the amplified bits to a read bus time domain 320. A latch 322 stores the information provided by the DSA 312. The latch 322 is timed to a read bus enable signal LBusRdEnMRD. Timing for the read bus enable signal LBusRdEnMRD can be provided based on a read bus clock signal. The latch 322 can help transfer data from the masked read domain 310 to the read bus domain 320. The data stored in the latch 322 (along with data from other similar latches) is provided along a common read bus LBusRd as an input to a read syndrome tree 324. Thus, both the DSA 312 and the latch 322 can be close to their associated memory banks, while the syndrome tree 324 can be located in a shared area of the memory 300. The syndrome tree 324 can be part of a read portion of an ECC circuit 302.

[0049] The syndrome tree 324 can include a plurality of logic gates and can generate syndrome information based on the state of the read data received along the read bus. The syndrome information can be based on the state of one or more data bits read out along the read bus LBusRd. For example, 8 syndrome bits can be generated based on 128 data bits. Instance syndrome trees are described in more detail in Figures 6A to 6C which is described in more detail below.

[0050] The syndrome tree 324 can receive both the read data from the memory array and the read parity associated with the read data along the read bus LBusRd. The syndrome tree 324 can generate a parity check based on the read data and compare this parity check with the read parity (e.g., using XOR logic). Based on this comparison, the syndrome tree 324 can generate read syndrome information that can indicate whether (and where) there are any differences between the read parity and the parity check generated based on the read data. These differences can indicate a difference in the read data between when it was written and when it was read, and the syndrome information can be used to correct such differences.

[0051] The syndrome tree 324 provides the syndrome to the components of the syndrome field 330, and the latch 322 provides the read data to the syndrome field 330. Specifically, the latch 332 may receive syndrome information, and the latch 334 may receive data. The latches 332 and 334 may be clocked to the syndrome signal syn0CapMRD, which may be (or may be based on) the syndrome clock signal that governs the syndrome clock domain 330. The latch 332 provides the syndrome to the error burst check circuit 336. The error burst check 336 may review the syndrome information to determine if any errors exist in the syndrome information. The error burst check 336 may send information about any detected errors to the parity checker 345. For example, the error burst check circuit 336 may provide information that encodes the location of the error within the syndrome.

[0052] During a mask write operation, the error burst check circuit 336 may also receive the data mask signal DM. The data mask signal DM may indicate whether the detected error is associated with a masked (e.g., maintained) or unmasked (e.g., about to be overwritten by new write data from the DQ terminals) data bit. The error burst check circuit 336 may receive the DM signal and may use the DM signal to determine whether to mask any error bits. If the DM signal indicates that the detected error bit is unmasked, then the memory 300 may not take any action to correct the detected error (e.g., because the error will be "corrected" when the bit is overwritten). If the DM signal indicates that the detected error bit is masked, then the memory 300 may update the state of the parity check provided by the syndrome tree 344 (e.g., using the parity check edit circuit 345). In some embodiments, errors in the read data may be corrected before being written back to the memory array (e.g., by using a correction circuit between the multiplexer 342 and the latch 347). In some embodiments, errors in the read data may be written back to the memory array as is. The error burst check circuit 336 may provide a signal indicating whether a given bit should be corrected based on the syndrome information and the DM signal.

[0053] The write data from the data terminals DQ and the data read from the memory array (e.g., stored in the latch 334) are provided as inputs to the multiplexer 342. The multiplexer 342 may have a selector terminal coupled to the data mask signal DM. The data mask signal DM may indicate which bits of the read data should be replaced by the new write data from the DQ terminals and which read data should be written back to the memory array. Thus, the multiplexer 342 may generate corrected data by replacing certain read bits with the write data from the DQ terminals. The syndrome may be operated in timing based on the write domain 340.

[0054] The multiplexer 342 provides the corrected data to the syndrome tree 344. In some embodiments, the syndrome tree 344 may be similar to the syndrome tree 324. In some embodiments, the two syndrome trees 324 and 344 may have the same logic, except that the syndrome tree 342 may have additional XOR logic that compares the read parity with the generated parity, while the syndrome tree 344 generates the parity but does not compare it. The syndrome tree 344 provides parity information based on the corrected write data. The parity information is provided to the parity edit circuit 345, which uses the syndrome error information from the error burst check circuit 336 to edit the syndrome provided by the syndrome tree 344. The parity edit circuit 345 may correct errors in the syndrome provided by the syndrome tree 344. The parity edit circuit 345 may provide the parity to the latch 346. The latch 347 may receive the corrected data from the multiplexer 342.

[0055] The parity edit circuit 345 may include an XOR logic gate having an input coupled to the read syndrome information (e.g., from the syndrome tree 324), and an input coupled to the write parity provided by the syndrome tree 344. The XOR gate provides a signal indicating whether the read syndrome is different from the write parity. The output of the XOR gate is coupled to a multiplexer having another input terminal coupled to the write parity from the syndrome tree 344. The multiplexer has a select terminal coupled to a signal from the error burst check circuit 336 indicating whether the write parity needs to be edited. If the write parity does not need to be edited, then the write parity is passed as the parity through the multiplexer. If the write parity needs to be edited, then the output of the XOR gate is used as the output of the multiplexer as the parity.

[0056] The latches 346 and 347 may be coupled to the write column select signal CDTSW, which may be part of the write domain 340. The latch 347 may store the corrected write data (e.g., a mixture of read data from the DQ terminals and new data), while the latch 346 stores the corrected parity associated with the corrected write data. The latches 346 and 347 provide the corrected data and parity along the write bus LBusWr to a bank-associated circuit such as the latch 348. The latch 348 may store the corrected write data and parity information until it is time to write it to the memory array.

[0057] The latch 348 provides the corrected write data and syndrome data to the write driver 349 (e.g., Figure 2 206), which writes the information to the memory cells of the memory array along the MIO bus.

[0058] In addition to the components described as part of the masked write operation in Figure 3 , the memory 300 may also include components used in read operations, such as decoder 352 and correction circuit 354. These circuits are shown disconnected from the other components because they are not used as part of the masked write operation. However, it should be understood that additional couplers and selectors (e.g., multiplexers and switches) may be used to couple decoder 352 and correction circuit 354 to various other components during read operations.

[0059] During a read operation, read data and parity may be read out to latch 322 via DSA 312. The read data may be provided along a read bus and used as an input to syndrome tree 324 and may also be transmitted to correction circuit 354. Syndrome tree 324 may generate syndrome information based on the read data, and the syndrome information may be provided to decoder circuit 352. Decoder circuit 352 may decode the syndrome information into a signal indicating which bits are in error. Correction circuit 354 may change one or more bits of the decoded signal from decoder circuit 352 based on the read data. The corrected read data may then be provided to data terminal DQ for reading from memory 300.

[0060] During (non-masked) write operations, the components of write domain 340 may be used in a manner generally similar to that described previously, except that multiplexer 342 and parity edit circuit 345 may not be used. Alternatively, syndrome tree 344 may generate syndrome information, which may be encoded as parity information. The parity information and data from the DQ terminals may then be passed along a write bus and written to the memory cells of the memory array.

[0061] Figure 4 FIG. 400 is a timing diagram of operations in a memory device according to some embodiments of the present disclosure. In some embodiments, timing diagram 400 may represent the operation of a memory, such as Figure 1 memory 100 and / or Figure 2 memory 200. Timing diagram 400 represents operations within a single bank (e.g., Figure 2 bank 202 of

[0062] The horizontal axis of timing diagram 300 shows time represented by the number of cycles of system clock CK. The vertical axis represents different functional components of the memory, where the boxes indicate that the functional components are performing the labeled tasks within the specified time length. When an internal masked write (MWR) command is issued, the origin of the horizontal axis is set at the first time t1. The internal masked write command can be issued in response to a masked write command received by the memory (e.g., from the controller). Thus, the command at the initial time t0 at -32 on the horizontal axis can indicate that the initial time t0 is 32 clock cycles before the first time t1. It should be understood that Figure 4 the timing shown is for illustrative purposes only, and other timings can be used for other operations.

[0063] Prior to the initial time t0, the memory receives a write command WR along the C / A terminals. At time t0, the memory issues an internal write command WR. Approximately at the same time, the memory starts receiving write data along the DQ terminals. After the data is received (e.g., for 8 clock cycles, one for each of the 8 serial bits), the data bus inversion (DBI) circuit of the I / O circuit can start deserializing the data, which can then be provided along a channel by the I / O circuit. The channel can couple the I / O circuit to the write ECC circuit.

[0064] After the data is provided along the channel (e.g., at approximately time -16), the write portion (ECC-W) of the ECC circuit can process the write data. For example, a write syndrome tree (e.g., Figure 3 344) can generate a syndrome that can be encoded as a parity. Then the write data and the generated parity can be provided to the memory bank along the write bus (LBusWr). The process of generating the parity along the write bus and providing the data and parity can take approximately 10 clock cycles (e.g., from approximately -16 to approximately -6).

[0065] In the memory bank (e.g., the memory bank activated by the memory bank address), the write data and parity can be loaded along the input / output buses of the memory array (e.g., main input / output MIO and local input / output LIO). As the data is loaded along the main bus and the local bus, the data can start being provided along the various columns of the memory. The columns can be specified by the column select signal CS. The data bits and parity bits can be written to the memory cells at the intersection of the activated column and the activated row.

[0066] As can be seen from timing diagram 400, during a (non-masked) write operation, the longest of any component used in the write path is approximately 8 clock cycles. This represents the timing tCCD. Different timings can be used in other example embodiments of the memory.

[0067] At the first time t1 or before, the memory may receive a Mask Write (MWR) command at the C / A terminal. At the first time t1, the memory may issue an internal MWR command. Along with the mask write command (e.g., at the C / A terminal of the memory), the memory may also start receiving write data at the DQ terminal. This is generally similar to a write operation starting at t0. Except when receiving data at the DQ terminal, soon after receiving the MWR command, the memory may start reading data from the memory array. The above situation may involve activating the column select CS signal of the memory to activate one or more columns, so as to read data from the memory cells (at the intersection with the active row) along the columns. Reading data from the memory array (e.g., by activating the CS signal) may overlap with the write data incoming along the DQ terminal.

[0068] At about 8 clock cycles after time t1, data reception may stop and it may move to the Data Bus Inversion DBI circuit. At about the same time, the read data may start being transferred along the memory's Local Input / Output bus LIO to the Data Sense Amplifier DSA. The use of LIO and DSA may overlap with the column select signal still being active.

[0069] At about 12 clock cycles after time t1, the write data may be transferred from the DBI to the channel. At about the same time, the read data may be transferred from the Data Sense Amplifier DSA to the Read bus LBusRd. This may move the read data (and associated read parity) to a memory area containing shared components (such as the ECC circuit).

[0070] At about 16 clock cycles after time t1, both the write part and the read part of the ECC circuit may become active. The read part and the write part may both be active simultaneously because the read part and the write part contain separate syndrome trees (e.g., 324 and 344 respectively for Figure 3 . The read part of the ECC circuit may generate and check parity based on the read data. The write part of the ECC circuit may synthesize the new write data from the DQ circuit and the read data together to generate corrected write data, and then may generate write parity based on the corrected data. The parity based on the read data may be used to correct any errors present in the write parity to generate corrected parity.

[0071] Approximately 20 clock cycles after time t1, the corrected write data and the corrected parity are provided along the write bus LBusWr to the bank specified by the bank address provided together with the masked write command MWR. Approximately 26 clock cycles after time t1, the corrected write data and the parity may be in the bank and may be provided along the main I / O bus MIO and the local I / O bus LIO. The column select signal CS may be activated as part of the write operation to provide the bits of the corrected write data and the parity data along a single bit line (column) such that those bits may be written to the memory cells at the intersection of those bit lines and the activated row.

[0072] Figure 5 Is a timing diagram for operations in multiple banks according to some embodiments of the present disclosure. Figure 5 The timing diagram 500 may be similar to Figure 4 The timing diagram 400, except that the commands and operations associated with multiple banks are shown in the timing diagram 500 (as opposed to Figure 4 A single bank). For the sake of brevity, features similar to those described with respect to Figure 5 Will not be described again. For clarity, certain operations of the MIO / LIO lines have been omitted as these are bank specific and the operations in different banks may overlap. Figure 4 In the timing diagram 500, different shadings are used to indicate that certain different operations are associated with commands issued to different banks. It should be understood that some components (e.g., the MIO bus and the LIO bus, columns) are bank specific and different shadings represent different components, while other components (e.g., the ECC circuit, the write and read buses) are shared between banks and the shading indicates that the shared component is performing a task associated with data from the specified bank. Similar to

[0073] The commands, Figure 4 The commands may represent internal commands issued by the memory (e.g., from Figure 5 The command decoder 106) in response to an external command provided to the memory (e.g., by the controller). Figure 1 The command decoder 106) in response to an external command provided to the memory (e.g., by the controller).

[0074] At an initial time t0, a write command is issued to the first bank. The memory may process the write command in a manner similar to the write command described starting at t0 in Figure 4 At a first time t1, a write command for the second bank is received. The first time t1 may be separated from the initial time t0 by the minimum specified time between commands tCCD. At Figure 5In the example, the time tCCD is 8 clock cycles, and thus when the time t0 is -40 clock cycles (starting from 0 time at the fifth time t5), the time t1 is at approximately -32 clock cycles. As can be seen, from time t0 to t1, data associated with the write operation to the first memory bank is provided along the DQ terminal. However, at time t1, the DQ terminal starts to receive data associated with the write operation to the second memory bank. At the same time, at t1, the data associated with the write operation to the first memory bank is on the DBI (and then on the channel). In this way, the memory can process commands associated with multiple memory banks simultaneously because there is no need for one component to process the information associated with two access commands.

[0075] At time t2 (which is tCCD after t1), a third write command is received for the third memory bank. At time t3 (which is tCCD after t2), a fourth write command is received for the fourth memory bank. At time t4, the first memory bank receives a masked write command. At time t4, the DQ terminal is receiving write data associated with the masked write command, the DBI and the channel are processing data associated with the write command for the fourth memory bank, the (write part of the) ECC circuit is processing data for the third memory bank, the write bus is finishing processing data for the second memory bank, and the first memory bank is still finishing writing the write data from the write command along the column at t0. Although there is some overlap between the new masked write command issued at t4 and the original write command issued at t0, there is also a delay between when the first memory bank receives the masked write command (at t4) and when it starts accessing the column of the first memory bank (e.g., approximately 4 clock cycles after t4). Since the column select signal associated with the write command at t0 ends approximately 2 clock cycles after t4, the two operations do not overlap in the column select signal. Note that the column select signal for the masked read operation associated with the masked write command received at t4 can overlap with the column select signal that is active in other memory banks (e.g., the second memory bank as shown), because the memory banks are independent components of each other.

[0076] At a fifth time t5, the second memory bank receives a masked write command. At a sixth time t6, the second memory bank receives an (unmasked) write command. Using separate read and write buses and separate read and write portions of the ECC circuitry may allow a masked write command to be received at tCCD timing, although the masked write command takes 4*tCCD to complete and requires both a read component and a write component. For example, shortly after time t6, the write bus is occupied with data and parity bits associated with the masked write command issued to the first memory bank at t4, while simultaneously the read bus is occupied with read data associated with the masked write command issued to the second memory bank at t5. Similarly, even though the second memory bank receives a masked write command at time t5, it also receives an (unmasked) write command at t6, which is tCCD (e.g., 8 clock cycles) after t5.

[0077] Figures 6A to 6C FIG. is a schematic diagram of a logic tree according to some embodiments of the present disclosure. Figure 6A Illustrates diagram 600, which depicts a particular arrangement of logic for generating coded bits. Figure 6B and 6C Illustrates portions 601 and 610 of the logic tree that can be used to implement all or part of diagram 600. In some embodiments, portions 601 and 610 may be included in Figure 3 syndrome subtree 324 and / or syndrome subtree 344 of. It should be understood that other logic arrangements and logic trees may be used in other example embodiments.

[0078] Logic diagram 600 and circuits 601 and 610 may represent a portion of a logic tree that is used as part of an access operation, such as a read operation, a write operation, and / or a masked write operation, to generate parity information. Diagram 600 shows data bits arranged in columns along the left side. Each of the rows represents one of the data bits provided as an input to the syndrome subtree. In Figures 6A to 6C , the syndrome subtree is labeled as a write syndrome subtree (e.g., Figure 3 344 of), and the input bits are labeled as write data WD, although it should be understood that read data may also be used as an input when the syndrome subtree is a read syndrome subtree (e.g., Figure 3 324 of). Similarly, when the output of the syndrome subtree is labeled as write parity WP', a read parity may also be generated as an output if the syndrome subtree is a read syndrome subtree. A read syndrome subtree (e.g., Figure 3 324 of) may include additional logic gates and / or a set of logic gates, such as XOR gates, that compare the read parity with the generated parity based on the read data.

[0079] The write bit WD is arranged to correspond to the data terminal DQ and the bits received as a burst on the data terminal. In Figures 6A to 6C the illustrated embodiment, there may be eight data terminals, and each of the data terminals may receive a burst of eight bits. In other embodiments, other numbers of terminals and bits are also possible. The columns of the diagram 600SH0 to SH7 show different syndromes that can be used to encode data bits to generate parity bits. The columns are arranged into a first determinant H1 associated with the logic circuit 601, and the columns arranged in the second determinant H2 are associated with the logic circuit 610.

[0080] The logic circuit 601 includes a first block 602 and a second block 603 of logic circuits. Blocks 602 and 603 receive the write data bits WD indicated by "1" in the first column SHO of the diagram 600. The write data bits are grouped in units of six (e.g., WD1, WD3, WD5, and WD7) and provided to the four input terminals of an "exclusive OR" (XOR) gate. The XOR gate provides an output based on the four inputs. Four such XOR gates (e.g., coupled to 16 WD bits) each provide an output to an XOR gate in a third block 604. The second block 603 is similar to the first block 602 and has four XOR gates coupled to 16 write data WD bits and provides four outputs to the inputs of an XOR gate in the third block 604. The third block 604 includes two four-input XOR gates respectively coupled to the four outputs of the first block 602 and the four outputs of the second block 603. These two XOR gates in turn provide outputs that are XORed together to produce the connected write parity bit WP'0 corresponding to the column SH0 of the diagram 600. Logic similar to the circuit 601 can be used to generate the parity bits WP'1 and WP'2 for the next two columns SH1 and SH2 of the diagram 600.

[0081] The circuit 610 shows an example logic circuit that can be used to generate the parity bits WP'3 to WP'7 associated with the columns SH3 to SH7 of the diagram 600. In the circuit 601, a set number of inputs (e.g., 32 bits) are active (e.g., marked with 1) in each column of the diagram 600. However, in the circuit 610, there may be different numbers of inputs in different columns. The circuit 610 includes a first block 611 that includes a plurality of XOR gates, as indicated by the diagram 600, and the XOR gates are coupled to different input bits WD. The outputs of the XOR gates in the first block 611 are provided as inputs to the XOR gates 612 in turn. Each of the XOR gates 612 provides one of the write parity bits WP'.

[0082] Figure 7 A flowchart depicting a method according to some embodiments of the present disclosure. The method 700 may represent the use of, such asFigures 1 - 6C A method for performing a masked write operation by components and timings described in one or more of

[0083] Method 700 starts at block 710, which describes reading read data from a memory array of a memory along a read bus in response to a masked write command. The memory may receive the masked write command at a command / address terminal (C / A), as well as bank, row, and column addresses indicating which memory cells should be read. The memory may also receive a data mask signal DM, which may indicate which of the read bits should be overwritten with new data to generate corrected data, and the corrected data is written back to the memory cells indicated by the bank, row, and column addresses. The data may be read out along data sense amplifiers and then provided along the read bus. The read bus may couple the memory array to an ECC circuit.

[0084] Block 710 may generally be followed by block 720, which describes generating read syndrome information based on the read data using a read syndrome tree. The read syndrome tree may be part of a read portion of the ECC circuit. The read syndrome information may be checked (e.g., by an error burst checking circuit) to determine if there are any errors in the read parity information.

[0085] Block 720 may generally be followed by block 730, which describes receiving write data along a data terminal of the memory. The write data may represent fewer bits compared to the bits provided as part of a (non-masked) write operation. The write data may be provided as a burst in serial format and then deserialized into parallel format.

[0086] Block 730 may generally be followed by block 740, which describes generating corrected write data based on the write data and the read data. A multiplexer in a write portion of the ECC circuit may be used to combine the write data and the read data to generate the corrected write data. For example, the data mask signal DM may indicate which bits of the read data should be replaced by the write data.

[0087] Block 740 may generally be followed by block 750, which describes generating corrected syndrome information based on the corrected write data and the read syndrome information using a write syndrome tree. The ECC circuit may include the read syndrome tree as part of a read portion of the ECC circuit. The read syndrome tree may generate parity information based on the corrected write data, and the corrected write data may be edited based on the detected errors in the read parity information to generate corrected syndrome information.

[0088] The frame 750 may typically be followed by a frame 760 that describes writing the corrected write data and the corrected syndrome information to the memory array along a write bus of the memory. The corrected write data may be provided back to the memory array along the write bus and written to the bank, row, and column indicated by the bank row and column addresses.

[0089] Of course, it should be understood that any one of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or performed in separate devices or device parts according to the present system, apparatus, and method.

[0090] Finally, the foregoing discussion is intended to be illustrative only of the present system and should not be construed as limiting the appended claims to any particular embodiment or set of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that those of ordinary skill in the art may devise many modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative manner and not to limit the scope of the appended claims.

Claims

1. An apparatus, comprising: A memory bank; Data terminals; A write bus; A read bus; A write portion of an error correction code circuit, configured to receive write data from the data terminals, generate parity bits based on the write data, and provide the write data and parity data to the memory bank along the write bus; And A read portion of the error correction code circuit, configured to receive read data and read parity along the read bus from the memory bank, and generate read syndrome information based on the read data and the read parity, Wherein the write portion of the error correction code circuit includes a write logic tree and the read portion of the error correction code circuit includes a read logic tree.

2. The apparatus according to claim 1, further comprising a second memory bank, wherein the write bus is commonly coupled to the memory bank and the second memory bank, and wherein the read bus is commonly coupled to the memory bank and the second memory bank.

3. The apparatus according to claim 1, wherein the read portion of the error correction code circuit includes a correction circuit, the correction circuit being configured to generate corrected read data based on the read data, the read parity, and the read syndrome information as part of a read operation.

4. An apparatus, comprising: A memory bank; Data terminals; A write bus; A read bus; A write portion of an error correction code circuit, configured to receive write data from the data terminals, generate parity bits based on the write data, and provide the write data and parity data to the memory bank along the write bus; And A read portion of the error correction code circuit, configured to receive read data and read parity along the read bus from the memory bank, and generate read syndrome information based on the read data and the read parity, wherein the write portion of the error correction code circuit operates in a timing based on a first clock signal, and the read portion of the error correction code circuit operates in a timing based on a second clock signal.

5. An apparatus, comprising: A memory bank; Data terminals; A write bus; A read bus; A write portion of an error correction code circuit, configured to receive write data from the data terminals, generate parity bits based on the write data, and provide the write data and parity data to the memory bank along the write bus; And A read portion of the error correction code circuit, configured to receive read data and read parity along the read bus from the memory bank, and generate read syndrome information based on the read data and the read parity, wherein the read portion of the error correction code circuit includes an error burst check circuit, the error burst check circuit being configured to check whether there is an error in the read syndrome information, and wherein the write portion of the error correction code circuit includes a parity edit circuit, the parity edit circuit being configured to correct an error based on parity bits in the read syndrome information as part of a masked write operation.

6. An apparatus, comprising: A memory bank; Data terminals; A write bus; Read bus; A write portion of an error correction code circuit configured to receive write data from the data terminals, generate parity bits based on the write data, and provide the write data and parity data to the memory bank along the write bus; And A read portion of the error correction code circuit configured to receive read data and read parity from the memory bank along the read bus and generate read syndrome information based on the read data and the read parity, wherein the write portion of the error correction code circuit includes a multiplexer configured to generate corrected write information based on the read data and the write data as part of a masked write operation and provide the corrected write information to the memory array along the write bus.

7. An apparatus comprising: A read syndrome tree configured to receive read data along a read bus and provide syndrome information based on the read data; A latch configured to store the read data from the read bus; A multiplexer configured to receive the read data from the latch and write data from a data terminal and provide corrected write data along a write bus based on the read data and the write data; And A write syndrome tree configured to receive the corrected write data and generate write parity based on the corrected write data, wherein the read syndrome tree operates in a timing based on a first clock signal, the latch operates in a timing based on a second clock signal, and the multiplexer and the write syndrome tree operate in a timing based on a third clock signal.

8. The apparatus according to claim 7, further comprising a data sense amplifier configured to receive the read data from the memory array and provide the read data along the read bus, wherein the data sense amplifier operates in a timing based on a fourth clock signal.

9. The apparatus according to claim 7, further comprising an error burst check circuit configured to provide error information based on the syndrome information, wherein the error burst check circuit operates in a timing based on the second clock signal.

10. The apparatus according to claim 9, further comprising a parity edit circuit configured to provide corrected write parity based on the write parity and the error information, wherein the parity edit circuit operates in a timing based on the third clock signal.

11. The apparatus according to claim 7, further comprising a memory array coupled to the read syndrome tree along the read bus and coupled to the write syndrome tree along the write bus.

12. The apparatus according to claim 11, wherein the corrected write data is written to the memory array as part of a masked write operation.

13. The apparatus according to claim 12, further comprising a write driver configured to write the corrected write data and the write parity to the memory array in a timing based on the third clock signal.

14. A method, comprising: In response to a mask write command, reading read data from a memory array of a memory along a read bus; Generating read syndrome information based on the read data by using a read syndrome tree; Receiving write data along a data terminal of the memory; Generating corrected write data based on the write data and the read data; Generating corrected syndrome information based on the corrected write data and the read syndrome information by using a write syndrome tree; And Writing the corrected write data and the corrected syndrome information to the memory array along a write bus of the memory.

15. The method according to claim 14, further comprising checking, by an error burst checking circuit, whether there is an error in the read syndrome information.

16. The method according to claim 14, further comprising generating the read syndrome information while generating the corrected syndrome information.

17. The method according to claim 14, further comprising reading read data associated with a first command along the read bus while writing the corrected write data associated with a second command along the write bus.

18. The method according to claim 14, further comprising generating the read syndrome information in a timing based on a first clock domain, and generating the corrected syndrome information in a timing based on a second clock domain.

19. The method according to claim 18, further comprising reading the read data in a timing based on a third clock domain.

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