Transistor Structure and Related Manufacturing Method

Abstract

The present invention discloses a transistor structure and a related manufacturing method. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is located beside the first conductive region. The length of the first conductive region is controlled by a single lithography process, and the single lithography process is originally used to define the length of the gate structure. Therefore, compared with the prior art, the present invention can accurately control the lengths of the source / drain and contact openings of the transistor structure to effectively reduce the transistor structure.

Description

Technical Field

[0001] The present invention relates to a transistor structure and a related manufacturing method, and particularly to a transistor structure and a related manufacturing method having a source / drain and a contact opening with accurately controllable lengths to effectively reduce the size. Background Art

[0002] In 1974, R. Dennard et al. published a paper that disclosed the design criteria for reducing all dimensions of a metal-oxide-semiconductor field-effect transistor (MOSFET). Therefore, how to reduce the size of a transistor has become a major technical requirement, and the major technical requirement has changed the minimum feature size of the linear dimension of a silicon wafer from several micrometers (μm) to several nanometers (nm). The minimum feature size or length is usually referred to as Lamda (λ), which depends on the miniaturization ability of photolithographic masking technology and component reduction technology (for the sake of simplicity of description and comparison, what is measured by minimizing the printed line width resolution is also referred to as λ). However, another uncontrollable factor that limits component reduction is the misalignment tolerance caused by the inadequacy and inaccuracy of photolithography equipment, that is, Delta-Lamda (Δλ). In addition, due to the misalignment tolerance, it is very difficult to make the distance between the gate edge and the source (or drain) edge of the transistor less than the sum of λ and Δλ. After that, if it is necessary to manufacture a square contact hole on the drain (or source) again by using the photolithographic masking technology for the future connection between the metal interconnection and the drain (or the source), it is very difficult to make the minimum size of each side of the contact hole less than λ. In addition, to ensure that the contact hole within the drain includes the misalignment tolerance, it is very difficult to make the length of each side of the drain (with a rectangular periphery) less than the sum of λ and Δλ. However, reducing the size of a transistor is necessary for integrating more transistors within a planar area of a silicon wafer, and separately reducing the areas occupied by the drain and source of the transistor is a necessary and effective way to achieve the above goal, which also helps to reduce leakage current and power consumption.

[0003] Therefore, how to effectively reduce the size of a transistor to integrate more transistors within the planar area of the silicon wafer has become an important problem to be solved by the designers of the transistor. Summary of the Invention

[0004] An embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure and a dummy shield gate structure above the active region; forming a first isolation region to replace the dummy shield gate structure; forming a self-alignment pillar above the active region; and removing the self-alignment pillar and forming the first conductive region between the gate structure and the first isolation region.

[0005] In another embodiment of the present invention, before the step of removing the self-alignment pillar, the manufacturing method further includes forming a second isolation region above the first isolation region, wherein the self-alignment pillar is located between the gate structure and the second isolation region.

[0006] In another embodiment of the present invention, after the step of removing the self-alignment pillar, the manufacturing method further includes forming a spacer layer between the gate structure and the first isolation region to define a contact hole, wherein the contact hole is located above the first conductive region.

[0007] In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

[0008] In another embodiment of the present invention, the substrate is a silicon substrate, and the self-alignment pillar is an intrinsic silicon pillar formed by selective epitaxy growth.

[0009] Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure on the active region; and forming a self-alignment pillar, wherein the self-alignment pillar is used to allocate a contact hole above the first conductive region.

[0010] In another embodiment of the present invention, the manufacturing method further includes forming an isolation region on the active region before forming the self-alignment pillar.

[0011] In another embodiment of the present invention, the manufacturing method further includes removing the self-alignment pillar, wherein the self-alignment pillar is formed between the gate structure and the isolation region; and forming a spacer layer between the gate structure and the isolation region to define a contact hole, wherein the contact hole is located above the first conductive region.

[0012] In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

[0013] Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure above the active region; forming the first conductive region beside the gate structure; and defining a contact hole above the first conductive region, wherein defining the contact hole is independent of a photolithography process.

[0014] In another embodiment of the present invention, the first conductive region is formed between the gate structure and an isolation region, wherein the isolation region extends upward above the active region.

[0015] In another embodiment of the present invention, the contact hole is defined by forming a spacer layer, wherein the spacer layer covers a sidewall of the gate structure and a sidewall of the isolation region.

[0016] In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

[0017] Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes performing a first photolithography process, wherein the first photolithography process is used to define the width of the gate structure and the length of an active region; performing a second photolithography process, wherein the second photolithography process is used to define the length of the gate structure within the active region, and wherein the second photolithography process is further used to define the length of the first conductive region.

[0018] In another embodiment of the present invention, the length of the first conductive region defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

[0019] In another embodiment of the present invention, the length of the gate structure defined by the second photolithography process is equal to or substantially equal to a minimum feature length.

[0020] In another embodiment of the present invention, the length of the active region defined by the first photolithography process is approximately equal to 4 times a minimum feature length.

[0021] Another embodiment of the present invention discloses a method for manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region. The manufacturing method includes forming an active region on a substrate; forming the gate structure on the active region; forming the first conductive region beside the gate structure; and forming a contact hole above the first conductive region, wherein the shape of the contact hole does not need to be defined by a lithography process.

[0022] In another embodiment of the present invention, the first conductive region is formed between the gate structure and an isolation region.

[0023] In another embodiment of the present invention, the contact hole is defined by forming a spacer layer, wherein the spacer layer covers a sidewall of the gate structure and a sidewall of the isolation region.

[0024] In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

[0025] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The contact hole is located above the first conductive region. Wherein the periphery of the contact hole is surrounded by the periphery of the first conductive region.

[0026] In another embodiment of the present invention, the periphery of the first conductive region is a rectangle.

[0027] In another embodiment of the present invention, the length of the contact hole is less than a minimum feature length.

[0028] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a contact hole. The semiconductor substrate has a semiconductor surface. The channel region is located below the gate structure. The contact hole is located above the first conductive region. Wherein the length of the contact hole is less than a minimum feature length.

[0029] In another embodiment of the present invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the contact hole is less than the minimum feature length, wherein the sidewall of the contact hole is away from the sidewall of the gate structure.

[0030] In another embodiment of the present invention, a horizontal distance between a sidewall of the gate structure and a sidewall of the first conductive region is approximately equal to the minimum feature length, wherein the sidewall of the first conductive region is away from the sidewall of the gate structure.

[0031] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first isolation region, a first spacer layer, a second spacer layer, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The channel region is located below the semiconductor surface. The first isolation region extends upward and downward from the semiconductor surface. The first spacer layer covers a first sidewall of the gate structure, and the second spacer layer covers a sidewall of the first isolation region. The first conductive region is electrically coupled to the channel region and is located between the gate structure and the first isolation region. The first contact hole is formed between the first spacer layer and the second spacer layer.

[0032] In another embodiment of the present invention, the transistor structure further includes a covering layer and a first metal region. The covering layer covers the gate structure. The first metal region fills the first contact hole and contacts the first conductive region. The first metal region extends upward from the first conductive region to a predetermined position, wherein the predetermined position is higher than the top of the covering layer.

[0033] In another embodiment of the present invention, the width of the first metal region is substantially equal to the length of the first contact hole plus a minimum feature length.

[0034] In another embodiment of the present invention, the transistor structure further includes a second isolation region and a second conductive region. The second isolation region extends upward and downward from the semiconductor surface. The second conductive region is electrically coupled to the channel region and is located between the gate structure and the second isolation region.

[0035] In another embodiment of the present invention, a horizontal distance between a second sidewall of the gate structure and a sidewall of the second isolation region is substantially equal to a minimum feature length, wherein the sidewall of the first isolation region is away from the sidewall of the gate structure.

[0036] In another embodiment of the present invention, the transistor structure further includes a second contact hole. The second contact hole is located above the second conductive region, wherein the length of the second contact hole is less than a minimum feature length.

[0037] In another embodiment of the present invention, the transistor structure further includes a third spacer layer and a fourth spacer layer. The third spacer layer covers a second sidewall of the gate structure. The fourth spacer layer covers a sidewall of the second isolation region, wherein the second contact hole is formed between the third spacer layer and the fourth spacer layer.

[0038] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first isolation region. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. The first isolation region is located beside the first conductive region. Wherein the length of the first conductive region is controlled by a single lithography process, and the single lithography process was originally used to define the length of the gate structure.

[0039] In another embodiment of the present invention, the length of the first conductive region is equal to or substantially equal to a minimum feature length.

[0040] Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a semiconductor substrate, a gate structure, a channel region, a first conductive region, and a first contact hole. The semiconductor substrate has a semiconductor surface. The gate structure has a length. The first conductive region is electrically coupled to the channel region. Wherein the periphery of the first contact hole is independent of a lithography process.

[0041] In another embodiment of the present invention, the length of the first contact hole is less than a minimum feature length.

[0042] In another embodiment of the present invention, the length of the first conductive region is equal to or substantially equal to the minimum feature length.

[0043] In another embodiment of the present invention, the first contact hole is located above the first conductive region. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a top view of a miniaturized metal oxide semiconductor field effect transistor disclosed in an embodiment of the present invention.

[0045] Figure 2A is a flowchart of a manufacturing method of a miniaturized metal oxide semiconductor field effect transistor disclosed in another embodiment of the present invention.

[0046] Figures 2B - 2F is to illustrate Figure 2A of the

[0047] Figure 3It is a top view showing the pad nitride layer and the shallow trench isolation - first oxide layer.

[0048] Figure 4 is Figure 3 a cross-sectional view along the X-axis direction in

[0049] Figure 5 a schematic diagram showing the photolithographic misalignment tolerance (PMT) of the alignment between the edge of the gate structure of a metal oxide semiconductor field effect transistor and the boundary edge between the source and the shallow trench isolation - first oxide layer.

[0050] Figure 6 a schematic diagram showing a new structure that can eliminate the negative impact caused by the photolithographic misalignment tolerance.

[0051] Figure 7 a schematic diagram showing the deposition of a spin-on dielectric layer.

[0052] Figure 8 a schematic diagram showing the deposition and etching of a well-designed gate photomask layer.

[0053] Figure 9 a schematic diagram showing the removal of a dummy shield gate, a nitride layer, a dielectric insulator, and the substrate corresponding to the dummy shield gate by an anisotropic etching technique.

[0054] Figure 10 a schematic diagram showing the removal of the gate photomask layer, the etching of the spin-on dielectric layer, the deposition of a second oxide layer, and the etch-back of the second oxide layer to form a shallow trench isolation - second oxide layer.

[0055] Figures 11 - 14 a schematic diagram showing the relationship between the position of the true gate and the position of the dummy shield gate.

[0056] Figure 15 a schematic diagram showing the deposition and etching of a third oxide layer to form a third oxide spacer layer, the formation of a lightly doped drain in the substrate, the deposition and etch-back of a nitride layer to form a nitride spacer layer, and the removal of the dielectric insulator.

[0057] Figure 16 a schematic diagram showing the growth of intrinsic silicon using selective epitaxial growth technology.

[0058] Figure 17 a schematic diagram showing the deposition and etch-back of a chemical vapor deposition - shallow trench isolation - third oxide layer, the removal of intrinsic silicon, and the formation of the source and drain of a metal oxide semiconductor field effect transistor.

[0059] Figure 18It is a schematic diagram showing the deposition and etching of an oxide spacer layer to form a contact hole opening.

[0060] Figure 19 It is a schematic diagram showing the deposition and etch-back of a first metal layer to form a first metal layer interconnect.

[0061] Figure 20 It is a schematic diagram of forming source and drain using a merged semiconductor junction and metal conductor structure, and forming a first metal layer interconnect, which is disclosed in another embodiment of the present invention.

[0062] Figure 21 It is a schematic diagram showing the removal of a gate photomask layer, depositing a second oxide layer to fill trenches and other voids on a horizontal silicon surface to form the shallow trench isolation - second oxide layer, and then planarizing the shallow trench isolation - second oxide layer by chemical mechanical polishing technology.

[0063] Figure 22 It is a schematic diagram showing the deposition and etching of a third oxide layer to form a third oxide spacer layer, forming a lightly doped region in a substrate, depositing and etch-back of a nitride layer to form a nitride spacer layer, and removing a dielectric insulator.

[0064] Figure 23 It is a schematic diagram showing the growth of intrinsic silicon using the selective epitaxial growth technology.

[0065] Figure 24 It is a schematic diagram showing the deposition and etching of an oxide spacer layer to form a contact hole opening.

[0066] Figure 25 It is a schematic diagram showing the deposition and etching of a first metal layer to form a first metal layer interconnect.

[0067] Among them, the reference numerals are explained as follows:

[0068] 100 Metal Oxide Semiconductor Field Effect Transistor

[0069] 101 Gate structure

[0070] 103, 1704, 2402 Source

[0071] 105, 1102 Isolation region

[0072] 107, 1706, 2404 Drain

[0073] 109, 111 Contact hole

[0074] 102 Substrate

[0075] 302 Pad oxide layer

[0076] 304 Pad nitride layer

[0077] 306 Shallow Trench Isolation - First Oxide Layer

[0078] 402 Dielectric Insulator

[0079] 404, 602 Gate Layer

[0080] 406, 604 Nitride Layer

[0081] 702 Spin - on Dielectric Layer

[0082] 802 Gate Photomask Layer

[0083] 902 Trench

[0084] 1002, 2102, STI - oxide - 2 Shallow Trench Isolation - Second Oxide Layer

[0085] 1502, 2202 Third Oxide Spacer Layer

[0086] 1504, 2204 Lightly Doped Drain

[0087] 1506, 2206 Nitride Spacer Layer

[0088] 1602, 2302 Intrinsic Silicon

[0089] 1702, 2304 Chemical Vapor Deposition - Shallow Trench Isolation - Third Oxide Layer

[0090] 1802, 2406 Oxide Spacer Layer

[0091] 1804 First Contact Hole

[0092] 1806 Second Contact Hole

[0093] 1902, 2502 First Metal Layer

[0094] 1904, 2504 Minimum Space

[0095] 1906 First Semiconductor Region

[0096] 1908 First Metal - containing Region

[0097] 1910 Second Semiconductor Region

[0098] 1912 Second Metal - containing Region

[0099] 1914 First Oxide Protection Layer

[0100] 1916 Second Oxide Protection Layer

[0101] Lengths of D(L), G(L), S(L), C-S(L), C-D(L)

[0102] Widths of D(W), G(W), S(W), C-S(W), C-D(W)

[0103] Distances of GEBESI, GEBEDI

[0104] HSS (Horizontal Silicon Surface)

[0105] DSG (Dummy Shield Gate)

[0106] TG, TG2, TG3 (True Gate)

[0107] λ (Minimum Feature Length)

[0108] Δλ (Lithography Misalignment Tolerance)

[0109] Steps of 10 - 70, 202 - 228 Detailed Implementation Manner

[0110] The present invention discloses a new method for accurately controlling the linear dimensions of the source (or drain) of a transistor, where the dimensions can be as small as the minimum feature size Lamda (λ), that is, the transistor can be printed or manufactured on a wafer (such as a silicon wafer) without adding the misalignment tolerance Delta - Lamda (Δλ). Furthermore, contact holes with linear dimensions smaller than λ can be realized within the drain (or source) of the transistor. Therefore, the present invention generates a new structure of the source and drain with the minimum feature size, where the minimum feature size is from the edge of the gate structure of the transistor to the edge of the source (or drain) beside the edge of the isolation region of the transistor, and contact holes with linear dimensions smaller than λ are provided on the source and the drain. Thus, the present invention can avoid the misalignment tolerance caused by the lithography mask technology when forming the source and the drain respectively.

[0111] Please refer to Figure 1 . Figure 1 is a top view of the miniaturized metal - oxide - semiconductor field - effect transistor 100 disclosed in an embodiment of the present invention. As Figure 1As shown, the metal oxide semiconductor field effect transistor 100 includes: (1) a gate structure 101, where the gate structure 101 has a length G(L) and a width G(W); (2) a source 103 on the left side of the gate structure 101, where the source 103 has a length S(L) and a width S(W), and the length S(L) is the linear dimension from the edge of the gate structure 101 to the edge of an isolation region 105; (3) a drain 107 on the right side of the gate structure 101, where the drain 107 has a length D(L) and a width D(W), and the length D(L) is the linear dimension from the edge of the gate structure 101 to the edge of the isolation region 105; (4) in the center of the source 103, a contact hole 109 is formed by self-alignment technology, where the length and width of the contact hole 109 are C-S(L) and C-S(W) respectively; (5) similarly, in the center of the drain 107, a contact hole 111 is formed by self-alignment technology, where the length and width of the contact hole 111 are C-D(L) and C-D(W) respectively.

[0112] To form the metal oxide semiconductor field effect transistor 100, a first lithography process can be used to define the width G(W) and the pseudo length of an active region, and a second lithography process can be used to define the length G(L) in the active region, where the second lithography process can further be used to control the length S(L) between the gate structure 101 and the isolation region 105. In an embodiment of the present invention, the pseudo length of the active region defined by the first lithography process is approximately 4 times the minimum feature length λ. In an embodiment of the present invention, the length G(L) can be equal to or substantially equal to the minimum feature length λ. Of course, in other embodiments, the length G(L) can be greater than the minimum feature length λ.

[0113] The first feature of the present invention is that both the length S(L) and the length D(L) can be accurately designed and defined according to the target dimensions, where the target dimensions can be fabricated on the surface of a wafer and are not affected by the inevitable photolithographic misalignment tolerances (PMT).

[0114] The second feature of the present invention is that both the length S(L) and the length D(L) can be as small as the minimum feature length λ, where the minimum feature length is a specific process limit defined at a process node (for example, the minimum feature length λ is 7 nm at the 7 nm node, or 28 nm at the 28 nm node, or 180 nm at the 180 nm node).

[0115] The third feature of the present invention is that if the length G(L) is designed to be λ, the minimum dimension along the length direction of the metal-oxide-semiconductor field-effect transistor 100 (i.e., the distance between the left edge of the source 103 and the right edge of the drain 107) can be as small as 3λ (i.e., 1λ is the length S(L), 1λ is the length D(L), and 1λ is the length G(L)). Then the linear dimension of the metal-oxide-semiconductor field-effect transistor 100 along the said length direction can be miniaturized. Otherwise, when the linear dimension of the metal-oxide-semiconductor field-effect transistor 100 along the said length direction does not include the isolation region 105, the linear dimension of the metal-oxide-semiconductor field-effect transistor 100 along the said length direction is reduced to only 3λ.

[0116] The fourth feature of the present invention is that the lengths S(L) and D(L) can create a narrower length C-S(L) of the contact hole 109 and a narrower length C-D(L) of the contact hole 111 without being restricted by the lithography misalignment tolerance (because most of the critical photomask steps for manufacturing the contact holes 109 and 111 are excluded). Otherwise, the lengths S(L) and D(L) can be clearly defined by self-alignment technology. Furthermore, the deposition interconnect layer of the first metal layer (metal-1) can be effectively defined by the photolithographic masking technique to achieve a narrower width of the first metal layer (i.e., the sum of the contact hole opening and twice the lithography misalignment tolerance), where the deposition interconnect layer can fully fill the contact holes 109 and 111 to create natural metal contact points connecting the first metal layer to the source 103 and the drain 107 respectively.

[0117] As in the aforementioned invention, the minimum component length dimension of the metal-oxide-semiconductor field-effect transistor structure (including the isolation region and the interconnect of the first metal layer) can be miniaturized without being enlarged by the inevitable lithography misalignment tolerance.

[0118] Please refer to Figures 2A - 2F Figures 3, 4, 6 - 19. Figure 2A is a flowchart of a method for manufacturing a miniaturized metal-oxide-semiconductor field-effect transistor disclosed in another embodiment of the present invention. Among them, the method for manufacturing the metal-oxide-semiconductor field-effect transistor in Figure 2A can accurately control the lengths of the source and drain of the metal-oxide-semiconductor field-effect transistor. The detailed steps of the manufacturing method are as follows:

[0119] Step 10: Start;

[0120] Step 20: Form an active region and a trench structure on the substrate 102;

[0121] Step 30: Form a dummy shield gate and a true gate of the metal oxide semiconductor field effect transistor on the horizontal silicon surface (HSS) of the substrate 102;

[0122] Step 40: Replace the dummy shield gate with an isolation region to define the boundaries of the source / drain of the metal oxide semiconductor field effect transistor;

[0123] Step 50: Form the source and the drain of the metal oxide semiconductor field effect transistor;

[0124] Step 60: Form smaller contact holes within the boundaries of the source and the drain, and form a first metal layer interconnect to contact the source or the drain through the contact holes;

[0125] Step 70: End.

[0126] Please refer to Figure 2B and Figure 3 、 4 . Step 20 may include:

[0127] Step 202: Form a pad oxide layer 302 on the substrate 102 and deposit a pad nitride layer 304;

[0128] Step 204: Define the active region of the metal oxide semiconductor field effect transistor, and remove the silicon material outside the active region to fabricate the trench structure;

[0129] Step 206: Deposit a first oxide layer in the trench structure, and etch back the first oxide layer to form a shallow trench isolation - first oxide layer 306 (STI - oxide - 1) below the horizontal silicon surface HSS;

[0130] Step 207: Remove the pad oxide layer 302 and the pad nitride layer 304, and form a dielectric insulating layer 402 above the horizontal silicon surface HSS.

[0131] Please refer to Figure 2C and Figure 6 . Step 30 may include:

[0132] Step 208: Deposit a gate layer 602 and a nitride layer 604 above the horizontal silicon surface HSS;

[0133] Step 210: Etch the gate layer 602 and the nitride layer 604 to form the true gate and the dummy shield gate of the metal oxide semiconductor field effect transistor, wherein there is a required linear distance between the dummy shield gate and the true gate.

[0134] Please refer to Figure 2D and Figures 7 - 10 . Step 40 may include:

[0135] Step 212: Deposit a spin-on dielectrics (SOD) 702, and then etch back the spin-on dielectrics 702;

[0136] Step 214: Form a well-designed gate photomask layer 802 through the photolithography mask technology;

[0137] Step 216: Use the anisotropic etching technique to remove the nitride layer 604 on the dummy shield gate DSG, and remove the dummy shield gate DSG, the dielectric insulation layer 402 corresponding to the dummy shield gate DSG, and the substrate 102 corresponding to the dummy shield gate DSG;

[0138] Step 218: Remove the gate photomask layer 802, etch the spin-on dielectrics 702, and deposit a second oxide layer, and then etch back the second oxide layer to form the shallow trench isolation - second oxide layer 1002.

[0139] Please refer to Figure 2E and Figures 15 - 17 . Step 50 may include:

[0140] Step 220: Deposit and etch back a third oxide layer to form a third oxide spacer layer 1502, form a lightly doped drain (LDD) 1504 in the substrate 102, deposit and etch back a nitride layer to form a nitride spacer layer 1506, and remove the dielectric insulation layer 402;

[0141] Step 222: Use a selective epitaxy growth (SEG) technique to generate an intrinsic silicon 1602;

[0142] Step 224: Deposit and etch back a chemical vapor deposition (CVD) - shallow trench isolation - third oxide layer 1702, remove the intrinsic silicon 1602, and form the source (n+ source) 1704 and the drain (n+ drain) 1706 of the metal oxide semiconductor field effect transistor.

[0143] Please refer to Figure 2F and Figure 18 、 19 . Step 60 may include:

[0144] Step 226: Deposit and etch a nitride spacer layer 1802 to form contact-hole openings on the source (n+ source) 1704 and the drain (n+ drain) 1706;

[0145] Step 228: Deposit and etch a first metal layer 1902 to form the first metal layer interconnect.

[0146] First part: Utilize the dummy-shield-gate (DSG) added on the gate mask and achieve the designed distance GEBESI from the edge of the gate to the boundary edge between the source and the isolation region by avoiding the lithography misalignment tolerance. Similarly, there is also a designed distance GEBEDI from the edge of the gate to the boundary edge between the drain and the isolation region.

[0147] Taking an n-type metal oxide semiconductor field effect transistor as an example, the substrate 102 may be a p-type substrate. The detailed description of the foregoing manufacturing method is as follows. Starting from step 20, please refer to Figure 2B and Figure 3 、 4 . In step 202, a pad oxide layer 302 is formed above the horizontal silicon surface HSS of the substrate 102, and then a pad nitride layer 304 is deposited above the pad oxide layer 302.

[0148] In step 204, the active region of the metal oxide semiconductor field effect transistor can be defined by the lithography mask technology, resulting in the exposure of the horizontal silicon surface HSS outside the active region. Since the horizontal silicon surface HSS outside the active region is exposed, part of the silicon material outside the active region can be removed by the anisotropic etching technology to fabricate the trench structure.

[0149] In step 206, deposit the first oxide layer to fill the trench structure, and then etch back the first oxide layer to form a shallow trench isolation - first oxide layer 306 below the horizontal silicon surface HSS, as Figure 4 shown. Figure 4 is a cross-sectional view along the Figure 3 X-axis direction shown. Additionally, since Figure 3 is a top view, so Figure 3Only the liner nitride layer 304 and the shallow trench isolation - first oxide layer 306 are shown. Then, in step 207, the liner oxide layer 302 and the liner nitride layer 304 on the active region are removed, and a dielectric insulating layer 402 (with a high dielectric constant) is formed above the horizontal silicon surface HSS.

[0150] Figure 5 is a schematic diagram showing the prior art for realizing the geometric relationship between the gate and the transistor isolation region in a smaller size. After the dielectric insulating layer 402 is formed above the horizontal silicon surface HSS, a gate layer 404 (metal gate) is deposited above the dielectric insulating layer 402. Then a nitride layer 406 (nitride capping layer) with a well - designed thickness is deposited on the gate layer 404. Next, as Figure 5 shown, the lithography mask technology is used to define the gate structure 1, where the gate structure 1 includes the gate layer 404 and the nitride layer 406 so that the gate structure 1 has an appropriate metal gate material, and the metal gate material can provide the work function required for the metal - insulator - to - substrate 102 to achieve the appropriate threshold voltage of the metal - oxide - semiconductor field - effect transistor. Additionally, since the shallow trench isolation - first oxide layer 306 is formed below the horizontal silicon surface HSS, a tri - gate FET structure or a fin field - effect transistor (FinFET) structure can be formed (as Figure 5 shown).

[0151] After using the first lithography process to define a pseudo - length of the active region and the second lithography process to define the length G(L) of the active region, the distance from the edge of the gate structure 1 to the boundary edge between the source of the metal - oxide - semiconductor field - effect transistor and the shallow trench isolation (referred to as GEBESI) can be defined (as Figure 5 shown). Similarly, the distance from the edge of the gate structure to the boundary edge between the drain of the metal - oxide - semiconductor field - effect transistor and the shallow trench isolation (referred to as GEBEDI) can also be defined.

[0152] However, as Figure 5As shown, when aligning the edge of the gate structure 1 and the boundary edge between the source of the metal-oxide-semiconductor field-effect transistor (or the drain of the metal-oxide-semiconductor field-effect transistor) and the shallow trench isolation - first oxide layer 306 using the lithography mask technology, there is an inevitable undesirable factor called the lithography misalignment tolerance. If the linear dimension of the lithography misalignment tolerance measured along the X-axis direction is Δλ, then Δλ should be related to the minimum feature size specified by the lithography resolution of the equipment available for a specific process node. For example, for a 7-nanometer process node, the minimum feature size λ should be equal to 7 nanometers and the lithography misalignment tolerance Δλ can be 3.5 nanometers. Therefore, if the desired actual size of the source of the metal-oxide-semiconductor field-effect transistor (or the drain of the metal-oxide-semiconductor field-effect transistor) is set to λ (e.g., 7 nanometers), then in the prior art process methods, the required length of the source of the metal-oxide-semiconductor field-effect transistor (or the drain of the metal-oxide-semiconductor field-effect transistor) must be greater than the sum of λ and Δλ (e.g., greater than 10.5 nanometers).

[0153] Therefore, the present invention utilizes a new structure to eliminate the negative impact caused by the lithography misalignment tolerance. That is, any dimension of the distance GEBESI from the edge of the gate structure to the boundary edge between the source of the metal-oxide-semiconductor field-effect transistor and the shallow trench isolation (or the distance GEBEDI from the edge of the gate structure to the boundary edge between the drain of the metal-oxide-semiconductor field-effect transistor and the shallow trench isolation) can be achieved without reserving an additional dimension for the lithography misalignment tolerance along the length direction of the metal-oxide-semiconductor field-effect transistor (i.e., the X-axis direction as shown in Figure 4 , 5 ).

[0154] In step 208, as shown in Figure 6 , after forming the dielectric insulating layer 402 above the horizontal silicon surface HSS, the gate layer 602 and the nitride layer 604 are deposited. Then in step 210, the gate layer 602 and the nitride layer 604 are etched to form the gate structure (where the gate layer 602 can be the gate structure of the metal-oxide-semiconductor field-effect transistor). Figure 6 The new structure shown in Figure 5The main difference between the structures shown is that when the true gate TG of the metal oxide semiconductor field effect transistor is defined by the lithography mask technology, the pseudo shield gate DSG parallel to the true gate TG can also be defined as required, so that a target linear distance (e.g., λ, which is 7 nanometers in the 7-nanometer process node) can exist between the pseudo shield gate DSG and the true gate TG without the need to reserve any additional dimension (i.e., Δλ) for the lithography misalignment tolerance. The pseudo shield gate DSG and the true gate TG designed on the same mask can be formed simultaneously on top of the dielectric insulating layer 402 covering the active region. Additionally, as Figure 6 shown, the true gates TG2, TG3 correspond to other metal oxide semiconductor field effect transistors.

[0155] The next step is to illustrate how to replace the pseudo shield gate DSG with an isolation region raised above the horizontal silicon surface HSS. In step 212, as Figure 7 shown, a spin-on dielectric layer 702 is deposited, and then the spin-on dielectric layer 702 is etched back using chemical mechanical polishing (CMP) technology so that the top of the spin-on dielectric layer 702 is as high as the top of the nitride layer 604.

[0156] In step 214, as Figure 8 shown, a gate photomask layer 802 is deposited, and then the gate photomask layer 802 is etched through the lithography mask technology to complete the target of covering the true gates TG, TG2, TG3 but exposing the pseudo shield gate DSG, where the exposed pseudo shield gate DSG has a safe lithography misalignment tolerance Δλ in the middle of the lengths at distances GEBESI and GEBEDI respectively.

[0157] For clarity, in Figure 8 , the distance between the true gate TG under the gate photomask layer 802 and the pseudo shield gate DSG on the left can be marked as GEBESI, and the distance between the true gate TG under the gate photomask layer 802 and the pseudo shield gate DSG on the right can be marked as GEBEDI. Because after replacing the pseudo shield gate DSG with the isolation region shown in Figures 9 - 10 below, Figure 8 the distance between the true gate TG and the pseudo shield gate DSG in Figure 5 will become the distance from the edge of the true gate TG to the boundary edge between the source (or the drain of the metal oxide semiconductor field effect transistor) and the isolation region of the metal oxide semiconductor field effect transistor, that is, GEBESI (or GEBEDI) as described previously in

[0158] In step 216, as Figure 9As shown in (a), the anisotropic etching technique can be used to etch the pseudo-shield gate DSG and the nitride layer 604 corresponding to the pseudo-shield gate DSG, and can also be used to etch the dielectric insulating layer 402 corresponding to the pseudo-shield gate DSG to reach the horizontal silicon surface HSS. Then, the anisotropic etching technique is used to remove the silicon material of the substrate 102 located below the horizontal silicon surface HSS to form a trench 902 below the horizontal silicon surface HSS, where the depth of the trench 902 can be equal to the depth of the bottom of the shallow trench isolation - first oxide layer 306. Therefore, as Figure 9 shown in (a), the lithography misalignment tolerances are avoided respectively when creating the precisely controlled distances GEBESI and GEBEDI. Because the lengths of the distances GEBESI and GEBEDI are well-defined by the true gate TG and the pseudo-shield gate DSG on the same photomask, so Figure 1 the length of the source S(L) and the length of the drain D(L) shown can both be well-defined. That is to say, the single lithography photomask technique is not only used to define the true gate TG and the pseudo-shield gate DSG, but also used to control the lengths of the distances GEBESI and GEBEDI. Therefore, the dimensions of the length S(L) and the length D(L) can be accurately controlled, and can even reach the optimal miniaturization size as small as the minimum feature size λ. Because the length S(L) and the length D(L) can be equal to λ, the length S(L) and the length D(L) are substantially equal to the length of the true gate TG (that is, the gate structure). Additionally, Figure 9 (b) is a top view corresponding to Figure 9 (a).

[0159] In step 218, as Figure 10 shown in (a), the gate photomask layer 802 and the spin-on dielectric layer 702 are removed, and then a second oxide layer is deposited to fill the trench 902 and other voids on the horizontal silicon surface HSS. Then, the second oxide layer can be etched back to the same surface height as the horizontal silicon surface HSS to form the shallow trench isolation - second oxide layer 1002. Figure 10 (b) is a top view corresponding to Figure 10 (a).

[0160] Therefore, the temporarily formed pseudo-shield gate DSG can be replaced by the shallow trench isolation - second oxide layer 1002 to define the boundaries of the source / drain. Then, any existing technology that can form a lightly doped drain (LDD), a spacer around the true gate TG, the source, and the drain can be used to complete the metal oxide semiconductor field effect transistor, where the source and the drain can be formed respectively according to the accurately controlled distances GEBESI and GEBEDI.

[0161] Part II: Using the Dummy Shield Gate (DSG) design principle, an adaptive Dummy Shield Gate design is adopted to respectively achieve the target lengths for the distances GEBESI and GEBEDI for a variable-shaped active region (on an active area (AA) mask).

[0162] Since the shape of an isolation region of a transistor and the position of the isolation region between the transistor and adjacent transistors can be quite diverse (even in the above embodiments), another structure will be described below, which designs an adaptive Dummy Shield Gate by extending the principle of the above embodiments.

[0163] Figure 11 It illustrates the layout geometric conditions of the active regions of adjacent transistors, where the layout geometric conditions of the active regions of the adjacent transistors are different from Figure 6 . For example, as Figure 6 shown, before the deposition of the True Gate (TG), True Gate TG2, True Gate TG3, and Dummy Shield Gate (DSG), the adjacent active regions of adjacent transistors are connected. Then, the connected active regions can be divided into individual precise target distances by the length of the Dummy Shield Gate (DSG). However, as Figure 11 shown, it is assumed that before and after the True Gate of the transistor is defined, the active region on the source (or drain) of the transistor has been completely isolated from any other active regions by the isolation region 1102. Therefore, as described below, what is proposed here is how to design the active region on the source and the adaptive Dummy Shield Gate (DSG) (the same applies to the drain). For example, if the final length of the distance GEBESI is set to λ (or any other target length L(S)), then the length of the active area mask (AA mask) corresponding to the distance GEBESI should be designed to be equal to the sum of λ and Δλ (or the sum of the length L(S) and Δλ). Then, on the gate mask, the Dummy Shield Gate (DSG) can have the shape as Figure 11 shown, that is, the length of the rectangular shape of the Dummy Shield Gate (DSG) is equal to λ, and the width is equal to the sum of the width of the active region and 2Δλ (sharing 0.5Δλ on each side). Additionally, the designed distance between the True Gate (TG) and the Dummy Shield Gate (DSG) on the source side is still exactly the length of the distance GEBESI (e.g., λ).

[0164] From Figure 11 the mask stage of the active region and the gate to the wafer stage, the derived results will be depicted in Figure 12 . As Figure 12As shown, when the true gate TG is defined by the lithography mask technology, the pseudo shield gate DSG is designed to be parallel to the true gate TG, and there is a target distance (e.g., λ, where λ is 7 nm at the 7 nm process node) between the pseudo shield gate DSG and the true gate TG. As a result of the nominal process (i.e., no significant misalignment is introduced in the lithography process), the pseudo shield gate DSG covers the active region (corresponding to the source) by a distance of Δλ, and both the true gate TG and the pseudo shield gate DSG are disposed above the dielectric insulating layer 402 covering the active region. Additionally, there is a nitride capping layer (i.e., nitride layer 604) above both the true gate TG and the pseudo shield gate DSG.

[0165] As Figure 13 shown, if the lithography misalignment tolerance causes a displacement (e.g., Δλ) to the right of the active region for both the true gate TG and the pseudo shield gate DSG, then the next process is to remove the pseudo shield gate DSG to form the isolation region STI-oxide-2 (i.e., shallow trench isolation - second oxide layer 1002), where the position of the isolation region STI-oxide-2 is exactly the position of the originally existing pseudo shield gate DSG described in the first part of the process steps. Additionally, the next process can make the length of the isolation region STI-oxide-2 equal to λ, and the isolation region STI-oxide-2 can become the physical geometry of the source, where the length of the distance GEBESI between the true gate TG and the source is equal to λ (because the distance between the true gate TG and the pseudo shield gate DSG is designed to be λ). On the other hand, as Figure 14 shown, if the lithography misalignment tolerance causes a displacement (e.g., Δλ) to the left of the active region for both the true gate TG and the pseudo shield gate DSG, then the next process steps for removing the pseudo shield gate DSG and forming the isolation region STI-oxide-2 will make the length of the isolation region STI-oxide-2 equal to λ, and the length of the distance GEBESI between the true gate TG and the source will still be equal to λ.

[0166] When the lithography misalignment tolerance causes an adverse displacement in the width direction (i.e., the up and down direction) of the active region, the design of the adaptive pseudo shield gate (the width of the pseudo shield gate is the sum of the width of the active region and 2Δλ) will not affect the geometric dimensions of the active region. This innovative design using the adaptive pseudo shield gate always produces an isolation region STI-oxide-2 with a length of λ, and produces a distance GEBESI with a length that meets the design goal (e.g., λ). The present invention can surely be applied to all different shapes of isolation regions, sources, and drains with their respective target lengths.

[0167] Part III: A precisely defined source (or drain) enables the contact-hole opening to be precisely controlled through a self-aligned spacer layer, reducing the steps of the contact mask and the opening process.

[0168] After disclosing how to optimally design and fabricate the distances GEBESI and GEBEDI into precisely controlled small sizes (as small as λ), another new invention is how to separately fabricate contact-hole openings with lengths C-S(L) and C-D(L), where the lengths C-S(L) and C-D(L) are respectively less than the distances GEBESI and GEBEDI. Two designs and processes will be described below.

[0169] A. Design and Process (I)

[0170] Please continue to refer to Figure 10 (a) and use the true gate TG for the following description. In step 220, as Figure 15 (a) shows, deposit and etch back the third oxide layer to form the third oxide spacer layer 1502, where the third oxide spacer layer 1502 covers the true gate TG. Then, form a lightly doped region in the substrate 102, and perform rapid thermal annealing (RTA) on the lightly doped region to form a lightly doped drain 1504 beside the true gate TG. Then deposit and etch the nitride layer to form the nitride spacer layer 1506, where the nitride spacer layer 1506 covers the third oxide spacer layer 1502. Then remove the dielectric insulation layer 402 that is not covered by the nitride spacer layer 1506 and the third oxide spacer layer 1502. Additionally, Figure 15 (b) is a top view corresponding to Figure 15 (a).

[0171] In step 222, as Figure 16 (a) shows, by using the exposed horizontal silicon surface HSS as a silicon seed, use the selective epitaxial growth technique to grow intrinsic silicon 1602 only above the exposed horizontal silicon surface HSS, and the height of the intrinsic silicon 1602 is the same as the top of the nitride layer 604 (above the top of the true gate TG). Additionally, Figure 16 (b) is a top view corresponding to Figure 16 (a).

[0172] In step 224, as Figure 17As shown in (a), a chemical vapor deposition - shallow trench isolation - third oxide layer 1702 is deposited to fill all the voids, and the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 is planarized by a Chemical - Mechanical Polishing (CMP) technique so that the height of the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 is flush with the top of the nitride layer 604, where the nitride layer 604 is above the top of the true gate TG. Then, the bulk silicon 1602 is removed to expose the horizontal silicon surface HSS corresponding to the source and the drain, where the horizontal silicon surface HSS corresponding to the source and the drain is surrounded by the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 and the nitride spacer layer 1506.

[0173] The bulk silicon 1602 is used like a self - alignment pillar to enclose or seal the area where a contact hole will be configured later, but the self - alignment pillar is not limited to silicon material. According to the material of the seed for the selective epitaxial growth technique, the self - alignment pillar can be a metal material or other semiconductor materials (e.g., silicon carbide (SiC), silicon germanium (SiGe), gallium nitride (GaN), etc.). Additionally, the substrate 102 can be a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, or a gallium nitride substrate, etc.

[0174] Any prior art that can form the source (n + source) 1704 and drain (n + drain) 1706 of the metal - oxide - semiconductor field - effect transistor can use the horizontal silicon surface HSS to achieve a flat surface for the source 1704 and the drain 1706, where the source (n + source) 1704 can be a first conductive region, and the drain (n + drain) 1706 can be a second conductive region. Additionally, as Figure 17 shown in (a), a channel region exists between the lightly doped drains 1504 and below the horizontal silicon surface HSS, and the channel region can be electrically coupled to the source (n + source) 1704 and the drain (n + drain) 1706. Additionally, as Figure 17 shown in (a), the source (n + source) 1704 is placed between the gate structure (i.e., the true gate TG (gate layer 602)) and the shallow trench isolation - second oxide layer 1002 and the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 on the left side of the gate structure, where the shallow trench isolation - second oxide layer 1002 and the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 on the left side of the gate structure can be referred to as a first isolation region, and the first isolation region is adjacent to the first conductive region (i.e., the source (n + source) 1704). Additionally, as Figure 17As shown in (a), the drain (n+ drain) 1706 is placed between the gate structure and the shallow trench isolation - second oxide layer 1002 and the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 on the right side of the gate structure. The shallow trench isolation - second oxide layer 1002 and the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 on the right side of the gate structure can be referred to as a second isolation region, and the second isolation region is adjacent to the second conductive region (i.e., the drain (n+ drain) 1706). Additionally, as Figure 17 shown in (a), it can be clearly seen that the first isolation region and the second isolation region extend upward and downward from the horizontal silicon surface HSS. Additionally, Figure 17 (b) is a top view corresponding to Figure 17 (a).

[0175] In step 226, as Figure 18 shown in (a), since the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 on the isolation region (i.e., the first isolation region and the second isolation region) and the nitride spacer layer 1506 surrounding the true gate TG are higher than the horizontal silicon surface HSS, like four sidewalls, a well-designed oxide spacer 1802 (referred to as the oxide spacer for contact hole, oxide - SCH) can be fabricated outside the four sidewalls to form a first contact hole 1804. The position of the first contact hole 1804 is above the first conductive region (i.e., the source (n+ source) 1704) and within the boundary of the source (n+ source) 1704. Similarly, the position of a second contact hole 1806 is above the second conductive region (i.e., the drain (n+ drain) 1706) and within the boundary of the drain (n+ drain) 1706. Therefore, as Figure 18As shown in (a), the first contact hole 1804 and the second contact hole 1806 are naturally formed in a self-aligned manner without using any etching techniques to create the contact hole openings, and the lengths of the contact hole openings can be made less than the lengths of the distances GEBESI and GEBEDI respectively through the proper design (with thickness tOSCH) of the oxide spacer layer for the contact holes. The innovative part of the present invention lies in that the position of the contact hole openings is almost at the center of the boundary of the source 1704 (or drain 1706), and the length of the contact hole openings can be designed to be less than λ (since the length of the contact hole opening = the length of the distance GEBESI - 2 times the thickness tOSCH. Thus, for example, if the thickness tOSCH = 0.2λ and the length of the distance GEBESI = λ, then the length of the contact hole opening = 0.6λ). Therefore, since the length of the contact hole opening is mainly governed by the thickness tOSCH of the oxide spacer layer 1802, the periphery of the first contact hole 1804 (and the second contact hole 1806) is independent of the photolithography mask technology, and as Figure 18 As shown in (b), it can be clearly seen that the periphery of the first contact hole 1804 is within the periphery of the first conductive region, and the periphery of the second contact hole 1806 is within the periphery of the second conductive region.

[0176] In addition, as Figure 18 As shown in (b), since the length of the contact hole opening is less than λ, the length of the first contact hole 1804 (the length of the second contact hole 1806) is less than the length of the gate structure (since as Figure 6 shown, the length of the gate structure is equal to λ). In addition, as Figure 18 As shown in (a), since the oxide spacer layer 1802 has a thickness tOSCH and the length of the distance GEBESI is equal to the length of the gate structure, it is obvious that the horizontal distance between a first sidewall of the gate structure (located on the left side of the gate structure) and the sidewall of the first contact hole 1804 away from the gate structure will be less than the length of the gate structure (i.e., λ). In addition, as Figure 18 As shown in (a), the horizontal distance between the first sidewall of the gate structure and the sidewall of the first conductive region (i.e., the source 1704) away from the gate structure is approximately equal to the length of the gate structure. Similarly, as Figure 18 As shown in (a), the horizontal distance between a second sidewall of the gate structure (located on the right side of the gate structure) and the sidewall of the second isolation region away from the gate structure is substantially equal to the length of the gate structure.

[0177] In addition, as Figure 18As shown in (a), an oxide spacer 1802 (i.e., a first spacer) located on the left side of and adjacent to the gate structure covers the first sidewall of the gate structure, and an oxide spacer 1802 (i.e., a second spacer) located on the left side of and away from the gate structure covers a sidewall of the first isolation region, wherein a first contact hole 1804 is formed between the first spacer and the second spacer.

[0178] In addition, as Figure 18 shown in (a), an oxide spacer 1802 (e.g., a third spacer) located on the right side of and adjacent to the gate structure covers a second sidewall (located on the right side of the gate structure) of the gate structure, and an oxide spacer 1802 (e.g., a fourth spacer) located on the right side of and away from the gate structure covers a sidewall of the second isolation region, wherein a second contact hole 1806 is formed between the third spacer and the fourth spacer.

[0179] In addition, as Figure 18 shown in (b), obviously, the periphery of the first contact hole 1804 is surrounded by the periphery of the first conductive region (or source 1704), the shape of the periphery of the first contact hole 1804 is similar to the shape of the periphery of the first conductive region, and the periphery of the first conductive region is in a shape similar to a rectangle. Additionally, a similar situation also applies to the second contact hole 1806 and the second conductive region (or drain 1706).

[0180] According to the present invention, the self - aligned contact holes (the first contact hole 1804 and the second contact hole 1806) exhibit a minimum contact hole length (the dimension of which can be less than λ), which is smaller than the length of the contact hole opening fabricated by any prior - art design and by the lithography mask technology and complex etching process. In addition, the present invention omits most of the difficult - to - control factors and most of the expensive masks used to define and fabricate the first metal layer contacts (e.g., the first contact hole 1804 and the second contact hole 1806 for the source 1704 and the drain 1706 respectively) and the subsequent task of drilling the contact hole opening. In addition, Figure 18 (b) is a top view corresponding to Figure 18 (a).

[0181] In step 228, as Figure 19 shown, after depositing a first metal layer 1902 to fill the contact holes (the first contact hole 1804 and the second contact hole 1806), the first metal layer 1902 can be defined by the lithography mask technology. As Figure 19As shown, the first metal layer 1902 must have a width with precisely controlled dimensions, where the width of the first metal layer 1902 must fully cover the contact hole opening and leave room for any unavoidable lithography misalignment tolerances. That is, the width of the first metal layer 1902 corresponding to the source 1704 is equal to the length C-S(L) of the contact hole opening (on the source 1704) plus 2Δλ, and the width of the first metal layer 1902 corresponding to the drain 1706 is equal to the length C-D(L) of the contact hole opening (on the drain 1706) plus 2Δλ. If the length of the contact hole opening can be controlled within 0.6λ (which can be controlled because, as can be known from the calculations described above, the dimensions of the oxide spacer layer 1802 within the contact hole can be well controlled), then the width of the first metal layer 1902 can be as small as the sum of the length of the contact hole opening and 2Δλ. (If in an embodiment of the present invention, Δλ = 0.5λ (i.e., half of the length of the gate structure), and the length of the contact hole opening = 0.6λ, then in order to fully cover the contact hole opening under unavoidable lithography misalignment tolerances, the width of the first metal layer 1902 can be as narrow as 1.6λ. That is, in order to fully cover the contact hole opening under unavoidable lithography misalignment tolerances, the width of the first metal layer 1902 can be equal to the length of the first contact hole 1804 plus the length of the gate structure). According to the present invention, the width of the first metal layer 1902 as narrow as 1.6λ can be one of the minimum widths for the first metal layer interconnection. Additionally, a minimum space 1904 between two of the closest first metal layer interconnections cannot be less than λ. Additionally, as Figure 19 shown, the first metal layer 1902 (i.e., a first metal region) fills the first contact hole 1804 and contacts the first conductive region (i.e., the source 1704), where the first metal region extends upward from the first conductive region to a predetermined position, and the predetermined position is above the top of the nitride layer 604 (i.e., the nitride capping layer).

[0182] Additionally, as Figure 20As shown, without an adjacent first metal layer interconnect for the source (and / or drain), for example, using a merged semiconductor junction and metal conductor (MSMC) structure (disclosed in U.S. Patent Application No. 16 / 991,044, filed on August 12, 2020, incorporated herein by reference in its entirety), the width of the chemical vapor deposition - shallow trench isolation - third oxide layer 1702 defined by the pseudo shield gate can be made as small as the minimum feature size λ, without being limited by the space between any adjacent first metal layer interconnects, where the source (and / or drain) is grounded and directly connected to the substrate 102 of the metal oxide semiconductor field effect transistor. Additionally, as Figure 20 shown, the source includes a first semiconductor region (n+ heavily doped semiconductor region) 1906 and a first metal-containing region 1908, the drain includes a second semiconductor region (n+ heavily doped semiconductor region) 1910 and a second metal-containing region 1912, where a first oxide guard layer (OGL) 1914 only covers one sidewall of the first metal-containing region 1908 and does not cover the bottom of the first metal-containing region 1908, and a second oxide guard layer 1916 (in the Figure 20 shown groove) covers one sidewall and the bottom of the second metal-containing region 1912. Therefore, the first metal-containing region 1908 is coupled to the substrate 102 through the bottom of the first metal-containing region 1908.

[0183] An important advantage of the present invention is that almost every critical dimension, such as the lengths of the distances GEBESI and GEBEDI, the length of the contact hole opening, and the width of the first metal layer interconnect, can be precisely controlled without being affected by uncertain lithography misalignment tolerances. Thus, based on the consistency of the critical dimensions, the repeatability, quality, and reliability of each critical dimension can be ensured.

[0184] B. Design and Process (II)

[0185] The above principle will continue to be adopted in the following embodiments, but the difference lies in how to form the spacer layer and the contact hole opening. Continuing Figure 9 (a), as Figure 21As shown in (a), the gate lithography mask layer 802 is removed, and then the second oxide layer is deposited to fill the trench 902 and other voids above the horizontal silicon surface HSS to form a shallow trench isolation - second oxide layer 2102. Then, the shallow trench isolation - second oxide layer 2102 is planarized by the chemical mechanical polishing technique so that the top of the shallow trench isolation - second oxide layer 2102 is flush with the top of the spin - on dielectric layer 702 and the top of the nitride layer 604, where the nitride layer 604 is above the true gate TG. Additionally, Figure 21 (b) is the top view corresponding to Figure 21 (a).

[0186] Then, as shown in Figure 22 (a), the spin - on dielectric layer 702 is removed. Then, the third oxide layer is deposited, and the third oxide layer is etched back using the anisotropic etching technique to form a third oxide spacer layer 2202, where the third oxide spacer layer 2202 covers the true gate TG. Then, a lightly doped region is formed in the substrate 102, and rapid thermal annealing is performed on the lightly doped region to form the lightly doped drain 2204 beside the true gate TG. Then, the nitride layer is deposited and etched back to form a nitride spacer layer 2206, where the nitride spacer layer 2206 covers the third oxide spacer layer 2202. Then, the dielectric insulating layer 402 under the previously existing spin - on dielectric layer 702 is removed. Additionally, Figure 22 (b) is the top view corresponding to Figure 22 (a).

[0187] Next, as shown in Figure 23 (a), by using the exposed horizontal silicon surface HSS region as a silicon seed, an intrinsic silicon 2302 is grown only above the exposed horizontal silicon surface HSS using the selective epitaxial growth technique, where the height of the intrinsic silicon 2302 is flush with the top of the nitride layer 604, and the nitride layer 604 is above the top of the true gate TG. Different from paragraph A of the aforementioned third part, the shape of the intrinsic silicon 2302 grown by the selective epitaxial growth can be better controlled because the two sides of the intrinsic silicon 2302 are sandwiched between the shallow trench isolation - second oxide layer 2102 and the true gate TG, and the other two sides of the intrinsic silicon 2302 face the air above the cliff edge of the active region, where the active region is still covered by the dielectric insulating layer 402 and above the adjacent shallow trench isolation - first oxide layer 306 (STI - oxide - 1). Then, a chemical vapor deposition - shallow trench isolation - third oxide layer 2304 (as shown in Figure 23 (b)) is deposited to fill all voids, and the top of the chemical vapor deposition - shallow trench isolation - third oxide layer 2304 is planarized by the chemical mechanical polishing technique to be flush with the top of the nitride layer 604 (above the top of the true gate TG). Additionally, Figure 23 (b) is the top view corresponding toFigure 23 Top view of (a).

[0188] In addition, as Figure 24 shown in (a), the intrinsic silicon 2302 is removed to expose a horizontal silicon surface HSS corresponding to a source (n+ source) 2402 and a drain (n+ drain) 2404 region, wherein the source 2402 and the drain 2404 are surrounded by two walls of the chemical vapor deposition - shallow trench isolation - third oxide layer 2304, one wall of the nitride spacer layer 2206 on the shallow trench isolation - second oxide layer 2102, and one wall of the nitride spacer layer 2206 surrounding the true gate TG. Any prior art capable of forming the source 2402 and the drain 2404 of the metal oxide semiconductor field effect transistor can use the horizontal silicon surface HSS to achieve a flat surface for the source 2402 and the drain 2404.

[0189] As Figure 24 shown in (a), since the two walls of the chemical vapor deposition - shallow trench isolation - third oxide layer 2304, the nitride spacer layer 2206 on the shallow trench isolation - second oxide layer 2102, and the nitride spacer layer 2206 surrounding the true gate TG are all higher than the horizontal silicon surface HSS like four sidewalls, another well - designed four - oxide spacer layer 2406 (referred to as an oxide spacer for contact hole, oxide - SCH) can be newly created to cover the four sidewalls. Therefore, the contact hole opening is naturally formed in a self - aligned manner without using any etching technology for manufacturing the contact hole opening, and through a proper design of the oxide spacer for the contact hole (oxide - SCH) (with a thickness tOSCH), the length dimension of the contact hole opening can be less than the lengths of the distances GEBESI and GEBEDI respectively. The innovative part of the present invention is that the positions of the contact hole openings are respectively at the center of the boundaries of the source and the drain, and the length of the contact hole opening can be designed to be less than λ (because the length of the contact hole = the length of the distance GEBESI - 2 times the thickness tOSCH. Thus, for example, if the thickness tOSCH = 0.2λ and the length of the distance GEBESI = λ, then the length of the contact hole = 0.6λ). According to the present invention, the self - aligned contact hole exhibits a minimum contact hole length (whose size can be less than λ), which is smaller than the lengths of the contact hole openings manufactured by any prior art design and through the photolithography mask technology and complex etching processes. In addition, the present invention omits most of the difficult - to - control factors and most of the expensive masks for defining and manufacturing the first metal layer contact and the subsequent task of drilling the contact hole opening. In addition, Figure 24 (b) is the top view corresponding to Figure 24 (a).

[0190] Figure 25 It is a schematic diagram showing that after depositing a first metal layer 2502 to fill the contact hole opening, the first metal layer 2502 is defined by using the photolithography mask technology. As Figure 25 shown, the first metal layer 2502 must have a width with precisely controlled dimensions, where the width of the first metal layer 2502 must completely cover the contact hole opening and leave a tolerance for any unavoidable photolithography misalignment. That is, the width of the first metal layer 2502 corresponding to the source is equal to the length C-S(L) of the contact hole opening (on the source) plus 2Δλ, and the width of the first metal layer 2502 corresponding to the drain is equal to the length C-D(L) of the contact hole opening (on the drain) plus 2Δλ. If the length of the contact hole opening can be controlled within 0.6λ (which can be controlled because, as known from the foregoing calculations, the dimensions of the oxide spacer layer 2406 in the contact hole can be well controlled), then the width of the first metal layer 2502 can be as small as the sum of the length of the contact hole opening and 2Δλ. (If in an embodiment of the present invention, Δλ = 0.5λ and the length of the contact hole opening = 0.6λ, then in order to completely cover the contact hole opening under unavoidable photolithography misalignment tolerance, the width of the first metal layer 2502 can be as narrow as 1.6λ. According to the present invention, the width of the first metal layer 2502 as narrow as 1.6λ can be one of the minimum widths for the first metal layer interconnection. Additionally, a minimum space 2504 between two closest first metal layer interconnections cannot be less than λ. Additionally, an important advantage of the present invention is that almost every critical dimension, such as the lengths of the distances GEBESI and GEBEDI, the length of the contact hole opening, and the width of the first metal layer interconnection, can be precisely controlled without being affected by uncertain photolithography misalignment tolerance. Thus, based on the consistency of the critical dimensions, the reproducibility, quality, and reliability of each critical dimension can be ensured.)

[0191] In summary, the metal oxide semiconductor field effect transistor structure disclosed in the embodiments of the present invention can bring several major improvements to the design of future integrated circuits by avoiding photolithography misalignment tolerance, especially in terms of the geometric relationships between the gate and the source, the gate and the drain, the contact hole openings between the first metal layer and the source / drain, etc., and the design and process improvements of the width of the first metal layer interconnection and its self-alignment method for filling the contact hole:

[0192] (1) Precise definition of the length S(L) and length D(L) respectively from the two edges of the gate by excluding the uncertainties caused by photolithography misalignment tolerance.

[0193] (2) Both the length S(L) and the length D(L) can be designed to be the minimum feature length λ allowed by the lithography mask and the process resolution, thereby significantly reducing the sizes of the source and the drain. Thus, the area of the metal oxide semiconductor field effect transistor can be reduced, and the standby and operating currents and power consumption can be reduced, and accordingly, the operating speed of the metal oxide semiconductor field effect transistor can be improved.

[0194] (3) Since both the length S(L) and the length D(L) can be precisely controlled, through the spacer layers created around the four sidewalls of the source and the drain, the self-alignment technique of the present invention can precisely fabricate self-alignment contact holes (SACH) with controllable shapes and sizes and respectively close to the centers of the source and the drain.

[0195] (4) The length of the self-alignment contact hole can be designed to be less than the minimum feature size λ, such as as small as 0.6λ or even narrower.

[0196] (5) The other width dimensions of the self-alignment contact hole can be well designed through the self-alignment spacer layer and the well-defined active region width; since the formation of the self-alignment contact hole is through the spacer layer technology, rather than the prior art of defining the contact hole through the lithography mask technology with difficult-to-control misalignment tolerances and contact hole shapes, where the spacer layer technology depends on the developed technology of using chemically deposited thin films with controllable thickness and the anisotropic etching technology. The contact hole opening of the present invention can be well designed and defined (although the contact hole may not have a consistent square contact shape, the contact hole has a well-defined rectangular shape and the filling result actually depends on the narrower length dimension of the contact hole).

[0197] (6) Eliminate the most difficult and expensive contact steps and masks.

[0198] (7) Separate a square hole or multiple square holes completely into a single rectangular contact hole or a single contact trench between multiple contact holes to change the design of the contact hole; thus, the width (or length) of the source (or the drain) can be exactly the same as the width (or length) of the gate without being limited by the dimensional difference between the width of the gate adjusted by using the dog-bone layout and the width of the source (or the drain) that may have multiple square contact holes.

[0199] (8) Since the success of filling the first metal layer interconnect with a well-designed thickness depends on the minimum size of the contact holes (usually the length of the self-aligned contact (SACH) holes), the first metal layer interconnect can indeed fill all existing contact holes, so that the two steps used in the prior art to form contact posts (such as filling tungsten plus a planarization process, that is, the tungsten post process and the first metal layer embedding process disclosed in the prior art) can be simplified into a first metal layer deposition process.

[0200] (9) Through the above-integrated self-aligned contact hole and first metal layer formation process and the gate being covered under the nitride capping layer and protected by the spacer layer (where both the nitride capping layer and the spacer layer can create a flat plane on the area outside the self-aligned contact holes), the first metal layer interconnect can be designed to have various layouts to create an optimally distributed first metal layer interconnect network.

[0201] (10) Combining the above advantages, the metal oxide semiconductor field effect transistor structure disclosed in the present invention can be manufactured to have a very small size, where the metal oxide semiconductor field effect transistor structure has a minimum length dimension of 4λ (that is, including a length S(L) equal to λ, a length D(L) equal to λ, a gate length equal to λ, 1 / 2λ for isolation on the left, and 1 / 2λ for isolation on the right) and a minimum width dimension of 2λ, that is, a single transistor with the world's smallest size having contact holes and a first metal layer interconnect respectively connected to the source and the drain can be realized within an area of 8λ. 2

[0202] Of course, according to design requirements, the length G(L), the length S(L), or the length D(L) can be greater than the minimum feature length λ.

[0203] Since the present invention eliminates the uncertainty of lithography misalignment tolerance and adopts new self-aligned design and process technologies, all the advantages of the present invention are not only not limited to being applied to a single metal oxide semiconductor field effect transistor, but can also be applied to complementary metal oxide semiconductor (CMOS) circuits. For example, many optimized functional units in terms of area (such as Static Random Access Memory (SRAM), NAND gate, NOR gate, and any logic gate) can reduce the chip area, current, power consumption, and speed through the design and manufacturing principles of the present invention, and have accuracy, repeatability, consistency, and better margin.

[0204] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method of manufacturing a transistor, wherein the transistor includes a gate structure and a first conductive region, characterized in that Comprising: Forming an active region on a substrate; Forming the gate structure and a pseudo-shield gate structure above the active region; Forming a first isolation region to replace the pseudo-shield gate structure; Forming a self-aligned pillar on the surface between the gate structure and the first isolation region above the active region using the substrate; And Removing the self-aligned pillar to form a contact hole between the gate structure and the first isolation region, and forming the first conductive region between the gate structure and the first isolation region through the contact hole.

2. The manufacturing method according to claim 1, characterized in that Before removing the self-aligned pillar, the manufacturing method further comprises: Forming another part of the first isolation region above the first isolation region, wherein the self-aligned pillar is located between the gate structure and the another part of the first isolation region.

3. The manufacturing method according to claim 1, characterized in that After removing the self-aligned pillar, the manufacturing method further comprises: Forming a spacer layer between the gate structure and the first isolation region to define the contact hole; Wherein the contact hole is located above the first conductive region.

4. The manufacturing method according to claim 3, characterized in that The length of the contact hole is less than a minimum feature length, and the minimum feature length is related to the process resolution of the process node used to manufacture the transistor.

5. The manufacturing method according to claim 1, characterized in that The substrate is a silicon substrate, and the self-aligned pillar is an intrinsic silicon pillar formed by selective epitaxial growth.

6. The manufacturing method according to claim 1, wherein The self-aligned pillar is used to distribute the contact hole above the first conductive region.

7. The manufacturing method according to claim 1, wherein The contact hole is defined above the substrate for forming the first conductive region, wherein defining the contact hole is independent of a lithography process.

8. The manufacturing method according to claim 7, characterized in that The another part of the first isolation region extends upward in the upper direction of the active region.

9. The manufacturing method according to claim 8, characterized in that The contact hole is defined by forming a spacer layer, and the spacer layer covers a sidewall of the gate structure and a sidewall of the first isolation region.

10. The manufacturing method according to claim 1, wherein The width of the gate structure and the length of the active region are defined by a first lithography process; The length of the gate structure within the active region is defined by a second lithography process; Wherein the second lithography process is further used to define the length of the first conductive region.

11. The manufacturing method according to claim 10, characterized in that The length of the gate structure defined by the second lithography process is equal to a minimum feature length, and the minimum feature length is related to the process resolution of the process node used to manufacture the transistor.

12. The manufacturing method according to claim 11, characterized in that The length of the active region defined by the first lithography process is approximately equal to 4 times of a minimum feature length.

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