Method of fabricating memory cells, high voltage devices and logic devices on a substrate

Abstract

The invention relates to a method of forming a semiconductor device by the steps of: recessing an upper surface of a semiconductor substrate in a first region and a second region but not a third region; forming a first conductive layer in the first region and the second region; forming a second conductive layer in all three regions; removing the first conductive layer and the second conductive layer from the second region and removing part of the first conductive layer and the second conductive layer from the first region, thereby forming a stack structure pair, each stack structure pair having a control gate over a floating gate; forming a third conductive layer in the first region and the second region; forming a protective layer in the first region and the second region; and then removing the second conductive layer from the third region; then forming a block of conductive material in the third region; then etching in the first region and the second region to form a select gate and an HV gate; and replacing the blocks of conductive material with blocks of metallic material.

Description

Technical Field

[0001] This invention relates to a semiconductor device having an embedded non-volatile memory cell. Background Technology

[0002] Non-volatile memory semiconductor devices formed on silicon semiconductor substrates are well known. For example, U.S. Patents 6,747,310, 7,868,375, and 7,927,994 disclose memory cells formed on semiconductor substrates having four gates (floating gate, control gate, select gate, and erase gate), which are incorporated herein by reference for all purposes. Source and drain regions are formed as diffusion-implanted regions extending into the substrate, thereby defining a channel region within the source and drain regions of the substrate. A floating gate is disposed over a first portion of the channel region and controls the conductivity of that first portion; a select gate is disposed over a second portion of the channel region and controls the conductivity of that second portion; a control gate is disposed over the floating gate; and an erase gate is disposed over the source region and laterally adjacent to the floating gate.

[0003] It is also known to form low-voltage logic devices and high-voltage logic devices on the same substrate as non-volatile memory cells. See, for example, U.S. Patent 9,276,005, which is incorporated herein by reference for all purposes. Novel gate materials, such as high-k dielectric gates and metal gates, are also used to improve performance. However, the fabrication steps for forming memory cells can adversely affect currently manufactured logic devices, and vice versa.

[0004] An improved method is needed to fabricate devices comprising memory cells, low-voltage logic devices, and high-voltage devices on the same substrate. Summary of the Invention

[0005] The aforementioned problems and needs are addressed by a method for forming a semiconductor device, the method comprising:

[0006] A substrate for providing semiconductor material is provided, the substrate for semiconductor material comprising a first region, a second region, and a third region;

[0007] The upper surface of the substrate in the first region and the upper surface of the substrate in the second region are recessed relative to the upper surface of the substrate in the third region.

[0008] A first conductive layer is formed, which is disposed above the upper surface of the first region and the second region and is insulated from the upper surface;

[0009] A second conductive layer is formed, which is disposed above the first conductive layer in the first region and the second region and is insulated from the first conductive layer, and is disposed above the upper surface in the third region and is insulated from the upper surface;

[0010] One or more etching operations are performed to selectively remove portions of the first and second conductive layers in a first region to completely remove the first and second conductive layers from the second region while retaining the second conductive layer in a third region. The one or more etching operations result in the formation of a stacked structure pair in the first region. Each stacked structure in the stacked structure includes a control gate of the second conductive layer, which is disposed above and insulated from the floating gate of the first conductive layer.

[0011] A first source region is formed in the substrate, and each first source region is disposed between one stacked structure pair in the stacked structure pair;

[0012] A third conductive layer is formed, which is disposed above the upper surface of the substrate in the first region and the second region and is insulated from the upper surface of the substrate.

[0013] A protective layer is formed over the third conductive layer in the first and second regions;

[0014] After the protective layer is formed, the second conductive layer is removed from the third region;

[0015] After the second conductive layer is removed from the third region, a conductive material block is formed, which is disposed above and insulated from the upper surface of the third region.

[0016] After forming a conductive material block in the third region, portions of the protective layer in the first and second regions and portions of the third conductive layer are etched to form multiple select gates of the third conductive layer. Each select gate is disposed adjacent to one of the stacked structures in the stacked structure, and multiple HV gates of the third conductive layer are formed. Each HV gate is disposed above the upper surface in the second region and is insulated from the upper surface.

[0017] A first drain region is formed in the substrate, and each first drain region is adjacent to a select gate in the select gate;

[0018] A second source region is formed in the substrate, and each second source region is adjacent to an HV gate in the HV gate;

[0019] A second drain region is formed in the substrate, and each second drain region is adjacent to an HV gate in the HV gate;

[0020] A third source region is formed in the substrate, and each third source region is adjacent to a conductive material block in the conductive material block;

[0021] A third drain region is formed in the substrate, each third drain region being adjacent to a conductive material block in the conductive material block; and

[0022] Replace each conductive block in the conductive material block with a metal material block.

[0023] Other objects and features of the invention will become apparent from a review of the specification, claims and drawings. Attached Figure Description

[0024] Figures 1A to 16A This is a cross-sectional view of the memory cell region, showing the steps involved in forming the memory cell.

[0025] Figures 1B to 16B This is a cross-sectional view of the HV region, showing the steps involved in forming the HV device.

[0026] Figures 1C to 16C This is a cross-sectional view of the logic region, showing the steps involved in forming the logic device.

[0027] Figure 17 This is a cross-sectional view of the memory cell area, showing the finished memory cell.

[0028] Figure 18 This is a cross-sectional view of the HV region, showing the finished HV equipment.

[0029] Figure 19 This is a cross-sectional view of the logic region, showing the finished logic device.

[0030] Figure 20 This is a cross-sectional view of the logic region, showing the finished logic device in an alternative implementation.

[0031] Figure 21 This is a cross-sectional view of the logic region, showing the finished logic device in an alternative implementation. Detailed Implementation

[0032] This invention relates to a process for forming semiconductor devices by simultaneously forming memory cells, low-voltage logic devices, and high-voltage logic devices on the same semiconductor substrate. The process described herein relates to forming memory cells in one or more memory cell regions (also referred to as first or MC regions) 2 of substrate 10, forming high-voltage logic devices in one or more high-voltage logic device regions (also referred to as second or HV regions) 4 of substrate 10, and forming low-voltage logic devices in one or more low-voltage logic device regions (also referred to as third or logic regions) 6 of substrate 10. A process is described that simultaneously forms a pair of memory cells in MC region 2, a high-voltage logic device in HV region 4, and a low-voltage logic device in logic region 6. However, multiple such devices may be formed simultaneously in each region. Substrate 10 is a substrate of a semiconductor material (e.g., silicon).

[0033] See MC area 2 Figures 1A to 16A See HV region 4. Figures 1B to 16B And logical region 6 see Figures 1C to 16C The diagram shows a cross-sectional view of the process steps for manufacturing a semiconductor device. The process begins by recessing the upper surface 10a of the silicon substrate 10 in the MC region 2 and HV region 4 relative to the logic region 6 by a recess amount R. The recessing of the upper surface 10a is preferably performed by forming a silicon dioxide (hereinafter referred to as "oxide") layer on the upper surface 10a and a silicon nitride (hereinafter referred to as "nitride") layer on the oxide layer. A photolithography masking step is performed to cover logic region 6 with photoresist without covering MC region 2 and HV region 4 (i.e., photoresist is formed on all three regions, portions of the photoresist are selectively exposed, and portions of the photoresist are selectively removed, thereby exposing portions of the underlying structure (in this case, the nitride layers in MC region 2 and HV region 4), while the remaining portions of the underlying structure are covered by photoresist (in this case, the nitride layers in logic region 6). Nitride etching and oxide etching are performed to remove these layers from MC region 2 and HV region 4, thereby exposing the upper surface 10a in these regions. After removing the photoresist, thermal oxidation is then performed to form oxide layers on the exposed portions of the upper surface 10a in MC region 2 and HV region 4. This thermal oxidation process consumes some silicon from the substrate, thereby effectively reducing the upper surface 10a in these regions. Then, nitride etching and oxide etching are used to remove all oxide and nitride layers, resulting in... Figure 1A , Figure 1B and Figure 1C The structure shown. The upper surface 10a in MC region 2 and HV region 4 is recessed by an amount R (e.g., 200A-700A) relative to the upper surface 10a in logic region 6.

[0034] Next, an oxide layer 12 is formed on the upper surface 10a (e.g., by deposition or by thermal growth, etc.). Thereafter, a conductive layer such as polysilicon (hereinafter referred to as "poly") 14 is formed on the oxide layer 12. The polysilicon layer 14 can alternatively be in-situ doped or undoped amorphous silicon. If undoped polysilicon or amorphous silicon is used for layer 14, implantation and annealing are performed. Then, a photolithography masking step is performed to cover the MC region 2 and HV region 4 with photoresist 16, but leaving the logic region 6 exposed (i.e., as part of the masking step, the photoresist 16 is removed from the logic region 6). Then, polysilicon etching is used to remove the polysilicon layer 14 from the logic region 6, as... Figure 2A , Figure 2B and Figure 2C As shown.

[0035] After removing the photoresist 16, an optional oxide layer 18 is formed over the structure, followed by a nitride layer 20 on the oxide layer 18. A photolithography masking step is used to selectively cover portions of each region with photoresist. Nitride etching, oxide etching, polysilicon etching, and silicon etching are used to form trenches that penetrate through the nitride 20, oxide 18, polysilicon 14, oxide 12, and into the silicon substrate 10. Preferably, these trenches are 2000 Å-3500 Å deep in logic region 6 of the substrate 10 and 1600 Å-3300 Å deep in MC region 2 and HV region 4 of the substrate 10. These trenches are then filled with oxide 22, terminated by oxide deposition on the nitride layer 20 and chemical mechanical polishing (CMP). Figure 3A , Figure 3B and Figure 3C As shown. Oxide 22 can also be referred to as STI (Shallow Trench Isolation), which is a well-known isolation technique. Oxide 22 may include an inner lining oxide formed by thermal oxidation prior to oxide deposition.

[0036] A series of implantations can be performed to form a desired well in the substrate 10 in each of regions 2 / 4 / 6 (where photoresist protects one or more regions in other regions during each implantation), followed by oxide etchback to recess the STI oxide 22 beneath the top of the nitride layer 20. The nitride layer 20 is then removed using nitride etching. An insulating layer 24 is then formed over this structure. Preferably, the insulating layer 24 is an ONO composite layer having oxide / nitride / oxide sublayers (formed by oxide, nitride, oxide deposition and annealing). However, the insulating layer 24 may alternatively be formed from a composite of other dielectric layers or a single dielectric material without sublayers. A conductive layer, such as a polysilicon layer 26, is then formed on this structure by polysilicon deposition. The polysilicon layer 26 may alternatively be in-situ doped or undoped amorphous silicon. If undoped polysilicon or amorphous silicon is used for layer 14, polysilicon implantation and annealing are performed. A hard mask layer 28 is then formed on the polysilicon layer 26. The hard mask layer 28 can be a nitride, SiCN, or even a composite of oxide, nitride, and / or SiCN layers. The resulting structure is... Figure 4A , Figure 4B and Figure 4C As shown in the image.

[0037] A photolithography masking step is used to form photoresist 30 on the structure, wherein the photoresist is removed from HV region 4 and selectively removed from MC region 2 to expose layer 28 in HV region 4 and only partially expose layer 28 in MC region 2. A series of etching steps are used to remove the exposed portions of hard mask layer 28, polysilicon layer 26, and ONO layer 24, thereby leaving spaced stacked structures S1 and S2 pairs of hard mask layer 28, polysilicon layer 26, and ONO layer 24 in MC region 2, and these layers are completely removed from HV region 4. The resulting structure is... Figure 5A , Figure 5B and Figure 5C As shown in the image.

[0038] After removing the photoresist 30, oxide deposition or thermal oxidation and etching are used to form spacers 32 along the sides of the stacks S1 and S2 in MC region 2. Nitride deposition and etching are used to form nitride spacers 34 along the sides of the oxide spacers 32. The oxide etching and nitride etching can be combined. Polysilicon etching is performed to remove the exposed portions of the polysilicon layer 14, resulting in each spaced stack structure S1 / S2 also including a polysilicon layer 14 block. The polysilicon layer 14 is completely removed from HV region 4. Oxide insulators 36 are formed on the sides of the stack structures S1 / S2 (including the exposed ends along the polysilicon layer 14 blocks) by oxide deposition and oxide anisotropic etching, as shown. Figure 6A , Figure 6B and Figure 6C As shown.

[0039] A photolithography masking step is used to cover MC region 2 and logic region 6 with photoresist, but leaving HV region 4 exposed. Oxide etching is used to remove oxide layer 12 from HV region 4. After photoresist removal, an insulating layer 38 is then formed on the substrate upper surface 10a in HV region 4 and on these structures in MC region 2 and logic region 6 by thermal growth and / or deposition. Insulating layer 38 may be an oxide and / or oxynitride and will be used as the gate oxide of the HV device. However, it should be noted that removing and replacing oxide 12 with insulating layer 38 is optional, and oxide 12 may alternatively be used as part or all of the gate oxide of the HV device. After photoresist removal, photoresist 40 is formed on the structure, and this photoresist is removed only from the region between stacks S1 and S2 in MC region 2 (referred to herein as the inner stack region). An implantation process is performed to form source region 42 in the substrate between stacks S1 and S2. Then, oxide etching is used to remove oxide layer 38, oxide spacers 36, and oxide layer 12 from the inner stacked regions. The resulting structure is... Figure 7A , Figure 7B and Figure 7C As shown in the image.

[0040] After removing the photoresist 40, a tunnel oxide 44 is formed on the structure. The tunnel oxide 44 can be an oxide and / or oxynitride formed by deposition and / or thermal growth. Due to the catalytic effect of the higher dopant level in the source region 42, the tunnel oxide 44 can have a thicker portion 44a on the source region 42. A photolithography masking step is used to cover the HV region 4 and logic region 6, as well as the inner stacked region in the MC region, with photoresist. The regions on the other side of the stacked structures S1 and S2 (referred to herein as the outer stacked regions) remain exposed. At this time, implantation can be performed on the portion of the substrate 10 in the outer stacked regions (i.e., those substrate portions below the select gate to be formed later). Oxide etching is used to remove the exposed oxide layer 12 in the outer stacked regions. After removing the photoresist, an oxide layer 46 is then formed on the structure. The oxide layer 46 can be an oxide and / or oxynitride or any other suitable dielectric material formed by deposition and / or thermal growth. The formation of the oxide layer 46 thickens or incorporates the tunnel oxide 44 and the insulating layer 38. The resulting structure is Figure 8A , Figure 8B and Figure 8C As shown in the image.

[0041] A conductive layer, such as a polysilicon layer 48, is formed on this structure. The polysilicon layer 48 may be in-situ doped or undoped, and may alternatively be amorphous silicon. If undoped polysilicon or amorphous silicon is used for layer 48, doping and annealing are performed. A buffer oxide layer 50 is formed on the polysilicon layer 48. A photolithography masking step is used to cover the buffer oxide layer 50 in HV region 4, but exposes the buffer oxide layer 50 in MC region 2 and logic region 6. The exposed portions of the buffer oxide layer 50 are then removed by oxide etching in MC region 2 and logic region 6. After removing the photoresist, a conductive layer, such as a polysilicon layer 52 (which may alternatively be amorphous silicon with the same doping as the polysilicon layer 48), is then deposited on this structure. Figure 9A , Figure 9B and Figure 9CAs shown. Polysilicon chemical mechanical polishing (CMP) is performed to planarize the top surface of the structure, terminating on hard mask layer 28. A further polysilicon etch-back process is used to recess the upper surface of polysilicon layer 48 below the top of stacked S1 and S2. This completes the formation of most memory cells. Oxide etching is used to remove buffer oxide 50 in HV region 4. A protective insulating layer 54 is formed over the structure. Layer 54 can be oxide, nitride, SiCN, or a combination thereof. A photolithography masking step is used to cover MC region 2 and HV region 4 with photoresist, while exposing logic region 6. Etching is used to remove the protective layer 54 in logic region 6. After removing the photoresist, a series of etching steps are then performed to remove all material layers in logic region 6, thereby exposing the upper surface 10a of the substrate, as shown. Figure 10A , Figure 10B and Figure 10C As shown. Protective layer 54 protects MC region 2 and HV region 4 from this series of etchings.

[0042] At this point, implantation can be performed to form doped P-wells and N-wells in the substrate 10 within logic region 6. A dielectric layer 56 (which can be used as the gate dielectric of a logic device) is formed on the exposed upper surface 10a of the substrate in logic region 6. The dielectric layer 56 can be silicon oxide, silicon oxynitride, a high-k dielectric layer, or a combination thereof. A high-k insulating material is an insulating material whose dielectric constant K is greater than that of silicon dioxide. Examples of high-k insulating materials include HfO2, ZrO2, TiO2, Ta2O5, and combinations thereof. A pseudo-conductive layer, such as a polysilicon layer 58, is then formed over this structure. A hard mask layer 60 is then formed on the pseudo-polysilicon layer 58. A photolithography masking step is used to cover selected portions of logic region 6 with photoresist, thereby exposing the hard mask layer 60 throughout the MC region 2 and HV region 4, and in a portion of logic region 6. Etching is then used to remove the exposed areas of the hard mask layer 60 in MC region 2, HV region 4, and logic region 6. After removing the photoresist, etching is used to remove the exposed portions of the pseudo-polysilicon layer 58 and dielectric layer 56 (i.e., all portions of logic region 6 not protected by the remaining portion of the hard mask layer 60), leaving logic stack structures LS1 and LS2 in logic region 6. Dielectric spacers 62 are formed on the sides of the logic stack structures LS1 / LS2 by deposition and etching. At this point, implantation into the substrate 10 can be performed in logic region 6. The resulting structure... Figure 11A , Figure 11B and Figure 11C As shown in the image.

[0043] A photolithography masking step is used to cover a portion of logic region 6, HV region 4, and MC region 2 with photoresist 64 (i.e., covering the inner stacked regions, stacked structures S1 and S2, and the portions of the outer stacked regions immediately adjacent to stacked structures S1 and S2). Etching is used to remove exposed portions of the protective layer 54 and polysilicon layer 48, such as... Figure 12A , Figure 12B and Figure 12C As shown. After removing the photoresist 64, additional selective implantation and etching (i.e., implantation via additional photomask steps) can be performed in different exposed portions of the substrate 10. For example, the MC region 2 can be exposed by covering the HV region 4 and logic region 6 with photoresist, and implantation can be performed on the portion of the substrate 10 covered only by the oxide layer 46. The HV region 4 can be exposed by covering the MC region 2 and logic region 6 with photoresist, and implantation can be performed on the portion of the substrate 10 covered only by the oxide layer 38. Furthermore, oxide etching can be used to thin the oxide layer 38 (which also thins the protective layer 54 in the HV region 4). The resulting structure is shown in Figure 13A , Figure 13B and Figure 13C As shown in the image.

[0044] Oxide and nitride deposition are used, followed by spacer etching to form oxide spacers 66 and nitride spacers 68 on the sides of stacked structures S1 / S2 in MC region 2, on the sides of stacked structures LS1 / LS2 in logic region 6, and on the sides of these structures in HV region 4. A semi-conformal layer 70 is formed on this structure. This layer has some conformality of the underlying morphology, but is thinner at the top of the underlying morphology compared to the locations where the vertical and horizontal surfaces intersect. To achieve this varying thickness, a flowable material is preferably used to form layer 70. A non-limiting exemplary material for the semi-conformal layer 70 is BARC material (bottom antireflective coating), which is typically used to reduce reflectivity at resist interfaces during photolithography. BARC material is flowable and wettable, and is easy to etch and remove with minimal process damage due to its high selectivity relative to oxides. Other materials that can be used for the semi-conformal layer 70 include photoresist or spin-on glass (SOG). A photolithography masking step is used to cover HV region 4 and logic region 6 with photoresist, while exposing MC region 2. Etching (e.g., anisotropic) is used to remove the semi-conformal layer 70 from the protective layer 54 on the stacked structures S1 / S2 and polysilicon block 48, exposing the protective layer while keeping the semi-conformal layer 70 covering the oxide layer 46 (i.e., this portion of the semi-conformal layer 70 serves as a hard mask for the next etching step). Etching is used to thin or remove the protective layer 54 on the stacked structures S1 / S2 and to thin the protective layer on the polysilicon block 48 adjacent to the stacked structures S1 / S2. The resulting structure... Figure 14A , Figure 14B and Figure 14C As shown in the image (after removing the photoresist).

[0045] After removing the semi-conformal layer 70, implantation is performed to form a drain region 74 in the substrate adjacent to spacer 68 in region MC 2, a source region 76 and a drain region 78 adjacent to spacer 68 in region HV 4, and a drain region 80 / 82 adjacent to spacer 68 in region 6. Implantation of any given region can be performed by forming photoresist to prevent implantation into other regions to be implanted. For example, the drain region 74 in region MC 2, the source region 76 / drain region 78 in region HV 4, and the source region 80 / drain region 82 of the same doping type in region 6 can be formed simultaneously by forming photoresist on regions with opposite source / drain doping types, and then performing single implantation in region MC 2, region HV 4, and region 6. At this time, a barrier layer 84 can be formed by deposition, masking steps, and etching to prevent any silanization in the next step. During the etching process described above, any remaining portions of the protective layer 54 not protected by the barrier layer 84 in MC region 2 and HV region 4 are also removed, thereby exposing the gate polysilicon 48 to subsequent silicide formation. Metal deposition and annealing are then performed to form silicide on the top surface of the exposed blocks of polysilicon 48, source regions 76 / 80, and drain regions 74 / 78 / 82. The barrier layer 84 prevents silicide formation in any areas where it is not desired. Optionally, the barrier layer 84 may be retained in selected portions of the source / drain regions 74 / 76 / 78 / 80 / 82 and / or the polysilicon gate region 48 to prevent silicide formation in these selected regions. The resulting structure in Figure 15A , Figure 15B and Figure 15C As shown in the image.

[0046] Etching is used to remove the remainder of the hard mask layer 60 on the stacked structures LS1 / LS2 in logic region 6, the nitride layer 28 on the stacked structures S1 / S2 in MC region 2, and any exposed nitride spacers 68 in all three regions. A layer 88 (e.g., nitride) is formed over this structure. A thick interlayer dielectric (ILD) insulating material layer 90 is then formed on layer 88. CMP is performed to planarize and recess the ILD insulating material 90, thereby exposing the pseudo-polysilicon 58 in logic region 6. A photolithography masking step is used to cover MC region 2 and HV region 4 with photoresist while exposing logic region 6. Polysilicon etching is then used to remove the polysilicon layer 58 block in logic region 6. Optionally, a dielectric layer 56 may also be removed in this step. After removing the photoresist, a dielectric layer 92, such as silicon oxide, oxide oxynitride, a high-k dielectric layer, or a composite thereof, may optionally be deposited over this structure. A layer of metal gate material 94, such as Al, Ti, TiAlN, TaSiN, TaN, TiN, or other suitable metal materials or composites thereof, is formed above the dielectric layer 92. Then, CMP is performed to remove the dielectric layer 92 and the metal layer 94, leaving a block of metal 94 with the dielectric layer 92 as a backing in logic region 6. The final structure is shown in... Figure 16A , Figure 16B and Figure 16C As shown in the image.

[0047] Figure 17 The final memory cell structure in MC region 2 is shown, comprising pairs of memory cells, each pair sharing a source region 42 spaced apart from two drain regions 74, with a channel region 96 in silicon 10 extending between them. Each memory cell includes: a floating gate 14a disposed above and insulated from a first portion of the channel region 96 for controlling the conductivity of the first portion; a select gate 48a (also referred to as a word line gate) disposed above and insulated from a second portion of the channel region 96 for controlling the conductivity of the second portion; a control gate 26a disposed above and insulated from the floating gate 14a; and an erase gate 48b (shared by the memory cell pairs) disposed above and insulated from the source region 42. The memory cell pairs extend along the column direction (BL direction) and form columns of memory cells, with an insulator 22 between adjacent columns. A row of control gates is formed as a continuous control gate line, which connects the control gates of an entire row of memory cells together. A row of select gates is formed as a continuous select gate line (also called a word gate line), which connects the select gates of an entire row of memory cells together. A row of erase gates is formed as a continuous erase gate line, which connects the erase gates of an entire row of memory cells together.

[0048] The final HV device is in Figure 18 As shown in the diagram. Each HV device includes a spaced-apart source region 76 and a drain region 78, with a channel region 98 of the silicon substrate 10 extending between them. A conductive gate 48c is disposed above and insulated from the channel region 98 for controlling the conductivity of the channel region.

[0049] The final logic device is in Figure 19 As shown in the figure. Each logic device includes a spaced-apart source region 80 and a drain region 82, wherein a channel region 100 of the silicon substrate 10 extends between them. A metal gate 94 is disposed above and insulated from the channel region 100 (through the dielectric layer 92) for controlling the conductivity of the channel region. Figure 20 The final logic device is shown with dielectric layer 56 retained and the formation of dielectric layer 92 omitted. Figure 21 The final logic device is shown with dielectric layer 56 maintained and dielectric layer 92 formed.

[0050] The method described above for forming memory cells, HV devices, and logic devices on the same substrate has many advantages. The formation of the memory cells and HV devices is completed before the formation of the optional high-k dielectric gate and metal gate in logic region 6, ensuring that the optional high-k dielectric layer 92 and metal gate 94 in logic region 6 are not adversely affected by the formation of the memory cells and HV devices. The process steps for forming the gates in MC region 2 and HV region 4 are separate and independent from the process steps for forming the gates in logic region 6 (and can be customized relative to the process steps for forming the gates in the logic region). After most of the memory cells and HV devices have been formed and before processing in logic region 6 (i.e., before removing the layers left by the formation of the memory cells and HV devices in logic region 6 and before depositing and removing the layers used to form the logic devices (including pseudo-polysilicon removal), etc.), MC region 2 and HV region 4 are covered by a protective layer 54. The upper surface 10a of substrate 10 is recessed in MC region 2 and HV region 4 relative to the upper surface of substrate in logic region 6 to accommodate higher structures in MC region 2 / HV region 4 (i.e., such that the top of the shorter logic device in logic region 6 is slightly higher than the top of the taller memory cell and HV device in MC region 2 / HV region 4, and such that CMP can be performed across all three regions, for example, during the CMP step of logic gate formation, the tops of select gate 48a and HV gate 48c remain intact). A protective layer 88 protects the silicide polysilicon block 48 from the CMP used to form the metal logic gate 94, and a control gate polysilicon 26 assists as a termination layer for this CMP. Silicide 86 improves the conductivity of drain region 74 and source regions 76 / drain region 78, source region 80 / drain region 82, select gate 48a, erase gate 48b, and HV gate 48c. As the protective layer 54 is thinned, the semi-conformal layer 70 protects the oxides and silicon in the source / drain regions of the MC region 2. The memory cell select gate 48a, memory cell erase gate 48b, and HV device gate 48c can be formed using a single conductive material deposition (i.e., a single polysilicon layer formed by a single polysilicon deposition can be used to form all three types of gates). Furthermore, the same polysilicon etching can be used to define one edge of each select gate 48a and both edges of each HV gate 48c. The thicknesses of the various gate oxides 46, 12, 38, and 56 are independent of each other, and each gate oxide is optimized for its corresponding gate operation. For example, layer 46 beneath the select gate 48a is preferably thinner than layer 12 beneath the floating gate.

[0051] It should be understood that the invention is not limited to the embodiments described above and shown herein, but covers any and all variations falling within the scope of the appended claims. For example, references to the invention herein are not intended to limit the scope of any claims or claim terminology, but only to one or more features that may be covered by one or more of these claims. The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting the claims. Furthermore, it will be apparent from the claims and specification that not all method steps need to be performed in the exact order shown or claimed, but rather in any order that allows for the proper formation of the memory cell regions and logic regions of the invention, unless otherwise specified in the claims. Finally, a single material layer may be formed as multiple such or similar material layers, and vice versa.

[0052] It should be noted that, as used herein, the terms “above” and “on” both encompass “directly on” (without intermediate material, elements, or space between) and “indirectly on” (with intermediate material, elements, or space between). Similarly, the term “adjacent” encompasses “directly adjacent” (without intermediate material, elements, or space between) and “indirectly adjacent” (with intermediate material, elements, or space between). For example, forming an element “above a substrate” can include forming an element directly on the substrate without intermediate material / elements between, and forming an element indirectly on the substrate with one or more intermediate materials / elements between.

Claims

1. A method for forming a semiconductor device, comprising: A substrate for providing semiconductor material is provided, the substrate for semiconductor material comprising a first region, a second region, and a third region; The upper surface of the substrate in the first region and the upper surface of the substrate in the second region are recessed relative to the upper surface of the substrate in the third region; A first conductive layer is formed, which is disposed above the upper surface in the first region and the second region and is insulated from the upper surface; A second conductive layer is formed, which is disposed above the first conductive layer in the first region and the second region and is insulated from the first conductive layer, and is disposed above the upper surface in the third region and is insulated from the upper surface; One or more etching operations are performed to selectively remove portions of the first conductive layer and the second conductive layer in the first region, to completely remove the first conductive layer and the second conductive layer from the second region, while retaining the second conductive layer in the third region, wherein the one or more etching operations result in the formation of a stacked structure pair in the first region, wherein each stacked structure includes a control gate of the second conductive layer, the control gate of the second conductive layer being disposed above and insulated from the floating gate of the first conductive layer. A first source region is formed in the substrate, and each first source region is disposed between one stacked structure pair in the stacked structure pair; A third conductive layer is formed, the third conductive layer being disposed above the upper surface of the substrate in the first region and the second region and being insulated from the upper surface of the substrate; A protective layer is formed over the third conductive layer in the first region and the second region; After the protective layer is formed, the second conductive layer is removed from the third region; After removing the second conductive layer from the third region, a conductive material block is formed, which is disposed above and insulated from the upper surface in the third region. After the conductive material block is formed in the third region, portions of the protective layer and the third conductive layer in the first and second regions are etched to form a plurality of select gates of the third conductive layer. Each select gate is disposed adjacent to one of the stacked structures in the stacked structure, and a plurality of HV gates of the third conductive layer are formed. Each HV gate is disposed above the upper surface in the second region and is insulated from the upper surface. For each stacked structure pair in the stacked structure pair, the erase gate of the third conductive layer is disposed between the stacked structure pairs and is disposed above one of the source regions and is insulated from the one of the source regions. After forming the plurality of selection gates and the plurality of HV gates: A semi-non-conformal layer of material capable of flow is formed in the first region, the second region, and the third region; A portion of the semi-non-conformal layer of the flowable material is removed from the protective layer in the first region, while the semi-non-conformal layer of the flowable material is retained in the second and third regions; Thin the protective layer in the first region; as well as Remove the remaining portion of the semi-non-conformal layer of the flowable material in the first region and the semi-non-conformal layers in the second and third regions; A first drain region is formed in the substrate, and each first drain region is adjacent to one of the select gates; A second source region is formed in the substrate, and each second source region is adjacent to one of the HV gates in the HV gate; A second drain region is formed in the substrate, and each second drain region is adjacent to one of the HV gates in the HV gate; A third source region is formed in the substrate, and each third source region is adjacent to one of the conductive material blocks in the conductive material block; A third drain region is formed in the substrate, and each third drain region is adjacent to one of the conductive material blocks in the conductive material block; Remove the thinned protective layer in the first region to expose the select gate and the erase gate; Silicates are formed on the select gate and the erase gate; as well as Replace each conductive material block in the conductive material block with a metal material block.

2. The method of claim 1, wherein each of the metal material blocks is insulated from the upper surface in the third region by a high-K insulating material layer.

3. The method of claim 1, wherein prior to the replacement, each conductive material block in the conductive material blocks is insulated from the upper surface in the third region by a high-K insulating material layer, and wherein the replacement further comprises forming each metal material block in the metal material blocks on the high-K insulating material layer.

4. The method of claim 1, wherein each of the first conductive layer, the second conductive layer and the third conductive layer is formed of polycrystalline silicon or amorphous silicon.

5. The method of claim 1, wherein forming the first conductive layer further comprises forming the first conductive layer in the third region, and wherein the method further comprises removing the first conductive layer from the third region.

6. The method of claim 1, wherein forming the third conductive layer further comprises forming the third conductive layer in the third region, and wherein the method further comprises removing the third conductive layer from the third region.

7. The method according to claim 1, further comprising: Silicides are formed on the first drain region, the second drain region, and the third drain region, as well as on the second source region and the third source region.

8. The method according to claim 1, further comprising: A silicide is formed on the HV gate.

9. The method of claim 8, wherein after the silicide is formed on the select gate, the erase gate, and the HV gate, and before each of the conductive material blocks is replaced with the metal material block, the method further comprises: A protective material layer is formed on the silicide in the first region and the second region.

10. The method of claim 1, wherein for each of the stacked structures, the control gate is insulated from the floating gate by an ONO insulating layer.

11. The method of claim 1, wherein after forming the third conductive layer, the method further comprises: An insulating material layer is formed on the third conductive layer in the second region; A pseudo-conductive material layer is formed on the third conductive layer in the first region and the third region, and on the insulating material layer in the second region; Perform chemical mechanical polishing to remove the pseudo-conductive material layer in the first region, the second region, and the third region; And then Remove the insulating material layer from the second region.

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