A semiconductor device, manufacturing method and its application

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate; an interface for generating a two-dimensional charge carrier gas; a first electrode and a second electrode; a first semiconductor layer of a first type of doping formed on the substrate, a first region in which the first type of doping atoms are not electroactive and a second region in which the first type of doping atoms are electroactive are formed in the first semiconductor layer; a part coplanar with the first region is included in the second region. The semiconductor device can avoid damage to the crystal structure, is easy to implement in terms of process, and can maintain good transport properties of the two-dimensional charge carrier gas, which is beneficial to the improvement of device performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a group-III nitride semiconductor device, a manufacturing method thereof, and an application thereof. Background Art

[0002] Group-III nitride semiconductors are an important new type of semiconductor material, mainly including AlN, GaN, InN, and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Utilizing the advantages of the group-III nitride semiconductors such as direct bandgap, wide bandgap, and high breakdown electric field strength, through the optimized design of device structures and processes, group-III nitride semiconductors have great prospects in the field of power semiconductors.

[0003] Taking advantage of the above-mentioned advantages of the group-III nitride semiconductors, through the optimized design of device structures and processes, it is desirable to develop semiconductor devices with high performance such as high power and low on-resistance.

[0004] In existing group-III nitride semiconductor devices, most of them process the semiconductor layer near the gate or anode by selective area growth to realize the desired device. However, the above-mentioned process method involves a large topography generated by selective area growth, so the process control is relatively complex.

[0005] To solve the existing problems, the present disclosure aims to provide a novel manufacturing process and structure for a group-III nitride semiconductor normally-closed device, which can not only avoid damage to the crystal structure, but also be easily realized in the process, and can maintain good two-dimensional charge carrier gas transport properties, which is beneficial to the improvement of device performance. Summary of the Invention

[0006] A brief overview of the present disclosure will be given below to provide a basic understanding of certain aspects of the present disclosure. It should be understood that this overview is not an exhaustive overview of the present disclosure. It is not intended to identify the key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is only to present certain concepts in a simplified form as a prelude to the more detailed description to follow.

[0007] According to one aspect of the present disclosure, there is provided a device structure, which includes: a substrate; an interface for generating a two-dimensional charge carrier gas; a first electrode and a second electrode; a first semiconductor layer formed on the substrate and containing a first type of doped atoms, in which a first region where the first type of doped atoms are not electroactive or the electroactivity of the first type of doped atoms is partially compensated and a second region where the first type of doped atoms are electroactive are formed; and a part of the second region coplanar with the first region.

[0008] Furthermore, the first region is a co-doped region of first-type doping atoms and second-type doping atoms, the second region is a first-type doping atom doped region, and the first region does not deplete the two-dimensional charge carrier gas at its corresponding interface, while a sub-region in the second region substantially depletes the two-dimensional charge carrier gas at its corresponding interface.

[0009] Furthermore, when the semiconductor device is a HEMT or a diode, the first region is overall N-type, weakly P-type, high-resistance type or insulating type; when the semiconductor device is a HHMT, the first region is overall P-type or weakly N-type, high-resistance type or insulating type.

[0010] Furthermore, the thickness of the first region is less than or equal to the thickness of the second region.

[0011] Furthermore, the first region at least corresponds to the region between the first electrode and the second electrode.

[0012] Furthermore, when the semiconductor device is a HEMT / HHMT, the projection of a sub-region in the second region relative to the substrate is less than or equal to the projection range of the second electrode relative to the substrate; when the semiconductor device is a diode, the projection of a sub-region in the second region relative to the substrate is greater than the projection range of the second electrode relative to the substrate.

[0013] Furthermore, the second-type doping atoms are N-type or atoms that can produce deep-level effects, the first-type doping atoms are P-type atoms, or the second-type doping atoms are P-type or atoms that can produce deep-level effects, and the first-type doping atoms are N-type.

[0014] Furthermore, the doping concentration of the second-type doping atoms is greater than 10% of the doping concentration of the first-type doping atoms.

[0015] Furthermore, the doping concentration of the second-type doping atoms is uniformly distributed or gradually decreasing along the direction perpendicular to the substrate of the first electrode.

[0016] Furthermore, the N-type doping atoms are silicon or germanium, and the P-type doping atoms are magnesium.

[0017] Furthermore, the atoms that can produce deep-level effects are nitrogen, carbon, iron or argon, and the P-type doping atoms are magnesium.

[0018] Furthermore, the first region is continuous or discrete; or the shapes of the cross-sections of the first region are regular or irregular.

[0019] Further, when the first region is discrete, the thicknesses of the first regions are equal or unequal.

[0020] Further, it further includes a second semiconductor layer formed on the first semiconductor layer, and a two-dimensional charge carrier gas is formed at an interface between the first semiconductor layer and the second semiconductor layer.

[0021] Further, it further includes a third semiconductor layer formed on the first semiconductor layer, and a two-dimensional charge carrier gas is formed at an interface between the third semiconductor layer and the second semiconductor layer.

[0022] Further, the doping concentration of the first-type doping atoms in the first semiconductor layer is set to: gradually increase in a direction perpendicular to the substrate from the electrode, or be set in a manner that is high at both ends and low in the middle in a direction perpendicular to the substrate from the electrode.

[0023] Further, a passivation layer is further provided on the second semiconductor layer.

[0024] Further, a nucleation layer, a buffer layer, or an insertion layer is further provided on the substrate.

[0025] Further, the first electrode is a cathode and the second electrode is an anode.

[0026] Further, the first electrode is a source or a drain, and the second electrode is a gate.

[0027] Further, it further includes a bulk electrode, and the bulk electrode is electrically connected to or not connected to the first electrode.

[0028] Further, it further includes a bulk electrode, and the bulk electrode forms an ohmic contact with the second region of the first semiconductor layer.

[0029] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, which includes: providing a substrate; forming an interface for generating a two-dimensional charge carrier gas; at least forming a first electrode and a second electrode; forming a first semiconductor layer doped with first-type doping atoms on the substrate, doping a second-type doping atom in a first region in the first semiconductor layer such that the first-type doping atoms in the first region are not electroactive, and the first-type doping atoms in a second region in the first semiconductor layer where the second-type doping atoms are not doped are electroactive.

[0030] Further, the second type of doping atoms is an N-type or an atom that can produce a deep energy level effect, the first type of doping atoms is a P-type atom, or the second type of doping atoms is a P-type or an atom that can produce a deep energy level effect, and the first type of doping atoms is an N-type.

[0031] Further, the doping concentration of the second type of doping atoms is greater than 10% of the doping concentration of the first type of doping atoms.

[0032] Further, the doping concentration of the second type of doping atoms is uniformly distributed or gradually decreases along the direction perpendicular to the substrate of the first electrode.

[0033] Further, the N-type doping atoms are silicon or germanium, the P-type doping atoms are magnesium, and the atoms that can produce a deep energy level effect are carbon, argon, iron, or nitrogen.

[0034] Further, the first region does not deplete the two-dimensional charge carrier gas at its corresponding interface, and a sub-region in the second region substantially depletes the two-dimensional charge carrier gas at its corresponding interface.

[0035] Further, the first region is formed at least in the first semiconductor layer corresponding to the region between the first electrode and the second electrode.

[0036] Further, the first region is formed by forming a mask layer on the first semiconductor layer, lithographically etching the mask layer to form a pattern with an opening, and then ion-implanting the second type of doping atoms.

[0037] Further, the opening is selected from:

[0038] Covering the upper surface of the first semiconductor layer corresponding to the second electrode and near the first electrode in the direction away from the second electrode;

[0039] Or, covering the upper surface of the first semiconductor layer corresponding to the second electrode.

[0040] Further, the formation method of the first region is selected from:

[0041] Method 1: Form a second type of doping atom material layer on the first semiconductor layer, lithographically etch the material layer to form a pattern with an opening, and then the second type of doping atoms diffuse from the material layer into the first semiconductor layer through heat treatment.

[0042] Method 2: A mask layer with an opening is formed on the first semiconductor layer, and then a second type of dopant atom material layer is formed on the mask layer. By peeling off the mask layer, only the second type of dopant atom material layer at the mask opening is left, and then the second type of dopant atoms are diffused from the material layer into the first semiconductor layer through heat treatment.

[0043] Furthermore, the opening in the first embodiment is selected from:

[0044] exposing an upper surface of the first semiconductor layer corresponding to the second electrode and near the first electrode in a direction away from the second electrode;

[0045] exposing an upper surface of the first semiconductor layer corresponding to the second electrode;

[0046] The openings in the second embodiment and the openings in the first embodiment are in complementary patterns.

[0047] Furthermore, the openings are arranged so that the first region is formed into continuous or discrete, regular or irregular sub-regions, or a combination thereof.

[0048] Furthermore, the depth of ion implantation or ion diffusion in each sub-region is less than or equal to the thickness of the first semiconductor layer, and the implantation dose or diffusion time between each sub-region is the same or different, or a combination of the above.

[0049] Furthermore, the method further includes selectively forming a third semiconductor layer on the first semiconductor layer.

[0050] Furthermore, it also includes forming a second semiconductor layer on the first semiconductor layer or the third semiconductor layer, so as to form the two-dimensional charge carrier gas at the interface between the first / second semiconductor layer or at the interface between the third / second semiconductor layer.

[0051] Furthermore, it also includes forming a first electrode, a second electrode and a third electrode; wherein the first electrode and the third electrode are in ohmic contact with the two-dimensional charge carrier gas, and the second electrode forms a Schottky contact with the second semiconductor layer or the first semiconductor layer.

[0052] Furthermore, it also includes forming an insulating layer between the second electrode and the second semiconductor layer.

[0053] Furthermore, it further includes forming a passivation layer on the second semiconductor layer; or

[0054] A nucleation layer and / or a buffer layer is formed on the substrate.

[0055] Further, it further includes forming a fourth electrode, and the fourth electrode is in ohmic contact with the second region of the first semiconductor layer.

[0056] Further, the fourth electrode is electrically connected or not connected to the first electrode.

[0057] According to another aspect of the present disclosure, there is provided an electronic device including the semiconductor device of any one of the above.

[0058] The solution of the present disclosure can at least contribute to achieving one of the following effects: avoiding damage to the crystal structure, being easy to implement in terms of process, maintaining good transport properties of two-dimensional charge carriers, achieving better stability of the threshold voltage, contributing to the electric field distribution of the device, achieving higher breakdown voltage capabilities, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The specific content of the present disclosure will be described below with reference to the accompanying drawings, which will help to more easily understand the above and other objects, features, and advantages of the present disclosure. The drawings are only for showing the principle of the present disclosure. The dimensions and relative positions of the units do not have to be drawn to scale in the drawings. In the drawings:

[0060] Figure 1-2 A schematic cross-sectional view according to the first embodiment is shown;

[0061] Figures 3-11 A schematic cross-sectional view according to the second embodiment is shown;

[0062] Figures 12-15 A schematic cross-sectional view according to the third embodiment is shown;

[0063] Figures 16-17 A schematic cross-sectional view according to the fourth embodiment is shown;

[0064] Figures 18-24 A schematic cross-sectional view according to the fifth embodiment is shown;

[0065] Figures 25-28 A schematic cross-sectional view according to the sixth embodiment is shown. DETAILED DESCRIPTION

[0066] Hereinafter, the exemplary disclosure of the present disclosure will be described with reference to the accompanying drawings. For clarity and conciseness, not all features for implementing the present disclosure are described in the specification. However, it should be understood that many decisions specific to the present disclosure may be made during the development of any implementation of the present disclosure in order to achieve the specific goals of the developer, and these decisions may vary depending on the present disclosure.

[0067] Here, it should also be noted that in order to avoid obscuring the present disclosure with unnecessary details, only the device structures closely related to the solutions according to the present disclosure are shown in the drawings, while other details less relevant to the present disclosure are omitted.

[0068] It should be understood that the present disclosure is not limited to the described embodiments only by the following description with reference to the drawings. In the present disclosure, where feasible, features between different embodiments may be replaced or borrowed, and one or more features may be omitted in one embodiment.

[0069] In the following specific embodiments, reference may be made to the drawings, which form a part of the present disclosure and illustrate exemplary embodiments. In addition, it should be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) are only used to assist in the description of the features in the drawings and are not to be taken in a limiting sense only in the following specific embodiments.

[0070] As used in the specification and the appended claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" also include the plural forms. It will also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0071] Specifically, the semiconductor device of the present disclosure is a compound semiconductor device containing a nitride semiconductor material, also referred to as a nitride semiconductor device, wherein the nitride semiconductor device is a group III nitride semiconductor device. Further, the group III nitride semiconductor device includes a transistor using a wurtzite group III nitride semiconductor material and a GaN diode containing a GaN semiconductor material. Still further, the transistor is a GaN transistor containing a GaN semiconductor material. In particular, the GaN transistor is a normally-closed transistor GaN-HEMT and / or GaN-HHMT.

[0072] First Embodiment

[0073] Currently, the process for fabricating a normally-closed device of a group III nitride semiconductor is generally achieved by fabricating a P-type nitride semiconductor gate electrode on a barrier layer. Due to the poor insulation performance of the barrier layer, a relatively large gate current is likely to occur. At the same time, the gate electrode is also relatively far from the channel due to the spacing of the barrier layer, which is not conducive to obtaining a high threshold voltage.

[0074] In view of this, the present application provides a normally-closed device of group-III nitride semiconductor, which overcomes the existing defects and achieves the beneficial technical effects as described above by designing a new process flow method.

[0075] Refer to Figure 1-2 to describe the semiconductor device according to the first embodiment, where Figure 1 the structure of the HEMT is shown, Figure 2 and the structure of the diode is shown.

[0076] As Figure 1-2 shown, in the first embodiment, the semiconductor device includes a substrate 100. The material of the substrate 100 can be selected according to actual needs, and the specific form of the substrate 100 is not limited in this embodiment. Optionally, the substrate 100 can be ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3 or single-crystalline silicon, etc.; preferably, the substrate 100 can be (0001)-plane Al2O3; more preferably, the substrate 100 can be a (111)-plane silicon substrate 100.

[0077] A first semiconductor layer 201 formed on the first surface 1001 of the substrate 100. The first semiconductor layer 201 has a first surface A and a second surface B. Exemplarily, the first semiconductor layer 201 can be P-GaN. Further, the P-doping concentration in the first semiconductor layer 201 can be uniform; or the doping concentration in the first semiconductor layer 201 varies along the direction from the first surface A to the second surface B. For example, it can be gradually increasing from the first surface A to the second surface B, or the doping concentrations of the first surface A and the second surface B are relatively high and the middle concentration is relatively low. The doping concentration of the P-type impurity can be set in the range of 1E+17 / cm3 - 1E+20 / cm3.

[0078] A second semiconductor layer 202 formed on the first semiconductor layer 201. The first semiconductor layer 201 has a smaller bandgap than the second semiconductor layer 202, and a two-dimensional charge carrier gas, such as 2DEG, is formed between the first semiconductor layer 201 and the second semiconductor layer 202. Optionally, the second semiconductor layer 202 is an AlN, AlGaN, InAlGaN, InAlN layer, etc.

[0079] It can be understood that a third semiconductor layer 203 can also be formed on the first semiconductor layer 201. The third semiconductor layer 203 serves as a channel layer, which can reduce the scattering effect caused by P-GaN or impurities and improve the electron mobility of the channel. A two-dimensional charge carrier gas, such as 2DEG, is formed between the third semiconductor layer 203 and the second semiconductor layer 202. The third semiconductor layer 203 can be an intrinsic or unintentionally doped GaN layer.

[0080] Next, as Figure 1 described in Figure 2 a source electrode 301, a gate electrode 302, and a drain electrode 303 are formed on the second semiconductor layer 202. The drain electrode and the source electrode form an ohmic contact with the two-dimensional charge carrier gas, and the gate electrode forms a Schottky contact with the second semiconductor layer, or the gate electrode forms a MIS gate with the second insulating layer and the second semiconductor layer; or as

[0081] shown in

[0082] a cathode 304 and an anode 305 are formed on the second semiconductor layer 202. The cathode forms an ohmic contact with the two-dimensional charge carrier gas, and the anode forms a Schottky contact with the first semiconductor layer or the second semiconductor layer. Figure 1 It can be understood that a first insulating layer 400 can also be formed on the second semiconductor layer 202. The insulating layer 400 can be a passivation layer, which can make the device more stable. Optionally, the material of the passivation layer is SiO2, SiN, Al2O3, etc. As

[0083] The sub-region 2012’ (equivalent to a sub-region of the second region) in the first semiconductor layer 201 can enable the interface formed by the second semiconductor layer and the first or third semiconductor layer to have no 2DEG at the interface due to the depletion of the first semiconductor layer without applying a bias voltage, but there is 2DEG at the interface under the condition of the positive bias voltage. Exemplarily, the doping concentration of P-type impurities can be 1E+17 / cm3 - 1E+20 / cm3, and the impurities can be magnesium atoms. The upper and lower surfaces of the sub-region 2012’ are coplanar or non-coplanar with the upper and lower surfaces of the sub-region 2011 (equivalent to the first region) / 2013 (equivalent to the first region) in the first semiconductor layer 201. Preferably, the thickness of the sub-region 2012’ is 10 - 100 nm, which can better improve the performance parameters of the device. It should be noted that the first-type doping atoms formed in the first region of the first semiconductor layer 201 are not electroactive or the electroactivity of the first-type doping atoms is fully or partially compensated.

[0084] As Figure 1 shown, at the sub-region 2011 corresponding to between the source electrode and the gate electrode in the first semiconductor layer 201, at the sub-region 2013 corresponding to between the drain electrode and the gate electrode in the first semiconductor layer 201, or as Figure 2 shown, there are also impurity atoms doped with a type different from P-type in the sub-region 2011 corresponding to between the cathode and the anode in the first semiconductor layer 201. The doped impurity atoms can be N-type atoms such as silicon or germanium. The doping concentration of the N-type atoms such as silicon or germanium is such that the region 2011 / 2013 in the first semiconductor layer 201 where the N-doped atoms and the P-type atoms coexist as a whole presents an N-type or weakly P-type form. Exemplarily, the doping concentration of the N-type atoms such as silicon or germanium is greater than or equal to 10% of the doping concentration of the P-type atoms. Exemplarily, the doping depth is between 1 nanometer and 50 nanometers.

[0085] Or the doped impurity is an atom such as carbon, nitrogen, iron or argon, and its doping concentration can be selected such that the region 2011 / 2013 in the first semiconductor layer 201 where the doped atoms and the P-type atoms coexist as a whole presents a form with an impedance more than ten times higher than the impedance of the region 2012 (equivalent to the second region) in the first semiconductor layer 201 where there are no two different atoms coexisting. Exemplarily, the doping concentration is between 1 nanometer and 50 nanometers.

[0086] Figure 1In the first semiconductor layer 201 described in [reference], the region 2011 corresponding to the region between the source and the gate may include a region range starting from the edge E1 of the gate 302 close to the source 301 to the edge F1 of the source far from the gate, or Figure 2 In the first semiconductor layer 201 described in [reference], the region 2011 corresponding to the region between the cathode and the anode may include the region range in the first semiconductor layer 201 starting from the edge E1' of the cathode close to the anode to the edge F1' of the cathode far from the anode. Correspondingly, the region 2013 in the first semiconductor layer 201 corresponding to the region between the drain and the gate may be a region range starting from the edge E2 of the gate 302 close to the drain 303 to the edge F2 of the drain far from the gate. When the device is a HEMT, the length of the sub-region 2012' of the first semiconductor layer may be less than or equal to the size of the gate. Preferably, the length is 1 / 5 - 1 / 4 of the length between the first electrode and the third electrode. When the device is a diode, the length of the sub-region 2012' of the first semiconductor layer may be greater than the size of the anode. Preferably, the length is 1 - 10 micrometers.

[0087] It is not difficult to understand that the doping concentration of N-type atoms such as silicon or germanium with adjustable width of the coexistence region 2011 / 2013 of different doped atoms in the first semiconductor layer 201 may be uniformly distributed or non-uniformly distributed. For example, it gradually decreases along the direction of the first electrode perpendicular to the substrate 100, that is, from the first surface 2011 vertically pointing to the second surface 2012. The doping depth of N-type atoms such as silicon or germanium may be less than or equal to the thickness of the first semiconductor layer. Figure 1 The regions 2011 and 2013 in [reference] are discrete or continuous. Figure 2 The region 2011 in [reference] is continuous. Preferably, the doping depth of impurity atoms in the region 2011 may be less than the doping depth of impurity atoms in the region 2013 to further meet the requirement of more uniform electric field distribution between the gate and the drain. The regions 2011 / 2013 may be regular regions, or each may be an irregular region, or any combination of the above. The setting of the regions is also used to adapt to the requirement of uniform electric field.

[0088] It should be noted that the regions 2011 / 2013 do not show the depletion of the two-dimensional charge carrier gas by the P-type nitride layer, thus maintaining good transport properties.

[0089] The sub-region 2012’ in the first semiconductor layer 201 corresponds to the region of the gate or the anode, and the size of this sub-region 2012’ can also be precisely controlled, thereby achieving the previously described length dimension. The existence of this region 2012’ enables the interface formed by the first or third semiconductor layer and the second semiconductor layer to have no 2DEG at the interface due to the depletion of the first semiconductor layer without applying a bias voltage. That is to say, in this region 2012’, the electrical activity of P-GaN is still retained. Since reducing the length of the portion 2012’ can effectively reduce the on-resistance of the device, it is also beneficial to reduce the size of the device and improve the wafer area utilization rate. However, it should also be pointed out that too short a length may lead to a large leakage current when the device is reverse-biased. Exemplarily, when the semiconductor device is a HEMT / HHMT, the length of this region can be 2-4 microns; when the semiconductor device is a diode, this region can be 6-8 microns.

[0090] In the above device structure, an intrinsic or unintentionally doped GaN layer can also be grown at the position of the first semiconductor layer, and the first semiconductor layer (P-GaN) layer is disposed on the second semiconductor layer, and the corresponding treatment of the first semiconductor layer (P-GaN) layer is performed as described above.

[0091] However, it should be noted that, compared with the structure in which the first semiconductor layer (P-GaN) is disposed above the second semiconductor layer and then the corresponding region doping treatment is performed, for the structure in which the first semiconductor layer (P-GaN) is disposed below the second semiconductor layer and then the corresponding region doping treatment is performed, since the distance between the gate electrode and the first / third semiconductor layer is relatively close, performance tests show that this setting method has better performance, such as being more conducive to obtaining a higher threshold voltage and better process control to avoid damage, etc. Therefore, in this embodiment, it is most preferred to use the structure in which the first semiconductor layer (P-GaN) is disposed below the second semiconductor layer and then the corresponding region doping treatment is performed.

[0092] It can be understood that although the setting of the first semiconductor layer in the above device is described by taking P-GaN as an example, those skilled in the art know that when the device is a HHMT, the first semiconductor layer can be set as N-GaN, and the co-doping types existing in the sub-region 2011 and the sub-region 2013 are correspondingly and adaptively changed, so that the overall region 2011 / 2013 in the first semiconductor layer 201 where the doped atoms coexist presents a P-type, weakly N-type morphology, high-resistance state or insulating state, and the other parts are set correspondingly according to the foregoing HEMT method.

[0093] Second Embodiment

[0094] Now refer to Figures 3-11An exemplary description will be given of a manufacturing method for manufacturing a semiconductor device of the first embodiment. It should be understood that although the semiconductor device in this embodiment takes HEMT and diode as examples, it is only for illustrative purposes and does not limit the type of the semiconductor device.

[0095] Step 100: Provide a substrate 100. For the selection of the substrate 100 material, refer to the description in the first embodiment and will not be elaborated here.

[0096] Step 200: Form the first semiconductor layer 201 on the first surface of the substrate 100. The first semiconductor layer 201 includes a P-type nitride semiconductor, such as P-GaN. Here, it is preferred to form the first semiconductor layer 201 by a material growth method, such as by epitaxial growth, so as to avoid damage to the crystal structure caused by ion implantation. The doping pattern of the first semiconductor layer can be as described in the first embodiment and will not be elaborated here.

[0097] Step 300: Form a mask layer 206 on the first semiconductor layer 201, and then only retain the mask corresponding to the position of the subsequent gate region or anode region, and ion-implant N-type impurities such as Si, Ge, or ion-implant atoms such as N, Ar, C, Fe. Thus, the regions 2011 / 2013 in the first semiconductor layer not protected by the mask are formed to present an overall N-type, weakly P-type morphology, or a state with a higher resistance value or an insulating state than the region 2012 of the first semiconductor layer protected by the mask.

[0098] It can be understood that corresponding masks can also be designed according to specific requirements, and parameters such as injection dose and time can be adjusted so that the region 2011 presents an overall N-type, weakly P-type, high resistance value or insulating state. The size, shape, depth, doping concentration, etc. of the region are all adjustable and controllable.

[0099] Then remove the mask, and repair the lattice through heat treatment to reduce the damage caused by ion implantation.

[0100] In this embodiment, the regions 2011 / 2013 in the first semiconductor layer 201 not protected by the mask are formed to present an overall N-type, weakly P-type morphology, or a state with a higher resistance value or an insulating state than the region 2012 of the first semiconductor layer protected by the mask through ion implantation. This manufacturing method has simple process manufacturing and control, and avoids P-GaN being very close to the drain electrode, thereby causing a sharp reduction in the breakdown voltage resistance of the device.

[0101] Step 400: Form the second semiconductor 202 on the processed first semiconductor layer 201, thereby forming a two-dimensional charge carrier gas at the interface between the second semiconductor layer and the first semiconductor layer. It should be understood that a third semiconductor layer 203 can also be epitaxially grown on the processed first semiconductor layer 201 first, and then the second semiconductor layer 202 can be formed thereon.

[0102] Step 500: Form a passivation layer 400 on the second semiconductor layer 202.

[0103] Step 600: Form openings at corresponding positions of the passivation layer 400 and the second semiconductor layer 202 to form the source electrode 301 and the drain electrode 303 respectively, and form an opening at a corresponding position of the passivation layer 400 to form the gate electrode 302 on the second semiconductor layer 202, or form openings at corresponding positions of the passivation layer 400 and the second semiconductor layer 202 to form the cathode 304 and the anode 305 respectively.

[0104] Step 700: Optionally, form a second insulating layer 401 between the second semiconductor layer 202 and the gate electrode 402.

[0105] It can be understood that before step 200, a nucleation layer, a buffer layer, etc. can be formed on the substrate 100 first.

[0106] Third Embodiment

[0107] Now refer to Figures 12-15 to exemplarily describe another manufacturing method for manufacturing the semiconductor device of the first embodiment.

[0108] The difference between this manufacturing method and the foregoing manufacturing method is only that:

[0109] Step 300: Deposit a material layer 207 containing an N-type impurity to be diffused in the first semiconductor layer 201. For example, a silicon-containing material layer, a germanium-containing material layer, or a material layer containing amorphous carbon or iron element, etc. Then perform photolithography and etching on the material layer 207 to remove the material layer corresponding to the position of the subsequent formed gate region or anode region, then heat to diffuse the impurity material into the first semiconductor layer 201, and then remove the material layer 207.

[0110] It can be understood that step 300 can also adopt a stripping process: a mask layer with an opening is formed on the first semiconductor layer 201, and then a material layer 207 of N-type impurities to be diffused is formed on the mask layer, for example, a silicon-containing material layer, a germanium-containing material layer, or a material layer containing amorphous carbon or iron elements, etc. By stripping the mask layer, only the material layer of the second type of doping atoms at the mask opening is left, and then the second type of doping atoms diffuse into the first semiconductor layer from the material layer through heat treatment.

[0111] It can be understood that corresponding masks, doping doses, time and other parameters can also be designed according to specific requirements so that the whole presents regions of N-type, weak P-type, high resistance or insulating states, and their sizes, shapes, depths, doping concentrations, etc. are adjustable and controllable.

[0112] It can be understood that the above method of introducing impurities by diffusion, since the ion implantation method is not adopted, the implementation and control of the process are very simple, and compared with the ion implantation method, its production cost is lower, and there is no damage caused by ion implantation, which is more conducive to the improvement of device performance.

[0113] Fourth Embodiment

[0114] Refer to Figures 16-17 to describe the semiconductor device according to the fourth embodiment.

[0115] The difference between the fourth embodiment and the first embodiment is that the region in the first semiconductor layer 201 where there is no coexistence of two different atoms, that is, the region 2012 where the P-type impurity electroactivity is retained, not only includes the region corresponding to the gate or the anode, but also includes the sub-region 2012" starting from the edge F1 of the source or the edge F1 of the cathode away from the gate or the anode.

[0116] Then a body electrode 306 that makes an ohmic contact with the first semiconductor layer is formed on the sub-region 2012". It should be noted that although the body electrode 306 is located on the sub-region 2012" in this embodiment, the body electrode can also be located at other positions as long as it makes an ohmic contact with the second region 2012 of the first semiconductor layer.

[0117] The body electrode 306 can be physically connected, electrically connected to the source electrode, or not electrically connected to the source electrode.

[0118] Fifth Embodiment

[0119] Now refer to Figures 18-24 to exemplarily describe the manufacturing method for manufacturing the semiconductor device of the fourth embodiment.

[0120] The difference between the manufacturing method and the manufacturing method in the third embodiment lies in steps 300 and 600. The remaining steps are the same as those in the manufacturing method of the third embodiment:

[0121] Step 300: Deposit a material layer 207 containing impurities to be diffused in the first semiconductor layer 201, such as a silicon-containing material layer, a germanium-containing material layer, a carbon-containing material layer, an iron-containing material layer, etc. Then, perform photolithography and etching on the material layer 207 to remove the material layer corresponding to the position of the subsequent gate region or anode region, and remove the material layer corresponding to the position of the subsequent source or cathode away from the gate or anode, that is, remove the material layer in the sub-regions 2012” and 2012’. Then, heat to cause the impurity material to diffuse into the first semiconductor layer 201, and then remove the material layer 207.

[0122] It can be understood that step 300 can also be similar to the steps of the lift-off process described in the third embodiment. By setting a mask opening, depositing the material layer 207, and removing the material layer in the regions 2012” and 2012’ by lifting off the mask layer, and then the second type of doping atoms diffuse from the material layer into the sub-regions 2011 / 2013 in the first semiconductor layer through heat treatment.

[0123] It can be understood that corresponding masks, doping doses, time and other parameters can also be designed according to specific requirements, so that the size, shape, depth, number, doping concentration, etc. of the regions showing N-type, weakly P-type, high resistance or insulating states can be adjusted and controlled.

[0124] Step 600: Form openings at corresponding positions of the passivation layer 400 and the second semiconductor layer 202 to respectively form the source electrode 301, the drain electrode 303 and the body electrode 306, and form an opening at a corresponding position of the passivation layer 400 to form a gate 302 on the second semiconductor layer, or form openings at corresponding positions of the passivation layer 400 and the second semiconductor layer 202 to respectively form the cathode 304, the anode 305 and the body electrode 306.

[0125] Sixth Embodiment

[0126] Refer to Figures 25-28 to describe the manufacturing method of the semiconductor device according to the fourth embodiment.

[0127] The difference between the sixth embodiment and the fifth embodiment lies in step 300:

[0128] Step 300: A mask layer is formed on the first semiconductor layer 201, and then the mask layer corresponding to the position of the subsequently formed gate region or anode region is retained, and the mask layer 206 corresponding to the position of the source or the cathode away from the gate or the anode is retained, that is, the regions 2012” and 2012’ are covered by the mask layer, and N-type impurities such as Si and Ge are ion-implanted, or atoms such as N, Ar, C, and Fe are ion-implanted. Thus, the overall morphology of the unmasked first semiconductor layer presents an N-type, weak P-type morphology, or a state with a higher resistance value or an insulating state than that of the masked first semiconductor layer.

[0129] It can be understood that corresponding masks can also be designed according to specific requirements, and parameters such as injection dose and time can be adjusted to make the size, shape, depth, doping concentration, etc. of the regions presenting an N-type, weak P-type, high resistance value, or insulating state adjustable and controllable.

[0130] The Seventh Embodiment

[0131] An electronic device, which can be a voltage regulator, a rectifier, an inverter, a charger, etc. The electronic device includes any one of the semiconductor devices in the above embodiments, and the semiconductor device constitutes a basic component unit in the electronic power device.

[0132] The above content of the present disclosure has been described in combination with specific embodiments, but those skilled in the art should understand that these descriptions are exemplary and not a limitation on the protection scope of the present disclosure. Those skilled in the art can make various variations and modifications according to the spirit and principle of the present disclosure, and these variations and modifications are also within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: A substrate; An interface for generating a two-dimensional charge carrier gas; A first electrode and a second electrode; A first semiconductor layer formed on the substrate and containing first-type doping atoms, in which a first region where the first-type doping atoms are not electroactive or the electroactivity of the first-type doping atoms is partially compensated and a second region where the first-type doping atoms are electroactive are formed; A portion coplanar with the first region is included in the second region; Wherein the doping concentration of the first-type doping atoms in the first semiconductor layer is set such that: the direction perpendicular to the substrate of the first electrode, that is, the direction from the first surface to the second surface of the first semiconductor layer, gradually increases, or is set in a manner that is high at both ends and low in the middle in the direction perpendicular to the substrate of the electrode; wherein, the second surface of the first semiconductor layer is closer to the substrate than the first surface.

2. The semiconductor device according to claim 1, wherein the first region is a co-doped region of first-type doping atoms and second-type doping atoms, the second region is a first-type doping atom doped region, and the first region does not deplete the two-dimensional charge carrier gas at its corresponding interface, and a sub-region in the second region substantially depletes the two-dimensional charge carrier gas at its corresponding interface.

3. The semiconductor device according to claim 1, when the semiconductor device is a HEMT or a diode, the first region is entirely N-type, weakly P-type, high-resistance type or insulating type; when the semiconductor device is a HHMT, the first region is entirely P-type or weakly N-type, high-resistance type or insulating type.

4. The semiconductor device according to claim 1, wherein the thickness of the first region is less than or equal to the thickness of the second region.

5. The semiconductor device according to claim 1, wherein the first region at least corresponds to the region between the first electrode and the second electrode.

6. The semiconductor device according to claim 1, wherein when the semiconductor device is a HEMT / HHMT, the projection of a sub-region in the second region relative to the substrate is less than or equal to the projection range of the second electrode relative to the substrate; when the semiconductor device is a diode, the projection of a sub-region in the second region relative to the substrate is greater than the projection range of the second electrode relative to the substrate.

7. The semiconductor device according to claim 2, wherein the second-type doping atoms are N-type or atoms that can produce a deep level effect, the first-type doping atoms are P-type atoms, or the second-type doping atoms are P-type or atoms that can produce a deep level effect, and the first-type doping atoms are N-type.

8. The semiconductor device according to claim 2, wherein the doping concentration of the second-type doping atoms is greater than 10% of the doping concentration of the first-type doping atoms.

9. The semiconductor device according to claim 2, wherein the doping concentration of the second-type doping atoms is uniformly distributed along the direction perpendicular to the substrate of the first electrode or gradually decreases along the direction from the first surface to the second surface of the first semiconductor layer.

10. The semiconductor device according to claim 7, wherein the N-type doping atoms are silicon or germanium, and the P-type doping atoms are magnesium.

11. The semiconductor device according to claim 7, wherein the atoms capable of producing deep-level effects are nitrogen, carbon, iron, or argon, and the P-type doping atoms are magnesium.

12. The semiconductor device according to claim 1, wherein the first region is continuous or discrete; or the shape of each cross-section of the first region is regular or irregular.

13. The semiconductor device according to claim 12, wherein when the first region is discrete, the thicknesses of the first regions are equal or unequal.

14. The semiconductor device according to claim 1, further comprising a second semiconductor layer formed on the first semiconductor layer, and a two-dimensional charge carrier gas is formed at the interface between the first semiconductor layer and the second semiconductor layer.

15. The semiconductor device according to claim 14, further comprising a third semiconductor layer formed on the first semiconductor layer, and a two-dimensional charge carrier gas is formed at the interface between the third semiconductor layer and the second semiconductor layer.

16. The semiconductor device according to claim 14, wherein a passivation layer is further provided on the second semiconductor layer.

17. The semiconductor device according to claim 1, wherein a nucleation layer, a buffer layer, or an insertion layer is further provided on the substrate.

18. The semiconductor device according to claim 1, wherein the first electrode is a cathode and the second electrode is an anode.

19. The semiconductor device according to claim 1, wherein the first electrode is a source or a drain, and the second electrode is a gate.

20. The semiconductor device according to claim 1, further comprising a body electrode, and the body electrode is electrically connected to or not connected to the first electrode.

21. The semiconductor device according to claim 1, further comprising a body electrode, and the body electrode forms an ohmic contact with the second region of the first semiconductor layer.

22. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming an interface for generating a two-dimensional charge carrier gas; forming at least a first electrode and a second electrode; forming a first semiconductor layer doped with first-type doping atoms on the substrate, and doping a second-type doping atom in a first region in the first semiconductor layer such that the first-type doping atoms in the first region are not electroactive or the electroactivity of the first-type doping atoms is partially compensated, and the first-type doping atoms in a second region in the first semiconductor layer where the second-type doping atoms are not doped are electroactive; wherein the doping concentration of the first-type doping atoms in the first semiconductor layer is set such that the doping concentration gradually increases in the direction perpendicular to the substrate of the first electrode, that is, in the direction from the first surface to the second surface of the first semiconductor layer, or is set in a manner that is high at both ends and low in the middle in the direction perpendicular to the substrate of the electrode; wherein, the second surface of the first semiconductor layer is closer to the substrate than the first surface.

23. The manufacturing method of claim 22, wherein the second type of doping atoms are N-type or atoms capable of producing a deep energy level effect, and the first type of doping atoms are P-type atoms, or the second type of doping atoms are P-type or atoms capable of producing a deep energy level effect, and the first type of doping atoms are N-type. 24 . The manufacturing method of claim 22 , wherein a doping concentration of the second type of doping atoms is greater than 10% of a doping concentration of the first type of doping atoms. 25 . The manufacturing method according to claim 22 , wherein the doping concentration of the second type doping atoms is uniformly distributed along a direction perpendicular to the substrate of the first electrode or gradually decreases along a direction from the first surface to the second surface of the first semiconductor layer.

26. The manufacturing method according to claim 23, wherein the N-type doping atom is silicon or germanium, the P-type doping atom is magnesium, and the atom capable of producing a deep level effect is carbon, argon, iron or nitrogen. 27 . The manufacturing method of claim 22 , wherein the first region does not deplete the two-dimensional charge carrier gas at its corresponding interface, and a subregion in the second region substantially depletes the two-dimensional charge carrier gas at its corresponding interface.

28. The manufacturing method according to claim 22, wherein the first region is formed in at least the first semiconductor layer corresponding to a region between the first electrode and the second electrode.

29. The manufacturing method according to claim 22, wherein the first region is formed by forming a mask layer on the first semiconductor layer, photolithographically etching the mask layer to form a pattern having openings, and then ion implanting the second type of dopant atoms.

30. The manufacturing method according to claim 29, wherein the opening is selected from: The upper surface of the first semiconductor layer corresponding to the second electrode and the vicinity of the first electrode in a direction away from the second electrode is shielded; or the upper surface of the first semiconductor layer corresponding to the second electrode is shielded.

31. The manufacturing method according to claim 22, wherein the first region is formed by one of the following methods: Method 1: forming a second type dopant atom material layer on the first semiconductor layer, photolithographically etching the material layer to form a pattern having openings, and then diffusing the second type dopant atoms from the material layer into the first semiconductor layer through thermal treatment; Method 2: A mask layer with an opening is formed on the first semiconductor layer, and then a second type of dopant atom material layer is formed on the mask layer. By peeling off the mask layer, only the second type of dopant atom material layer at the mask opening is left, and then the second type of dopant atoms are diffused from the material layer into the first semiconductor layer through heat treatment.

32. The manufacturing method according to claim 31, wherein the opening in the first embodiment is selected from: exposing an upper surface of the first semiconductor layer corresponding to the second electrode and near the first electrode in a direction away from the second electrode; exposing an upper surface of the first semiconductor layer corresponding to the second electrode; The opening in the second method and the opening in the first method are in a complementary pattern.

33. The manufacturing method according to claim 30 or 31, wherein the first region is formed to include continuous or discrete, regular or irregular sub-regions through the opening arrangement, or in the above combined manner.

34. The manufacturing method according to claim 33, wherein the depth of ion implantation or the depth of ion diffusion in each sub-region is less than or equal to the thickness of the first semiconductor layer, and the implantation dose or the diffusion time between the sub-regions is the same or different, or in the above combined manner.

35. The manufacturing method according to claim 22 further includes selectively forming a third semiconductor layer on the first semiconductor layer.

36. The manufacturing method according to claim 35 further includes forming a second semiconductor layer on the first semiconductor layer or the third semiconductor layer, so as to form the two-dimensional charge carrier gas at the interface between the first semiconductor layer and the second semiconductor layer or at the interface between the third semiconductor layer and the second semiconductor layer.

37. The manufacturing method according to claim 36, further including forming a first electrode, a second electrode, and a third electrode; wherein the first electrode and the third electrode are in ohmic contact with the two-dimensional charge carrier gas, and the second electrode forms a Schottky contact with the second semiconductor layer or the first semiconductor layer.

38. The manufacturing method according to claim 36, further including forming an insulating layer between the second electrode and the second semiconductor layer.

39. The manufacturing method according to claim 36, further including forming a passivation layer on the second semiconductor layer; or forming a nucleation layer and / or a buffer layer on the substrate.

40. The manufacturing method according to claims 22-39, further including forming a fourth electrode that is in ohmic contact with the second region of the first semiconductor layer.

41. The manufacturing method according to claim 40, wherein the fourth electrode is electrically connected or not connected to the first electrode.

42. An electronic device, comprising the semiconductor device according to any one of claims 1-21.

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