Chip simulation method, device, equipment, system and storage medium

Abstract

Embodiments of the present application disclose a chip simulation method, device, equipment, system and storage medium, and belong to the technical field of chip simulation. The method comprises the following steps: sending vector type to-be-processed data corresponding to chip simulation to a preset vector execution module; obtaining a first data processing result of data processing of the vector type to-be-processed data by the vector execution module, so as to generate a simulation result corresponding to the chip simulation according to the first data processing result. The technical scheme of the embodiments of the present application separates the vector operation in the chip simulation and processes it independently, so that the efficiency of the chip simulation is improved.

Description

Technical Field

[0001] This invention relates to the field of chip simulation technology, and specifically discloses a chip simulation method, apparatus, device, system, and storage medium. Background Technology

[0002] With the development of technology, the processing power requirements for chips (such as CPU chips) are becoming increasingly demanding, making chip simulation crucial. Taking CPU chips as an example, simulation is performed by building a corresponding CPU chip simulation environment. Currently, there are two main methods for building a CPU chip simulation environment: one is to directly implement the CPU chip simulation algorithm using a hardware description language and integrate it into an application-specific integrated circuit (ASIC) to build the simulation environment; the other is to use a high-level language to abstract the CPU chip and establish an object-oriented CPU chip simulation system.

[0003] In CPU chip simulation, scalar and vector operations need to be performed, which affects the running speed of CPU chip simulation. In particular, vector operations can severely reduce the running speed of CPU chip simulation, resulting in low efficiency of CPU chip simulation. Summary of the Invention

[0004] This invention provides a chip simulation method, apparatus, device, system, and storage medium to improve the efficiency of chip simulation.

[0005] In a first aspect, embodiments of the present invention provide a chip simulation method, comprising:

[0006] The vector-type data to be processed corresponding to the chip simulation is sent to the preset vector execution module;

[0007] The first data processing result of the vector execution module on the vector data to be processed is obtained, and the simulation result corresponding to the chip simulation is generated based on the first data processing result.

[0008] In a second aspect, embodiments of the present invention provide a computer device, the computer device including a memory and a processor;

[0009] Memory is used to store computer programs;

[0010] A processor is used to execute computer programs and, in executing computer programs, implement chip emulation methods as described above.

[0011] Thirdly, embodiments of the present invention provide a chip simulation method, including:

[0012] Obtain the vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module;

[0013] The vector-type data to be processed is processed to obtain the first data processing result, which is then used by the scalar execution module to generate the simulation result corresponding to the chip simulation.

[0014] Fourthly, embodiments of the present invention provide a chip emulation device, which includes a memory and a processor;

[0015] Memory is used to store computer programs;

[0016] A processor is used to execute computer programs and, in executing computer programs, implement chip emulation methods as described above.

[0017] Fifthly, embodiments of the present invention also provide a chip emulation system, which includes the computer equipment described above and the chip emulation device described above, wherein the computer equipment and the chip emulation device are communicatively connected.

[0018] In a sixth aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to implement the chip emulation method described above.

[0019] This invention discloses a chip simulation method, apparatus, device, and storage medium. By sending the vector-type data to be processed corresponding to the chip simulation to a preset vector execution module, the vector execution module processes the vector-type data to obtain a corresponding first data processing result. Based on the first data processing result, the simulation result corresponding to the chip simulation is generated. That is, the vector operations in the chip simulation are separated and processed independently, thereby improving the efficiency of chip simulation. Attached Figure Description

[0020] Figure 1 This is a schematic block diagram of a chip simulation system provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic block diagram of a chip emulation device provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic flowchart illustrating the steps of a chip simulation method provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic flowchart illustrating the steps of another chip simulation method provided in this embodiment of the invention;

[0025] Figure 6This is a schematic diagram of the CPU chip simulation process provided in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0028] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0029] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0031] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no inherent meaning. Therefore, "module," "part," or "unit" may be used interchangeably.

[0032] Embodiments of the present invention provide a chip emulation method, apparatus, device, system, and storage medium to improve the efficiency of chip emulation. The chip includes, but is not limited to, a CPU chip, and may also include other integrated chips. This invention uses a CPU chip as an example to explain the various embodiments of the invention.

[0033] Please see Figure 1 , Figure 1This is a schematic block diagram of a chip emulation system provided in an embodiment of the present invention. The chip emulation system 100 includes a computer device 10 and a chip emulation apparatus 20. A wired or wireless communication connection is established between the computer device 10 and the chip emulation apparatus 20.

[0034] Computer device 10 includes a scalar execution module 11, wherein the scalar execution module 11 includes a software simulation unit 111; chip simulation device 20 includes a vector execution module 21, wherein the vector execution module 21 includes a vector core unit 211. The scalar execution module 11 is implemented using a high-level language, and the vector execution module 21 is implemented using a semi-custom hardware system, thereby accelerating vector operations.

[0035] For example, the vector execution module 21 includes, but is not limited to, hardware systems that can provide vector operation optimization, such as field-programmable gate arrays (FPGAs) and graphics processing units (GPUs).

[0036] The vector core unit 211 is a hardware execution system optimized for vector operations. It can accelerate vector operations in CPU simulation based on the scalar vector deployment in CPU chip simulation, while ensuring the flexible construction of the scalar execution module 11.

[0037] The scalar execution module 11 sends configuration information corresponding to the CPU chip simulation to the vector execution module 21. After receiving the configuration information, the vector execution module 21 completes the configuration of the vector core unit 211 according to the configuration information, and sends the corresponding configuration completion information to the scalar execution module 11 after the vector core unit 211 is configured. After receiving the configuration completion information sent by the vector execution module 21, the soft simulation unit 111 starts to perform CPU chip system simulation, continuously sending vector-type data to be processed and the corresponding data parameters to the vector execution module 21. The data parameters include, but are not limited to, data size, data attributes, data operation type, etc. The vector core unit 211 continuously acquires the vector-type data to be processed and the corresponding data parameters, processes the data, and feeds back the results to the scalar execution module 11. The scalar execution module 11 decides whether to end the simulation and give the simulation results based on the feedback results.

[0038] For example, the scalar execution module 11 also includes a scheduling unit 112 and a message transmission unit 113, and the vector execution module 21 also includes a shared storage unit 212 and a cache identifier unit 213.

[0039] After determining the vector deployment for CPU chip simulation, the scheduling unit 112 determines the construction method of the vector core unit 211 according to the deployment and sends the corresponding script file to the vector execution module 21. The vector execution module 21 constructs the vector core unit 211 according to the script file.

[0040] The message transmission unit 113 continuously sends vector-type data to be processed and corresponding data parameters to the vector execution module 21. The vector core unit 211 continuously acquires the vector-type data to be processed and the corresponding data parameters, processes them, and returns the results. Furthermore,

[0041] The message transmission unit 113 can optimize the granularity of scalar and vector partitioning, that is, optimize the partitioning granularity of vector data to be processed and scalar data to be processed, thereby giving full play to the performance of scalar-vector separation and improving simulation efficiency.

[0042] The shared storage unit 212 is connected to the scalar execution module 11 via a physical connection, for example, through a corresponding physical interface. Vector-type data to be processed is stored in the shared storage unit 212.

[0043] The cache identifier unit 213 is used to store the physical address and data parameters corresponding to the vector data to be processed. The vector core unit 211 performs data indexing in the shared storage unit 212 according to the physical address cached in the cache identifier unit 213, obtains the corresponding vector data to be processed, and performs data processing.

[0044] The scalar execution module 11 and the vector execution module 21 transmit data through shared memory via physical address mapping, reducing the number of data moves and further improving the efficiency of CPU chip simulation.

[0045] For example, the simulation operations of the vector core unit 211 and the soft simulation unit 111 can be performed in parallel. That is, on one side, the soft simulation unit 111 processes the scalar data to be processed, and on the other side, the vector core unit 211 processes the vector data to be processed, thereby improving the operating efficiency of the CPU chip simulation system.

[0046] Please see Figure 2 , Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. The computer device 200 includes a processor 201 and a memory 202, wherein the processor 201 and the memory 202 are connected via a bus.

[0047] The memory 202 may include a non-volatile storage medium and internal memory.

[0048] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any chip emulation method.

[0049] The processor 201 provides computing and control capabilities to support the operation of the entire terminal device.

[0050] Internal memory provides an environment for the execution of computer programs stored in non-volatile storage media. When these computer programs are executed by the processor, the processor can perform any chip emulation method.

[0051] Understandable. Figure 2 The structures shown are merely block diagrams of some structures related to the embodiments of the present invention, and do not constitute a limitation on the computer devices on which the embodiments of the present invention are applied. Specific computer devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0052] It should be understood that processor 201 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, the general-purpose processor can be a microprocessor or any conventional processor.

[0053] In some embodiments, the processor is used to run a computer program stored in memory to perform the following steps:

[0054] The vector-type data to be processed corresponding to the chip simulation is sent to the preset vector execution module;

[0055] The first data processing result of the vector execution module on the vector data to be processed is obtained, and the simulation result corresponding to the chip simulation is generated based on the first data processing result.

[0056] In some embodiments, before the processor sends the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module, it is further configured to: send the configuration information corresponding to the chip simulation to the vector execution module, so that the vector execution module can configure the vector core unit according to the configuration information and perform data processing on the vector-type data to be processed through the vector core unit.

[0057] In some embodiments, the vector execution module includes a shared memory unit, which, when the processor sends the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module, is used to:

[0058] The vector-type data to be processed is sent to the shared storage unit so that the vector core unit can retrieve the vector-type data to be processed from the shared storage unit;

[0059] When the processor acquires the first data processing result from the vector execution module's data processing of the vector-type data to be processed, it is used to:

[0060] Retrieve the first data processing result stored in the shared storage unit.

[0061] In some embodiments, the vector execution module further includes a cached identifier unit, and the processor is further configured to implement:

[0062] The data parameters corresponding to the vector data to be processed are sent to the cache identifier unit so that the vector kernel unit can obtain the data parameters from the cache identifier unit and determine the processing method of the vector data to be processed based on the data parameters, and perform data processing on the vector data to be processed.

[0063] In some embodiments, the processor is further configured to: perform data processing on scalar data to be processed corresponding to chip simulation, and obtain a second data processing result;

[0064] After acquiring the first data processing result from the vector execution module's data processing of the vector-type data to be processed, the processor is also used to implement:

[0065] Simulation results are generated based on the first and second data processing results.

[0066] In some embodiments, the processor is further configured to configure the granularity of the partitioning of vector-type data to be processed and scalar-type data to be processed.

[0067] Please see Figure 3 , Figure 3 This is a schematic block diagram of a chip emulation device provided in an embodiment of the present invention. The chip emulation device 300 includes a processor 301 and a memory 302, wherein the processor 301 and the memory 302 are connected via a bus.

[0068] The memory 302 may include a non-volatile storage medium and internal memory.

[0069] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any chip emulation method.

[0070] The processor 301 provides computing and control capabilities to support the operation of the entire terminal device.

[0071] Internal memory provides an environment for the execution of computer programs stored in non-volatile storage media. When these computer programs are executed by the processor, the processor can perform any chip emulation method.

[0072] Understandable. Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the embodiments of the present invention, and does not constitute a limitation on the chip emulation device to which the embodiments of the present invention are applied. A specific chip emulation device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0073] It should be understood that processor 301 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0074] In some embodiments, the processor is used to run a computer program stored in memory to perform the following steps:

[0075] Obtain the vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module;

[0076] The vector-type data to be processed is processed to obtain the first data processing result, which is then used by the scalar execution module to generate the simulation result corresponding to the chip simulation.

[0077] In some embodiments, when the processor acquires the vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module, it is used to:

[0078] Obtain the physical address corresponding to the vector-type data to be processed stored in the cache identifier unit;

[0079] Data is indexed in the shared storage unit based on the physical address to obtain vector-type data to be processed. The scalar execution module then sends the vector-type data to be processed to the shared storage unit.

[0080] In some embodiments, when the processor performs data processing on vector-type data to be processed, it is used to implement:

[0081] The data parameters corresponding to the vector-type data to be processed stored in the cache identifier unit are obtained, wherein the scalar execution module sends the data parameters to the cache identifier unit;

[0082] Determine the processing method for the vector-type data to be processed based on the data parameters, and then perform data processing according to the processing method for the vector-type data to be processed.

[0083] In some embodiments, after processing the vector-type data to be processed and obtaining a first data processing result, the processor is further configured to:

[0084] The first data processing result is saved to the shared storage unit, and the physical address corresponding to the first data processing result is saved to the cache identifier unit.

[0085] For ease of understanding, the following will combine Figure 1 Chip simulation system in Figure 2 Computer equipment and Figure 3 The chip simulation apparatus described above provides a detailed introduction to the chip simulation method provided in the embodiments of the present invention. It should be noted that the chip simulation system, computer equipment, and chip simulation apparatus described above do not constitute a limitation on the application scenarios of the chip simulation method provided in the embodiments of the present invention.

[0086] like Figure 4 As shown, Figure 4 This is a schematic flowchart illustrating the steps of a chip simulation method provided in an embodiment of the present invention. This method can be used in the aforementioned computer equipment to improve the efficiency of chip simulation.

[0087] Specifically, such as Figure 4 As shown, the method includes steps S101 to S102.

[0088] S101. Send the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module.

[0089] In CPU chip simulation, scalar and vector operations correspond to scalar and vector data to be processed, respectively. Before performing scalar and vector operations, the scalar and vector data to be processed are distinguished, and the determined vector data to be processed is sent to a pre-configured vector execution module. This vector execution module, designed and implemented on a semi-custom hardware system, accelerates the execution of vector operations.

[0090] For example, the vector execution module includes, but is not limited to, hardware systems such as FPGAs and GPUs, which can provide vector operation functions.

[0091] After receiving the vector-type data to be processed, the vector execution module performs corresponding data processing on the data. This data processing includes operations such as time-domain / frequency-domain conversion and data encoding / decoding.

[0092] In some embodiments, before step S101, the method may further include: sending the configuration information corresponding to the chip simulation to the vector execution module, so that the vector execution module can configure the vector core unit according to the configuration information and perform data processing on the vector data to be processed through the vector core unit.

[0093] Before performing the simulation, the vector core unit of the vector execution module is configured. The vector core unit is the core unit of the vector execution module. It is a hardware execution system optimized for vector operations and is used to process vector data. It can accelerate vector operations in CPU simulation.

[0094] Optionally, the configuration information corresponding to the CPU chip simulation is sent to the vector execution module. After receiving the configuration information, the vector execution module configures its vector core unit according to the configuration information. For example, taking the configuration of a Digital Signal Processing (DSP) core execution unit as an example, by sending the DSP core configuration information for communication application chip simulation to the vector execution module, the vector execution module constructs the DSP core execution unit according to the configuration information to handle large-scale vector operations in mobile communication.

[0095] For example, after determining the vector deployment for CPU chip simulation, the construction method of the vector core units in the vector execution module is determined according to the deployment, and the corresponding script file is sent to the vector execution module. After receiving the script file, the vector execution module configures the vector core units according to the script file.

[0096] After the vector core unit is configured, the vector execution module sends back the corresponding configuration completion information. Upon receiving this information, the CPU chip simulation begins, and the corresponding vector-type data to be processed is sent to the vector execution module. After receiving the vector-type data, the vector execution module performs corresponding data processing on the data through the configured vector core unit to obtain the corresponding data processing result. For ease of description, the data processing result obtained from processing the vector-type data will be referred to as the first data processing result.

[0097] S102. Obtain the first data processing result of the vector execution module on the vector data to be processed, so as to generate the simulation result corresponding to the chip simulation based on the first data processing result.

[0098] The vector kernel unit performs corresponding data processing on the vector-type data to be processed, and after obtaining the first data processing result, it acquires the first data processing result. For example, after obtaining the first data processing result, the vector execution module returns the first data processing result, and the system directly receives the first data processing result returned by the vector execution module.

[0099] For example, after obtaining the first data processing result through data processing, the vector execution module saves the first data processing result to the corresponding storage device. Therefore, the first data processing result can be obtained by querying the storage device.

[0100] The first data processing result serves as intermediate information for CPU chip simulation. Based on the first data processing result, it is determined whether the CPU chip simulation is complete, and the corresponding simulation result is generated.

[0101] In some embodiments, while sending vector-type data to be processed to the vector execution module, data processing is performed on the corresponding scalar-type data to be processed to obtain the data processing result corresponding to the scalar-type data to be processed. For ease of description, the data processing result obtained by processing the scalar-type data to be processed is referred to as the second data processing result below.

[0102] That is, while processing the vector-type data to be processed through the vector execution module, it also processes the scalar-type data to be processed through itself, and obtains the first data processing result corresponding to the vector-type data to be processed and the second data processing result corresponding to the scalar-type data to be processed.

[0103] Based on the first and second data processing results, a comprehensive analysis is performed on the first and second data processing results to generate simulation results corresponding to the CPU chip simulation.

[0104] In some embodiments, the vector execution module further includes a shared storage unit for storing the data to be processed and the corresponding data processing results. Sending the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module may include: sending the vector-type data to be processed to the shared storage unit so that the vector core unit can obtain the vector-type data to be processed from the shared storage unit; obtaining the first data processing result of the vector execution module processing the vector-type data to be processed may include: obtaining the first data processing result stored in the shared storage unit.

[0105] By sending vector-type data to be processed to the shared storage unit of the vector execution module, the shared storage unit stores the vector-type data to be processed. The vector core unit can directly retrieve the stored vector-type data to be processed from the shared storage unit, perform data processing on the retrieved vector-type data to obtain the corresponding first data processing result, and save the first data processing result to the shared storage unit. Afterwards, the first data processing result corresponding to the vector-type data to be processed can be retrieved by accessing the shared storage unit.

[0106] In some embodiments, the vector execution module further includes a cache identifier unit, which can be used to store data parameters corresponding to the vector-type data to be processed. These data parameters include, but are not limited to, data size, data attributes, data operation types, etc. Simultaneously with sending the vector-type data to be processed to the shared storage unit, the data parameters corresponding to the vector-type data to be processed are also sent to the cache identifier unit. The vector kernel unit retrieves the stored vector-type data to be processed from the shared storage unit and obtains the data parameters corresponding to the vector-type data to be processed from the cache identifier unit. Based on the data parameters, it determines the processing method for the vector-type data to be processed and then performs data processing according to that processing method on the vector-type data to be processed.

[0107] In some embodiments, the physical address corresponding to the vector-type data to be processed stored in the shared memory unit is saved in the cache identifier unit. The vector kernel unit, by obtaining the physical address corresponding to the vector-type data to be processed saved in the cache identifier unit, can index the data in the shared memory unit based on the physical address, retrieve the corresponding vector-type data to be processed, and then process the vector-type data. That is, data transfer is performed through shared memory with physical address mapping, reducing the number of data moves and thus improving the simulation speed.

[0108] In some embodiments, the data parameters corresponding to the vector-type data to be processed, along with the vector-type data to be processed, can be sent to the shared storage unit. The shared storage unit stores the vector-type data to be processed and the data parameters corresponding to the vector-type data to be processed in association. The vector core unit can retrieve the stored vector-type data to be processed and the data parameters corresponding to the vector-type data to be processed from the shared storage unit, determine the processing method for the vector-type data to be processed based on the data parameters, and then perform data processing on the vector-type data to be processed according to that processing method.

[0109] In some embodiments, the granularity of the partitioning of vector-type and scalar-type data to be processed is configured periodically or when a preset condition is met; that is, the granularity of scalar and vector partitioning is optimized. For example, if the time consumed by each cache identifier unit call is the same, the scalar and vector processes are integrated, the granularity of scalar and vector partitioning is optimized, and the number of cache identifier unit calls is reduced.

[0110] like Figure 5 As shown, Figure 5 This is a schematic flowchart illustrating a chip simulation method according to another embodiment of the present invention. This chip simulation method can be applied in a chip simulation device and includes steps S201 and S202.

[0111] S201. Obtain the vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module.

[0112] In CPU chip simulation, before performing scalar and vector operations, a scalar execution module configured in the computer device first distinguishes between scalar and vector data to be processed, and then sends the determined vector data to the chip simulation device. The scalar execution module is implemented using a high-level language. For example, the chip simulation device may have a pre-built vector execution module, which is designed and implemented on a semi-custom hardware system to accelerate vector operations. For example, the vector execution module may include, but is not limited to, hardware systems such as FPGAs and GPUs, which can provide vector operation functionality. The chip simulation device receives the vector data to be processed sent by the scalar execution module through the vector execution module.

[0113] For example, the vector execution module includes a vector core unit, through which it receives vector-type data to be processed sent by the scalar execution module.

[0114] In some embodiments, obtaining the vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module may include: obtaining the physical address corresponding to the vector-type data to be processed stored in the cache identifier unit; and performing data indexing in the shared memory unit according to the physical address to obtain the vector-type data to be processed, wherein the scalar execution module sends the vector-type data to be processed to the shared memory unit.

[0115] The vector execution module includes a shared memory unit and a cache identifier unit. The shared memory unit stores vector-type data to be processed, and the cache identifier unit stores the physical addresses corresponding to the vector-type data. By obtaining the physical address of the vector-type data to be processed stored in the cache identifier unit, the corresponding vector-type data to be processed is retrieved by indexing the data in the shared memory unit based on the physical address. In other words, data transfer is performed through shared memory with physical address mapping, reducing the number of data moves and thus improving the simulation speed.

[0116] S202. Perform data processing on the vector-type data to be processed to obtain the first data processing result, so that the scalar execution module can generate the simulation result corresponding to the chip simulation based on the first data processing result.

[0117] After obtaining the vector-type data to be processed, data processing is performed on the vector-type data to obtain the corresponding data processing result. For ease of description, the data processing result corresponding to the vector-type data to be processed will be referred to as the first data processing result below.

[0118] In some embodiments, data processing of vector-type data to be processed may include: obtaining data parameters corresponding to the vector-type data to be processed stored in the cache identifier unit, wherein the scalar execution module sends the data parameters to the cache identifier unit; determining the processing method of the vector-type data to be processed according to the data parameters, and performing data processing on the vector-type data to be processed according to the processing method.

[0119] The data parameters corresponding to the vector-type data to be processed include, but are not limited to, data size, data attributes, and data operation types. The cache identifier unit can also be used to store the data parameters corresponding to the vector-type data to be processed. The scalar execution module sends the vector-type data to be processed to the shared storage unit, and simultaneously sends the corresponding data parameters to the cache identifier unit. By retrieving the saved vector-type data to be processed from the shared storage unit and obtaining the corresponding data parameters from the cache identifier unit, the processing method for the vector-type data to be processed is determined based on these parameters, and then the data is processed according to that method.

[0120] In some embodiments, after processing the vector-type data to be processed and obtaining the first data processing result, the process may include: saving the first data processing result to a shared storage unit and saving the physical address corresponding to the first data processing result to a cache identifier unit.

[0121] After obtaining the first data processing result corresponding to the vector-type data to be processed, the first data processing result is not directly returned to the scalar execution module. Instead, it is saved to the shared storage unit and its corresponding physical address in the shared storage unit, and then saved to the cache identifier unit. Subsequently, the scalar execution module retrieves the first data processing result by obtaining the physical address corresponding to the first data processing result saved in the cache identifier unit and performing a data index in the shared storage unit.

[0122] The scalar execution module generates simulation results corresponding to the CPU chip simulation based on the first data processing result. For example, the scalar execution module processes the corresponding scalar data to be processed, obtaining a data processing result corresponding to the scalar data to be processed. For ease of description, the data processing result obtained from processing the scalar data to be processed is referred to as the second data processing result. That is, while processing the vector data to be processed through the vector execution module, the scalar execution module processes the scalar data to be processed simultaneously, obtaining the first data processing result corresponding to the vector data to be processed, and the second data processing result corresponding to the scalar data to be processed. The scalar execution module performs a comprehensive analysis of the first and second data processing results to generate the simulation results corresponding to the CPU chip simulation.

[0123] like Figure 6 As shown, the detailed process of CPU chip simulation is as follows:

[0124] Step 1: The scalar execution module sends configuration information to the vector execution module;

[0125] Step 2: The vector execution module completes the vector core unit configuration based on the configuration information;

[0126] Step 3: The scalar execution module continuously updates and sends vector-type data to be processed, as well as the corresponding data parameters;

[0127] Step 4: The vector kernel unit continuously acquires vector-type data to be processed, as well as the corresponding data parameters;

[0128] Step 5: The vector kernel unit processes the vector-type data to be processed and feeds back the results to the scalar execution module;

[0129] Step 6: The scalar execution module determines whether the simulation is complete based on the feedback result; if yes, it proceeds to Step 7; otherwise, it returns to Step 3.

[0130] Step 7: Output simulation results.

[0131] In the above embodiments, the vector-type data to be processed corresponding to the chip simulation is sent to a preset vector execution module. The vector execution module processes the vector-type data to be processed to obtain the corresponding first data processing result. Based on the first data processing result, the simulation result corresponding to the chip simulation is generated. That is, the vector operation in the chip simulation is separated and processed independently, thus improving the efficiency of chip simulation.

[0132] The embodiments of the present invention also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, and a processor executing the program instructions to implement any of the chip simulation methods provided in the embodiments of the present invention.

[0133] For example, when the computer program is loaded by the processor, it can perform the following steps:

[0134] The vector-type data to be processed corresponding to the chip simulation is sent to the preset vector execution module;

[0135] The first data processing result of the vector execution module on the vector data to be processed is obtained, and the simulation result corresponding to the chip simulation is generated based on the first data processing result.

[0136] The computer-readable storage medium can be an internal storage unit of the chip emulation system described in the foregoing embodiments, such as the hard disk or memory of the chip emulation system. Alternatively, the computer-readable storage medium can be an external storage device of the chip emulation system, such as a pluggable hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the chip emulation system.

[0137] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip emulation method, comprising: The scalar execution module sends the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module; The vector execution module can accelerate vector operations in CPU simulation; the scalar execution module and the vector execution module are communicatively connected; the vector execution module includes a cache identifier unit; the cache identifier unit is used to store the data parameters and physical addresses corresponding to the vector data to be processed; The scalar execution module obtains the first data processing result of the vector execution module performing data processing on the vector-type data to be processed; The scalar execution module processes the scalar data to be processed corresponding to the chip simulation to obtain a second data processing result. Based on the first data processing result and the second data processing result, simulation results are generated; Where the time consumed by each call to the cache identifier unit is the same, the scalar execution module optimizes the granularity of the partitioning of the vector-type data to be processed and the scalar-type data to be processed by integrating scalar and vector processes.

2. The chip simulation method according to claim 1, characterized in that, Before sending the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module, the process includes: The configuration information corresponding to the chip simulation is sent to the vector execution module so that the vector execution module can configure the vector core unit according to the configuration information and perform data processing on the vector data to be processed through the vector core unit.

3. The chip simulation method according to claim 2, characterized in that, The vector execution module further includes a shared storage unit, and the step of sending the vector-type data to be processed corresponding to the chip simulation to the preset vector execution module includes: The vector-type data to be processed is sent to the shared storage unit so that the vector core unit can retrieve the vector-type data to be processed from the shared storage unit; The step of obtaining the first data processing result of the vector execution module processing the vector-type data to be processed includes: Obtain the first data processing result stored in the shared storage unit.

4. The chip simulation method according to claim 3, characterized in that, The method further includes: The data parameters corresponding to the vector data to be processed are sent to the cache identifier unit so that the vector kernel unit can obtain the data parameters from the cache identifier unit and determine the processing method of the vector data to be processed according to the data parameters, and perform data processing on the vector data to be processed according to the processing method.

5. A chip emulation method, comprising: The vector execution module acquires the vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module; The vector execution module can accelerate vector operations in CPU simulation; the scalar execution module and the vector execution module are communicatively connected; the vector execution module includes a cache identifier unit; The cache identifier unit is used to store the data parameters and physical address corresponding to the vector-type data to be processed; The vector-type data to be processed is processed to obtain a first data processing result, which is then used by the scalar execution module to generate the simulation result corresponding to the chip simulation based on the first data processing result and the second data processing result. The second data processing result is obtained by the scalar execution module processing the scalar-type data to be processed corresponding to the chip simulation. Wherein, when it is determined that the time consumed by each call to the cache identifier unit is the same, the scalar execution module optimizes the granularity of the partitioning of the vector-type data to be processed and the scalar-type data to be processed by integrating scalar and vector processes.

6. The chip simulation method according to claim 5, characterized in that, The acquisition of vector-type data to be processed corresponding to the chip simulation sent by the scalar execution module includes: Obtain the physical address corresponding to the vector-type data to be processed stored in the cache identifier unit; The vector-type data to be processed is obtained by indexing data in the shared storage unit according to the physical address, wherein the scalar execution module sends the vector-type data to be processed to the shared storage unit.

7. The chip simulation method according to claim 6, characterized in that, The data processing of the vector-type data to be processed includes: The data parameters corresponding to the vector-type data to be processed stored in the cache identifier unit are obtained, wherein the scalar execution module sends the data parameters to the cache identifier unit; The processing method for the vector-type data to be processed is determined based on the data parameters, and the vector-type data to be processed is then processed according to the processing method.

8. The chip simulation method according to claim 6 or 7, characterized in that, After processing the vector-type data to be processed to obtain the first data processing result, the process includes: The first data processing result is saved to the shared storage unit, and the physical address corresponding to the first data processing result is saved to the cache identifier unit.

9. A computer device, the computer device comprising a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and, in executing the computer program, implement the chip emulation method as described in any one of claims 1 to 4.

10. A chip emulation device, the chip emulation device comprising a memory and a processor; Memory is used to store computer programs; A processor for executing a computer program and, in executing the computer program, implementing the chip emulation method as described in any one of claims 5 to 8.

11. A chip emulation system, the chip emulation system comprising a computer device as claimed in claim 9 and a chip emulation apparatus as claimed in claim 10, wherein the computer device is communicatively connected to the chip emulation apparatus.

12. A computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the chip emulation method as described in any one of claims 1 to 4; Alternatively, the chip emulation method as described in any one of claims 5 to 8 can be implemented.

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