Memory device, dynamic random access memory array, and memory array

Abstract

A memory device, a dynamic random access memory array, and a memory array. The memory device includes a memory array having: a first memory cell in a first column of the memory array; a second memory cell in the first column of the memory array; a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell; and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.

Description

Technical Field

[0001] The present disclosure generally relates to a memory device, a dynamic random access memory array, and a memory array. Background Art

[0002] Memory devices are used in a variety of applications. A memory device is composed of a plurality of memory cells, which are typically arranged in an array of multiple rows and multiple columns. One type of memory cell is a Dynamic Random Access Memory (DRAM) cell. In some applications, compared with other types of memory devices based on memory cells, memory devices based on DRAM cells may be more favored because, compared with, for example, Static Random Access Memory (SRAM) cells, DRAM cells have lower cost, smaller area, and can accommodate more data. As applications require more and more memory, the number of DRAM cells in a memory device is constantly increasing. In addition, with the growing demand for product diversification, the cooperation between the circuit design and semiconductor manufacturing of DRAM memories has become increasingly important. However, current DRAM memories have limitations in the way these memories are configured and operated. Summary of the Invention

[0003] The present disclosure provides a memory device including a memory array, the memory array comprising: a first memory cell in a first column of the memory array; a second memory cell in the first column of the memory array; a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell; and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.

[0004] The present disclosure further provides a dynamic random access memory (DRAM) array, including: a plurality of DRAM cells, a first read bit line, a second read bit line, and a write bit line. The plurality of DRAM cells are arranged along a plurality of rows and a plurality of columns, where each row extends in a row direction, and where each column extends in a column direction, the column direction being perpendicular to the row direction. The first read bit line extends in the column direction and is connected to a first group of DRAM cells among these DRAM cells, the first group of DRAM cells being arranged along a first group of the rows in the first column of these columns. The second read bit line extends in the column direction and is connected to a second group of DRAM cells among these DRAM cells, the second group of DRAM cells being arranged along a second group of the rows in the first column. The write bit line extends in the column direction and is connected to each DRAM cell in the first group of DRAM cells in the first column and each DRAM cell in the second group of DRAM cells in the first column.

[0005] The present disclosure further provides a memory array, including: a plurality of memory cells, a first interconnect layer, a second interconnect layer, and a third interconnect layer. The plurality of memory cells are arranged along a first column of a plurality of rows and a plurality of columns, where each row extends in a row direction, and where each column extends in a column direction, the column direction being perpendicular to the row direction. The first interconnect layer is used to define a first read bit line in the layout design of the memory array, where the first interconnect layer is connected to a first group of these memory cells. The second interconnect layer is used to define a second read bit line in the layout design of the memory array, where the second interconnect layer is connected to a second group of these memory cells. The third interconnect layer is used to define a first read word line in the layout design of the memory array, where the third interconnect layer is connected to a first memory cell in the first group of these memory cells and a second memory cell in the second group of these memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of each feature may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 FIG. is an exemplary block diagram of a computing system according to some embodiments;

[0008] Figure 2 FIG. is an exemplary circuit diagram of a three transistor (3T) dynamic random access memory (DRAM) cell according to some embodiments;

[0009] Figure 3 FIG. is according to some embodiments of Figure 2 exemplary layout of DRAM cells;

[0010] Figure 4 Exemplary DRAM array according to some embodiments;

[0011] Figures 5A to 5C According to some embodiments Figure 4 Exemplary layout diagram of the DRAM array;

[0012] Figures 6A to 6C According to some embodiments Figure 2 Additional exemplary configuration of the DRAM cell;

[0013] Figure 7 Another exemplary DRAM array according to some embodiments.

[0014]

Symbol description

[0015] 2Y: Height

[0016] 4X: Width

[0017] 100: Computing system

[0018] 105: Host device

[0019] 110: Memory device

[0020] 115: Input device

[0021] 120: Output device

[0022] 125A, 125B, 125C: Interface

[0023] 130A, 130N: CPU core

[0024] 135: Standard cell layout application

[0025] 140: Memory controller

[0026] 145: Memory array

[0027] 150: Manufacturing tool

[0028] 200, 320A - 320G, 550, 560, 575: DRAM cell

[0029] 205: Storage capacitor

[0030] 210, 555, 580: Write transfer gate transistor

[0031] 215, 565, 585: Read pull - down transistor

[0032] 220, 385, 390, WBL[0], WBL[1]: Write bit line

[0033] 225, 365, 370, 375, 380, WWL[0], WWL[1], WWL[2], WWL[3]: Write Word Line

[0034] 230, 570, 590: Read Pass Gate Transistor

[0035] 235: Read Bit Line

[0036] 240, 355, 360, 600, 605, 610, 615, RWL[0], RWL[1], RWL[2], RWL[3]: Read Word Line

[0037] 245, 395, 400, 405, 410A - 410H: Layout Design

[0038] 250, 255: Active Region

[0039] 260: Y - direction

[0040] 265, 270, 275: Gate Structure

[0041] 280: X - direction

[0042] 285, 290, 295, 300, 305, 310: Local Interconnect Layer

[0043] 315, 595: DRAM Array

[0044] 325: First Column

[0045] 330, 345, ARBL[0], ARBL[1]: First Read Bit Line

[0046] 335, 350, BRBL[0], BRBL[1]: Second Read Bit Line

[0047] 340: Second Column

[0048] 415, 420, 425, 430, 435, 440, 445, 450, 455, 460, 465, 470, 475, 480, 485, 490, 495, 500, 505, 510, 515, 520, 525, 530: Interconnect Layer

[0049] 535: M1 Interconnect Layer

[0050] 540: M3 Interconnect Layer

[0051] 545: M2 Interconnect Layer

[0052] VSS: Ground

[0053] X - direction

[0054] Y - direction Detailed implementation manners

[0055] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, this disclosure may repeat element symbols and / or letters in each example. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0056] In addition, for ease of description, spatial relative terms (such as "beneath", "below", "lower", "above", "upper", and similar terms) may be used herein to describe the relationship of one element or feature shown in the figures to another element (or elements) or feature (or features). In addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the elements during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and thus the spatial relative descriptors used herein may be interpreted similarly.

[0057] Now refer to Figure 1 , an exemplary block diagram of a computing system 100 according to some embodiments of this disclosure. A circuit or layout designer may use the computing system 100 to perform standard cell layout of a circuit. As used herein, a "circuit" or "integrated circuit" is an interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor elements configured to achieve a desired functionality. The computing system 100 includes a host device 105 associated with a memory device 110. The host device 105 can be used to receive inputs from one or more input devices 115 and provide outputs to one or more output devices 120. The host device 105 can be used to communicate with the memory device 110, the input device 115, and the output device 120 via appropriate interfaces 125A, 125B, and 125C, respectively. The computing system 100 can be implemented in various computing devices, such as a computer (e.g., a desktop computer, a laptop computer, a server, a data center, etc.), a tablet computer, a personal digital assistant, a mobile device, other handheld or portable devices, or any other computing unit suitable for performing standard cell layout using the host device 105.

[0058] The input device 115 may include any of a variety of input technologies, such as a keyboard, a stylus, a touch screen, a mouse, a trackball, a keypad, a microphone, voice recognition, motion recognition, a remote control, an input port, one or more buttons, a dial, a joystick, and any other input peripheral device that is associated with the host device 105 and allows an external source, such as a user (e.g., a circuit or layout designer), to input information (e.g., data) into the host device 105 and send instructions to the host device 105. Similarly, the output device 120 may include a variety of output technologies, such as an external memory, a printer, a speaker, a display, a microphone, a light-emitting diode, a headset, a video device, and any other output peripheral device that is configured to receive information (e.g., data) from the host device 105. The "data" input to the host device 105 and / or output from the host device 105 may include any of the following various types of data: text data, circuit data, signal data, semiconductor component data, graphic data, combinations of the foregoing, or other types of analog and / or digital data suitable for processing using the computing system 100.

[0059] The host device 105 includes one or more processing units / processors or is associated with one or more processing units / processors, such as central processing unit (CPU) cores 130A-130N. The CPU cores 130A-130N may be implemented as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other type of processing unit. Each of the CPU cores 130A-130N is configured to execute instructions for running one or more applications of the host device 105. In some embodiments, the instructions and data required to run one or more applications may be stored in the memory device 110. The host device 105 is also configured to store the results of running one or more applications in the memory device 110. Accordingly, the host device 105 is configured to request the memory device 110 to perform various operations. For example, the host device 105 may request the memory device 110 to read data, write data, update or delete data, and / or perform administrative or other operations.

[0060] One such application program that the host device 105 can be used to run can be the standard cell layout application program 135. The standard cell layout application program 135 can be part of a computer-aided design or electronic design automation software suite, and the user of the host device 105 can use these software suites to generate the standard cell layout of a circuit (also referred to herein as "layout", "layout diagram", "layout design", and the like). The standard cell layout of a circuit can show various components and connections of the circuit to be manufactured. For example, the standard cell layout can show one or more active regions, gate electrodes, source and drain electrodes, metal wires, via contacts, openings for bonding pads, one or more metal layers, power supplies, input and output signals, clock signals, etc. that represent various components of the circuit; and how these components are interconnected when placed in a semiconductor substrate (such as a silicon wafer) or on a semiconductor substrate. The standard cell layout can be implemented by following a design process, which can include one or more of logic design, physical design, or placement and routing. The standard cell layout can be represented by one or more data files such as the GDSII file format or the DFII file format. In other embodiments, other file formats can be used. Thus, a circuit designer can use the standard cell layout application program 135 to generate the standard cell layout of a circuit. In some embodiments, the instructions required to execute or run the standard cell layout application program 135 can be stored in the memory device 110. The standard cell layout application program associated with the instructions from the memory device 110 can be executed by one or more of the CPU cores 130A - 130N.

[0061] Still referring to Figure 1, the memory device 110 includes a memory controller 140, which is used to read data from or write data to the memory array 145. In some embodiments, the memory array 145 may include various volatile and / or non-volatile memories. For example, in some embodiments, the memory array 145 may include a NAND flash memory core, a NOR flash memory core, a static random access memory (SRAM) core, a dynamic random access memory (DRAM) core, a magnetoresistive random access memory (MRAM) core, a phase change memory (PCM) core, a resistive random access memory (ReRAM) core, a 3D XPoint memory core, a ferroelectric random-access memory (FeRAM) core, and other types of memory cores suitable for use in the memory array. Generally speaking, the memory array 145 may include any of the following: random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), hard disk drive, flash drive, memory tape, optical drive, cloud memory, or any combination of main memory and / or secondary memory suitable for performing the operations described herein.

[0062] The memories within the memory array 145 can be individually and independently controlled by the memory controller 140. In other words, the memory controller 140 can be used to communicate individually and independently with each memory within the memory array 145. By communicating with the memory array 145, the memory controller 140 can be used to read data from or write data to the memory array in response to instructions received from the host device 105. Although Figure 1The memory controller 140 shown is part of the memory device 110, but in some embodiments, the memory controller 140 can be part of the host device 105 or part of another component of the computing system 100 and be associated with the memory device. The memory controller 140 can be implemented as software, hardware, firmware, or a logic circuit in a combination of the above to perform the functions described herein. For example, in some embodiments, the memory controller 140 can be used to retrieve instructions associated with the standard cell layout application 135 stored in the memory array 145 of the memory device 110 after receiving a request from the host device 105.

[0063] In some embodiments, the computing system 100 can also be associated with various fabrication tools 150. Among them, the fabrication tools 150 can be used to prepare and fabricate a set of masks based on the standard cell layout generated by the standard cell layout application 135. This set of masks can define the geometries of the photolithography steps used during the semiconductor fabrication of the circuit. Although the fabrication tools 150 are Figure 1 shown as separate from the host device 105, in some embodiments, at least some of the functions of the fabrication tools can be implemented by the host device, such as by the standard cell layout application 135 or another application associated with the standard cell layout application.

[0064] To prepare a set of masks, the fabrication tools 150 can be used to convert the standard cell layout of the circuit into a representative data file (RDF). Subsequently, the RDF can be used to fabricate a set of physical masks to fabricate the circuit.

[0065] In some embodiments, preparing the set of masks may include performing optical proximity correction (OPC) using lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, and the like in a standard cell layout. In some embodiments, a mask rule checker (MRC) of the fabrication tool 150 may utilize a set of mask generation rules to check the standard cell layout undergoing the process in the OPC. The mask generation rules may contain certain geometric and / or connectivity constraints to ensure sufficient tolerance to account for variability in the semiconductor manufacturing process and the like. In some embodiments, the MRC may modify the standard cell layout to compensate for the constraints during fabrication of the set of masks. In some embodiments, preparing the set of masks may also include resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof.

[0066] In some embodiments, preparation of the set of masks may further include lithography process checking (LPC), which may simulate the processes implemented to fabricate a circuit. The LPC may simulate these processes based on the standard cell layout to generate a simulated fabrication apparatus for the circuit. The LPC may consider various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof, to simulate the fabrication of the circuit. In some embodiments, after the simulated fabricated component has been generated by the LPC, if the simulated component does not meet certain design rules, the OPC and / or MRC may be repeated to further refine the standard cell layout.

[0067] To fabricate this set of masks, a mask writer can convert an RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple electron beams can be used to form a mask pattern on a semiconductor wafer to form a mask. In some embodiments, the mask pattern can include one or more opaque regions or one or more transparent regions. A radiation beam (such as an ultraviolet (UV) beam) for exposing an image-sensitive material layer (e.g., photoresist) coated on a semiconductor wafer can be blocked by the opaque regions and transmitted through the transparent regions. In one example, the mask pattern can include a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions to form a mask. In other embodiments, other or additional techniques can be used to fabricate the mask.

[0068] Once the mask is fabricated, a manufacturing entity (e.g., a manufacturing facility or a semiconductor fabrication plant) can use the fabricated mask to fabricate a circuit. In some embodiments, fabricating the circuit can involve using the mask (or masks) to deposit one or more materials in or on the semiconductor wafer. The semiconductor wafer can include a silicon substrate or other substrate with material layers formed thereon. The semiconductor wafer can further include one or more of various doped regions, dielectric features, multilevel interconnects, and the like formed using one or more of the masks.

[0069] It should be understood that although the manufacturing tool 150 is described as performing certain operations to prepare this set of masks and subsequently fabricate this set of masks, in some embodiments, the respective processes can be different from those described. In some embodiments, additional or other processes or operations can be used to prepare this set of masks and fabricate this set of masks. It should also be understood that Figure 1 only some components of the computing system 100 are illustrated and described. However, the computing system 100 can include other components, such as various batteries and power supplies, network connection interfaces, routers, switches, external memory systems, controllers, etc. Generally speaking, the computing system 100 can include any of various hardware, software, and / or firmware components needed or considered necessary in performing the functions described herein. Similarly, the host device 105, the input device 115, the output device 120, and the memory device 110 including the memory controller 140 and the memory array 145 can each include other hardware, software, and / or firmware components considered necessary or needed in performing the functions described herein.

[0070] Turn to Figure 2, An exemplary circuit diagram of a three-transistor or 3T dynamic random access memory (DRAM) cell 200 in accordance with some embodiments of the present disclosure is illustrated. The 3T DRAM cell 200 includes a storage capacitor 205, a first plate of the storage capacitor 205 is connected to a first terminal (e.g., a source terminal) of a write pass gate transistor 210 and a first terminal (e.g., a gate terminal) of a read pull-down transistor 215, and a second plate of this storage capacitor is connected to ground. A second terminal (e.g., a drain terminal) of the write pass gate transistor 210 is connected to a write bit line 220, and a third terminal (e.g., a gate terminal) of the write pass gate transistor 210 is connected to a write word line 225. A second terminal (e.g., a source terminal) of the read pull-down transistor 215 is connected to ground, and a third terminal (e.g., a drain terminal) of the read pull-down transistor is connected to a first terminal (e.g., a source terminal) of a read pass gate transistor 230. A second terminal (e.g., a drain terminal) of the read pass gate transistor 230 is connected to a read bit line 235, and a third terminal (e.g., a gate terminal) of the read pass gate transistor 230 is connected to a read word line 240. In some embodiments, each of the write pass gate transistor 210, the read pull-down transistor 215, and the read pass gate transistor 230 is an n-type transistor. In other embodiments, one or more of the write pass gate transistor 210, the read pull-down transistor 215, and the read pass gate transistor 230 may be p-type transistors, as discussed below in Figures 6A to 6C the alternative configurations of

[0071] The write transfer gate transistor 210 can be used to store or write data (e.g., charge) in the storage capacitor 205, while the read pull-down transistor 215 and the read transfer gate transistor 230 can be used to read the data (e.g., charge) stored in the storage capacitor. To write data to the storage capacitor 205, the write transfer gate transistor 210 can be turned on by applying an appropriate voltage at the write word line 225, and the data stored in the storage capacitor can be applied to the write bit line 220. When the write transfer gate transistor 210 is turned on, the data applied to the write bit line 220 is stored in the storage capacitor 205. To read data from the storage capacitor 205, the read transfer gate transistor 230 can be turned on by applying an appropriate voltage at the read word line 240, and the data read from the storage capacitor can be read from the read bit line 235. When the storage capacitor 205 stores logic 1 data, the read pull-down transistor 215 is turned on, and when the read transfer gate transistor 230 is turned on, the read pull-down transistor pulls the read bit line 235 to ground (e.g., because the read pull-down transistor is connected to ground) to read the inversion of the data stored in the storage capacitor. When the storage capacitor 205 stores logic 0 data, the read pull-down transistor 215 remains off, and even when the read transfer gate transistor 230 is turned on, the read bit line remains unchanged and maintains the previous state (e.g., pre-charged state).

[0072] Although the DRAM cell 200 is described herein as a 3T DRAM cell, in other embodiments, the DRAM cell 200 can take other configurations. For example, in some embodiments, the DRAM cell 200 can be a 4T DRAM cell, an 8T DRAM cell, a 10T DRAM cell, a 12T DRAM cell, etc. In other embodiments, the DRAM cell 200 can include any other number of transistors. Further, in other embodiments, the configuration of the DRAM cell 200 can vary. For example, the write transfer gate transistor 210, the read pull-down transistor 215, and the read transfer gate transistor 230 can be connected in different ways.

[0073] Referring to Figure 3, FIG. 245 illustrates an exemplary layout design of a 3T DRAM cell 200 according to some embodiments of the present disclosure. The layout design 245 may define features of active elements (e.g., write transfer gate transistor 210, read pull-down transistor 215, read transfer gate transistor 230, storage capacitor 205) of the DRAM cell 200 along an active region. The “active region” may be a fin region of one or more three-dimensional field-effect transistors (e.g., fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors including nanosheet transistors and nanowire transistors), or an oxide-definition (OD) region of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs). The active region may define source or drain terminals of the active elements (e.g., the transistors and storage capacitors described above). The gate terminals of those transistors may be defined by gate structures, which may be formed of one or more conductive materials (e.g., polysilicon, metal) and may cover corresponding portions of the active region to define the write transfer gate transistor 210, the read pull-down transistor 215, and the read transfer gate transistor 230.

[0074] For example, the layout design 245 illustrates active regions 250 and 255, which define source and drain regions of the write transfer gate transistor 210, the read pull-down transistor 215, and the read transfer gate transistor 230. In some embodiments, the active regions 250 and 255 may extend in the Y direction 260. The layout design 245 also illustrates gate structures 265, 270, and 275, which cover the active regions 250 and / or 255 and define the gate terminals of the write transfer gate transistor 210, the read pull-down transistor 215, and / or the read transfer gate transistor 230. In some embodiments, the gate structures 265-275 extend in the X direction 280. In some embodiments, the active regions 250, 255 may extend in the X direction 280 and the gate structures 265-275 may extend in the Y direction 260. Portions of the active regions 250, 255 disposed on either side of a respective one of the gate structures 265-275 may define source and drain terminals of the corresponding transistors (e.g., the write transfer gate transistor 210, the read pull-down transistor 215, and the read transfer gate transistor 230).

[0075] Thus, for example, a gate structure 270 covering the active region 250 defines the gate terminal of the write transfer gate transistor 210, while portions of the active region on either side of the gate structure define the source and drain terminals of the write transfer gate transistor. In some embodiments, the source and drain terminals of the write transfer gate transistor 210 may be connected to other connections (e.g., the source and drain terminals of other transistors) via local interconnections (e.g., LC0) 285 and 290. For example, the local interconnection 290 may be used to connect the source terminal of the write transfer gate transistor 210 to the storage capacitor 205.

[0076] A gate structure 275 covering the active region 255 defines the gate terminal of the read transfer gate transistor 230, where portions of the active region on either side of the gate structure define the source and drain terminals of the read transfer gate transistor 230. In some embodiments, the source and drain terminals of the read transfer gate transistor 230 may be connected to other connections (e.g., the source and drain terminals of other transistors) via local interconnect layers (e.g., LC0) 295 and 300. For example, the source terminal of the read transfer gate transistor 230 may be connected to the drain terminal of the read pull-down transistor 215 via the local interconnect layer 300. A gate structure 265 covering the active region 255 defines the gate terminal of the read pull-down transistor 215, where portions of the active region on either side of the gate structure define the source and drain terminals of the read pull-down transistor 215. In some embodiments, the source and drain terminals of the read pull-down transistor 215 may be connected to other connections (e.g., the source and drain terminals of other transistors) via the local interconnect layer (e.g., LC0) 300 and the local interconnect layer (e.g., LC0) 305. For example, the drain terminal of the read pull-down transistor 215 may be connected to the source terminal of the read transfer gate transistor 230 via the local interconnect layer 300.

[0077] A local interconnect layer 310 (e.g., LC1) connecting the source terminal of the write transfer gate transistor 210 (e.g., the local interconnect 290) and the gate structure 265 defines the storage capacitor 205. Additionally, the gate structures 270 and 275 defining the gate terminals of the write transfer gate transistor 210 and the read transfer gate transistor 230 may be connected to the write bit line 220, the write word line 225, the read bit line 235, and the read word line 240, respectively. In Figure 2The layout designs of the write bit line 220, the write word line 225, the read bit line 235, and the read word line 240 are not illustrated. In some embodiments, the connections between the gate structures 270 and 275 and the write bit line 220, the write word line 225, the read bit line 235, and the read word line 240 may be facilitated by electrically connecting their gate structures to an interconnect layer, such as a metal 0 (e.g., M0), a metal 1 (e.g., M1) layer, etc. Such interconnect layers are described in more detail below.

[0078] In some embodiments, the local interconnect layers 285, 290, 295, 300, 305 may each be used to connect the source / drain terminals of corresponding transistors to another connection, and may include a conductive material, such as one or more metal materials, and may be formed using local interconnect 0 or LC0 layer. Similarly, in some embodiments, the local interconnect layer 310 may be used to connect the source / drain terminals of corresponding transistors to another connection, and may include a conductive material, such as one or more metal materials, and may be formed using local interconnect 1 or LC1 layer. In some embodiments, the LC1 layer may be formed above the LC0 layer. In other words, on the layout design 245, the LC0 layer may be sandwiched between the LC1 layer and the active elements. Further, in some embodiments, the LC1 layer may extend perpendicular to the LC0 layer. For example, in some embodiments, the LC0 layer may extend in the X direction 280, while the LC1 layer may extend in the Y direction 260.

[0079] Now turn to Figure 4, FIGURE 315 illustrates an exemplary DRAM array in accordance with some embodiments of the present disclosure. The DRAM array 315 includes DRAM cells 200 and a plurality of additional DRAM cells 320A - 320G arranged in an array of rows and columns. Each of the plurality of DRAM cells 320A - 320G is similar to the DRAM cell 200 and is thus not described further. Thus, similar to the DRAM cell 200, each of the plurality of DRAM cells 320A - 320G includes, in series, a write transfer gate transistor (e.g., write transfer gate transistor 210) connected to a storage capacitor (e.g., storage capacitor 205), a read pull-down transistor (e.g., read pull-down transistor 215) connected to the storage capacitor, and a read transfer gate transistor (e.g., read transfer gate transistor 230) connected to the read pull-down transistor. Terminals (e.g., drain terminals) of the write transfer gate transistors of the DRAM cell 200 and each of the plurality of additional DRAM cells 320A - 320G may be connected to a write bit line (e.g., write bit line 220), and terminals of the read transfer gate transistors of the DRAM cell 200 and each of the plurality of additional DRAM cells 320A - 320G may be connected to a read bit line (e.g., read bit line 235). Further, terminals (e.g., gate terminals) of the write transfer gate transistors and the read transfer gate transistors of each of the DRAM cells and the plurality of additional DRAM cells 320A - 320G in the DRAM array 315 may be connected to a write word line (e.g., write word line 225) and a read word line (e.g., read word line 240), respectively.

[0080] Each row of the DRAM array 315 extends in the X direction (e.g., X direction 280), which is also referred to herein as the row direction, and each column of the DRAM array extends in the Y direction (e.g., Y direction 260), which is also referred to herein as the column direction. In other embodiments, each row in the DRAM array 315 may extend in the Y direction (e.g., Y direction 260), the Y direction may be the row direction, and each column may extend in the X direction (e.g., X direction 260), the X direction may be the column direction. Generally speaking, the row direction and the column direction are perpendicular or substantially perpendicular to each other. Although two columns and four rows of DRAM cells are illustrated in the DRAM array 315, in other embodiments, the DRAM array may include more or less than four rows and / or more or less than two columns. Generally speaking, DRAM cells may be formed at the intersections of rows and columns. Further, due to the current (I) flowing through those bit lines and word lines and the metal resistance (R) provided by those bit lines and word lines, each DRAM cell of the DRAM array 315 connected to the bit lines and word lines experiences a voltage drop (e.g., current-resistance voltage drop or IR drop). Depending on the number of rows in the DRAM array 315, DRAM cells farther from the read / write block (not shown in the figure) experience a greater IR drop than DRAM cells closer to the read / write block. In some embodiments, the IR drop caused by the bit lines may be more significant than the IR drop caused by the word lines. The longer the bit line, the greater the IR drop of the DRAM cell farthest from the read / write block. Further, due to the capacitance of the storage capacitor (e.g., storage capacitor 205), during the read operation in the DRAM array 315, the read current (I 单元 ) in the read bit line (e.g., read bit line 235) is smaller compared to the read operation in other types of memory arrays (e.g., SRAM memory arrays). Due to the smaller read current, the read operation in the DRAM array 315 is slower than, for example, the read operation in the SRAM array.

[0081] To increase the read speed in the DRAM array 315, the present disclosure provides a mechanism that reduces the effect of the capacitance of the storage capacitor 205 and increases the read current in the read bit line 235. In known DRAM arrays, the terminals (e.g., drain terminals) of the read transfer gates (e.g., read transfer gate 230) of each DRAM cell in a given column are connected to the same read bit line (e.g., read bit line 235). The present disclosure provides a mechanism in which each column of the DRAM array 315 includes two read bit lines instead of the single read bit line of known DRAM arrays. Specifically, rather than connecting the same read bit line to all DRAM cells in each column, a first read bit line (e.g., ARBL[0], ARBL[1]) can be connected to a first subset of the DRAM cells in each column and a second read bit line (e.g., BRBL[0], BRBL[1]) can be connected to the remaining subset of the DRAM cells in each column, thereby significantly reducing the capacitance in the read bit lines. For example, in some embodiments, if the first read bit line is connected to half of the DRAM cells in each column and the second read bit line is connected to the other half of the DRAM cells in each column, the capacitance in each of the first read bit line and the second read bit line can be half of the capacitance experienced by a single read bit line connected to all DRAM cells in a column. In other words, each of the first read bit line and the second read bit line has a capacitance that is half of the capacitance of the single read bit line of a known DRAM array.

[0082] Accordingly, the first column 325 of the DRAM array 315 includes a first read bit line (ARBL[0]) 330 and a second read bit line (BRBL[0]) 335. Similarly, the second column 340 of the DRAM array 315 includes a first read bit line (ARBL[1]) 345 and a second read bit line (BRBL[1]) 350. Accordingly, each column of the DRAM array 315 includes two read bit lines, rather than a single read bit line of a known DRAM array. Further, the first read bit line 330 and the second read bit line 335 are connected to alternating DRAM cells in the first column 325, and the first read bit line 345 and the second read bit line 350 are connected to alternating DRAM cells in the second column 340. For example, in the first column 325, the first read bit line 330 is connected to DRAM cells 320B and 320F, and the second read bit line 335 is connected to DRAM cells 200 and 320D. Similarly, in the second column 340, the first read bit line 345 is connected to DRAM cells 320C and 320G, and the second read bit line 350 is connected to DRAM cells 320A and 320E. Accordingly, each column of the DRAM array 315 has two read bit lines, where each read bit line is connected to alternating DRAM cells in the corresponding column.

[0083] Further, in some embodiments, a read word line (e.g., read word line 240) may be shared by two adjacent DRAM cells in a particular column. For example, in some embodiments, the read word line 355 (RWL[0]) may be shared by DRAM cells 320D and 320F in the first column 325, and by DRAM cells 320E and 320G in the second column 340. Similarly, the read word line 360 (RWL[1]) may be shared by DRAM cells 200 and 320B in the first column 325, and by DRAM cells 320A and 320C in the second column 340. In some embodiments, as Figure 4 shown, DRAM cells connected to the same read word line are connected to different read bit lines. For example, DRAM cells 320D and 320F are connected to the same read word line (e.g., read word line 355). However, DRAM cell 320D is connected to the second read bit line 335 and DRAM cell 320F is connected to the first read bit line 330. By being connected to different read bit lines, even though two DRAM cells connected to a single read word line may be activated simultaneously during a read operation, data from each DRAM cell can be read on separate read bit lines.

[0084] For example, when starting to read the word line 355 to turn on the read pass gate transistor (e.g., the read pass gate transistor 230), the read pass gate transistors of both DRAM cells 320D and 320F can be turned on, thereby enabling data to be read from each of these DRAM cells. However, since the DRAM cells 320D and 320F are connected to separate read bit lines, the data from these DRAM cells can be read from the read bit lines connected to these DRAM cells. For example, the data from the DRAM cell 320D can be read from the second read bit line 335, and the data from the DRAM cell 320F can be read from the first read bit line 330, thereby enabling two DRAM cells to be read simultaneously, so that the present disclosure can further increase the read speed compared with a known DRAM array in which each DRAM cell is connected to the same read bit line.

[0085] Further, in some embodiments, each DRAM cell in a specific column of the DRAM array 315 can be connected to a separate write word line. For example, in some embodiments, in the first column 325, the DRAM cell 200 can be connected to the write word line 365 (WWL[3]), the DRAM cell 320B can be connected to the write word line 370 (WWL[2]), the DRAM cell 320D can be connected to the write word line 375 (WWL[1]), and the DRAM cell 320F can be connected to the write word line 380 (WWL[0]). Similarly, in the second column 340, the DRAM cell 320A can be connected to the write word line 365 (WWL[3]), the DRAM cell 320C can be connected to the write word line 370 (WWL[2]), the DRAM cell 320E can be connected to the write word line 375 (WWL[1]), and the DRAM cell 320G can be connected to the write word line 380 (WWL[0]). Thus, the write word lines can be shared across all DRAM cells in a specific row (e.g., in the row direction) of the DRAM array 315. Additionally, in some embodiments, each column of the DRAM array 315 can share a common write bit line that extends in the column direction. For example, in some embodiments, each of the DRAM cells 200, 320B, 320D, and 320F in the first column 325 shares the write bit line 385 (WBL[0]), while each of the DRAM cells 320A, 320C, 320E, and 320G in the second column 340 shares the write bit line 390 (WBL[1]).

[0086] By providing two read bit lines in each column of the DRAM array 315 and by sharing a read word line between two consecutive DRAM cells in each column of the DRAM array, the capacitance in the read bit lines is cut in half in each column of the DRAM array as compared to known DRAM arrays. The reduced capacitance in the read bit lines results in an increased read current in the read bit lines, and thus the present disclosure increases the read speed of the read operations in the DRAM array 315 as compared to known DRAM arrays.

[0087] Referring Figures 5A to 5C , FIG. shows an exemplary layout design of a DRAM array 315 in accordance with some embodiments of the present disclosure. Specifically, Figure 5A FIG. shows a layout design 395 of DRAM cells and bit lines (e.g., first read bit lines 330, 345 and second read bit lines 335 and 350), Figure 5B FIG. shows a layout design 400 of read word lines 355 and 360, while Figure 5C FIG. shows a layout design 405 of write word lines 365, 370, 375 and 380. Specifically referring Figure 5A , the layout design 395 corresponds to the DRAM array 315. Thus, the layout design 395 is a combination of layout designs 410A - 410H, where the layout design 410A corresponds to the layout design of the DRAM cell 320B, the layout design 410E corresponds to the layout design of the DRAM cell 320F, the layout design 410B corresponds to the layout design of the DRAM cell 200, the layout design 410F corresponds to the layout design of the DRAM cell 320D, the layout design 410C corresponds to the layout design of the DRAM cell 320A, the layout design 410G corresponds to the layout design of the DRAM cell 320E, the layout design 410D corresponds to the layout design of the DRAM cell 320C, and the layout design 410H corresponds to the layout design of the DRAM cell 320G. Each of the layout designs 410A - 410H is similar to the layout design 245 and is thus not described further.

[0088] The layout design 395 further illustrates that the layout designs 410A and 410E (corresponding to DRAM cells 320B and 320F respectively) share a first read bit line 330, which is represented by the interconnect layer 415, and the layout designs 410B and 410F (corresponding to DRAM cells 200 and 320D respectively) share a second read bit line 335, which is represented by the interconnect layer 420. Further, in some embodiments, the interconnect layer 420 can be shared by 2 DRAM cells in the M0 direction to save routing tracks. The layout design 395 also illustrates that the layout designs 410C and 410G (corresponding to DRAM cells 320A and 320E respectively) share a second read bit line 350, which is represented by the interconnect layer 425, and the layout designs 410D and 410H (corresponding to DRAM cells 320C and 320G respectively) share a first read bit line 345, which is represented by the interconnect layer 430.

[0089] Additionally, the interconnect layer 435 represents a write bit line 385, which is shared by all DRAM cells (e.g., DRAM cells 200, 320B, 320D, and 320F) in the first column 325 of the DRAM array 315, and the interconnect layer 440 represents a write bit line 390, which is shared by all DRAM cells (e.g., DRAM cells 320A, 320C, 320E, and 320G) in the second column 340 of the DRAM array 315. The interconnect layers 445, 455, and 465 represent read word lines 360, while the interconnect layers 450, 460, and 470 represent read word lines 355. The interconnect layer 455 is shared by DRAM cells 200 and 320A, and the interconnect layer 460 is shared by DRAM cells 320D and 320E. The interconnect layers 475 and 505 represent write word lines 370, the interconnect layers 480 and 510 represent write word lines 380, the interconnect layers 485 and 495 represent write word lines 365, and the interconnect layers 490 and 500 represent write word lines 375. The interconnect layers 515, 520, 525, and 530 represent the ground (VSS) connections of the read pull-down transistors of each DRAM cell in the DRAM array 315.

[0090] In some embodiments, each of the interconnect layers 415-530 may include a conductive material, such as one or more metal materials, and may be formed using metal interconnect layers, such as a metal 0 (M0) layer, a metal 1 (M1) layer, a metal 2 (M2) layer, and so on. In some embodiments, the M0 layer may be formed directly above the gate structure (e.g., gate structures 265, 270, 275) such that the M0 layer may be sandwiched between the M1 layer and those gate structures. Similarly, the M1 layer may be sandwiched between the M0 layer and the M2 layer, and the M2 layer may be formed above the M1 layer. The M2 layer may be sandwiched between the M1 layer and the M3 layer, and so on. Further, in some embodiments, the M1 layer may extend perpendicular (or substantially perpendicular) to the M0 layer. For example, in some embodiments, the M0 layer may extend in the Y direction 260, while the M1 layer may extend in the X direction 280. Similarly, the M2 layer may extend perpendicular (or substantially perpendicular) to the M1 layer in the Y direction 260, and so on. In other embodiments, the respective interconnect layers may extend in other directions.

[0091] Further, in some embodiments, the interconnect layers 415 (representing the first read bit line 330), 420 (representing the second read bit line 335), 425 (representing the second read bit line 350), 430 (representing the first read bit line 345), 435 (representing the write bit line 385), 440 (representing the write bit line 390), and 515-530 (representing ground connections) may be formed at the M0 interconnect layer. The interconnect 435 representing the write bit line 385 may be shared by all DRAM cells in the first column 325 of the DRAM array 315. Similarly, the interconnect 440 representing the write bit line 390 may be shared by all DRAM cells in the second column 340 of the DRAM array 315.

[0092] In some embodiments, as Figure 5B shown, the interconnect layers 445-470 representing the read word lines 355 and 360 may be formed at the M1 interconnect layer 535, while as Figure 5C shown, the interconnect layers 475-510 representing the write word lines 365-380 may be formed at the M3 interconnect layer 540. In some embodiments, the M2 interconnect layer 545 (see Figure 5B and Figure 5C ) may be used to connect the M1 layer to the M3 layer. In other embodiments, other levels of interconnect layers are used for the first read bit lines 330 and 345, the second read bit lines 335 and 350, the write bit lines 285 and 390, the ground connections, the read word lines 355 and 360, and / or the write word lines 365-380.

[0093] Further, in some embodiments, an interconnect structure may be used to connect the gate structure to an interconnect layer or to connect one interconnect layer to another interconnect layer. The interconnect structure is represented by the symbol "X" in Figures 5A to 5C . In some embodiments, one or more of the interconnect structures may be via structures that provide electrical connections between the gate structure and the M0 layer, between the M0 layer and the M1 layer, between the M1 layer and the M2 layer, and so on. In other embodiments, the interconnect structure may be other types of conductive structures that are adapted to connect the gate structure to the M0 layer, connect the M0 layer to the M1 layer, connect the M1 layer to the M2 layer, and so on.

[0094] In some embodiments, the layout of each DRAM cell in layout design 395 may have a height and a width. In some embodiments, the layout may have a height Y in the Y direction 260 and a width X in the X direction 280. In the layout design of a known DRAM array, a DRAM array configured in two columns and four rows may have a height of 4Y (e.g., due to the four DRAM cells in the four rows) and a width of 2X (e.g., due to the two DRAM cells in the two columns). In a similar configuration of the DRAM array 315 (e.g., two columns and four rows), due to the shared read word lines 355 and 360, the layout design 395 has a height of 2Y and a width of 4X. Thus, the aspect ratio of the known layout design is different from the aspect ratio of the layout design 395 of the present disclosure. Therefore, compared with the layout design of the known DRAM array, the layout design 395 of the present disclosure has a height (e.g., 2Y) that is half the height (e.g., 4Y) of the known layout. A smaller height (Y) means a smaller capacitance. A smaller capacitance means a higher read current in the read bit line. Therefore, the capacitance in the read bit lines of the DRAM array 315 having two read bit lines during a read operation (where each read bit line is connected to approximately half of the DAM cells in a column) is half (or approximately half) of the capacitance of the known DRAM array during a read operation. Thus, by reducing the height Y of the layout design 395, the present disclosure can reduce the capacitance in the read bit lines and increase the read speed.

[0095] In some embodiments, the number of gate structures (e.g., polysilicon) in the M0 direction may be equal to the number of write word lines. For example, in some embodiments, the number of gate structures at a height of 1Y may be equal to two (e.g., referring to layout design 395). Further, the number of write word lines at the same height of 1Y may also be equal to two (e.g., as can be seen from the DRAM array 315, word lines 365 and 370 are at a height of 1Y, and word lines 375 and 380 are at the same height of 1Y). Thus, in each height of 1Y, the number of gate structures may be equal to the number of write word lines.

[0096] Now refer toFigures 6A to 6C , illustrates various additional configurations of DRAM cells according to some embodiments of the present disclosure. Figure 2 Describe an exemplary configuration of DRAM cell 200. In DRAM cell 200, write pass gate transistor 210, read pull-down transistor 215, and read pass gate transistor 230 are all n-type transistors. In some embodiments, one or more of write pass gate transistor 210, read pull-down transistor 215, and read pass gate transistor 230 may be configured as p-type transistors. For example, Figure 6A , illustrates DRAM cell 550 having a p-type write pass gate transistor 555. Except that write pass gate transistor 555 is a p-type transistor, DRAM cell 550 is similar to DRAM cell 200 and will not be described further. DRAM cell 550 may have a layout design similar to layout design 245 of DRAM cell 200.

[0097] Figure 6B , illustrates DRAM cell 560 having both a p-type read pull-down transistor 565 and a p-type read pass gate transistor 570. Except that read pull-down transistor 565 and read pass gate transistor 570 are p-type transistors, DRAM cell 560 is similar to DRAM cell 200 and will not be described further. In some embodiments, either read pull-down transistor 565 or read pass gate transistor 570 may be a p-type transistor. Figure 6C , illustrates DRAM cell 575 having a write pass gate transistor 580, a read pull-down transistor 585, and a read pass gate transistor 590, each of which is a p-type transistor. Except that write pass gate transistor 580, read pull-down transistor 585, and read pass gate transistor 590 are p-type transistors, DRAM cell 575 is similar to DRAM cell 200 and will not be described further.

[0098] DRAM cells 560 and 575 may also each have a layout similar to that of DRAM cell 200's layout design 245, with minor variations in the connections of read pull-down transistors 565 and 585 to read pass gate transistors 570 and 590, respectively. In some embodiments, for example, and in conjunction with Figure 3 refer to Figure 6B and Figure 6C , instead of the local interconnect layer 300 connecting the drain terminal of the read pull-down transistor to the read pass gate transistor, that local interconnect layer can now connect the source terminals of read pull-down transistors 565 and 585 to read pass gate transistors 570 and 590, respectively.

[0099] Each of the DRAM cells 550, 560, and 575 can be used in the DRAM array 315 instead of the DRAM cell 200. When used in the DRAM array 315, each of the DRAM cells 550, 560, and 575 can be configured as shown in Figure 4 , where each column has two read bit lines and a read word line shared by two consecutive DRAM cells in the same column.

[0100] Go to Figure 7 , which illustrates an example of a DRAM array 595 according to some embodiments of the present disclosure. The DRAM array 595 is similar to the DRAM 315, except for how the read word lines 355 and 360 are connected. In the DRAM array 315, the read word line 355 is shared by the DRAM cells 320D and 320F in the first column 325 and by the DRAM cells 320E and 320G in the second column 340. Similarly, in the DRAM array 315, the read word line 360 is shared by the DRAM cells 200 and 320B in the first column 325 and by the DRAM cells 320A and 320C in the second column 340. However, in the DRAM array 595, each DRAM cell in a particular column has a separate read word line. In other words, the DRAM cells in a column do not share a read word line. Thus, in the DRAM array 595, the DRAM cells 320F in the first column 325 and the DRAM cells 320G in the second column 340 are connected to the read word line 600 (RWL[0]), the DRAM cells 320D and 320E in the first and second columns are connected to the read word line 605 (RWL[1]), the DRAM cells 320B and 320C in the first and second columns are connected to the read word line 610 (RWL[2]), and the DRAM cells 200 and 320A in the first and second columns are connected to the read word line 615 (RWL[3]). Relative to the configuration of the DRAM array 315, additional routing resources may be required in the DRAM array 595 for the separate read word lines. However, the DRAM array 395 can still experience a reduction in power consumption.

[0101] In addition to the separate read word lines, the DRAM array 595 is configured similarly to the DRAM array 315. Thus, the DRAM array 595 also includes a first read bit line and a second read bit line in each column. Further, although the DRAM array 595 is illustrated as having DRAM cells configured similarly to the DRAM cell 200, in other embodiments, the DRAM array 595 can be configured such that at least one DRAM cell in the DRAM array is configured similarly to the DRAM cells 550, 560, and / or 575.

[0102] Accordingly, the present disclosure provides a DRAM array that achieves a faster read operation compared to known DRAM arrays. In some embodiments, the DRAM array of the present disclosure achieves a faster read operation by reducing the capacitance in the read bit lines during a read operation. In some embodiments, the DRAM array of the present disclosure reduces the capacitance in the read bit lines by separating a single read bit line of a known DRAM array into two separate read bit lines in each column of the DRAM array. For example, in each column of the DRAM array of the present disclosure, a single read bit line can be divided into a first read bit line and a second read bit line. The first read bit line can be connected to alternating DRAM cells in each column of the DRAM array. The second read bit line can be connected to the remaining alternating DRAM cells in each column of the DRAM array. In some embodiments, one read word line can be shared by two DRAM cells in a column of the DRAM array. Specifically, in some embodiments, two consecutive DRAM cells in a column (e.g., DRAM cells connected to different read bit lines) can be connected to the same read word line. By sharing the read word line in each column and separating a single read bit line into two read bit lines, the present disclosure reduces the capacitance in each read bit line, thereby reducing the total capacitance and increasing the read current in the read bit lines during a read operation.

[0103] According to some aspects of the present disclosure, a memory device is disclosed. The memory device includes a memory array having: a first memory cell in a first column of the memory array; a second memory cell in the first column of the memory array; a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell; and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell. Each of the first memory cell and the second memory cell is a dynamic random access memory cell. The dynamic random access memory cell is a three-transistor memory cell. Each of the first memory cell and the second memory cell is connected to the same read word line, and the read word line extends in a row direction perpendicular to the column direction. The first memory cell includes a first read transfer gate transistor connected to the read word line and the first read bit line, and the second memory cell includes a second read transfer gate transistor connected to the read word line and the second read bit line. The first memory cell further includes a first write transfer gate transistor connected to a write bit line extending in the column direction, and the second memory cell further includes a second write transfer gate transistor connected to the write bit line. The first write transfer gate transistor is connected to a first write word line extending in the row direction, and the second write transfer gate transistor is connected to a second write word line extending in the row direction. The first memory cell is connected to a first read word line extending in the row direction, the row direction being perpendicular to the column direction, and the second memory cell is connected to a second read word line extending in the row direction, and the first read word line is different from the second read word line. The first memory cell further includes a first read transfer gate transistor connected to the first read word line and the first read bit line, and the second memory cell further includes a second read transfer gate transistor connected to the second read word line and the second read bit line.

[0104] According to some other aspects of the present disclosure, a dynamic random access memory (DRAM) array is disclosed. The DRAM array includes a plurality of DRAM cells arranged along a plurality of rows and a plurality of columns. Each row extends in the row direction and each column extends in the column direction, the column direction being perpendicular to the row direction. The DRAM array further includes: a first read bit line, a second read bit line, and a write bit line. The first read bit line extends in the column direction and is connected to a first group of the plurality of DRAM cells such that the first group of DRAM cells is arranged along a first group of the plurality of rows in a first column of the plurality of columns. The second read bit line extends in the column direction and is connected to a second group of the plurality of DRAM cells such that the second group of DRAM cells is arranged along a second group of the plurality of rows in the first column. The write bit line extends in the column direction and is connected to each DRAM cell in the first group of DRAM cells in the first column and each DRAM cell in the second group of DRAM cells in the first column. Wherein each DRAM cell in the first group of DRAM cells and each DRAM cell in the second group of DRAM cells are connected to a separate write word line extending in the row direction. Wherein the first group of the plurality of rows includes a plurality of first alternating rows of the plurality of rows, and wherein the second group of the plurality of rows includes a plurality of second alternating rows of the plurality of rows. Wherein a first DRAM cell of the first group of DRAM cells in one of the plurality of first alternating rows and a second DRAM cell of the second group of DRAM cells in one of the plurality of second alternating rows are connected to the same read word line extending in the row direction. Wherein the first DRAM cell and the second DRAM cell are located in adjacent rows of the first column. Wherein each DRAM cell in the first group of DRAM cells and each DRAM cell in the second group of DRAM cells are connected to a separate read word line extending in the row direction.

[0105] According to yet other aspects of the present disclosure, a memory array is disclosed. The memory array includes a plurality of memory cells arranged along a first column of a plurality of rows and a plurality of columns. Each row extends in a row direction and each column extends in a column direction, the column direction being perpendicular to the row direction. The memory array further includes: a first interconnect layer, a second interconnect layer, and a third interconnect layer. The first interconnect layer defines a first read bit line in the layout design of the memory array such that the first interconnect layer is connected to a first group of the plurality of memory cells. The second interconnect layer defines a second read bit line in the layout design of the memory array such that the second interconnect layer is connected to a second group of the plurality of memory cells. The third interconnect layer defines a first read word line in the layout design of the memory array such that the third interconnect layer is connected to a first memory cell of the first group of the plurality of memory cells and a second memory cell of the second group of the plurality of memory cells. Wherein each of the first interconnect layer and the second interconnect layer is a metal 0 layer. Wherein the third interconnect layer is a metal 1 layer. Wherein the memory array further includes a fourth interconnect layer for defining a write word line and connecting to the first group of the plurality of memory cells and the second group of the plurality of memory cells, wherein the fourth interconnect layer is a metal 3 layer. Wherein the layout design in each memory cell has a height in the column direction, wherein each memory cell includes some gate structures within the height, and the number of these gate structures within the height is equal to the number of the plurality of write word lines within the height.

[0106] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that, Comprising: A memory array, comprising: A first memory cell, in a first column of the memory array; A second memory cell, in the first column of the memory array, the second memory cell adjacent to the first memory cell; A first read bit line, extending in a column direction and connected to the first memory cell to read data from the first memory cell; and A second read bit line, extending in the column direction and connected to the second memory cell to read data from the second memory cell, wherein the first memory cell is connected to a first read word line extending along a row direction; and The second memory cell is connected to a second read word line extending along the row direction.

2. The memory device according to claim 1, wherein Wherein each of the first memory cell and the second memory cell is a dynamic random access memory cell.

3. The memory device according to claim 2, wherein, Wherein the dynamic random access memory cell is a three-transistor memory cell.

4. The memory device according to claim 1, wherein Wherein each of the first memory cell and the second memory cell is connected to the same read word line, the read word line extending in a row direction perpendicular to the column direction.

5. The memory device according to claim 4, wherein Wherein the first memory cell includes a first read transfer gate transistor, the first read transfer gate transistor connected to the read word line and the first read bit line, wherein the second memory cell includes a second read transfer gate transistor, the second read transfer gate transistor connected to the read word line and the second read bit line.

6. The memory device according to claim 5, wherein Wherein the first memory cell further includes a first write transfer gate transistor, the first write transfer gate transistor connected to a write bit line extending in the column direction, wherein the second memory cell further includes a second write transfer gate transistor, the second write transfer gate transistor connected to the write bit line.

7. The memory device according to claim 6, characterized in that, Wherein the first write transfer gate transistor is connected to a first write word line extending in the row direction, wherein the second write transfer gate transistor is connected to a second write word line extending in the row direction.

8. The memory device according to claim 1, characterized in that, Wherein the first memory cell is connected to the first read word line extending in the row direction, the row direction perpendicular to the column direction, wherein the second memory cell is connected to the second read word line extending in the row direction, wherein the first read word line and the second read word line are different.

9. The memory device according to claim 8, wherein Wherein the first memory cell further includes a first read transfer gate transistor, the first read transfer gate transistor connected to the first read word line and the first read bit line, wherein the second memory cell further includes a second read transfer gate transistor, the second read transfer gate transistor connected to the second read word line and the second read bit line.

10. A dynamic random access memory array, characterized in that, Comprising: A plurality of dynamic random access memory cells, arranged along a plurality of rows and a plurality of columns, wherein each of the rows extends in a row direction, wherein each of the columns extends in a column direction, the column direction perpendicular to the row direction; A first read bit line extending in the column direction and connected to a first group of dynamic random access memory (DRAM) cells of the plurality of DRAM cells, wherein the first group of DRAM cells is arranged in a first group of the plurality of rows in a first column of the plurality of columns; A second read bit line extending in the column direction and connected to a second group of DRAM cells of the plurality of DRAM cells, wherein the second group of DRAM cells is arranged in a second group of the plurality of rows in the first column; A write bit line extending in the column direction and connected to each of the DRAM cells in the first group of DRAM cells in the first column and each of the DRAM cells in the second group of DRAM cells in the first column; And A plurality of read word lines extending in the row direction, wherein a first read word line of the plurality of read word lines is connected to a first DRAM cell in the first group, a second read word line of the plurality of read word lines is connected to a second DRAM cell in the second group, and the first DRAM cell is adjacent to the second DRAM cell.

11. The dynamic random access memory array according to claim 10, wherein wherein each DRAM cell in the first group of DRAM cells and each DRAM cell in the second group of DRAM cells is connected to a separate write word line extending in the row direction.

12. The dynamic random access memory array according to claim 10, wherein wherein the first group of the plurality of rows includes a plurality of first alternating rows of the plurality of rows, and the second group of the plurality of rows includes a plurality of second alternating rows of the plurality of rows.

13. The dynamic random access memory array according to claim 12, wherein wherein the first DRAM cell of the first group of DRAM cells in one of the plurality of first alternating rows and the second DRAM cell of the second group of DRAM cells in one of the plurality of second alternating rows are connected to the same read word line extending in the row direction.

14. The dynamic random access memory array according to claim 13, wherein wherein the first DRAM cell and the second DRAM cell are located in adjacent rows of the first column.

15. The dynamic random access memory array according to claim 10, wherein wherein each DRAM cell in the first group of DRAM cells and each DRAM cell in the second group of DRAM cells is connected to a separate read word line extending in the row direction.

16. A memory array, characterized in that, Comprising: A plurality of memory cells arranged in a first column of a plurality of rows and a plurality of columns, wherein each row extends in a row direction, and each column extends in a column direction, the column direction being perpendicular to the row direction; A first interconnect layer for defining a first read bit line in a layout design of the memory array, wherein the first interconnect layer is connected to a first group of the plurality of memory cells; A second interconnect layer for defining a second read bit line in the layout design of the memory array, wherein the second interconnect layer is connected to a second group of the plurality of memory cells; and a third interconnect layer for defining a first read character line and a second read character line in the layout design of the memory array, wherein the third interconnect layer is connected to a first memory cell in the first group of the plurality of memory cells and a second memory cell in the second group of the plurality of memory cells, wherein the first group includes the first memory cell, the second group includes the second memory cell, and the first read character line is connected to the first memory cell, the second read character line is connected to the second memory cell, and the first memory cell is adjacent to the second memory cell.

17. The memory array according to claim 16, wherein wherein each of the first interconnect layer and the second interconnect layer is a metal 0 layer.

18. The memory array according to claim 17, wherein, wherein the third interconnect layer is a metal 1 layer.

19. The memory array according to claim 18, wherein, Further included is: a fourth interconnect layer for defining a write character line and connected to the first group of the plurality of memory cells and the second group of the plurality of memory cells, wherein the fourth interconnect layer is a metal 3 layer.

20. The memory array according to claim 16, wherein wherein the layout design in each of the memory cells has a height in the column direction, wherein each of the memory cells includes some gate structures within the height, and the number of the gate structures within the height is equal to the number of the write character lines within the height.

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