Chip sealing ring

Abstract

The present invention provides a chip sealing ring, comprising: a substrate; first to N-th metal layers, formed sequentially on the upper layer of the substrate, the N metal layers being separated by dielectric layers, the first metal layer comprising a metal strip, which forms a rectangular ring structure around the chip, the N-th metal layer comprising N metal strips, and from the second to N-th metal layers, metal strips in the same metal layer are separated by dielectric layers and sequentially form a rectangular ring structure around the chip from the inside out, and from the first to N-1 metal layers, each metal strip is connected to a metal strip in the adjacent upper metal layer, and metal strips in the same metal layer cannot be connected to the same metal strip; N test pads, respectively arranged on the N metal strips on the N-th metal layer; and the quality of the dielectric layer between the metal layers respectively connected is judged by testing whether the voltage or capacitance of any two test pads is within a set range.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip sealing ring. Background Art

[0002] During the wafer packaging process, chips need to be diced. To protect the chip, a die seal ring is typically placed between the die and the dicing path. This seal ring prevents any cracks from invading the chip interior. Part of the die seal ring's structure is an interlayer dielectric (IMD).

[0003] However, numerous cases of chip cracking have occurred, whether using the advanced 28nm process or the more common 0.18μm process. Failure analysis generally indicates that mechanical forces generated during dicing break through the seal ring's protection, causing cracks in the seal ring. These cracks then extend into the chip, leading to disconnections and damage to internal circuits. Research by the inventors has revealed that the primary cause of this phenomenon is poor quality of the integrated device (IMD). Summary of the Invention

[0004] The object of the present invention is to provide a chip sealing ring, which can not only protect the chip but also detect whether the quality of the interlayer dielectric layer in the chip sealing ring is qualified.

[0005] In order to achieve the above object, the present invention provides a chip sealing ring, comprising:

[0006] a substrate surrounding the chip to form a rectangular ring structure;

[0007] The first metal layer to the Nth metal layer are sequentially formed on the upper layer of the substrate from bottom to top, and the N metal layers are separated by dielectric layers. The first metal layer includes a metal strip, which forms a rectangular ring structure around the chip. The second metal layer includes two metal strips. The Nth metal layer includes N metal strips. From the second metal layer to the Nth metal layer, all metal strips of the same metal layer are separated by dielectric layers and sequentially form a rectangular ring structure around the chip from the inside to the outside. From the first metal layer to the N-1th metal layer, each metal strip is connected to a metal strip in the adjacent upper metal layer, and metal strips in the same metal layer cannot be connected to the same metal strip, wherein N is an integer greater than or equal to 2; and

[0008] N test pads are respectively disposed on the N metal strips on the Nth metal layer.

[0009] Optionally, in the chip sealing ring, the metal strip includes four corners, and the test pad is located at one of the four corners.

[0010] Optionally, in the chip sealing ring, the first metal layer and the surface of the substrate are separated by a dielectric layer, and the first metal layer is connected to the substrate via a connector.

[0011] Optionally, in the chip sealing ring, each of the metal strips is connected to a metal strip in an adjacent upper metal layer via a connector.

[0012] Optionally, in the chip sealing ring, the cross section of the connecting member is square, with a side length of 0.3 μm to 0.4 μm.

[0013] Optionally, in the chip sealing ring, in the second metal layer to the (N-1)th metal layer, the width of the metal strip close to the chip in the same metal layer is greater than the width of other metal strips in the metal layer.

[0014] Optionally, in the chip sealing ring, the distance between adjacent metal strips in the same metal layer is 1 μm.

[0015] Optionally, in the chip sealing ring, N is four, and the four metal layers are respectively a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, the first metal layer to the fourth metal layer are located on the substrate from bottom to top, the first metal layer is connected to the substrate through a connector, and the four metal layers are separated by a dielectric layer; the first metal layer includes a first metal strip, and the first metal strip surrounds the chip to form a rectangular ring structure; the second metal layer includes a second metal strip and a third metal strip, and the second metal strip and the third metal strip surround the chip from inside to outside to form a rectangular ring structure; the third metal strip The metal layer includes a fourth metal strip, a fifth metal strip and a sixth metal strip, which surround the chip from the inside to the outside in sequence to form a rectangular ring structure; the fourth metal layer includes a seventh metal strip, an eighth metal strip, a ninth metal strip and a tenth metal strip, which surround the chip from the inside to the outside in sequence to form a rectangular ring structure; the first metal strip is connected to the third metal strip, the sixth metal strip and the tenth metal strip in sequence; the second metal strip is connected to the fifth metal strip and the ninth metal strip; the fourth metal strip is connected to the eighth metal strip in sequence.

[0016] Optionally, in the chip sealing ring, in the second metal, the second metal strip is arranged close to the chip, and the third metal strip is arranged around the second metal strip; in the third metal, the fourth metal strip is arranged close to the chip, the fifth metal strip is arranged around the fourth metal strip, and the sixth metal strip is arranged around the fifth metal strip; in the fourth metal, the seventh metal strip is arranged close to the chip, the eighth metal strip is arranged around the seventh metal strip, the ninth metal strip is arranged around the eighth metal strip, and the tenth metal strip is arranged around the ninth metal strip.

[0017] Optionally, in the chip sealing ring, the width of the first metal strip is 11 μm, the width of the second metal strip is 8 μm, the width of the third metal strip is 2 μm, the width of the fourth metal strip is 5 μm, the width of the fifth metal strip is 2 μm, the width of the sixth metal strip is 2 μm, and the widths of the seventh metal strip, the eighth metal strip, the ninth metal strip and the tenth metal strip are all 2 μm.

[0018] In the chip sealing ring provided in the embodiment of the present invention, the chip sealing ring not only protects the chip, but also can obtain the capacitance or voltage of any two test pads through probe contact with the test pad, thereby obtaining the voltage or capacitance between the metal layers connected to the two test pads. The quality of the dielectric layer between the two metal layers is judged by whether the voltage or capacitance value is within the qualified range, thereby preventing the chip sealing ring from being broken or even the chip from being broken due to the unqualified quality of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a chip sealing ring according to an embodiment of the present invention;

[0020] Figure 2 The embodiment of the present invention is along Figure 1 A schematic cross-sectional view of the chip sealing ring after being cut along line AB;

[0021] Figure 3 is a schematic diagram of a TOP metal layer according to an embodiment of the present invention;

[0022] In the figure: 1-chip sealing ring, 100-substrate, 210-first metal layer, 220-second metal layer, 221-second metal strip, 222-third metal strip, 230-third metal layer, 231-fourth metal strip, 232-fifth metal strip, 233-sixth metal strip, 240-fourth metal layer, 241-seventh metal strip, 242-eighth metal strip, 243-ninth metal strip, 244-tenth metal strip, 300-connector, 410-first test pad, 420-second test pad, 430-third test pad, 440-fourth test pad. DETAILED DESCRIPTION

[0023] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0024] Hereinafter, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if a method described herein comprises a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps may be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0025] The inventors have discovered that there are no methods or applications for testing the quality of IMDs in the prior art, and even fewer methods or applications for warning of the risk of cracks in IMDs.

[0026] Therefore, please refer to Figure 1 The present invention provides a chip sealing ring 1, which is located between the chip and the cutting path. Its cross section is in the shape of a rectangular ring. The middle of the inner circle of the rectangular ring is the area where the chip is located. The area outside the outer circle of the rectangular ring is the area where the cutting path is located. The area between the outer and inner circles of the rectangular ring is the area where the chip sealing ring 1 is located. Next, please refer to Figure 2 and Figure 3 , Figure 2 The embodiment of the present invention is along Figure 1 Schematic diagram of the cross section of the chip sealing ring after being cut along line AB. Figure 3 FIG. 1 is a schematic diagram of a TOP metal layer (Nth metal layer) according to an embodiment of the present invention. The chip seal ring includes:

[0027] The substrate 100 surrounds the chip to form a rectangular ring structure;

[0028] The first metal layer 210 to the Nth metal layer are sequentially formed on the upper layer of the substrate 100 from bottom to top, and the N metal layers are separated by dielectric layers. The first metal layer 210 includes a metal strip, which forms a rectangular ring structure around the chip. The second metal layer 220 includes two metal strips. The Nth metal layer includes N metal strips. In the second metal layer to the Nth metal layer, all metal strips in the same metal layer are separated by dielectric layers and sequentially form a rectangular ring structure around the chip from the inside to the outside. In the first metal layer 210 to the N-1th metal layer, each metal strip is connected to a metal strip in the adjacent upper metal layer, and metal strips in the same metal layer cannot be connected to the same metal strip, where N is an integer greater than 2;

[0029] N test pads are placed on N metal strips on the Nth metal layer. By testing whether the voltage or capacitance of any two test pads is within a set range, the quality of the dielectric layer between the metal layers connected to the two test pads can be determined. By contacting the test pads with a probe, the capacitance or voltage of any two test pads can be measured. Since the test pads are located on the metal strips, the voltage or capacitance between the metal strips connected to the two test pads can be measured. Since the metal strips are connected to the first through the N-1th layers, the voltage or capacitance between the two metal layers can be measured. The quality of the dielectric layer between the two metal layers can be determined by whether the voltage or capacitance value is within the acceptable range. Furthermore, the rectangular ring-shaped metal strip has four corners, and the test pad is located at one of the four corners. To facilitate testing, given the limited size of the metal strips, a test pad is provided on each strip to facilitate probe testing. To make the strips more regular, a test pad can be placed at a corner of each strip. However, having two test pads on a single strip is also possible, but it would be more wasteful. Furthermore, for balance and ease of manufacturing, the test pads of adjacent metal strips may not be located at the same corner, and preferably, multiple test pads are located at different corners as much as possible. For example, if there are four metal strips, each with four corners, and if the four corners are in the four directions of east, south, west, and north, then the test pad of one metal strip may be located at the east corner of the metal strip, the test pad of another metal strip may be located at the west corner of the metal strip, the test pad of another metal strip may be located at the south corner of the metal strip, and the test pad of the last metal strip may be located at the north corner of the metal strip.

[0030] In the embodiment of the present invention, the number of metal strips contained in each metal layer is the same as the number of layers that the metal layer is located in. That is, the second layer has two metal strips, the third layer has three metal strips, and the N-1th layer has N-1 metal strips. The number of metal strips is proportional to the layer number.

[0031] In the embodiment of the present invention, the first metal layer 210 and the surface of the substrate 100 are separated by a dielectric layer, and the first metal layer 210 is connected to the substrate 100 via a connector, and the connector is located in the dielectric layer.

[0032] Furthermore, each metal strip is connected to a metal strip in an adjacent upper metal layer via a connector, and the connector is located in the dielectric layer. Specifically, each metal strip can be connected to a metal strip in an adjacent upper metal layer via two connectors. In other embodiments of the present invention, each metal strip can also be connected to a metal strip in an adjacent upper metal layer via a single connector. The cross-section of the connector is square, with side lengths of 0.3 μm to 0.4 μm. In other embodiments of the present invention, the connector or the cross-section of the connector can also be circular. When it is square, the side length can also be of other sizes.

[0033] Preferably, in the second metal layer 220 through the (N-1)th metal layer, the width of the metal strip closest to the chip in the same metal layer is greater than the width of the other metal strips in the same metal layer. If the metal layer has at least two metal strips, the metal strips are sequentially arranged around the chip from the inside out. That is, one metal strip is first selected to surround the chip, and the remaining metal strips are then arranged around the previous metal strip.

[0034] In the embodiment of the present invention, the minimum distance between adjacent metal strips in the same metal layer is 1 μm, and the minimum distance between a test pad and an adjacent metal strip is also 1 μm.

[0035] Next, taking N as four as an example, the four metal layers are the first metal layer 210, the second metal layer 220, the third metal layer 230 and the fourth metal layer 240, the first metal layer 210 to the fourth metal layer 240 are respectively located on the substrate 100 in sequence, the first metal layer 210 is connected to the substrate 100 through a connector, and the four metal layers are separated by a dielectric layer; the first metal layer 210 includes a metal strip, which is the first metal strip, surrounding the chip to form a rectangular ring structure; the second metal layer 220 includes two metal strips, which are the second metal strip 221 and the third metal strip 222, and the second metal strip 221 and the third metal strip 222 surround the chip in sequence to form a rectangular ring structure; the third metal layer 230 includes three metal strips, which are the fourth metal strips. The metal strip 231, the fifth metal strip 232 and the sixth metal strip 233, the fourth metal strip, the fifth metal strip 232 and the sixth metal strip 233 form a rectangular ring structure around the chip in sequence; the fourth metal layer 240 includes four metal strips, namely the seventh metal strip 241, the eighth metal strip 242, the ninth metal strip 243 and the tenth metal strip 244, the seventh metal strip 241, the eighth metal strip 242, the ninth metal strip 243 and the tenth metal strip 244 form a rectangular ring structure around the chip in sequence; the first metal strip is connected to the third metal strip 222, the sixth metal strip 233 and the tenth metal strip 244; the second metal strip 221 is connected to the fifth metal strip 232 and the ninth metal strip 243; the fourth metal strip 231 is connected to the eighth metal strip 242. The fourth metal layer 240 is also the TOP metal layer in this example. Each metal strip in this layer also has a test pad. Therefore, the seventh metal strip 241 has a first test pad 410, the eighth metal strip 242 has a second test pad 420, the ninth metal strip 243 has a third test pad 430, and the tenth metal strip 244 has a fourth test pad 440. In the second metal layer, the second metal strip 221 is located close to the chip, and the third metal strip 222 is arranged around the second metal strip 221. In the third metal layer, the fourth metal strip 231 is located close to the chip, the fifth metal strip 232 is arranged around the fourth metal strip 231, and the sixth metal strip 233 is arranged around the fifth metal strip 232. In the fourth metal layer, the seventh metal strip 241 is located close to the chip, the eighth metal strip 242 is arranged around the seventh metal strip 241, the ninth metal strip 243 is arranged around the eighth metal strip 242, and the tenth metal strip 244 is arranged around the ninth metal strip 243. Specifically, the width of the first metal strip is 11 μm, the width of the second metal strip 221 is 8 μm, the width of the third metal strip 222 is 2 μm, the width of the fourth metal strip 231 is 5 μm, the width of the fifth metal strip 232 is 2 μm, the width of the sixth metal strip 233 is 2 μm, and the widths of the seventh metal strip 241, the eighth metal strip 242, the ninth metal strip 243 and the tenth metal strip 244 are all 2 μm.By testing the voltage or capacitance between the third test pad 430 and the fourth test pad 440, if the voltage or capacitance is outside the set range, it can be determined that the dielectric layer between the first metal layer 210 and the second metal layer 220 may have a problem. Regardless of where the dielectric layer is found to have a problem, the sealing ring structure needs to be marked for subsequent processing. In other embodiments of the present invention, N can also be other values, the metal strips can also be other values, and the widths of all metal strips can also be other sizes.

[0036] In summary, in the chip sealing ring provided in the embodiment of the present invention, the chip sealing ring can not only protect the chip, but also obtain the capacitance or voltage of any two test pads by contacting the test pads through a probe, so as to obtain the voltage or capacitance between the metal layers connected to the two test pads. Whether the value of the voltage or capacitance is within the qualified range can be used to judge whether the quality of the dielectric layer between the two metal layers is qualified, thereby preventing the chip sealing ring from being broken or even the chip from being broken due to the unqualified quality of the interlayer dielectric layer.

[0037] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A chip sealing ring, characterized in that: include: a substrate surrounding the chip to form a rectangular ring structure; The first metal layer to the Nth metal layer are sequentially formed on the upper layer of the substrate from bottom to top, and the N metal layers are separated by dielectric layers. The first metal layer includes a metal strip, which forms a rectangular ring structure around the chip. The second metal layer includes two metal strips. The Nth metal layer includes N metal strips. From the second metal layer to the Nth metal layer, all metal strips of the same metal layer are separated by dielectric layers and sequentially form a rectangular ring structure around the chip from the inside to the outside. From the first metal layer to the N-1th metal layer, each metal strip is connected to a metal strip in the adjacent upper metal layer through a connector, and metal strips in the same metal layer cannot be connected to the same metal strip, wherein N is an integer greater than 2; as well as N test pads are respectively disposed on the N metal strips on the Nth metal layer.

2. The chip sealing ring according to claim 1, wherein: The metal strip includes four corners, and the test pad is located at one of the four corners.

3. The chip sealing ring according to claim 1, wherein: The first metal layer and the surface of the substrate are separated by a dielectric layer, and the first metal layer is connected to the substrate through a connector.

4. The chip sealing ring according to claim 1, wherein: The cross section of the connecting piece is a square with a side length of 0.3 μm to 0.4 μm.

5. The chip sealing ring according to claim 1, wherein: In the second metal layer to the (N-1)th metal layer, the width of the metal strip close to the chip in the same metal layer is greater than the width of other metal strips in the metal layer.

6. The chip sealing ring according to claim 1, wherein: The distance between adjacent metal strips in the same metal layer is 1 μm.

7. The chip sealing ring according to claim 1, wherein: The N is four, and the four metal layers are respectively a first metal layer, a second metal layer, a third metal layer and a fourth metal layer. The first metal layer to the fourth metal layer are sequentially located on the substrate from bottom to top, the first metal layer is connected to the substrate through a connector, and the four metal layers are separated by a dielectric layer; the first metal layer includes a first metal strip, and the first metal strip surrounds the chip to form a rectangular ring structure; the second metal layer includes a second metal strip and a third metal strip, and the second metal strip and the third metal strip sequentially surround the chip from inside to outside to form a rectangular ring structure; the third metal layer includes a fourth metal strip. The fourth metal strip, the fifth metal strip and the sixth metal strip, the fourth metal strip, the fifth metal strip and the sixth metal strip surround the chip from the inside to the outside in sequence to form a rectangular ring structure; the fourth metal layer includes a seventh metal strip, an eighth metal strip, a ninth metal strip and a tenth metal strip, the seventh metal strip, the eighth metal strip, the ninth metal strip and the tenth metal strip surround the chip from the inside to the outside in sequence to form a rectangular ring structure; the first metal strip is connected to the third metal strip, the sixth metal strip and the tenth metal strip in sequence; the second metal strip is connected to the fifth metal strip and the ninth metal strip; the fourth metal strip is connected to the eighth metal strip in sequence.

8. The chip sealing ring according to claim 7, wherein: In the second metal, the second metal strip is arranged close to the chip, and the third metal strip is arranged around the second metal strip; in the third metal, the fourth metal strip is arranged close to the chip, the fifth metal strip is arranged around the fourth metal strip, and the sixth metal strip is arranged around the fifth metal strip; in the fourth metal, the seventh metal strip is arranged close to the chip, the eighth metal strip is arranged around the seventh metal strip, the ninth metal strip is arranged around the eighth metal strip, and the tenth metal strip is arranged around the ninth metal strip.

9. The chip sealing ring according to claim 8, wherein: The width of the first metal strip is 11 μm, the width of the second metal strip is 8 μm, the width of the third metal strip is 2 μm, the width of the fourth metal strip is 5 μm, the width of the fifth metal strip is 2 μm, the width of the sixth metal strip is 2 μm, and the widths of the seventh metal strip, the eighth metal strip, the ninth metal strip and the tenth metal strip are all 2 μm.

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