Embedded package structure

Abstract

Embodiments of the present application provide an embedded package structure, comprising: a lead frame having a first surface and a second surface opposite to the first surface, a solder mask disposed adjacent to the second surface, and the solder mask interposed between the first surface and the second surface. The purpose of the present application is to provide an embedded package structure to increase the yield of the embedded package structure.

Description

Technical Field

[0001] Embodiments of this application relate to embedded packaging structures. Background Technology

[0002] For embedded package structures, especially those suitable for high-power power modules, lead frames (LF) are often used as the substrate. For these high-power components, creepage distance control is very strict, therefore the lead frame sidewalls cannot be exposed. Currently, to address this issue, a solder mask (SM) is used to completely cover the lead frame sidewalls on the back side. Although the lead frame has been partially etched in previous processes, the remaining lead frame still has a considerable thickness, resulting in a thick SM fill, which affects thermal performance. Furthermore, a thicker SM may cause a loss in product yield during the exposure process. Summary of the Invention

[0003] In view of the problems existing in related technologies, the purpose of this invention is to provide an embedded packaging structure to increase the yield of embedded packaging structures.

[0004] To achieve the above objectives, embodiments of the present invention provide an embedded packaging structure, including: a lead frame having a first surface and a second surface opposite to the first surface, a solder mask being configured adjacent to the second surface, and the solder mask being located between the first surface and the second surface.

[0005] In some embodiments, the lead frame has a third surface located between the first and second surfaces, the third surface being closer to the second surface than to the first surface.

[0006] In some embodiments, the third side is lower than the second side.

[0007] In some embodiments, the lead frame further includes a fifth surface extending from the third surface to the first surface, and a welding mask covers a first portion of the fifth surface.

[0008] In some embodiments, it further includes: a dielectric layer covering a second portion of the first and fifth surfaces.

[0009] In some embodiments, the dielectric layer and the solder mask are in direct contact.

[0010] In some embodiments, the outer sidewalls of the dielectric layer and the solder mask are coplanar.

[0011] In some embodiments, the area of ​​the second portion is larger than the area of ​​the first portion.

[0012] In some embodiments, it further includes a protective layer located on the second surface.

[0013] In some embodiments, the protective layer covers a third portion of the third surface.

[0014] In some embodiments, the lead frame also includes a fourth side extending from the second side to the third side, and a protective layer also covers the fourth side.

[0015] In some embodiments, the thickness of the welding mask is less than the height of the fourth side.

[0016] In some embodiments, the welding mask covers a fourth portion of the third surface, the area of ​​the fourth portion being larger than the area of ​​the third portion.

[0017] In some embodiments, the lead frame includes a stepped structure recessed from the second surface toward the first surface, and a solder mask is disposed on the stepped structure.

[0018] In some embodiments, the system further includes: a wiring layer, with a first surface of the leadframe facing the wiring layer; and electronic components located in a cavity enclosed by the leadframe and the wiring layer, the electronic components being electrically connected to the wiring layer and electrically connected to the leadframe through the wiring layer.

[0019] In some embodiments, the cavity is recessed relative to the first surface.

[0020] In some embodiments, the device further includes an adhesive layer located between the electronic component and the lead frame, wherein the active side of the electronic component faces the circuit layer and the opposite side of the adhesive layer.

[0021] In some embodiments, the dielectric layer is located in the cavity and between the electronic components and the circuit layer.

[0022] In some embodiments, the dielectric layer is a molding compound.

[0023] In some embodiments, the lead frame is made of copper. Attached Figure Description

[0024] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0025] Figures 1 to 3 A schematic diagram of an existing embedded packaging structure is shown.

[0026] Figures 4 to 16 An embedded packaging structure and its formation process according to an embodiment of this application are shown. Detailed Implementation

[0027] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0028] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0029] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0030] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0031] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0032] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0033] Figure 1 A schematic diagram of an existing embedded package structure is shown, in which a solder mask 10 is disposed at the corner of the leadframe 12 to enclose the sidewall of the leadframe 12. In this structure, the solder mask 10 also covers the bottom surface of the leadframe 12, which requires a larger amount of metal part compound (TIM) to be filled between the two when the embedded package structure is subsequently placed on the heat sink, thus affecting heat dissipation.

[0034] Figures 2 to 3 Existing methods for solving the above problems are shown, wherein Figure 2 and Figure 3 yes Figure 1 Enlarged view of the corner of the embedded packaging structure shown. See also Figure 2 Using photolithography mask 20 to pattern and weld mask 10, we obtain... Figure 3 The patterned solder mask 10 is shown. Patterning the solder mask 10 solves the heat dissipation problem, but this process exposes the sides of the leadframe 12, making them susceptible to oxidation or corrosion. Furthermore, the solder mask 20 is prone to peeling off from the structure during subsequent monolithic fabrication processes. Even when a protective layer is formed on the exposed portion of the leadframe 12, the groove 21 is too deep (e.g., exceeding 70 μm), making it difficult for the protective layer to completely cover the exposed surface of the leadframe 12.

[0035] The embedded packaging structure of this application will now be described in detail with reference to the accompanying drawings.

[0036] Figure 4An embedded package structure 400 according to an embodiment of this application is shown, including: a leadframe 12 having a first surface 121 and a second surface 122 opposite to the first surface 121, and a solder mask 10 disposed adjacent to the second surface 122, the solder mask 10 being disposed between the first surface 121 and the second surface 122. In some embodiments, the leadframe 12 has a third surface 123 disposed between the first surface 121 and the second surface 122, the third surface 123 being closer to the second surface 122 than to the first surface 121. In some embodiments, when the second surface 122 is the top surface, the third surface 123 is lower than the second surface 122. In some embodiments, the leadframe 12 further includes a fifth surface 125 extending from the third surface 123 to the first surface 121, the solder mask 10 covering a first portion of the fifth surface 125. In some embodiments, it further includes: a dielectric layer 40 covering a second portion of the first surface 121 and the fifth surface 125. In some embodiments, the area of ​​the second portion is larger than the area of ​​the first portion. In some embodiments, the dielectric layer 40 and the solder mask 10 are in direct contact. In some embodiments, the outer sidewalls of the dielectric layer 40 and the solder mask 10 are coplanar. In some embodiments, a protective layer 42 is further included, located on the second surface 122. In some embodiments, the leadframe further includes a fourth surface 124 extending from the second surface 122 to the third surface 123, and the protective layer 42 also covers the fourth surface 124. In some embodiments, the thickness of the solder mask 10 is less than the height of the fourth surface 124. In some embodiments, the protective layer 42 covers a third portion of the third surface 123. In some embodiments, the solder mask 10 covers a fourth portion of the third surface 123, the area of ​​the fourth portion being larger than the area of ​​the third portion. In some embodiments, the leadframe includes a stepped structure recessed from the second surface 122 toward the first surface 121, and the solder mask 10 is disposed on the stepped structure, the solder mask comprising the fourth surface 124, the third surface 123, and the fifth surface 125. In some embodiments, the system further includes: a wiring layer 44, with a first surface 121 of the leadframe 12 facing the wiring layer 44; and an electronic component 46 located in a cavity 48 enclosed by the leadframe 12 and the wiring layer 44, the electronic component 46 being electrically connected to and connected to the wiring layer 44 and the leadframe 12 via the wiring layer 44. In some embodiments, the cavity 48 is recessed relative to the first surface 121. In some embodiments, the system further includes: an adhesive layer 50 located between the electronic component 46 and the leadframe 12, with the active surface of the electronic component 46 facing the wiring layer 44 and away from the adhesive layer 50. In some embodiments, a dielectric layer 40 is located in the cavity 48 and between the electronic component 46 and the wiring layer 44. In some embodiments, the dielectric layer 40 is a molding compound. In some embodiments, the material of the leadframe 12 includes copper.

[0037] Figures 5 to 12 A method for forming an embedded packaging structure 400 according to other embodiments of this application is shown.

[0038] See Figure 5 , and provide lead frame 12.

[0039] See Figure 6 The electronic component 46 is disposed in the cavity 48 of the lead frame 12, and the adhesive layer 50 is disposed between the electronic component 46 and the lead frame 12. In some embodiments, the electronic component 46 is a chip.

[0040] See Figure 7 A dielectric layer 40 is formed in cavity 48, which covers electronic components 46 and the feet of lead frame 12.

[0041] See Figure 8 An opening 80 is formed in the dielectric layer 40 to expose the electronic components 46 and the lead frame 12.

[0042] See Figure 9 A metallic material 90 is formed in the opening 80 and on the dielectric layer 40.

[0043] See Figure 10 The metal material 90 is patterned to form the circuit 100. A first etching process is performed to expose the lower surface of the dielectric layer 40, and a second etching process is performed to form a stepped structure consisting of the third surface 123, the fourth surface 124 and the fifth surface 125.

[0044] See Figure 11 A second dielectric layer 110 is formed on the dielectric layer 40, and the second dielectric layer 110 covers the circuit 100. The combination of the second dielectric layer 110 and the circuit 100 constitutes the circuit layer 44. A solder mask 10 is formed on the third surface 123 and the fifth surface 125 of the lead frame 12. After passing through Figure 11 After two etching processes, the space formed by the stepped structure can be filled by the solder mask 10, and the solder mask 10 can be lower than the top surface (bottom surface shown in the figure) of the lead frame 12. In some embodiments, the height difference between the thickness of the solder mask 10 and the height of the fourth surface 124 is about 10 μm, and the thickness of the solder mask 10 is 25 μm to 50 μm.

[0045] See Figure 12 A protective layer 42 is formed on the second surface 122 of the leadframe 12, the exposed portion of the fourth surface 124, and the exposed portion of the circuit 100. This forms another embodiment of the embedded semiconductor package structure 400 of this application. The specific etching shape of the leadframe 12 in this application achieves no exposed Cu on the package sidewalls and no protruding solder mask 10 on the top surface of the leadframe 12. This specific etching shape of the leadframe 12 enables good reliability and good surface finish (ENIG) deposition. In some embodiments, the embodiment further includes laser-etching markings on the surface of the embedded semiconductor package structure. Figures 4 to 12The formation process is illustrated using a single embedded semiconductor package structure as an example. In actual production, multiple semiconductor package structures are formed together, and then a monolithic process is performed to form a single embedded semiconductor package structure. In some embodiments, the monolithic process is dicing.

[0046] Figures 13 to 15 It shows Figures 11 to 12 Alternative embodiments. See also Figure 13 The welding mask 10 is also formed below the bottom surface of the lead frame 12.

[0047] See Figure 14 The portion of the solder mask 10 formed below the bottom surface of the lead frame 12 is removed. In some embodiments, the portion of the solder mask 10 located on the fourth surface 124 is also removed. In some embodiments, the aforementioned portion of the solder mask 10 is removed using a photolithography process.

[0048] See Figure 15 A protective layer 42 is formed on the second surface 122 of the lead frame 12, the exposed portion of the fourth surface 124, the exposed portion of the third surface 123, and the exposed portion of the circuit 100. This forms another embodiment of the embedded semiconductor package structure 400 of this application.

[0049] Figure 16 A semiconductor package structure 400 according to another embodiment of this application is shown, wherein a portion of the bonding mask 12 located on the dielectric layer 40 is recessed relative to a portion located on the third surface 123, because the dielectric layer 40 is recessed relative to the third surface 123.

[0050] The embodiments of this application, through the stepped structure on the back of the leadframe, reduce the height difference of subsequent solder mask filling. Simultaneously, because the required thickness of the solder mask is reduced, the predetermined shape can be formed more completely in subsequent exposure processes, and more heat dissipation surface of the leadframe is exposed. The embodiments of this application avoid a solder mask protruding from the top surface of the embedded package structure, reducing the thickness of the subsequent TIM and improving heat dissipation efficiency. Furthermore, the structure of this application avoids exposed sidewalls of the leadframe, improving the yield of the package structure.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An embedded package structure, comprising: Comprising: a leadframe having a first side and a second side opposite to the first side, a solder mask disposed adjacent to the second side, the solder mask interposed between the first side and the second side, wherein the leadframe has a third side between the first side and the second side and a fifth side extending from the third side to the first side, wherein the third side is closer to the second side than to the first side, the solder mask covers a corner portion formed by the third side and the fifth side, and covers a first portion of the fifth side.

2. The embedded package structure of claim 1, wherein, Further comprising: a dielectric layer covering the first side and a second portion of the fifth side.

3. The embedded package structure of claim 2, wherein, The dielectric layer and the solder mask are in direct contact, and outer sidewalls of the dielectric layer and the solder mask are coplanar.

4. The embedded package structure of claim 1, wherein, Further comprising: a protective layer on the second side, the protective layer covering a third portion of the third side.

5. The embedded package structure of claim 4, wherein, The leadframe further comprises a fourth side extending from the second side to the third side, and the protective layer further covers the fourth side.

6. The embedded package structure of claim 1, wherein, The leadframe comprises a stepped structure recessed from the second side toward the first side, and the solder mask is disposed on the stepped structure.

7. The embedded package structure of claim 1, wherein, Further comprising: a circuit layer, the first side of the leadframe facing the circuit layer; an electronic component in a cavity enclosed by the leadframe and the circuit layer, the electronic component electrically connected to the circuit layer and to the leadframe through the circuit layer.

8. The embedded package structure of claim 7, wherein, The cavity is recessed with respect to the first side.

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