Test structure, test system, and test methods

Abstract

This application discloses a test structure, test system, and test method that can improve the detection accuracy of short circuits in upper and lower layer contact plugs. The test structure is disposed on a wafer and located within a first region of the wafer. The test structure includes: a first conductive line comprising a first contact plug disposed in a first height region, the first contact plug including a first through-hole and conductive material disposed within the first through-hole; and a second conductive line comprising a second contact plug disposed in a second height region, the second contact plug including a second through-hole and conductive material disposed within the second through-hole. The first height region and the second height region are adjacently distributed along a direction perpendicular to the wafer surface, and the distance between the projections of the first contact plug and the second contact plug on the wafer surface is a preset threshold.

Description

Technical Field

[0001] This application relates to the field of semiconductor device testing, specifically to test structures, test systems, and test methods. Background Technology

[0002] In existing technologies, when wafer foundries inspect whether the production process is normal and whether the electrical performance of standard components meets the requirements, they usually perform the corresponding tests by adding WAT (wafer acceptable test) patterns to the dicing groove, and then provide the test results to the customer as a quality certificate.

[0003] In WAT diagrams, there is a type of diagram used to test whether the opening of the contact plug meets the requirements, such as... Figure 1 As shown. In Figure 1 In the illustrated embodiment, the first metal layer MET1 and the second metal layer MET2, disposed at different heights within the substrate, are segmented and have overlapping areas. The contact plug VIA1 is electrically connected vertically to the first metal layer MET1 and the second metal layer MET2, thereby connecting the first metal layer MET1 and the second metal layer MET2 into a chain shape. This WAT pattern can be used to test whether the through-hole chain is open-circuited; this can be achieved by testing the resistance between the first pin PIN1 and the second pin PIN2 at both ends of the WAT pattern. At this time, it can be verified whether the opening of the contact plug VIA1 meets the process requirements and whether there are any instances where the first metal layer MET1 and the second metal layer MET2 are not connected.

[0004] However, as critical dimensions in semiconductor processes continue to shrink, the distance between contact plugs at different heights within the substrate gradually decreases, making it easy for contact plugs at different heights to come into contact and short-circuit. The above... Figure 1 The WAT pattern described above cannot detect short circuits between contact plugs at different heights. A new method is needed to detect short circuits between contact plugs at different heights within the substrate.

[0005] Currently, most wafer fabs use optical inspection to confirm whether short circuits will occur in contact plugs located at different heights.

[0006] like Figure 2 The WAT diagram shown is used to detect whether there is a short circuit between the contact plugs of the upper and lower layers. Figure 2The diagram shows the alignment pattern of the second contact plug VIA2 and the second metal layer MET2. A similar alignment pattern exists between the first contact plug VIA1 and the second metal layer MET2. By measuring the offset of the second contact plug VIA2 relative to the second metal layer MET2, and the offset of the first contact plug VIA1 relative to the second metal layer MET2, the actual distance between the first contact plug VIA1 and the second contact plug VIA2 can be determined, thereby judging whether a short circuit will occur between the first contact plug VIA1 and the second contact plug VIA2.

[0007] However, this optical inspection method is an indirect measurement method and cannot directly obtain information on whether a short circuit has occurred between the upper and lower contact plugs. In addition, optical inspection is sometimes performed manually, which may result in missed or false detections. Summary of the Invention

[0008] In view of this, this application provides a test structure, a test system, and a test method that can improve the detection accuracy when short circuits occur in the upper and lower layer contact plugs.

[0009] This application provides a test structure disposed on a wafer. The test structure is located in a first region of the wafer. The test structure includes: a first conductive line, including a first contact plug disposed in a first height region, the first contact plug including a first through hole and conductive material disposed in the first through hole; and a second conductive line, including a second contact plug disposed in a second height region, the second contact plug including a second through hole and conductive material disposed in the second through hole; the first height region and the second height region are adjacently distributed along a direction perpendicular to the wafer surface, and the distance between the projections of the first contact plug and the second contact plug on the wafer surface is a preset threshold.

[0010] Optionally, the first conductive line further includes at least a first patterned metal layer and a second patterned metal layer disposed within the first height region, and the conductive material in the first contact plug is at least electrically connected to the first patterned metal layer and the second patterned metal layer.

[0011] Optionally, the second conductive line further includes at least a third patterned metal layer disposed in the second height region, and the conductive material in the second contact plug is at least electrically connected to the third patterned metal layer.

[0012] Optionally, the wafer is used to fabricate a semiconductor structure, the semiconductor structure including a first metal layer, a second metal layer, and a third metal layer disposed adjacent to each other at a height perpendicular to the surface of the wafer, a first primary plug connecting the first metal layer and the second metal layer is formed between the first metal layer and the second metal layer, and a second primary plug electrically connected to the third metal layer is formed in the third metal layer; the first patterned metal layer, the second patterned metal layer, and the third patterned metal layer are all formed by patterning the first metal layer, the second metal layer, and the third metal layer, the first contact plug is formed when fabricating the first primary plug, and the second contact plug is formed when fabricating the second primary plug.

[0013] Optionally, the first conductive line includes a first main line and a first branch line. The first main line is folded and bent, the first branch line is arranged along the first main line and connected to the first main line, and the projection of the first branch line on the wafer surface is directed toward the second conductive line.

[0014] Optionally, there are multiple first branch lines, and each first branch line is provided with a first contact plug, and multiple first contact plugs are evenly distributed on the first main line.

[0015] Optionally, the second conductive line includes a second main line and a second branch line. The projection of the second main line on the wafer surface surrounds the projection of the first conductive line on the wafer surface. The second branch line intersects with the second main line, and the extension direction of the projection of the second branch line on the wafer surface is toward the projection of the first conductive line on the wafer surface.

[0016] Optionally, there are multiple second branch lines, and each second branch line is provided with a second contact plug, and multiple second contact plugs are evenly distributed on the second main line.

[0017] Optionally, the number of the first branch lines is the same as the number of the second branch lines, and the distance between the first branch lines and the second branch lines is less than or equal to the preset threshold.

[0018] Optionally, the first region includes the dicing groove of the wafer.

[0019] Optionally, it also includes at least two first connection pins disposed on the first conductive line, and the first conductive line between the two first connection pins is a direct connection line;

[0020] It also includes at least one second connection pin disposed on the second conductive line.

[0021] This application also provides a testing system, including the aforementioned testing structure and a detection module, comprising two connection terminals, both of which are connected to the first conductive line to obtain the electrical parameters of the first conductive line, and / or, one connection terminal is connected to the first conductive line and the other connection terminal is connected to the second conductive line to obtain the electrical parameters between the first and second conductive lines.

[0022] Optionally, the first conductive line is provided with at least two first connection pins, and the first conductive line between the two first connection pins is a direct connection line; the second conductive line is provided with at least one second connection pin; one end of the detection module is connected to one of the first connection pins, and the other end is connected to the other of the first connection pins, or connected to the second connection pin.

[0023] Optionally, the detection module includes a ohmmeter.

[0024] This application also provides a testing method, comprising the following steps: forming a first conductive line in a first height region, wherein a first contact plug is formed on the first conductive line; forming a second conductive line in a second height region, wherein a second contact plug is formed on the second conductive line, the distance between the second contact plug and the first contact plug being a preset threshold, wherein the first height region and the second height region are adjacently distributed along a direction perpendicular to the wafer surface; detecting the electrical signal between any two points on the first conductive line to obtain the corresponding electrical parameters; detecting the electrical signal between a point on the second conductive line and a point on the first conductive line to obtain the corresponding electrical parameters; and obtaining test results based on the electrical parameters.

[0025] Optionally, the electrical parameters include resistance.

[0026] Optionally, when forming the first conductive line in the first height region, the method includes the following steps: patterning a first metal layer and a second metal layer in the first height region, wherein the first metal layer and the second metal layer are formed when the semiconductor is fabricated using the wafer, to form a first main line and a first branch line, wherein the projection of the first main line on the wafer surface is folded and bent, the first branch line is disposed along the first main line and connected to the first main line, and the projection of the first branch line on the wafer surface is disposed toward the second conductive line.

[0027] Optionally, when forming the second conductive line in the second height region, the method includes the following steps: patterning a third metal layer disposed in the second height region, wherein the third metal layer is a third metal layer formed when the semiconductor is fabricated using the wafer, to form a second main line and a second branch line, wherein the projection of the second main line on the wafer surface surrounds the projection of the first conductive line on the wafer surface, the second branch line intersects with the second main line, and the extension direction of the projection of the second branch line on the wafer surface is toward the projection of the first conductive line on the wafer surface.

[0028] The test structure, test system, and test method of this application are equipped with two conductive lines to detect short circuits between two adjacent through holes of different heights. The electrical detection method is used for direct detection, which can obtain intuitive electrical signals to directly determine whether there is a short circuit, making it more accurate and effectively reducing the probability of missed or false detections. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application.

[0030] Figure 1 This is a schematic diagram of the structure of a through-hole chain in the prior art.

[0031] Figure 2 This is a schematic diagram of the existing technology for detecting short circuits between the upper and lower contact plugs.

[0032] Figure 3 This is a schematic diagram of the test structure described in one embodiment of this application.

[0033] Figure 4 for Figure 3 A cross-sectional view of the test structure in the embodiment described herein, viewed from the direction shown in AB.

[0034] Figure 5 This is a schematic diagram of the test structure described in one embodiment of this application.

[0035] Figure 6 This is a schematic diagram of the contact plug shifting in one embodiment of this application.

[0036] Figure 7 This is a schematic diagram of the structure of the test system described in one embodiment of this application.

[0037] Figure 8 This is a flowchart illustrating the steps of the testing method described in one embodiment of this application. Detailed Implementation

[0038] The following description, in conjunction with the accompanying drawings and embodiments, further illustrates the test structure, test system, and test method.

[0039] Please see Figure 3 This is a schematic diagram of the test structure described in one embodiment of this application.

[0040] This application provides a test structure disposed on a wafer and located in a first region of the wafer, for detecting short circuits of contact plugs at different heights.

[0041] In this embodiment, the test structure includes a first conductive line 301 and a second conductive line 302, wherein the first conductive line 301 includes a first contact plug VIA1 disposed on a first height region, and the second conductive line 302 includes a second contact plug VIA2 disposed on a second height region.

[0042] In this embodiment, the first contact plug VIA1 includes a first through hole and a conductive material disposed within the first through hole. The second contact plug VIA2 includes a second through hole and a conductive material disposed within the second through hole. The conductive material includes a conductive metal material.

[0043] In this embodiment, the distance between the projections of the first contact plug VIA1 and the second contact plug VIA2 on the wafer surface is a preset threshold. If the first contact plug VIA1 and the second contact plug VIA2 shift relative to the preset position during formation, and the shift is sufficiently large, causing their projections on the wafer surface to connect, a short circuit will occur between the upper and lower contact plugs. Alternatively, if the shape or size of the first contact plug VIA1 or the second contact plug VIA2 changes compared to the preset shape or size during formation, and this change causes their projections on the wafer surface to connect, a short circuit will also occur between the upper and lower contact plugs.

[0044] In this embodiment, the preset threshold can be set according to the needs and the specific size requirements of the structure formed on the wafer to be tested. The smaller the preset threshold, the smaller the acceptable range of offset or change of the first contact plug VIA1 and the second contact plug VIA2 during the fabrication process, and the higher the measurement sensitivity of the short circuit between the upper and lower contact plugs.

[0045] The open circuit status of the first conductive line 301 between any two points can be determined by detecting the resistance between those two points. Specifically, if the resistance between the two connecting pins of the first conductive line 301 is infinite, it indicates that the first conductive line 301 is currently open.

[0046] The short circuit status between the first conductive line 301 and the second conductive line 302 can be determined by detecting the resistance between a point on the first conductive line 301 and a point on the second conductive line 302. Specifically, when the resistance between a point on the first conductive line 301 and a point on the second conductive line 302 is zero, it indicates that there is a short circuit between the first conductive line 301 and the second conductive line 302.

[0047] In one embodiment, for ease of testing, the test structure further includes at least two first connection pins (PIN1 and PIN2) disposed on the first conductive line 301, and the first conductive line 301 between the two first connection pins (PIN1 and PIN2) is a direct connection line.

[0048] To facilitate testing, the test structure also includes at least one second connection pin PIN3, which is disposed on the second conductive line 302.

[0049] Please see Figure 4 ,for Figure 3 A cross-sectional view of the test structure in the embodiment described herein, viewed from the direction shown in AB.

[0050] In this embodiment, the first conductive line 301 includes at least a first patterned metal layer MET1 and a second patterned metal layer MET2 arranged sequentially along the height direction, and a first contact plug VIA1 electrically connecting at least the two patterned metal layers, wherein the height direction is perpendicular to the wafer surface.

[0051] A first separation layer is provided between the first patterned metal layer MET1 and the second patterned metal layer MET2. The first separation layer may be made of an insulating material, and the through hole of the first contact plug is formed in the first separation layer.

[0052] A second separation layer is provided between the second patterned metal layer MET2 and the third patterned metal layer MET3. The second separation layer may be made of an insulating material, and the through hole of the second contact plug is formed in the second separation layer.

[0053] The insulating material includes silicon oxide, silicon nitride, etc. In fact, in some other embodiments, the first patterned metal layer MET1 and the second patterned metal layer MET2 may also be directly adjacent to each other.

[0054] exist Figure 3 , Figure 4In the illustrated embodiment, the first patterned metal layer MET1 is in the form of discontinuous lines, and these discontinuous lines are serpentine to increase their length. The second patterned metal layer MET2 is also in the form of discontinuous lines, intersecting with the first patterned metal layer MET1 and at least partially intersecting it. The first contact plug VIA1 is formed in the intersecting area to connect the first patterned metal layer MET1 and the second patterned metal layer MET2, which are of different heights, thereby achieving an electrical connection between the two patterned metal layers.

[0055] The first patterned metal layer MET1, the second patterned metal layer MET2, and the first contact plug VIA1 together constitute the first conductive line 301.

[0056] exist Figure 3 In the illustrated embodiment, the second conductive line 302 includes at least a third patterned metal layer MET3 and a portion of the second patterned metal layer MET2. The portion of the second patterned metal layer MET2 also partially overlaps with the third patterned metal layer MET3, and the second contact plug is formed in this overlapping area. Furthermore, the third patterned metal layer MET3, the second patterned metal layer MET2, and the first patterned metal layer MET1 are stacked sequentially in a direction perpendicular to the upper surface of the wafer.

[0057] In another embodiment, one end of the second contact plug is electrically connected only to the third patterned metal layer MET3, and the other end is connected to other patterned metal layers.

[0058] In one embodiment, the wafer is used to fabricate a semiconductor structure including a first metal layer, a second metal layer, and a third metal layer disposed adjacent to each other at a height perpendicular to the surface of the wafer. A first primary plug is formed between the first and second metal layers, connecting the first and second metal layers. A second primary plug is formed in the third metal layer, penetrating the second and third metal layers. The third metal layer, the second primary plug, the second metal layer, the first metal layer, and the first primary plug are sequentially fabricated on the wafer.

[0059] The first patterned metal layer MET1 and the second patterned metal layer MET2 are formed after patterning the first metal layer and the second metal layer, and the third patterned metal layer MET3 is formed after patterning the third metal layer. The first contact plug VIA1 is formed when forming the first original plug, and the second contact plug VIA2 is formed when forming the second original plug.

[0060] The shape, size, and positional deviation of the first contact plug VIA1 correspond one-to-one with the shape, size, and positional deviation of the first original plug, and the shape, size, and positional deviation of the second contact plug VIA2 correspond one-to-one with the shape, size, and positional deviation of the second original plug. Therefore, by detecting the short circuit between the first contact plug VIA1 and the second contact plug VIA2, the short circuit between the first original plug and the second original plug can be determined, thereby determining whether there are shape, size, and positional deviations in the first and second original plugs, and whether the semiconductor device is qualified.

[0061] In one embodiment, the first region where the test structure is located includes a dicing groove on the wafer to prevent the first conductive line 301 and the second conductive line 302 from affecting the structure of the semiconductor device formed in the non-dicing groove region of the wafer. In practice, the specific location of the first region can also be set as needed.

[0062] exist Figure 3 In the illustrated embodiment, in order to increase the detection sensitivity for open circuits and short circuits, the second conductive line 302 is arranged around the first conductive line 301, thereby increasing the possibility of short circuits when the first contact plug VIA1 and / or the second contact plug VIA2 have deviations in shape, size, and position.

[0063] Furthermore, in Figure 3 In the illustrated embodiment, to increase the detection sensitivity for open circuits and short circuits, multiple first contact plugs VIA1 and second contact plugs VIA2 are also provided. Figure 3 In the embodiment shown, the first contact plug VIA1 and the second contact plug VIA2 are evenly distributed on the first conductive line 301 and the second conductive line 302, respectively.

[0064] Please see Figure 5 This is a schematic diagram of the test structure described in one embodiment.

[0065] The first conductive line 301 includes a first main line 3011 and a first branch line 3012. The first main line 3011 is folded and bent. The first branch line 3012 is arranged along the first main line 3011 and connected to the first main line 3011. The projection of the first branch line 3012 on the wafer surface is directed toward the second conductive line 302.

[0066] There are multiple first branch lines 3012, and each first branch line 3012 is provided with a first contact plug VIA1. Multiple first contact plugs VIA1 are evenly distributed on the first main line 3011.

[0067] In fact, the first contact plug VIA1 can also be set at a non-end position of the first branch line 3012.

[0068] In this embodiment, the second conductive line 302 includes a second main line 3021 and a second branch line 3022. The projection of the second main line 3021 on the wafer surface surrounds the projection of the first conductive line 301 on the wafer surface. The second branch line 3022 intersects with the second main line 3021, and the extension direction of the projection of the second branch line 3022 on the wafer surface is toward the projection of the first conductive line 301 on the wafer surface.

[0069] There are multiple second branch lines 3022, and each second branch line 3022 is provided with a second contact plug VIA2. Multiple second contact plugs VIA2 are evenly distributed on the second main line 3021.

[0070] In fact, the second contact plug VIA2 can also be set at a non-end position of the second branch line 3022.

[0071] exist Figure 5 In the embodiment shown, the distance between the projection of the second contact plug VIA2 on the second branch line 3022 and the first contact plug VIA1 on the first conductive line 301 onto the wafer surface is equal to the preset threshold.

[0072] In this embodiment, both the first conductive line 301 and the second conductive line 302 are provided with a main line and a branch line, respectively. Since there are more first contact plugs VIA1 and second contact plugs VIA2, the sensitivity of the short-circuit detection can be effectively improved. In practice, the branch line can also be provided on only one of the first conductive lines as needed.

[0073] Please see Figure 6 ,for Figure 5 A schematic diagram of the contact plug shifting in the embodiments described herein.

[0074] In this embodiment, the first contact plug VIA1 and the second contact plug VIA2 are offset from their original preset positions during the formation process, and the offset is such that the projections of the first contact plug VIA1 and the second contact plug VIA2 on the wafer surface are connected, resulting in a short circuit between the upper and lower contact plugs. A resistance measurement performed on any point on the first conductive line 301 and a point on the second conductive line 302 yields a resistance value of 0.

[0075] In fact, when the shape and size of the first contact plug VIA1 or the second contact plug VIA2 change compared to the preset shape and size, it may also cause a short circuit between the upper and lower contact plugs.

[0076] The preset threshold value can be set according to the needs and the specific size requirements of the structure formed on the wafer to be tested. The larger the preset threshold value, the greater the range of acceptable offset or change of the first contact plug VIA1 and the second contact plug VIA2 during the fabrication process, and the lower the measurement sensitivity of the short circuit between the upper and lower contact plugs.

[0077] An embodiment of this application also provides a testing system.

[0078] Please see Figure 7 This is a schematic diagram of the test system described in one embodiment.

[0079] In this embodiment, the testing system includes the testing structure described in the above embodiments, and a detection module, including two connection terminals. Both connection terminals are connected to the first conductive line 301 to obtain the electrical parameters of the first conductive line 301, and / or, one connection terminal is connected to the first conductive line 301 and the other connection terminal is connected to the second conductive line 302 to obtain the electrical parameters between the first conductive line 301 and the second conductive line 302.

[0080] The first conductive line 301 is provided with at least two first connection pins (PIN1 and PIN2), and the first conductive line 301 between the two first connection pins (PIN1 and PIN2) is a direct connection line; the second conductive line 302 is provided with at least one second connection pin PIN3; one end of the detection module is connected to one of the first connection pins (PIN1 and PIN2), and the other end is connected to the other of the first connection pins (PIN1 and PIN2), or connected to the second connection pin PIN3.

[0081] The detection module includes a ohmmeter. The ohmmeter is used to measure resistance, obtain the resistance between any two points on the first conductive line 301, determine whether there is an open circuit between these two points, and obtain the resistance between a point on each of the first conductive line 301 and the second conductive line 302, determine whether there is a short circuit between the first conductive line 301 and the second conductive line 302, thereby determining whether there is a short circuit between the first through hole and the second through hole.

[0082] An embodiment of this application also provides a testing method.

[0083] Please see Figure 8 This is a flowchart illustrating the steps of the testing method described in one embodiment.

[0084] In this embodiment, the testing method includes the following steps:

[0085] Step S101: A first conductive line 301 is formed in the first height region, and a first contact plug VIA1 is formed on the first conductive line 301.

[0086] In this embodiment, the first conductive line 301 includes at least a first patterned metal layer MET1 and a second patterned metal layer MET2 arranged sequentially along the height direction, and a first contact plug VIA1 penetrating at least the two patterned metal layers, wherein the height direction is perpendicular to the wafer surface.

[0087] exist Figure 4 In the illustrated embodiment, a separating layer SEP1 is provided between the first patterned metal layer MET1 and the second patterned metal layer MET2. This separating layer SEP1 can be an insulating layer made of an insulating material, such as silicon oxide or silicon nitride. In fact, in some other embodiments, the first patterned metal layer MET1 and the second patterned metal layer MET2 may also be directly adjacent to each other.

[0088] exist Figure 3 , Figure 4 In the illustrated embodiment, the first patterned metal layer MET1 is in the form of discontinuous lines, and these discontinuous lines are serpentine to increase their length. The second patterned metal layer MET2 is also in the form of discontinuous lines, intersecting with the first patterned metal layer MET1 and at least partially intersecting it. The first contact plug VIA1 is formed in the intersecting area to connect the first patterned metal layer MET1 and the second patterned metal layer MET2, which are of different heights, thereby achieving an electrical connection between the two patterned metal layers.

[0089] The first patterned metal layer MET1, the second patterned metal layer MET2, and the first contact plug VIA1 together constitute the first conductive line 301.

[0090] In one embodiment, when forming a first conductive line 301 in a first height region, the method includes the following steps: patterning a first metal layer and a second metal layer disposed in the first height region, wherein the first metal layer and the second metal layer are first metal layers and second metal layers formed when the semiconductor is fabricated using the wafer, to form a first main line 3011 and a first branch line 3012, wherein the projection of the first main line 3011 on the wafer surface is folded and bent, the first branch line 3012 is disposed along the first main line 3011 and connected to the first main line 3011, and the projection of the first branch line 3012 on the wafer surface is disposed toward the second conductive line 302.

[0091] Step S102: A second conductive line 302 is formed in the second height region. A second contact plug VIA2 is formed on the second conductive line 302. The distance between the second contact plug VIA2 and the first contact plug VIA1 is a preset threshold. The first height region and the second height region are adjacent to each other along the direction perpendicular to the wafer surface.

[0092] The second conductive line 302 includes at least a third patterned metal layer MET3, which is stacked with the first patterned metal layer MET1 and the second patterned metal layer MET2 along the height direction.

[0093] In one embodiment, when forming the second conductive line 302 in the second height region, the method includes the following steps: patterning a third metal layer disposed in the second height region, the third metal layer being a third metal layer formed when the semiconductor is fabricated using the wafer, to form a second main line 3021 and a second branch line 3022, wherein the projection of the second main line 3021 on the wafer surface surrounds the projection of the first conductive line 301 on the wafer surface, the second branch line 3022 intersects with the second main line 3021, and the extension direction of the projection of the second branch line 3022 on the wafer surface is toward the projection of the first conductive line 301 on the wafer surface.

[0094] In one embodiment, the wafer is used to fabricate a semiconductor structure, the semiconductor structure including a first metal layer, a second metal layer and a third metal layer disposed adjacent to each other at a height perpendicular to the surface of the wafer, a first primary plug connecting the first metal layer and the second metal layer is formed between the first metal layer and the second metal layer, and a second primary plug penetrating the third metal layer is formed in the third metal layer.

[0095] The first patterned metal layer MET1 and the second patterned metal layer MET2 are formed after patterning the first metal layer and the second metal layer, and the third patterned metal layer MET3 is formed after patterning the third metal layer. The first contact plug VIA1 is formed when forming the first original plug, and the second contact plug VIA2 is formed when forming the second original plug.

[0096] The shape, size, and positional deviation of the first contact plug VIA1 correspond one-to-one with the shape, size, and positional deviation of the first original plug, and the shape, size, and positional deviation of the second contact plug VIA2 correspond one-to-one with the shape, size, and positional deviation of the second original plug. Therefore, by detecting the short circuit between the first contact plug VIA1 and the second contact plug VIA2, the short circuit between the first original plug and the second original plug can be determined, thereby determining whether there are shape, size, and positional deviations in the first and second original plugs, and whether the semiconductor device is qualified.

[0097] In this embodiment, the distance between the projections of the first contact plug VIA1 and the second contact plug VIA2 on the wafer surface is a preset threshold. If the first contact plug VIA1 and the second contact plug VIA2 shift relative to the preset position during formation, and the shift is sufficiently large, causing their projections on the wafer surface to connect, a short circuit will occur between the upper and lower contact plugs. Alternatively, if the shape or size of the first contact plug VIA1 or the second contact plug VIA2 changes compared to the preset shape or size during formation, and this change causes their projections on the wafer surface to connect, a short circuit will also occur between the upper and lower contact plugs.

[0098] In this embodiment, the preset threshold can be set according to the needs and the specific size requirements of the structure formed on the wafer to be tested. The smaller the preset threshold, the smaller the acceptable range of offset or change of the first contact plug VIA1 and the second contact plug VIA2 during the fabrication process, and the higher the measurement sensitivity of the short circuit between the upper and lower contact plugs.

[0099] Step S103: Detect the electrical signal between any two points on the first conductive line 301 to obtain the corresponding electrical parameters.

[0100] The electrical parameters include resistance. The open circuit status of the first conductive line 301 between any two points is determined by detecting the resistance between those two points. Specifically, if the resistance between the two connecting pins of the first conductive line 301 is infinite, it indicates that the first conductive line 301 is currently open.

[0101] Step S104: Detect the electrical signal between a point on the second conductive line 302 and a point on the first conductive line 301 to obtain the corresponding electrical parameters.

[0102] By detecting the resistance between a point on the first conductive line 301 and a point on the second conductive line 302, the short circuit status between the two lines can be determined. Specifically, when the resistance between a point on the first conductive line 301 and a point on the second conductive line 302 is zero, it indicates that a short circuit exists between the two lines.

[0103] Step S105: Obtain test results based on the electrical parameters.

[0104] The test results include: there is no short circuit between the first contact plug VIA1 and the second contact plug VIA2, or there is a short circuit between the first contact plug VIA1 and the second contact plug VIA2.

[0105] The test structure in the embodiments of this application retains the original open circuit detection function of the contact plug and adds test patterns of different layers. By measuring the resistance of the test patterns, the short circuit detection of the upper and lower contact plugs can be realized simultaneously. This realizes the use of electrical methods to check whether a short circuit has occurred between the upper and lower contact plugs, which is more direct and less prone to missed detection or false detection.

[0106] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A test structure, characterized by, The test structure is disposed on a wafer, and is located in a first region of the wafer, and the test structure comprises: a first conductive circuit comprising a first contact plug disposed in a first height region, the first contact plug comprising a first via, and a conductive material disposed in the first via; a second conductive circuit comprising a second contact plug disposed in a second height region, the second contact plug comprising a second via, and a conductive material disposed in the second via; the first height region and the second height region are adjacently distributed along a direction perpendicular to a surface of the wafer, and a distance between projections of the first contact plug and the second contact plug on the surface of the wafer is a preset threshold value; the first conductive circuit further comprises at least a first patterned metal layer and a second patterned metal layer disposed in the first height region, and the conductive material in the first contact plug is electrically connected to at least the first patterned metal layer and the second patterned metal layer; the second conductive circuit further comprises at least a third patterned metal layer disposed in the second height region, and the conductive material in the second contact plug is electrically connected to at least the third patterned metal layer; wherein the first patterned metal layer and the second patterned metal layer are staggered, and each is in the form of an intermittent line, the second patterned metal layer at least partially intersects the first patterned metal layer, and the first contact plug is formed in the intersecting region; and the first conductive circuit comprises a first main circuit and a first branch circuit, the first main circuit is arranged in a folded manner, the first branch circuit is arranged along the first main circuit and connected to the first main circuit, and a projection of the first branch circuit on the surface of the wafer is arranged towards the second conductive circuit.

2. The test structure of claim 1, wherein, The first region comprises a scribe groove of the wafer; the wafer is used to prepare a semiconductor structure, and the semiconductor structure comprises a first metal layer, a second metal layer, and a third metal layer adjacently disposed in a height direction perpendicular to a surface of the wafer, a first original plug is formed between the first metal layer and the second metal layer to connect the first metal layer and the second metal layer, and a second original plug is formed in the third metal layer to electrically connect the third metal layer; the first patterned metal layer, the second patterned metal layer, and the third patterned metal layer are formed by patterning the first metal layer, the second metal layer, and the third metal layer, the first contact plug is formed when the first original plug is prepared, and the second contact plug is formed when the second original plug is prepared.

3. The test structure of claim 1, wherein, The first branch circuit comprises a plurality of first branch circuits, and each of the first branch circuits is provided with the first contact plug, and a plurality of the first contact plugs are uniformly distributed on the first main circuit.

4. The test structure of claim 1, wherein, The second conductive circuit comprises a second main circuit and a second branch circuit, a projection of the second main circuit on the surface of the wafer surrounds a projection of the first conductive circuit on the surface of the wafer, the second branch circuit intersects the second main circuit, and an extension direction of a projection of the second branch circuit on the surface of the wafer is towards the projection of the first conductive circuit on the surface of the wafer. The second branch lines are multiple, and each of the second branch lines is provided with the second contact plug.

5. The test structure of claim 1, wherein, The first connecting pins are arranged on the first conductive line. The second connecting pin is arranged on the second conductive line.

6. A test system, characterized by The test structure comprises the test structure according to any one of claims 1 to 5, and: The detection module comprises two connecting ends, each of which is connected to the first conductive line to obtain the electrical parameter of the first conductive line, and / or one connecting end is connected to the first conductive line and the other connecting end is connected to the second conductive line to obtain the electrical parameter between the first conductive line and the second conductive line.

7. The test system of claim 6, wherein, The detection module comprises a resistance meter; the first conductive line is provided with at least two first connecting pins, and the first conductive line between the two first connecting pins is a straight line. The second conductive line is provided with at least one second connecting pin. One end of the detection module is connected to one of the first connecting pins, and the other end is connected to the other first connecting pin or the second connecting pin.

8. A test method applied to the test structure of any one of claims 1 to 5, characterized in that, The method comprises the following steps: The first conductive line is formed in the first height region, and the first contact plug is formed on the first conductive line, wherein the first metal layer and the second metal layer are patterned on the first height region, and the first metal layer and the second metal layer are first metal layers and second metal layers formed when a wafer is used to prepare a semiconductor, to form a first main line and a first branch line, the projection of the first main line on the surface of the wafer is folded and bent, and the first branch line is arranged along the first main line and connected to the first main line; The second conductive line is formed in the second height region, and the projection of the first branch line on the surface of the wafer is arranged towards the second conductive line, the second contact plug is formed on the second conductive line, the distance between the second contact plug and the first contact plug is a preset threshold, and the first height region and the second height region are adjacently distributed along the direction perpendicular to the surface of the wafer; The electrical signal between any two points on the first conductive line is detected to obtain the corresponding electrical parameter; The electrical signal between a point on the second conductive line and a point on the first conductive line is detected to obtain the corresponding electrical parameter; The test result is obtained based on the electrical parameter.

9. The test method of claim 8, wherein, The electrical parameter comprises resistance.

10. The test method of claim 8, wherein, When the second conductive line is formed in the second height region, the following steps are included: A third metal layer is patterned on the second height region, the third metal layer being a third metal layer formed when the wafer is used to fabricate a semiconductor, to form a second main line and a second branch line, a projection of the second main line on the wafer surface encircles a projection of the first conductive line on the wafer surface, the second branch line intersects the second main line, and an extension direction of a projection of the second branch line on the wafer surface is toward a projection of the first conductive line on the wafer surface.

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