Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method for forming the same, wherein the semiconductor device includes: a substrate; a plurality of fins including a plurality of channel layers along the normal direction of the substrate surface; a dividing layer located between at least a pair of adjacent fins, with a gap between the dividing layer and the channel layer; and a gate structure located on the substrate and spanning a plurality of the fins and surrounding the channel layer. Since there is a gap between the dividing layer and the channel layer, after the gate structure spanning the fins is formed on the substrate, the gate structure can surround the periphery of the channel layer, so that the control ability of the gate structure over the channel layer is enhanced, thereby improving the performance of the finally formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the most important components in modern integrated circuits. The basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; source and drain doping regions in the semiconductor substrate on both sides of the gate structure.

[0003] With the development of semiconductor technologies, the ability of traditional planar MOSFETs to control channel current becomes weaker, resulting in serious leakage current. A fin field-effect transistor (Fin FET) is an emerging multi-gate device. It generally includes fins protruding from the surface of the semiconductor substrate, a gate structure covering the top surface and sidewalls of part of the fins, and source and drain doping regions in the fins on both sides of the gate structure. Compared with planar MOSFETs, fin field-effect transistors have stronger short-channel suppression ability and stronger working current.

[0004] With the further development of semiconductor technologies, traditional fin field-effect transistors have limitations in further increasing the working current. Specifically, since only the regions near the top surface and sidewalls in the fins are used as the channel region, the volume of the fins used as the channel region is small, which limits the increase in the working current of fin field-effect transistors. Therefore, a MOSFET with a gate all around (GAA) structure is proposed, which increases the volume used as the channel region and further increases the working current of the GAA structure MOSFET.

[0005] However, the electrical performance of GAA structure MOSFETs in the prior art still needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor device.

[0007] To solve the above problems, the present invention provides a semiconductor device, including: a substrate; a plurality of fins, including a plurality of channel layers along the normal direction of the surface of the substrate; a dividing layer located between at least a pair of adjacent fins, and there is a gap between the dividing layer and the channel layer; a gate structure located on the substrate and spanning a plurality of the fins, and surrounding the channel layer.

[0008] Optionally, the size of the gap between the dividing layer and the channel layer is from 0 nm to 20 nm.

[0009] Optionally, the top surface of the dividing layer is higher than the top surface of the fin.

[0010] Optionally, the material of the dividing layer is a dielectric material.

[0011] Correspondingly, the present invention further provides a method for forming a semiconductor device, including: providing a substrate; forming a plurality of discretely arranged fins on the substrate, with isolation trenches between adjacent fins, and the fins including a plurality of fin sacrificial layers overlapping in a direction perpendicular to the surface of the substrate and an initial channel layer located between two adjacent fin sacrificial layers; etching away a part of the initial channel layer on the sidewall of the isolation trench to form a channel layer; forming a sacrificial layer on the sidewall of the channel layer; forming a dividing layer in at least one of the isolation trenches; etching away the sacrificial layer to form a gap between the dividing layer and the channel layer.

[0012] Optionally, before etching away the sacrificial layer to form a gap between the dividing layer and the channel layer, it further includes: forming a dummy gate structure across a plurality of the fins on the substrate.

[0013] Optionally, after forming the dummy gate structure, the step of etching away the sacrificial layer to form a gap between the dividing layer and the channel layer includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewall of the dummy gate structure; removing the dummy gate structure to form a gate opening in the dielectric layer; removing the fin sacrificial layer and the sacrificial layer exposed by the gate opening, forming a gate trench between adjacent channel layers, and forming a gap between the dividing layer and the channel layer.

[0014] Optionally, the size of the gap between the dividing layer and the channel layer is from 0 nm to 20 nm.

[0015] Optionally, after forming a gap between the dividing layer and the channel layer, a gate structure is formed in the gate opening and the gate trench, and the gate structure surrounds the channel layer.

[0016] Optionally, the material of the dividing layer is a dielectric material.

[0017] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0018] In the semiconductor device of the present invention, since there is a gap between the dividing layer and the channel layer, after forming a gate structure across the fin on the substrate, the gate structure can surround the four sides of the channel layer. On the one hand, due to the existence of the gap, the gate structure can surround the four side surfaces of the channel layer, thereby enhancing the control ability of the gate structure over the channel layer; on the other hand, due to the existence of the gap, the impurities between the gate structure and the channel layer are reduced, thereby improving the performance of the finally formed semiconductor device.

[0019] In the forming method of the present invention, a part of the initial channel layer on the sidewall of the isolation trench is etched away to form a channel layer; a sacrificial layer is formed on the sidewall of the channel layer, a dividing layer is formed in at least one isolation trench, and after removing the sacrificial layer, a gap can be formed between the dividing layer and the channel layer. In this way, when forming the gate structure, the gap between the dividing layer and the channel layer can also form the gate structure, so that the formed gate structure can surround the four sidewalls of the channel layer, enhancing the control ability of the gate structure over the channel layer and improving the electrical performance of the formed semiconductor device; and because a sacrificial layer is formed on the sidewall of the channel layer, during the process of removing the fin sacrificial layer and the sacrificial layer before forming the gate structure, it is also convenient to remove the fin sacrificial layer, reducing the difficulty of removing the fin sacrificial layer and reducing the impurities between the gate structure and the channel layer. This is because the existence of the sacrificial layer increases the distance between the channel layer and the dividing layer, and there is no fin sacrificial layer at the corner between the channel layer and the dividing layer, so the difficulty of removing the fin sacrificial layer is greatly reduced, and there is less fin sacrificial layer between the gate structure and the channel layer, thereby improving the quality of the finally formed semiconductor device. Brief Description of the Drawings

[0020] Figures 1 to 3 is a schematic structural diagram of a semiconductor device;

[0021] Figures 4 to 17 is a schematic diagram of the structures of the steps of an embodiment of the forming method of the semiconductor device of the present invention. Detailed Embodiments

[0022] Currently, as the size of the GAA structure MOSFET decreases, when cutting the gate structure to form the required semiconductor device, a Forksheet GAA structure MOSFET is introduced, but the electrical performance of this structure of GAA structure MOSFET still needs to be improved. The following will be specifically described with reference to the drawings.

[0023] Please refer to Figure 1, a substrate 100 is provided; a plurality of fin structures 101 arranged in parallel along a first direction are formed on the substrate 100, and an isolation trench (not labeled) is provided between adjacent fin structures 101. The fin structure 101 includes a plurality of fin sacrificial layers 103 overlapping along the normal direction of the surface of the substrate 100, and a channel layer 104 located between two adjacent fin sacrificial layers 103; an isolation structure 106 is provided on the substrate 100, and a dummy gate structure 105 spanning adjacent fin structures 101 is formed on the substrate 100. The dummy gate structure 105 extends along a second direction, and the first direction is perpendicular to the second direction.

[0024] Please refer to Figure 2 , a part of the dummy gate structure 105 is removed to expose the isolation trench; a split layer 102 is formed in the isolation trench.

[0025] Please refer to Figure 3 , after the split layer 102 is formed, the dummy gate structure 105 and the fin sacrificial layer 103 are removed to form a gate opening and a gate trench, and a gate structure 107 is formed in the gate opening and the gate trench.

[0026] The inventor found that in the above embodiments, the formed partition layer 102 covers one side wall of the fin sacrificial layer 103. In subsequent processes, the fin sacrificial layer 103 and the pseudo-gate structure 105 need to be removed by a wet etching process to form a gate trench and a gate opening. However, since one side wall of the fin sacrificial layer 103 is covered by the partition layer 102, during the process of removing the fin sacrificial layer 103, the etching solution can only etch and remove it from the other side wall of the fin sacrificial layer 103. This will not only affect the etching efficiency, but also cause incomplete removal of the fin sacrificial layer 103 at the corner of the channel layer 104 and the partition layer 102 and the fin sacrificial layer 103 covered by the partition layer 102. Additionally, after forming the gate trench, a gate structure needs to be formed in the gate trench, and the gate structure surrounds the channel layer 104. However, since one side of the gate trench is covered and blocked by the partition layer 102, during the process of forming the gate structure, the deposition of the gate structure can only be carried out from the other side of the gate trench. This will not only affect the formation efficiency, but also result in a low density of the finally formed gate structure. Moreover, the formed gate structure can only surround the channel layer 104 on three sides, reducing the area of the channel region formed by the gate structure surrounding the channel layer 104, thereby affecting the performance of the finally formed semiconductor device. Furthermore, in this embodiment, after forming the pseudo-gate structure, the pseudo-gate structure is etched to expose the isolation trenches between the fins, and then a partition layer is formed in the isolation trenches. During the process of etching the pseudo-gate structure to expose the isolation trenches between the fins and forming a partition layer in the isolation trenches, there is easily a problem of photomask misalignment. In this way, there is an easy overlap phenomenon between the formed partition layer and the fins, making it difficult to control the distance between the partition layer and the fins.

[0027] The inventor found through research that before forming the partition layer, a part of the initial channel layer on the side wall of the isolation trench is etched and removed to form a channel layer, shortening the size of the channel layer. A sacrificial layer is formed on the side wall of the channel layer, and then a partition layer is formed in the isolation trench. This reduces the difficulty of removing the fin sacrificial layer in the subsequent process, making the fin sacrificial layer easier to remove. At the same time, the formed gate structure can surround the four sides of the channel layer, enhancing the control ability of the gate structure over the channel layer and enhancing the electrical performance of the finally formed semiconductor device.

[0028] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the drawings.

[0029] Figures 4 to 17 It is a schematic structural diagram of the formation process of a semiconductor device according to an embodiment of the present invention.

[0030] Please refer toFigure 4 , a substrate 200 is provided.

[0031] In this embodiment, the material of the substrate 200 is single crystal silicon.

[0032] In other embodiments, the substrate 200 may also be polycrystalline silicon or amorphous silicon. The material of the substrate 200 may also be semiconductor materials such as germanium, silicon germanide, gallium arsenide, silicon on insulator (SOI), germanium on insulator (GOI), etc.

[0033] Please refer to Figure 5 and Figure 6 , Figure 6 is Figure 5 a schematic cross-sectional view along line A-A in

[0034] On the substrate 200, a plurality of fin portions are formed and arranged in parallel along the first direction Y. An isolation trench 201 is provided between adjacent fin portions. The fin portion includes a plurality of fin sacrificial layers 202 that overlap along the normal direction of the surface of the substrate 200, and an initial channel layer 203 located between adjacent two layers of the fin sacrificial layers 202.

[0035] In this embodiment, the number of the fin portions is three; the number of layers of the fin sacrificial layer 202 is three; the number of layers of the initial channel layer 203 is three.

[0036] In this embodiment, the materials of the fin sacrificial layer 202 and the initial channel layer 203 are different. The purpose is that when forming the gate structure subsequently, the fin sacrificial layer 202 needs to be removed. Therefore, by using different materials for the fin sacrificial layer 202 and the initial channel layer 203, a large etching selectivity is obtained, and the damage to the initial channel layer 203 during the removal of the fin sacrificial layer 202 is reduced.

[0037] In this embodiment, the material of the fin sacrificial layer 202 is silicon germanium; the material of the initial channel layer 203 is single crystal silicon.

[0038] In this embodiment, after etching the fin material film to form the fins, the following steps are further included: etching a part of the thickness of the substrate 200 using the fins as a mask; forming an isolation structure 204 on the substrate 200, and the top surface of the isolation structure 204 is lower than the top surface of the substrate 200.

[0039] In this embodiment, the material of the isolation structure 204 is silicon nitride.

[0040] In other embodiments, the material of the isolation structure 204 may further include one or a combination of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride carbonitride (SiOCN), silicon carbonitride boron nitride (SiCBN), etc.

[0041] In this embodiment, the function of the isolation structure 204 is to form electrical isolation.

[0042] In this embodiment, before forming the fins, the following steps are further included: forming an initial hard mask on a fin material film (not shown), and then, when etching the fin material film to form the fins, a hard mask layer 205 is formed on the top surface of the fins.

[0043] In this embodiment, the material of the hard mask layer 205 is silicon nitride; in other embodiments, the material of the hard mask layer 205 may also be at least one of silicon oxide, silicon carbide, or silicon oxynitride.

[0044] In this embodiment, the function of the hard mask layer 205 is to protect the top surface of the fins, and during subsequent process steps, it can ensure that the top surface of the fins has good formation quality.

[0045] Please refer to Figure 7 , Figure 7 and Figure 6 in the same view direction, etch and remove a part of the initial channel layer 203 on the sidewall of the isolation trench 201 to form the channel layer 206.

[0046] In this embodiment, after etching and removing a part of the initial channel layer 203 on the sidewall of the isolation trench 201 to form the channel layer 206, grooves 207 are formed on both sides of the channel layer 206.

[0047] In this embodiment, the process of etching the initial channel layer 203 is a wet etching process, and in the wet etching process, tetramethylammonium hydroxide (TMAH) is used as the etching solution to ensure that during the process of etching a part of the thickness of the initial channel layer 203, the fin sacrificial layer 202 is not affected.

[0048] In this embodiment, the purpose of etching the initial channel layer 203 to form the channel layer 206 is to increase the distance between the sidewall of the channel layer 206 and the sidewall of the isolation trench 201, so as to prepare for the subsequent gate structure to surround the four sidewalls of the channel layer 206.

[0049] In this embodiment, when etching the initial channel layer 203 to form the channel layer 206, when forming the split layer subsequently, the sidewall of the split layer will not be in close contact with the sidewall of the channel layer 206, and the distance between the split layer and the fin is also easy to control.

[0050] Please refer to Figure 8 , Figure 8 and Figure 7 for the same viewing direction, and a sacrificial layer 208 is formed on the sidewall of the channel layer 206.

[0051] In this embodiment, the sacrificial layer 208 is formed in the groove 207.

[0052] In this embodiment, the material of the sacrificial layer 208 is silicon germanium; in other embodiments, the material of the sacrificial layer 208 can also be at least one of silicon germanium, amorphous silicon, amorphous germanium or silicon oxide.

[0053] In this embodiment, the process of forming the sacrificial layer 208 includes: forming an initial sacrificial layer on the surface of the isolation structure 204, the sidewalls of the fin sacrificial layer 202, the sidewalls of the channel layer 206, and the sidewalls and top of the hard mask layer 205, and then back-etching the initial sacrificial layer to form the sacrificial layer 208 in the groove 207.

[0054] In this embodiment, the material of the sacrificial layer 208 being silicon germanium, the same as that of the fin sacrificial layer 202, is for the purpose of simplifying the process, improving the rate and quality of subsequent removal of the sacrificial layer 208 and the fin sacrificial layer 202, thereby enhancing the rate and quality of forming semiconductor devices.

[0055] In this embodiment, the process of forming the initial sacrificial layer is a chemical vapor deposition process; in other embodiments, at least one of atomic layer deposition process and physical vapor deposition process can also be used.

[0056] Please refer to Figure 9 , Figure 9 and Figure 8 for the same viewing direction, and a split layer 209 is formed in at least one of the isolation trenches 201.

[0057] In this embodiment, the material of the dividing layer 209 is a dielectric material, specifically, it can be one or a combination of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), silicon carbonitride boron (SiCBN), etc.

[0058] In this embodiment, the process for forming the dividing layer 209 is atomic layer deposition process; in other embodiments, the process for forming the dividing layer 209 may further include chemical vapor deposition process.

[0059] In this embodiment, the steps for forming the dividing layer 209 include: forming an initial dividing layer in the isolation trench 201 and on the hard mask layer 205, planarizing the initial dividing layer until the top surface of the hard mask layer 205 is exposed, and forming the dividing layer 209 in the isolation trench 201.

[0060] In this embodiment, the reason for using atomic layer deposition process to form the dividing layer is that the atomic layer deposition process can form the dividing layer 209 with a better coverage gradient, can be filled in the isolation trench 201 with a higher rate, and improve the quality of the formed dividing layer 209.

[0061] In this embodiment, the dividing layer 209 is formed only in one isolation trench 201, and the dividing layer 209 is subsequently used for the division of the gate structure to achieve a gate cut at the dividing layer 209.

[0062] In other embodiments, the dividing layer 209 may also be formed in multiple isolation trenches 201 simultaneously, which can be designed according to the actual circuit design requirements.

[0063] In this embodiment, before forming the pseudo-gate structure, the dividing layer 209 is formed in the isolation trench 201, so that there is no misalignment problem during the lithography process, and the distance between the dividing layer 209 and the fin can be well controlled.

[0064] Please refer to Figure 10 and Figure 11 , Figure 11 is Figure 10 the cross-sectional schematic diagram along line B-B in Figure 10 , please refer to

[0065] In this embodiment, the dummy gate structure 210 includes: a dummy gate dielectric layer 211 located on the fin, a dummy gate layer 212 located on the dummy gate dielectric layer 211, a protective layer 213 located on the dummy gate layer 212, and a spacer 214 located on the sidewalls of the dummy gate layer 212 and the protective layer 213.

[0066] In this embodiment, the material of the dummy gate layer 212 is polysilicon; in other embodiments, the material of the dummy gate layer 212 can also be amorphous silicon.

[0067] In this embodiment, the material of the protective layer 213 is silicon nitride; in other embodiments, the material of the protective layer can also be silicon oxide.

[0068] The method for forming the spacer 214 includes: forming a spacer material layer (not shown) on the top surface of the dummy gate dielectric layer 211, the sidewalls of the dummy gate layer 212, and the sidewalls and top surface of the protective layer 213; etching back the spacer material layer until the top surfaces of the protective layer 213 and the gate dielectric layer 211 are exposed, to form the spacer 214.

[0069] The forming process of the spacer material layer is one or a combination of chemical vapor deposition process, physical vapor deposition process, or atomic layer deposition process.

[0070] In this embodiment, the forming process of the spacer material layer uses atomic layer deposition process.

[0071] The material of the spacer 214 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the spacer 214 is silicon nitride.

[0072] In this embodiment, the spacer 214 is used to define the position of the subsequent source / drain doping layer.

[0073] In this embodiment, before forming the dummy gate structure 210, the hard mask layer 205 is removed.

[0074] Please refer to Figure 12 and Figure 13 , Figure 13 is Figure 12 a cross-sectional schematic diagram along the C-C line in , after forming the dummy gate structure 210, the fins on both sides of the dummy gate structure 210 are etched to form source / drain recesses (not shown) in the fins, and source / drain doping layers 215 are formed in the source / drain recesses.

[0075] In this embodiment, the function of the source / drain recess is to provide space for the subsequently formed source / drain doping layers.

[0076] The process of etching the fin includes: an anisotropic dry etching process or an anisotropic wet etching process.

[0077] In this embodiment, the process of etching the fin is an anisotropic dry etching process. The parameters of the dry etching process include: the etching gas used includes HBr and Ar. Among them, the gas flow rate of HBr is 10 sccm to 1000 sccm, and the gas flow rate of Ar is 10 sccm to 1000 sccm.

[0078] In this embodiment, the formation process of the source / drain doping layer 215 includes an epitaxial growth process; the process of doping the source / drain ions in the source / drain doping layer 215 includes an in-situ doping process.

[0079] When the semiconductor structure is a P-type device, the material of the source / drain doping layer 215 includes: silicon, germanium or silicon-germanium; the source / drain ions are P-type ions, and the source / drain ions include boron ions, BF 2- ions or indium ions; when the semiconductor structure is an N-type device, the material of the source / drain doping layer 215 includes: silicon, gallium arsenide or indium gallium arsenide; the source / drain ions are N-type ions, and the source / drain ions include phosphorus ions or arsenic ions.

[0080] In this embodiment, before forming the source / drain doping layer 215, a part of the fin sacrificial layer 202 on the sidewall of the source / drain groove is etched, and a barrier layer 216 is formed on the sidewall of the etched fin sacrificial layer. The barrier layer 216 is used to isolate the subsequently formed gate structure from the source / drain doping layer 215 and prevent punch-through between the two.

[0081] After forming the dummy gate structure 210, for the step of etching and removing the sacrificial layer 208 and forming a gap between the split layer 209 and the channel layer 206, please refer to Figures 14 to 16 .

[0082] Please refer to Figure 14 , Figure 14 and Figure 13 which has the same view direction. After forming the source / drain doping layer 215, a dielectric layer 217 is formed on the substrate 200 and the isolation structure 204, and the dielectric layer 217 covers the sidewall of the dummy gate structure 210.

[0083] In this embodiment, the dielectric layer 217 is located on the sidewall of the sidewall spacer 214 and exposes the top surface of the protection layer 213.

[0084] In this embodiment, the dielectric layer 217 is specifically formed on the isolation structure 204, and the dielectric layer 217 also covers the source / drain doping layer 215.

[0085] In this embodiment, the method for forming the dielectric layer 217 includes: forming an initial dielectric layer (not shown) on the substrate 200 and on the isolation structure 204, the initial dielectric layer covering the top surface and the sidewall surfaces of the protection layer 213; planarizing the initial dielectric layer until the top surface of the protection layer 213 is exposed, to form the dielectric layer 217.

[0086] In this embodiment, the material of the dielectric layer 217 is silicon oxide.

[0087] Please refer to Figure 15 , Figure 15 and Figure 14 in the same view direction, remove the dummy gate structure 210, and form a gate opening 218 in the dielectric layer 217.

[0088] In this embodiment, the process for removing the dummy gate structure 210 is a wet etching process, specifically using tetramethylammonium hydroxide (TMAH) as the etching solution.

[0089] In this embodiment, removing the dummy gate structure 210 is to prepare for the subsequent formation of the gate structure.

[0090] In this embodiment, remove the protection layer 213, the dummy gate layer 212 and the dummy gate dielectric layer located at the bottom of the protection layer 213.

[0091] Please refer to Figure 16 , Figure 16 and Figure 11 in the same view direction, remove the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218, form a gate trench 219 between adjacent channel layers 206, and form a gap 220 between the split layer 209 and the channel layer 206.

[0092] In this embodiment, the purpose of forming the gap 220 between the split layer 209 and the channel layer 206 is that when the gate structure is formed subsequently, the channel layer 206 on the sidewall of the split layer 209 can be completely surrounded by the formed gate structure, thereby enhancing the control effect of the gate structure on the channel layer 206.

[0093] In this embodiment, the size of the gap 220 between the splitting layer 209 and the channel layer 206 is greater than 0 nm and less than or equal to 20 nm; when the size of the gap 220 is greater than 20 nm, although a good-quality gate structure can be formed on the sidewalls around the channel layer 206 at this time, and the fin sacrificial layer between the splitting layer 209 and the channel layer 206 can be easily removed completely, but at this time the size of the channel layer 206 is too small, which is likely to cause the short-channel effect and reduce the electrical performance of the semiconductor device.

[0094] In this embodiment, the most preferred size of the gap 220 is 2 nm to 5 nm. This is because as the size of the semiconductor device becomes smaller and smaller and continuously develops towards the optimal performance, the most preferred size of the gap 220 is between 2 nm and 5 nm. This can not only ensure that the formed gate structure can surround the side surfaces around the channel layer and improve the control ability of the gate structure over the channel layer, but also ensure that there is less residue of the fin sacrificial layer left between the splitting layer and the channel layer, which is convenient for the removal of the fin sacrificial layer, and can also ensure that the length of the gate structure is not too long, thus facilitating the improvement of the integration and electrical performance of the semiconductor device.

[0095] In this embodiment, since the fin sacrificial layer 202 and the sacrificial layer 208 are made of the same material, they can be removed in one etching process, thereby reducing the number of processes and shortening the production cycle.

[0096] In this embodiment, the process of removing the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218 is a wet etching process.

[0097] In other embodiments, the dry etching process can also be used to remove the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218.

[0098] In this embodiment, the reason for using the wet etching process to remove the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218 is that the wet etching process has a high etching selectivity. During the process of removing the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218, almost no damage or very little damage is caused to the surface of the channel layer 206, which can ensure that the channel layer 206 has good surface quality and helps to form a high-quality semiconductor device.

[0099] In this embodiment, the parameters of the wet etching process include: the temperature is 25 °C to 300 °C, and HCl gas with a volume percentage of 20% to 90%.

[0100] In this embodiment, since the side wall of the segmentation layer 209 is no longer in close contact with the channel layer 206, but in close contact with the sacrificial layer 208, during the process of removing the fin sacrificial layer 202, the etching solution can etch and remove the fin sacrificial layer 202 simultaneously from the two side walls of the fin sacrificial layer 202. On the one hand, this improves the etching efficiency of removing the fin sacrificial layer 202. On the other hand, there is no longer a problem that the fin sacrificial layer 202 at the corner between the channel layer 206 and the segmentation layer 209 and the fin sacrificial layer 202 covered by the segmentation layer 209 are not completely removed, thus improving the quality and efficiency of removing the fin sacrificial layer 202.

[0101] Please refer to Figure 17 , a gate structure 221 is formed in the gate opening 218 and the gate groove 219, and the gate structure 221 surrounds the channel layer 206.

[0102] In this embodiment, since there is a gap 220 between the segmentation layer 209 and the channel layer 206, the gate structure 221 formed around the segmentation layer 209 can surround the four side walls of the channel layer 206, replacing the traditional situation where the gate structure 221 around the segmentation layer 209 can only surround three sides of the channel layer 206. In this way, the area of the channel region formed by the gate structure 221 surrounding the channel layer 206 is increased, thereby enhancing the control ability of the gate structure 221 over the channel layer 206 and improving the electrical performance of the finally formed semiconductor device.

[0103] In this embodiment, the gate structure 221 includes a gate dielectric layer 222 and a gate electrode layer 223 located on the gate dielectric layer 222.

[0104] In this embodiment, the gate dielectric layer 222 is a high-k dielectric material (dielectric constant greater than 3.9); the high-k dielectric material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0105] The material of the gate electrode layer 223 is metal, and the metal material includes one or a combination of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

[0106] Correspondingly, the present invention also provides a semiconductor device, including a substrate 200; a plurality of fins, including a plurality of layers of channel layers 206 along the normal direction of the surface of the substrate 200; a segmentation layer 209 located between at least a pair of adjacent fins, with a gap 220 between the segmentation layer 209 and the channel layer 206; and a gate structure 221 located on the substrate 200 and spanning a plurality of the fins, and surrounding the channel layer 206.

[0107] In this embodiment, there is a gap 220 between the splitting layer 209 and the channel layer 206. The gate structure 221 can be filled into the gap 220 to form a fully enclosed structure around the periphery of the channel layer 206, increasing the surface area of the gate structure 221 surrounding the channel layer 206, thereby enhancing the control ability of the gate structure 221 over the channel layer 206 and enhancing the electrical performance of the formed semiconductor device; and due to the existence of the gap 220, the impurities (i.e., the remaining fin sacrificial layer) between the gate structure 221 and the channel layer 206 are reduced, thereby improving the performance of the finally formed semiconductor device.

[0108] The size of the gap 220 between the splitting layer 209 and the channel layer 206 is greater than 0 nm and less than or equal to 20 nm; when the size of the gap 220 is greater than 20 nm, although a good-quality gate structure can be formed on the sidewalls around the channel layer 206 at this time and the fin sacrificial layer between the splitting layer 209 and the channel layer 206 is easily removed completely, but at this time the size of the channel layer 206 is too small, which is likely to cause the short-channel effect and reduce the electrical performance of the semiconductor device.

[0109] In this embodiment, the most preferred size of the gap 220 is between 2 nm and 5 nm. This is because as the size of the semiconductor device becomes smaller and smaller and continuously develops towards the most optimized performance, the most preferred size of the gap 220 is between 2 nm and 5 nm, which can not only ensure that the formed gate structure can surround the side surfaces around the channel layer, enhancing the control ability of the gate structure over the channel layer, but also ensure that there is less residue of the fin sacrificial layer left between the splitting layer and the channel layer, facilitating the removal of the fin sacrificial layer, and can also ensure that the length of the gate structure is not too long, thereby facilitating the improvement of the integration and electrical performance of the semiconductor device.

[0110] The top surface of the splitting layer 209 is higher than the top surface of the fin. The splitting layer 209 is subsequently used for the splitting of the gate structure to achieve a gate cut at the splitting layer 209.

[0111] In this embodiment, the material of the splitting layer 209 is a dielectric material including one or a combination of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), and silicon carbonitride boron (SiCBN).

[0112] The isolation structure 204 is located on the substrate 200.

[0113] In this embodiment, the material of the isolation structure 204 is silicon nitride.

[0114] In other embodiments, the material of the isolation structure 204 may further include one or a combination of materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride carbonitride (SiOCN), silicon carbide boronitride (SiCBN), etc.

[0115] In this embodiment, the function of the isolation structure 204 is to form electrical isolation.

[0116] It further includes: source-drain doping layers 215, which are located in the fins on both sides of the gate structure 221.

[0117] It further includes: a barrier layer 216, which is located between the gate structure 221 and the source-drain doping layers 215, and is used to isolate between the gate structure 221 and the source-drain doping layers 215 to prevent punch-through between the two.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A plurality of fin portions, including a plurality of channel layers along the normal direction of the substrate surface, the plurality of fin portions being parallelly distributed along a first direction, the channel layers having grooves on both sides along a second direction, and a sacrificial layer being formed in the grooves; A dividing layer, located between at least a pair of adjacent fin portions before forming a pseudo-gate structure, there being a gap between the dividing layer and the channel layer in the second direction; after forming the sacrificial layer, forming a pseudo-gate structure across a plurality of the fin portions on the substrate; after forming the pseudo-gate structure, etching away the pseudo-gate structure and the sacrificial layer; A gate structure, located on the substrate and spanning a plurality of the fin portions, and surrounding the channel layer, the gate structure extending along the second direction, the first direction being perpendicular to the second direction.

2. The semiconductor device according to claim 1, wherein The size range of the gap between the dividing layer and the channel layer is 2 nm - 20 nm.

3. The semiconductor device according to claim 1, wherein, The top surface of the dividing layer is higher than the top surface of the fin portion.

4. The semiconductor device according to claim 1, wherein, The material of the dividing layer is a dielectric material.

5. A method for forming a semiconductor device, characterized in that Comprising: Providing a substrate; Forming a plurality of discretely arranged fin portions on the substrate, there being isolation trenches between adjacent fin portions, the fin portions including a plurality of fin portion sacrificial layers overlapping along a direction perpendicular to the substrate surface, and an initial channel layer located between adjacent two fin portion sacrificial layers; Etching away a part of the initial channel layer on the sidewalls of the isolation trenches to form a channel layer; Forming grooves on both sides of the channel layer; forming a sacrificial layer in the grooves; After forming the sacrificial layer, forming a pseudo-gate structure across a plurality of the fin portions on the substrate; Before forming the pseudo-gate structure, forming a dividing layer in at least one of the isolation trenches; After forming the pseudo-gate structure, etching away the sacrificial layer to form a gap between the dividing layer and the channel layer.

6. The method for forming a semiconductor device according to claim 5, wherein, The step of, after forming the pseudo-gate structure, etching away the sacrificial layer to form a gap between the dividing layer and the channel layer includes: Forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the pseudo-gate structure; Removing the pseudo-gate structure to form a gate opening in the dielectric layer; Removing the fin portion sacrificial layer and the sacrificial layer exposed by the gate opening to form a gate trench between adjacent channel layers, and forming a gap between the dividing layer and the channel layer.

7. The method for forming a semiconductor device according to claim 5, wherein, The size range of the gap between the dividing layer and the channel layer is 2 nm - 20 nm.

8. The method for forming a semiconductor device according to claim 6, wherein, After forming a gap between the dividing layer and the channel layer, forming a gate structure in the gate opening and the gate trench, the gate structure surrounding the channel layer.

9. The method for forming a semiconductor device according to claim 5, wherein, The material of the dividing layer is a dielectric material.

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