A control circuit for a DC / DC boost system

Abstract

A control circuit of a DC / DC boost system, used for boosting a voltage signal V1 to output a voltage signal V2; a first transistor Q1, a second transistor Q2, an inductor L1, a constant on-time module, a gating module T1, a PWM generation module, a boost system drive control module and a current zero-crossing comparison module ZCDCMP; the gating module T1 outputs a PWM signal generated by the PWM generation module or a signal output by the constant on-time module according to the detection result of the current zero-crossing comparison module ZCDCMP on the boost same load working mode; the boost system drive control module receives the output of the gating module T1 to generate a signal CLKP for controlling the on-off of the second transistor Q2 and a signal CLKN for controlling the on-off of the first transistor Q1, so as to ensure that the on-off time of the first transistor Q1 is the fixed on-time set by the constant on-time module under light load. Therefore, the present invention enables the boost system in heavy load mode to work in a fixed frequency mode, and the boost system in light load mode to work in a constant on-time mode.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design and relates to a control circuit of a DC / DC boost system. Background Art

[0002] The control circuit of the DC / DC boost system is increasingly used in power boost applications such as LED lighting, mobile phones, headphones, and wearable devices. In order to make the DC / DC boost system work in power saving mode, the industry usually uses a control circuit to detect and control the DC / DC boost system to work in light load mode or heavy load mode.

[0003] See also Figure 1 , Figure 1 The schematic diagram of the control circuit of the DC / DC boost system in the prior art is shown. As shown in the figure, the control circuit includes a first voltage-dividing resistor RFB1, a second voltage-dividing resistor RFB2, a voltage-stabilizing capacitor C1 for V1, a voltage-stabilizing capacitor C2 for V2, an inductor L1, a first transistor Q1, a second transistor Q2, a fixed minimum on-time module (Fixed MINON Time), an oscillator module OSC, an error amplifier module EAMP, a comparator module PWMCMP, a logic control module LOGIC, a drive module DRIVER and a current zero-crossing comparison module ZCDCMP.

[0004] Among them, voltage V1 is an input voltage signal, which is usually provided by various batteries or solar energy. Voltage V2 is an output voltage signal, which provides voltage to various downstream devices. In a boost system, voltage V1 is usually less than voltage V2. The fixed minimum on time module (Fixed MIN ON Time) is used to set the minimum time for controlling the first transistor Q1 to be turned on. The oscillator module OSC is used to generate the harmonic signal RAMP and the OSC signal CLK; the error amplifier module EAMP is used to amplify the difference between the reference voltage signal VREF and the feedback signal FB of V2, and output the COMP signal; the comparator module PWMCMP compares the COMP signal with the RAMP signal and outputs the PWM signal; the logic control module LOGIC is used to synthesize the PWM signal and CLK into the original drive signal DR1, and the drive module DRIVER generates CLKP and CLKN to control the opening and closing of the second transistor Q2 and the first transistor Q1 respectively; the current zero-crossing comparison module ZCDCMP is used to monitor whether the current of the inductor L is 0; the fixed minimum on-time module is used to control the minimum on-time of the first transistor Q1, and the minimum on-time module may not be used in some traditional architectures.

[0005] The specific working principle of the above circuit is as follows: when the signal CLKN and the signal CLKP are at a high level, the first transistor Q1 is turned on, the second transistor Q2 is turned off, SW is connected to the ground terminal GND (i.e., a low level), and the current of the inductor L increases; when the signal CLKP and the signal CLKN are at a low level, the second transistor Q2 is turned on, and the first transistor Q1 is turned off. At this time, SW is at a high level, VSW=V2+Ron_Q2*IQ2, and the current of the inductor L decreases.

[0006] When the current of the inductor L drops to 0, VSW = V2. At this time, the current zero-crossing comparison module ZCDCMP (comparing SW voltage and V2 voltage) outputs a high level, indicating that the boost system enters the light load mode. If the current of the inductor L never drops to 0, that is, VSW is always greater than the voltage V2, it means that the boost system has always been working in the heavy load mode. Of course, in some applications, the inductor current is close to 0, VSW = V2 + Vo, Vo is a small voltage value, and the current zero-crossing comparison module ZCDCMP output is also high, indicating that the boost system enters the light load mode.

[0007] When the boost system enters the light load mode, in order to achieve the light load energy saving effect, the frequency of the oscillator OSC will be reduced (or the ZCDCMP output signal will shut down the oscillator OSC, so that it no longer works or works at a reduced frequency). At this time, the overall operating frequency of the boost system is reduced, and the first transistor Q1 and the second transistor Q2 are turned off to achieve the light load energy saving effect.

[0008] However, in the above control process, the on-time of the first transistor Q1 may be unstable and may vary from time to time. In addition, when operating in a light load mode, a fixed minimum on-time module (Fixed MIN ONTime) is usually used to limit the minimum on-time of the first transistor Q1.

[0009] See also Figure 2 , Figure 2 Shown Figure 1 Waveform diagram of CLKN signal TON of the DC / DC boost system. As shown in the figure, since the minimum on-time (Fixed MIN ON Time) is fixed, for application scenarios with different voltages V1 and V2, the fixed minimum on-time is usually designed to be very small, resulting in a high frequency of system operation under light load, and unable to achieve better light load efficiency. Summary of the invention

[0010] To solve the above technical problems, the present invention proposes a control circuit for a DC / DC boost system, which ensures that the on-off time of the first transistor Q1 is the same under light load and heavy load, so as to achieve an ideal energy-saving effect when the boost system enters the light load mode.

[0011] To achieve the above object, the technical solution of the present invention is as follows:

[0012] A control circuit of a DC / DC boost system, used for boosting an input DC power supply voltage signal V1 into a DC power supply voltage signal V2 for output; it comprises:

[0013] A first transistor Q1, a second transistor Q2 and an inductor L1; the inductor L1 is connected between the input end of the DC power supply voltage signal V1 and a drain connection point SW of the first transistor Q1 and the second transistor Q2; the source of the first transistor Q1 is grounded, and the source of the second transistor Q2 is connected to the output end of the DC power supply voltage signal V2;

[0014] A current zero-crossing comparison module ZCDCMP detects the load working mode of the boost system and outputs a signal ZC according to the power supply voltage signal V1 and the power supply voltage signal V2; one input terminal of the current zero-crossing comparison module ZCDCMP is connected to the connection point SW, and the other input terminal is connected to the output terminal of the DC power supply voltage signal V2;

[0015] A PWM generation module is used to generate a PWM signal and a fixed period frequency signal;

[0016] A constant on-time module, which generates a fixed on-time proportional to the power supply voltage signal V1 and the power supply voltage signal V2 according to the detection result of the load working mode obtained by the current zero-crossing comparison module ZCDCMP, and outputs a corresponding control signal;

[0017] A gating module T1 receives the detection result of the load working mode of the current zero-crossing comparison module ZCDCMP, and outputs the PWM signal generated by the PWM generating module if the detection result is a heavy load working mode; and outputs the signal output by the constant on-time module if the detection result is a light load working mode;

[0018] The boost system driving control module is used to receive the output of the gating module T1 and the fixed period frequency signal, generate the signal CLKP for controlling the on and off of the second transistor Q2 and the signal CLKN for controlling the on and off of the first transistor Q1, so as to ensure that the on and off time of the first transistor Q1 is the fixed on time set by the constant on time module. Preferably, the fixed on time is in direct proportion to the difference between V2 and V1, and in inverse proportion to V2 itself.

[0019] Furthermore, the control circuit of the DC / DC boost system further comprises an on-off pre-control module, and when the current flowing through the first transistor Q1 is greater than a preset current threshold, the on-off pre-control module controls the gating module T1 to receive the output of the constant on-time module.

[0020] Furthermore, the on-off pre-control module includes a logic gate and a current monitoring module; the current monitoring module includes a zeroth transistor Q0, a comparator circuit CLCMP and a current source IOC; an input end of the logic AND gate is connected to the output end of the constant on-time module, an input end of the logic gate is connected to the output end of the comparator circuit CLCMP, the zeroth transistor Q0 is a mirror tube of the first transistor Q1, used to mirror the current of the first transistor Q1, and the current of the current source IOC is the current threshold; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP controls the logic gate to allow the output of the constant on-time module.

[0021] Furthermore, the constant on-time TON value of the first transistor Q1 is:

[0022] TON is greater than or equal to TOSC*(V2-V1) / V2

[0023] Wherein, TOSC is the cycle time of the fixed period frequency signal of the PWM generation module.

[0024] Further, the gating module T1 includes a logic inverter INV1, a transmission gate TG1 and a transmission gate TG2; the input end of the logic inverter INV1, the lower gate of the transmission gate TG1 and the upper gate of the transmission gate TG2 receive the output signal ZC of the current zero-crossing comparison module ZCDCMP, and the output end of the logic inverter INV1, the upper gate of the transmission gate TG1 and the lower gate of the transmission gate TG2 are connected together; the output ends of the transmission gate TG1 and the transmission gate TG2 are connected together, and the output results are input into the boost system drive control module; the on-off of the transmission gate TG1 controls the on-off of the constant on-time module, and the on-off of the transmission gate TG2 controls the on-off of the signal PWM; when entering the light load mode, the transmission gate TG1 is turned on and the transmission gate TG2 is turned off; when entering the heavy load mode, the transmission gate TG2 is turned on and the transmission gate TG1 is turned off.

[0025] Further, the constant on-time module includes a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a third PMOS transistor Q3, a fourth PMOS transistor Q4, a resistor RTON for generating a charging current for setting a TON time, a charging capacitor CTON for setting a TON time, an operational amplifier OP1, and a comparator TONCMP for generating a TON time; the positive end of the operational amplifier OP1 is connected to the output end of the control circuit, the negative end of the operational amplifier OP1 is connected to the source of the fifth NMOS transistor Q5, and the output end of the operational amplifier OP1 is connected to the gate of the fifth NMOS transistor Q5; the resistor RTON is connected between the source of the fifth NMOS transistor Q5 and the ground end; the drains of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the third PMOS transistor Q3, and the fourth PMOS transistor Q4 and the comparator TONMP are connected. The positive electrodes of the comparator TONCMP and the comparator TONCMP are connected together, the negative electrode of the comparator TONCMP is connected to the voltage VC, the source and gate of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 are connected together, the charging capacitor CTON is connected between the drain and source of the sixth NMOS transistor Q6, and the gate of the sixth NMOS transistor Q6 is connected to the inverted signal of the signal DR1; wherein, the voltage VC is the negative terminal voltage of the comparator TONCMP, and its value is V2-V1; when the signal DR1 is at a high level, the sixth NMOS transistor Q6 is turned off, and the current of the fourth PMOS transistor Q4 charges the capacitor CTON, and its voltage signal is VRC; when the upper voltage VRC of the capacitor CTON is greater than the negative terminal signal VC of the comparator TONCMP; the comparator TONCMP generates a comparison signal TON1, and the signal TON1 is the output signal of the constant on-time module.

[0026] Furthermore, the PWM generation module includes an error amplifier module EAMP, a comparator module PWMCMP and an oscillator OSC, the positive input terminal of the error amplifier module EAMP is connected to a reference voltage, the other input terminal of the error amplifier module EAMP is connected to a voltage divider of an output voltage V2, and the output terminal of the error amplifier module EAMP is connected to a negative input terminal of the comparator module PWMCMP; the oscillator OSC provides a sawtooth wave signal to the positive input terminal of the comparator module PWMCMP and a fixed period frequency to the boost system drive control module according to the signal ZC, and the output terminal of the comparator module PWMCMP is connected to the selection module T1.

[0027] Furthermore, the boost system drive control module includes a logic control module LOGIC and a drive module DRIVER. The logic control module LOGIC receives a pulse clock signal CLK and the output of the selection module T1, generates a drive signal DR1 to the drive module DRIVER, and the drive module DRIVER outputs a signal CLKP and a signal CLKN.

[0028] Furthermore, the logic control module LOGIC is an RS latch.

[0029] Furthermore, the fixed period frequency is a pulse clock signal CLK.

[0030] Furthermore, the control circuit of the DC / DC boost system also includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected in parallel between the DC power supply voltage signal V1 input terminal and the ground terminal GND; the second capacitor C2 is connected in parallel between the DC power supply voltage signal V2 output terminal and the ground terminal GND.

[0031] It can be seen from the above technical solutions that the control circuit of the DC / DC boost system in the present invention adds a constant on-time control module (Constant ON Time) in the light load mode, the boost system in the heavy load mode works in the fixed frequency mode, and the boost system in the light load mode works in the constant on-time mode. That is to say, since the present invention fixes the on-time of the first transistor Q1, it not only achieves the ideal energy-saving effect after the boost system enters the light load mode, but also increases the stability of the boost system when working in the light load mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The figure is a schematic diagram of a control circuit of a DC / DC boost system in the prior art.

[0033] Figure 2 Shown Figure 1 Waveform diagram of CLKN signal TON of DC / DC boost system

[0034] Figure 3 FIG. 1 is a schematic diagram of a preferred embodiment of a control circuit of a DC / DC boost system of the present invention.

[0035] Figure 4 The figure shows a schematic diagram of a constant on-time module in a control circuit of a DC / DC boost system of the present invention.

[0036] Figure 5 FIG. 1 is a schematic diagram of another preferred embodiment of the control circuit of the DC / DC boost system of the present invention.

[0037] Figure 6 Shown Figure 3 or Figure 5 Waveform diagram of CLKN signal TON of DC / DC boost system DETAILED DESCRIPTION

[0038] The following is combined with Figure 3-6 , the specific implementation modes of the present invention are further described in detail.

[0039] It should be noted that the biggest difference between the present invention and the prior art is that in the control circuit of the DC / DC boost system of the present invention, a constant on-time module and a gating module T1 are added to replace the fixed minimum on-time module in the prior art.

[0040] Specifically, in the following embodiments of the present invention, the control circuit of the DC / DC boost system is used to boost the input DC power supply voltage signal V1 into a DC power supply voltage signal V2 for output; it may mainly include a first transistor Q1, a second transistor Q2, an inductor L1, a current zero-crossing comparison module ZCDCMP, a PWM generation module, a gating module T1, a constant on-time module and a boost system drive control module.

[0041] Wherein, the inductor L1 is connected between the input terminal of the DC power supply voltage signal V1 and the drain connection point SW of the first transistor Q1 and the second transistor Q2; the source of the first transistor Q1 is grounded, and the source of the second transistor Q2 is connected to the output terminal of the DC power supply voltage signal V2; the current zero-crossing comparison module ZCDCMP detects the load working mode of the boost system according to the power supply voltage signal V1 and the power supply voltage signal V2 and outputs a signal ZC; one input terminal of the current zero-crossing comparison module is connected to the connection point SW, and the other input terminal is connected to the output terminal of the DC power supply voltage signal V2; the PWM generation module is used to generate a PWM signal and a fixed cycle frequency (for example, a pulse clock signal CLK); the constant on-time module detects the load working mode of the boost system according to the detection result of the load working mode obtained by the current zero-crossing comparison module ZCDCMP The result is to generate a fixed on-time proportional to the power supply voltage signal V1 and the power supply voltage signal V2, and output a corresponding control signal; a gating module T1, which receives the detection result of the load working mode of the current zero-crossing comparison module ZCDCMP, and if the detection result is the heavy load working mode, outputs the PWM signal generated by the PWM generating module; if the detection result is the light load working mode, outputs the signal output by the constant on-time module; a boost system drive control module, which is used to receive the output of the gating module T1 and the fixed cycle frequency, and generate a signal CLKP that controls the on-off of the second transistor Q2 and a signal CLKN that controls the on-off of the first transistor Q1, so as to ensure that the on-off time of the first transistor Q1 is the same under light load and heavy load.

[0042] That is to say, when the system operates in the light load energy-saving mode, the system operates at a constant on-time (ConstantON Time), and the constant on-time (fixed on-time of the first transistor Q1) is consistent with the on-time when the system operates stably under heavy load. In this way, the on-time of the first transistor Q1 remains consistent regardless of whether the system is under light load or heavy load, which is very beneficial to the stability of the system when operating under light load.

[0043] Example 1

[0044] See also Figure 3 , Figure 3 The schematic diagram of a preferred embodiment of the control circuit of the DC / DC boost system of the present invention is shown. As shown in the figure, the control circuit of the DC / DC boost system includes a first voltage-dividing resistor RFB1, a second voltage-dividing resistor RFB2, a voltage-stabilizing capacitor C1 for V1, a voltage-stabilizing capacitor C2 for V2, a voltage source DC, an inductor L1, a first transistor Q1, a second transistor Q2, a constant on-time module, a gating module T1, an oscillator module OSC, an error amplifier module EAMP, a comparator module PWMCMP, a logic control module LOGIC, a drive module DRIVER and a current zero-crossing comparison module ZCDCMP; the voltage V1 is a voltage signal at the input end of the control circuit, and the voltage V2 is a voltage signal at the output end of the control circuit, and the voltage V1 is usually less than the voltage V2.

[0045] Specifically, the inductor L1 is connected between the node SW and the input end of the control circuit, the node SW is the connection point between one input end of the current zero-crossing comparison module ZCDCMP and the drain of the first transistor Q1 and the drain of the second transistor Q2, and the source of the first transistor Q1 is connected to the ground end; the voltage source DC and the voltage-stabilizing capacitor C1 are connected in parallel between the input end of the control circuit and the ground end; the output end of the control circuit is connected with the other input end of the current zero-crossing comparison module ZCDCMP, one end of the voltage-stabilizing capacitor C2, one end of the first voltage-dividing resistor RFB1 and the source of the second transistor Q2, and one end of the voltage-stabilizing capacitor C2 is connected to the ground end; the driving module DRIVER receives the output signal ZC of the current zero-crossing comparison module ZCDCMP and the output DR1 of the logic control module LOGIC, and outputs the signal CLKP to the gate of the second transistor Q2, and outputs the signal CLKN to the gate of the first transistor Q1; the oscillator module OSC receives the output signal ZC of the current zero-crossing comparison module ZCDCMP Output ZC, and output the pulse clock signal CLK to the constant conduction time module and the logic control module LOGIC, and output the sawtooth wave signal RAMP to the positive input terminal of the comparator module PWMCMP; the constant conduction time module is respectively connected to the control circuit input terminal, the control circuit output terminal and the first input terminal of the gating module T1; the second input terminal of the gating module T1 receives the PWM signal of the comparator module PWMCMP; the logic control module LOGIC receives the pulse clock signal CLK and the output of the gating module T1, and generates a driving signal DR1 to the driving module DRIVER; the second voltage-dividing resistor RFB2 is connected between the other end of the first voltage-dividing resistor RFB1 and the ground; the positive input terminal of the error amplifier module EAMP is connected to the reference voltage, the error amplifier module EAMP is connected to the connection point of the first voltage-dividing resistor RFB1 and the second voltage-dividing resistor RFB2, and the output terminal of the error amplifier module EAMP is connected to the negative input terminal of the comparator module PWMCMP.

[0046] The constant on-time module is used to set the on-time of the first transistor Q1 under light load, and the selection module T1 is used to switch the on-control signal of the first transistor Q1.

[0047] In an embodiment of the present invention, a current zero-crossing comparison module ZCDCMP is used to determine whether the system enters the light load mode. When entering the light load mode, a constant on-time module is used to generate a fixed constant on-time (ConstantOn Time) value TON. The constant on-time is directly proportional to the difference between V2 and V1, and inversely proportional to V2 itself.

[0048] And, the constant on-time value can be:

[0049] TON=TOSC*(V2-V1) / V2; or

[0050] TON>TOSC*(V2-V1) / V2

[0051] Wherein, TOSC is the cycle time of the fixed period frequency signal of the PWM generation module.

[0052] Specifically, the logic control module LOGIC can be an RS latch. When working in the light load mode, the gate module

[0053] T1 uses the constant on-time value TON signal to replace the PWM signal and the pulse clock signal CLK through the logic control module LOGIC to perform RS latching to generate the signal DR1; when working in the heavy load mode, the selection module T1 still uses the PWM signal and the pulse clock signal CLK through the logic control module LOGIC to perform RS latching to generate the signal DR1. The signal DR1 generates the signal CLKP and the signal CLKN through the driving module DRIVER.

[0054] In an embodiment of the present invention, when the system operates in a light load mode and a heavy load mode, the conduction time of the first transistor Q1 is the same. When the system operates in the light load mode, the current zero-crossing comparison module ZCDCMP outputs a signal ZC at a high level, and the conduction control signal of the first transistor Q1 is determined by the output of the constant conduction time module; when the system operates in the heavy load mode, the current zero-crossing comparison module ZCDCMP outputs a signal ZC at a low level, and the conduction control signal of the first transistor Q1 is determined by the output of the comparator module PWMCMP.

[0055] In the embodiment of the present invention, the gating module T1 can also be used Figure 3 The specific circuit implementation in the dotted box is shown in the figure. The selection module T1 may include a logic inverter INV1, a transmission gate TG1 and a transmission gate TG2; the input end of the logic inverter INV1, the lower gate of the transmission gate TG1 and the upper gate of the transmission gate TG2 receive the signal ZC, and the output end of the logic inverter INV1, the upper gate of the transmission gate TG1 and the lower gate of the transmission gate TG2 are connected together; the output ends of the transmission gate TG1 and the transmission gate TG2 are connected together, and the output result is input to the logic control module LOGIC; the constant on-time module controls the on-off of the transmission gate TG1, and the output signal PWM of the comparator module PWMCMP controls the on-off of the transmission gate TG2; when entering the light load mode, the signal ZC is high level, the transmission gate TG1 is turned on, and the transmission gate TG2 is turned off; when entering the heavy load mode, ZC is low level, the transmission gate TG2 is turned on, and the transmission gate TG1 is turned off.

[0056] See also Figure 4 , Figure 4The figure shows a schematic diagram of a constant on-time module in a control circuit of a DC / DC boost system of the present invention. In an embodiment of the present invention, the constant on-time module includes a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a third PMOS transistor Q3, a fourth PMOS transistor Q4, a resistor RTON for generating a charging current for setting a TON time, a charging capacitor CTON for setting a TON time, an operational amplifier OP1, and a comparator TONCMP for generating a TON time.

[0057] The positive terminal of the operational amplifier OP1 is connected to the output terminal of the control circuit, the negative terminal of the operational amplifier OP1 is connected to the source of the fifth NMOS transistor Q5, and the output terminal of the operational amplifier OP1 is connected to the gate of the fifth NMOS transistor Q5; the resistor RTON is connected between the source of the fifth NMOS transistor Q5 and the ground terminal; the drains of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the third PMOS transistor Q3, and the fourth PMOS transistor Q4 are connected together with the positive electrode of the comparator TONCMP, the negative electrode of the comparator TONCMP is connected to the voltage VC, the source and gate of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 are connected together, the charging capacitor CTON is connected between the drain and the source of the sixth NMOS transistor Q6, and the gate of the sixth NMOS transistor Q6 is connected to the inverted signal of the signal DR1.

[0058] Among them, the voltage VC is the negative terminal voltage of the comparator TONCMP, and its value is V2-V1; the operational amplifier OP1 is used to generate a current I1 flowing through the fifth NMOS transistor Q5 and the third PMOS transistor Q3; I1=V2 / RTON; the fourth PMOS transistor Q4 is a mirror tube of the third PMOS transistor Q3, IQ4=K*IQ3, k is the ratio of the current flowing through the fourth PMOS transistor Q4 to the current flowing through the third PMOS transistor Q3.

[0059] TON time is the constant on time of the first transistor Q1; TOSC is the operating frequency of the oscillator module OSC, and the values ​​of the charging resistor RTON and the charging capacitor CTON must satisfy:

[0060] TON=TOSC*(V2-V1) / V2

[0061] When the signal DR1 is at a high level, the sixth NMOS transistor Q6 is turned off, and the current of the fourth PMOS transistor Q4 charges the capacitor CTON, and its voltage signal is VRC;

[0062] When the upper voltage VRC of the capacitor CTON is greater than the negative terminal signal VC of the comparator TONCMP, the comparator TONCMP generates a comparison signal TON1, and the signal TON1 is the output signal of the constant on-time module.

[0063] Therefore, it can be seen from the above technical solution that the present invention removes the fixed minimum on-time module (Fixed MIN ON Time) in the light load mode and adds a constant on-time module and a gating module T1, so that the system works in the fixed frequency mode under heavy load and in the constant on-time mode under light load.

[0064] In some embodiments of the present invention, a fixed minimum on time module (Fixed MIN ON Time) and a constant on time module may exist simultaneously. When the time generated by the constant on time module is less than the fixed minimum on time module (Fixed MIN ON Time), the constant on time of the first transistor Q1 is the larger one.

[0065] Example 2

[0066] In the embodiment of the present invention, by adding an on-off pre-control module, when the current flowing through the first transistor Q1 is greater than a preset current threshold, the on-off pre-control module controls the gating module T1 to receive the output of the constant on-time module. That is, the on-time of the first transistor Q1 must not only satisfy TON>=TOSC*(V2-V1) / V2, but also satisfy that the on-current of the on-Q1 reaches a set current value.

[0067] Specifically, the on-off pre-control module includes a logic gate and a current monitoring module; the current monitoring module includes a zeroth transistor Q0, a comparator circuit CLCMP and a current source IOC; one input end of the logic gate is connected to the output end of the constant on-time module, one input end of the logic gate is connected to the output end of the comparator circuit CLCMP, the zeroth transistor Q0 is a mirror tube of the first transistor Q1, used to mirror the current of the first transistor Q1, and the current of the current source IOC is the current threshold; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP controls the logic AND gate to allow the output of the constant on-time module.

[0068] See also Figure 5 , Figure 5The schematic diagram of another preferred embodiment of the control circuit of the DC / DC boost system of the present invention is shown. As shown in the figure, the control circuit of the DC / DC boost system includes a first voltage-dividing resistor RFB1, a second voltage-dividing resistor RFB2, a voltage-stabilizing capacitor C1 for V1, a voltage-stabilizing capacitor C2 for V2, a voltage source DC, an inductor L1, a logic AND gate, a first transistor Q1, a second transistor Q2, a constant on-time module, a gating module T1, an oscillator module OSC, an error amplifier module EAMP, a comparator module PWMCMP, a comparator module CLCMP, a zeroth transistor Q0, a logic control module LOGIC, a driving module DRIVER, a reference current source IOC and a current zero-crossing comparison module ZCDCMP; the voltage V1 is a voltage signal at the input end of the control circuit, and the voltage V2 is a voltage signal at the output end of the control circuit, and the voltage V1 is usually less than the voltage V2.

[0069] Specifically, the inductor L1 is connected between the node SW and the input end of the control circuit, the node SW is a connection point between one input end of the current zero-crossing comparison module ZCDCMP and the drain of the first transistor Q1, one input end of the comparator module CLCMP and the drain of the second transistor Q2, and the source of the first NMOS transistor Q1 is connected to the ground end; the voltage source DC and the voltage-stabilizing capacitor C1 are connected in parallel between the input end of the control circuit and the ground end; the output end of the control circuit is connected to the other input end of the current zero-crossing comparison module ZCDCMP, one end of the voltage-stabilizing capacitor C2, one end of the first voltage-dividing resistor RFB1 and the second The sources of the transistors Q2 are connected together, and one end of the voltage-stabilizing capacitor C2 is connected to the ground; the driving module DRIVER receives the output signal ZC of the current zero-crossing comparison module ZCDCMP and the output DR1 of the logic control module LOGIC, and outputs the signal CLKP to the gate of the second transistor Q2, and outputs the signal CLKN to the gate of the first transistor Q1; the oscillator module OSC receives the output of the current zero-crossing comparison module ZCDCMP, and outputs the pulse clock signal CLK to the constant conduction time module and the logic control module LOGIC, and outputs the sawtooth wave signal RAMP to the positive input end of the comparator module PWMCMP; the constant conduction time module is respectively connected to the input end of the control circuit, the output end of the control circuit and one input end of the logic gate; the output end of the logic AND gate is connected to the first input end of the gating module T1; the second input end of the gating module T1 receives the PWM signal of the comparator module PWMCMP; the logic control module LOGIC receives the pulse clock signal CLK and the output of the gating module T1, and generates a driving signal DR1 to the driving module DRIVER; the second voltage-dividing resistor RFB2 is connected between the other end of the first voltage-dividing resistor RFB1 and the ground. The positive input terminal of the error amplifier module EAMP is connected to the reference voltage, the error amplifier module EAMP is connected to the connection point of the first voltage-dividing resistor RFB1 and the second voltage-dividing resistor RFB2, and the output terminal of the error amplifier module EAMP is connected to the negative input terminal of the comparator module PWMCMP; the other input terminal of the comparator module CLCMP receives the current of the reference current source IOC and is connected to the drain of the zeroth transistor Q0, the source of the zeroth transistor Q0 is grounded, and the gate of the zeroth transistor Q0 is connected to the signal CLKN; the output terminal of the comparator module CLCMP is connected to the other input terminal of the logic gate.

[0070] Among them, the constant on-time module outputs a signal TON1, which is used to set the on-time of the first transistor Q1 under light load; the selection module T1 is used to switch the on-time control signal of the first transistor Q1, so that the on-time of the first transistor Q1 is the same regardless of whether the system operates in a light load mode or a heavy load mode; the comparator circuit CLCMP is used to detect the current flowing through the first transistor Q1, and the zeroth transistor Q0 is a mirror tube of the first transistor Q1, which is used to mirror the current of the first transistor Q1; when the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP is reversed.

[0071] When the system operates in light load mode and heavy load mode, the on-time of the first transistor Q1 is the same. When the system operates in light load mode, the output signal ZC of the current zero-crossing comparison module ZCDCMP is high level, and the on-control signal of the first transistor Q1 is determined by the output of the constant on-time module; when the system operates in heavy load mode, the output signal ZC of the current zero-crossing comparison module ZCDCMP is low level, and the on-control signal of the first transistor Q1 is determined by the output of the comparator module PWMCMP.

[0072] Similar to the first embodiment, in the embodiment of the present invention, the current zero-crossing comparison module ZCDCMP is used to determine whether the system enters the light load mode. When entering the light load mode, the constant on-time module is used to generate a fixed constant on-time (Constant On Time) value TON. The constant on-time is directly proportional to the difference between V2 and V1, and inversely proportional to V2 itself. In addition, the constant on-time value can be:

[0073] TON=TOSC*(V2-V1) / V2; or

[0074] TON>TOSC*(V2-V1) / V2

[0075] Wherein, TOSC is the cycle time of the fixed period frequency signal of the PWM generation module.

[0076] Specifically, the logic control module LOGIC can be an RS latch. When working in the light load mode, the selection module T1 uses the constant on-time value TON signal to replace the PWM signal and the pulse clock signal CLK to RS latch and generate the signal DR1 through the logic control module LOGIC; when working in the heavy load mode, the selection module T1 still uses the signal PWM and the pulse clock signal CLK to RS latch and generate the signal DR1 through the logic control module LOGIC; the signal DR1 generates the signal CLKP and the signal CLKN through the driving module DRIVER.

[0077] Similarly, the specific circuits of the constant on-time module and the gating module T1 in the first embodiment can also be referred to in the second embodiment, and will not be described in detail here.

[0078] It should be noted that the positive terminal of the comparator module CLCMP is connected to the VSW signal (the VSW signal is the voltage value of the SW node); the negative terminal thereof is connected to the voltage VQ0, VQ0 = IOC*Ron_Q0; Ron_Q0 is the on-resistance of the zeroth NMOS transistor Q0.

[0079] When the voltage VSW is greater than the voltage VQ0, the output signal VCL of the comparator CLCMP becomes high level. At this time, the output signal TON1 of the constant on-time module can pass through the logic gate and the selection module T1 to control the closing of the Q1 terminal.

[0080] That is to say, the on-time of the first transistor Q1 must not only satisfy TON>=TOSC*(V2-V1) / V2, but also satisfy that the on-current of the first NMOS transistor Q1 reaches a set current value, which is ICL=IOC*M1; M1 is a ratio of the first transistor Q1 to the zeroth transistor Q0.

[0081] See also Figure 6 , Figure 6 Shown Figure 3 or Figure 5 Schematic diagram of the waveform of the CLKN signal TON of the DC / DC boost system. As shown in the figure, the CLKN signal TON of the DC / DC boost system of the present invention is fixed, which is very conducive to the waveform formation of light load energy saving; and the value of TON is related to the power input voltage V1 and the power output V2, so that the conduction time of the first transistor Q1 is consistent with the conduction time when the system works stably under heavy load.

[0082] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.

Claims

1. A control circuit of a DC / DC boost system, used for boosting an input DC power supply voltage signal V1 into a DC power supply voltage signal V2 for output; characterized in that: include: A first transistor Q1, a second transistor Q2 and an inductor L1; the inductor L1 is connected between the input end of the DC power supply voltage signal V1 and a drain connection point SW of the first transistor Q1 and the second transistor Q2; the source of the first transistor Q1 is grounded, and the source of the second transistor Q2 is connected to the output end of the DC power supply voltage signal V2; A current zero-crossing comparison module ZCDCMP detects the load working mode of the boost system and outputs a signal ZC according to the power supply voltage signal V1 and the power supply voltage signal V2; one input terminal of the current zero-crossing comparison module ZCDCMP is connected to the connection point SW, and the other input terminal is connected to the output terminal of the DC power supply voltage signal V2; A PWM generation module is used to generate a PWM signal and a fixed period frequency signal; A constant on-time module, which generates a fixed on-time proportional to the power supply voltage signal V1 and the power supply voltage signal V2 according to the detection result of the load working mode obtained by the current zero-crossing comparison module ZCDCMP, and outputs a corresponding control signal; A gating module T1 receives the detection result of the load working mode of the current zero-crossing comparison module ZCDCMP, and outputs the PWM signal generated by the PWM generating module if the detection result is a heavy load working mode; If the detection result is a light load working mode, outputting a signal output by the constant on-time module; A boost system drive control module, used for receiving the output of the gating module T1 and the fixed period frequency signal, generating a signal CLKP for controlling the on-off of the second transistor Q2 and a signal CLKN for controlling the on-off of the first transistor Q1, so as to ensure that the on-off time of the first transistor Q1 is the fixed on-time under light load; The boost system drive control module includes a logic control module LOGIC and a drive module DRIVER. The logic control module LOGIC receives the pulse clock signal CLK and the output of the gating module T1, generates a drive signal DR1 to the drive module DRIVER, and the drive module DRIVER outputs a signal CLKP and a signal CLKN. It also includes a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 is connected in parallel between the DC power supply voltage signal V1 input terminal and the ground terminal GND; the second capacitor C2 is connected in parallel between the DC power supply voltage signal V2 output terminal and the ground terminal GND.

2. The control circuit of the DC / DC boost system according to claim 1; characterized in that: It also includes an on-off pre-control module. When the current flowing through the first transistor Q1 is greater than a preset current threshold, the on-off pre-control module controls the gating module T1 to receive the output of the constant on-time module.

3. The control circuit of the DC / DC boost system according to claim 2; characterized in that: The on-off pre-control module includes a logic gate and a current monitoring module; the current monitoring module includes a zeroth transistor Q0, a comparator circuit CLCMP and a current source IOC; one input end of the logic gate is connected to the output end of the constant on-time module, one input end of the logic gate is connected to the output end of the comparator circuit CLCMP, the zeroth transistor Q0 is a mirror tube of the first transistor Q1, and is used to mirror the current of the first transistor Q1, and the current of the current source IOC is the current threshold; When the current of the zeroth transistor Q0 is greater than IOC, the comparator circuit CLCMP controls the logic gate to enable the output of the constant on-time module.

4. The control circuit of the DC / DC boost system according to claim 1, characterized in that: The constant on-time TON value of the first transistor Q1 is: TON is greater than or equal to TOSC*(V2-V1) / V2 Wherein, TOSC is the cycle time of the fixed period frequency signal of the PWM generation module.

5. The control circuit of the DC / DC boost system according to claim 1, characterized in that: A fixed minimum on-time module (Fixed MIN ON Time) is also included. When the time generated by the constant on-time module is less than the fixed minimum on-time module (Fixed MIN ON Time), the constant on-time of the first transistor Q1 under light load is the larger one.

6. The control circuit of the DC / DC boost system according to any one of claims 1 to 5, characterized in that: The gating module T1 includes a logic inverter INV1, a transmission gate TG1 and a transmission gate TG2; the input end of the logic inverter INV1, the lower gate of the transmission gate TG1 and the upper gate of the transmission gate TG2 receive the output signal ZC of the current zero-crossing comparison module ZCDCMP, and the output end of the logic inverter INV1, the upper gate of the transmission gate TG1 and the lower gate of the transmission gate TG2 are connected together; the output ends of the transmission gate TG1 and the transmission gate TG2 are connected together, and the output result is input to the boost system drive control module; the on-off of the transmission gate TG1 controls the on-off of the constant on-time module, and the on-off of the transmission gate TG2 controls the on-off of the PWM signal; when entering the light load mode, the transmission gate TG1 is turned on and the transmission gate TG2 is turned off; when entering the heavy load mode, the transmission gate TG2 is turned on and the transmission gate TG1 is turned off.

7. The control circuit of the DC / DC boost system according to any one of claims 1 to 5, characterized in that: The constant on-time module includes a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a third PMOS transistor Q3, a fourth PMOS transistor Q4, a resistor RTON for generating a charging current for setting a TON time, a charging capacitor CTON for setting a TON time, an operational amplifier OP1, and a comparator TONCMP for generating a TON time; The positive terminal of the operational amplifier OP1 is connected to the output terminal of the control circuit, the negative terminal of the operational amplifier OP1 is connected to the source of the fifth NMOS transistor Q5, and the output terminal of the operational amplifier OP1 is connected to the gate of the fifth NMOS transistor Q5; the resistor RTON is connected between the source of the fifth NMOS transistor Q5 and the ground terminal; the drains of the fifth NMOS transistor Q5, the sixth NMOS transistor Q6, the third PMOS transistor Q3, the fourth PMOS transistor Q4 and the positive electrode of the comparator TONCMP are connected together, the negative electrode of the comparator TONCMP is connected to the voltage VC, the source and gate of the third PMOS transistor Q3 and the fourth PMOS transistor Q4 are connected together, the charging capacitor CTON is connected between the drain and source of the sixth NMOS transistor Q6, and the gate of the sixth NMOS transistor Q6 is connected to the inverted signal of the signal DR1; wherein the voltage VC is the negative terminal voltage of the comparator TONCMP, and its value is V2-V1; When the signal DR1 is at a high level, the sixth NMOS transistor Q6 is turned off, and the current of the fourth PMOS transistor Q4 charges the capacitor CTON, and its voltage signal is VRC; When the upper voltage VRC of the capacitor CTON is greater than the negative terminal signal VC of the comparator TONCMP, the comparator TONCMP generates a comparison signal TON1, and the signal TON1 is the output signal of the constant on-time module.

8. The control circuit of the DC / DC boost system according to claim 1, characterized in that: The PWM generation module includes an error amplifier module EAMP, a comparator module PWMCMP and an oscillator OSC. The positive input terminal of the error amplifier module EAMP is connected to a reference voltage, the other input terminal of the error amplifier module EAMP is connected to a voltage divider of an output voltage V2, and the output terminal of the error amplifier module EAMP is connected to an input terminal of the comparator module PWMCMP; the oscillator OSC provides a sawtooth wave signal to the other input terminal of the comparator module PWMCMP and provides a fixed period frequency to the boost system drive control module according to the signal ZC, and the output terminal of the comparator module PWMCMP is connected to the selection module T1.

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