Receiver for cancelling common mode offset and cross talk

Abstract

A receiver for canceling common mode offset and crosstalk, the receiver amplifying a voltage difference between an input signal and a reference voltage to generate a first output signal and a second output signal and an internal signal, generating a third output signal and a fourth output signal identical to the first output signal and the second output signal, generating an average voltage level of the third output signal and the fourth output signal using a first switching element and a second switching element and a low pass filter to output the average voltage level as a first feedback signal and a second feedback signal, and canceling a common mode offset between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal, and generating a control signal to cancel crosstalk of the internal signal by turning on / off the first switching element and the second switching element connected to the low pass filter.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0078802, filed with the Korean Intellectual Property Office on June 26, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to receivers, and more specifically, to a receiver circuit for eliminating common-mode offset and crosstalk. Background Technology

[0004] Semiconductor devices can use signals that swing to current-mode logic (CML) levels for high-speed operation of signal input / output (I / O) interfaces, such as transmitters / receivers. CML level refers to a predetermined or alternatively desired direct current (DC) level, or an average level determined by a specific standard. A signal that swings to a CML level is a signal that switches within an amplitude or swing range based on a DC level known as the CML level.

[0005] For example, when the power supply voltage (hereinafter referred to as VDD) level of a semiconductor device is approximately 1.2 volts (V) and the ground voltage (hereinafter referred to as VSS) level is 0V, the CML level of a signal based on CML level swing can be approximately 1.0V, and the signal swing width can be approximately 0.5V. Compared to the Complementary Metal-Oxide-Semiconductor (CMOS) level, which is the digital signal level used as an internal signal of a semiconductor device, the CML level signal has a relatively small swing width. CMOS level signals swing completely from VDD level to VSS level. Because the swing width of the CML level signal is smaller than that of the CMOS level signal, the CML level signal can operate with relatively low power and can switch at high speed.

[0006] Transmitters / receivers can send and receive signals using either single-ended signaling or differential signaling. Single-ended signaling requires one signal line per signal, while differential signaling requires two signal lines per signal. Because single-ended signaling requires fewer pins and lines than differential signaling, circuits using single-ended signaling occupy less area in semiconductor devices.

[0007] However, in a single-ended signaling method, when several single-ended ports of a transmitter are simultaneously switched in the same direction, current flowing through a parasitic inductor can induce noise (e.g., simultaneous switching output induced noise (SSN)), so jitter of an output driver can increase due to reflected noise, and input voltage margin of a receiver can decrease. In addition, a single-ended signaling method can be affected by transitions of adjacent signal lines, so crosstalk can occur due to transient changes in a transition position, and high-frequency components of a signal can be attenuated due to low-pass filtering characteristics of a signal line. Furthermore, inter-symbol interference (ISI) distortion, in which a state of a previous signal affects timing of a current signal, can occur due to propagation delay.

[0008] When a receiver, particularly a single-ended signaling receiver in a poor signal line environment (e.g., interference distortion, reflected noise, and / or crosstalk), receives an input signal having a CML level, sensing margin of the receiver can decrease. However, the receiver must be able to accurately determine a logic level of the input signal from a small swing width voltage level of the input signal. Accordingly, when the input signal having the CML level is converted into a digital signal having a CMOS level, data inviolability can be maintained. SUMMARY

[0009] The present inventive concept provides a receiver that eliminates common mode offset and crosstalk to maintain data inviolability.

[0010] According to an aspect of the present inventive concept, a receiver includes a first circuit configured to receive an input signal, amplify a voltage difference between a voltage level of the input signal and a level of a reference voltage to generate a first output signal and a second output signal, and output an internal signal based on a voltage difference between the first output signal and the second output signal, the internal signal being a digital signal corresponding to a bit of the input signal; a second circuit configured to receive the input signal, amplify a voltage difference between a voltage level of the input signal and the level of the reference voltage to generate a third output signal and a fourth output signal, generate an average voltage level of the third output signal by a first switching element in response to a control signal to output the average voltage level of the third output signal as a first feedback signal, and generate an average voltage level of the fourth output signal by a second switching element in response to the control signal to output the average voltage level of the fourth output signal as a second feedback signal; and a control circuit configured to output a control signal of a pulse type whenever a logic level of the internal signal transitions, wherein the first switching element and the second switching element are selectively turned on or turned off according to a logic pulse level of the control signal.

[0011] According to another aspect of the inventive concept, there is provided a receiver including: a first circuit configured to receive an input signal, amplify a voltage difference between a voltage level of the input signal and a level of a reference voltage to generate a first output signal and a second output signal, and output an internal signal based on a voltage difference between the first output signal and the second output signal, the internal signal being a digital signal corresponding to a phase of the input signal; a second circuit configured to receive the input signal, amplify a voltage difference between a voltage level of the input signal and a level of the reference voltage to generate a third output signal and a fourth output signal, generate an average voltage level of the third output signal through a first switching element to output the average voltage level of the third output signal as a first feedback signal in response to a control signal, and generate an average voltage level of the fourth output signal through a second switching element to output the average voltage level of the fourth output signal as a second feedback signal in response to the control signal; and a control circuit configured to output, based on a selection signal, a control signal of a pulse type or a control signal having a fixed logic level each time a logic level of the internal signal transitions.

[0012] According to another aspect of the inventive concept, there is provided a receiver for receiving an input signal and outputting an internal signal which is a digital signal corresponding to a phase of the input signal, the receiver including: a first amplifier circuit configured to amplify a voltage difference between a voltage level of the input signal and a level of a reference voltage to output a first output signal to a first node line and a second output signal to a second node line; a second amplifier circuit configured to amplify a voltage difference between the first output signal and the second output signal to output a fifth output signal and a sixth output signal, the second amplifier circuit being connected to the first node line and the second node line; a level conversion circuit configured to amplify a first swing width of the fifth output signal and the sixth output signal to a second swing width which is greater than the first swing width and to generate the internal signal; a first equalizer circuit configured to receive the input signal, amplify a voltage difference between a voltage level of the input signal and a level of the reference voltage to generate a third output signal and a fourth output signal, generate an average voltage level of the third output signal by a first switching element in response to a control signal to output the average voltage level of the third output signal as a first feedback signal, and generate an average voltage level of the fourth output signal by a second switching element in response to the control signal to output the average voltage level of the fourth output signal as a second feedback signal, and adjust the voltage difference between the first output signal and the second output signal based on a voltage difference between the first feedback signal and the second feedback signal; and a control circuit configured to output a control signal of a pulse type whenever a logic level of the internal signal is transitioned, wherein the first switching element and the second switching element are selectively turned on or turned off according to a logic pulse level of the control signal. BRIEF DESCRIPTION OF DRAWINGS

[0013] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a block diagram conceptually illustrating a transmitter and a receiver according to an example embodiment of the inventive concept;

[0015] Figure 2 is a block diagram of a receiver according to an example embodiment of the inventive concept;

[0016] Figure 3 is a circuit diagram of a receiver circuit which is an implementation example of the receiver of Figure 2 ;

[0017] Figure 4 is a timing diagram illustrating an operation of the receiver circuit of Figure 3 ;

[0018] Figure 5 is a circuit diagram of a receiver circuit according to an example embodiment of the inventive concept;

[0019] Figure 6 , Figure 7 and Figure 8 is a timing diagram illustrating the operation of the receiver circuit of Figure 5 ;

[0020] Figure 9 is a circuit diagram of a receiver circuit according to an example embodiment of the inventive concept, and Figure 10 is a timing diagram illustrating the operation of the receiver circuit of Figure 9 ;

[0021] Figure 11 is a circuit diagram of a receiver circuit according to an example embodiment of the inventive concept; and

[0022] Figure 12 is a block diagram of a system to which a receiver according to an example embodiment of the inventive concept is applied. DETAILED DESCRIPTION

[0023] Figure 1 is a block diagram conceptually illustrating a transmitter 100 and a receiver 200 according to an example embodiment of the inventive concept.

[0024] Referring to Figure 1 , the receiver 200 can receive an input signal SIG from the transmitter 100 through a channel 120. The channel 120 can be a signal line physically or electrically connecting the transmitter 100 to the receiver 200. The channel 120 can be coupled to respective pins of the transmitter 100 and the receiver 200 at ends of the channel 120. The term "pin" refers broadly to an electrical interconnection with an integrated circuit and can include, for example, a pad or other electrical contact on an integrated circuit.

[0025] The channel 120 can be implemented using, for example, traces of a printed circuit board (PCB) or a coaxial cable, and can attenuate high-frequency components of the input signal SIG transmitted through the channel 120 due to skin effect, dielectric loss, etc. Channel loss can occur in the receiver 200 when the input signal SIG is transmitted through the channel 120. Impedance mismatch can occur in the channel 120 due to connectors and other physical interfaces between boards and cables. Impedance mismatch of the channel 120 can manifest as a notch in the frequency response of the channel 120 and can cause reflected noise in the receiver 200. The following phenomenon (e.g., inter-symbol interference (ISI)) can occur: each bit of the input signal SIG transmitted through the channel 120 can interfere with the next bit (BER) due to channel loss or bandwidth limitation and an increase in bit error rate as adjacent symbols overlap each other.

[0026] The transmitter 100 can transmit the input signal SIG using a single-ended signaling method. The transmitter 100 can transmit the input signal SIG including serial bits to the receiver 200 through the channel 120. The input signal SIG can be transmitted as a bit signal having a current mode logic (CML) level. The receiver 200 can receive the input signal SIG transmitted through the channel 120. The receiver 200 can receive the input signal SIG having the CML level, determine bits of the input signal SIG, and output an internal signal INT_SIG. The internal signal INT_SIG can be outputted in a CMOS level as a digital signal level. That is, the receiver 200 can convert the input signal SIG having the CML level into a signal having a CMOS level, and output the signal having the CMOS level as the internal signal INT_SIG. The internal signal INT_SIG can be configured to perform an operation corresponding to a function of the input signal SIG in a semiconductor device including the receiver 200.

[0027] When the semiconductor device is implemented as a memory device, the input signal SIG transmitted through the channel 120 can include a command signal, an address signal, and / or a data input / output signal. The receiver 200 can convert the input signal SIG having the CML level including the received command signal, address signal, and / or data input / output signal into a signal having a CMOS level, and can output the signal having the CMOS level as the internal signal INT_SIG corresponding to a function of the input signal SIG. The memory interfacing such as selecting a row and a column corresponding to a memory cell, writing data to the memory cell, or reading the written data can be performed using the internal signal INT_SIG.

[0028] Figure 2 is a block diagram of a receiver 200 according to an example embodiment of the inventive concept.

[0029] Referring to Figure 2 The receiver 200 includes an amplifier circuit 210, an equalizer circuit 220, a level conversion circuit 230, and / or a control circuit 240. The amplifier circuit 210 can be connected to an input signal (SIG) line, and can generate first and second output signals PRE_F and PRE_FB and fifth and sixth output signals AMP_O and AMP_OB based on a voltage level of the input signal SIG. The amplifier circuit 210 can include a first amplifier circuit 211 and / or a second amplifier circuit 212. The first amplifier circuit 211 can amplify the voltage level of the input signal SIG with a reference voltage VREF (see Figure 3The second amplifier circuit 212 can amplify the voltage difference between the first output signal PRE_F and the second output signal PRE_FB and generate a fifth output signal AMP_O and a sixth output signal AMP_OB, and the generated fifth output signal AMP_O and sixth output signal AMP_OB can be provided to the level conversion circuit 230.

[0030] The equalizer circuit 220 can be connected to the input signal (SIG) line, the first output signal (PRE_F) line and the second output signal (PRE_FB) line, and the control signal (CTRL) line, and can include a first equalizer circuit 221 and / or a second equalizer circuit 222. The first equalizer circuit 221 can amplify the voltage difference between the voltage level of the input signal SIG and the level of the reference voltage REF and generate a third output signal PRE_S and a fourth output signal PRE_SB (see Figure 3 ) which are the same as the first output signal PRE_F and the second output signal PRE_FB, respectively. The first equalizer circuit 221 can generate the average voltage level of the third output signal PRE_S and the fourth output signal PRE_SB in response to the control signal CTRL provided from the control circuit 240, and output a first feedback signal FB_INB and a second feedback signal FB_IN (see Figure 3 ). In addition, the first equalizer circuit 221 can adjust the amount of current in the first output signal (PRE_F) line and the second output signal (PRE_FB) line according to the voltage levels of the first feedback signal FB_INB and the second feedback signal FB_IN, and adjust the voltage levels of the first output signal (PRE_F) line and the second output signal (PRE_FB) line. The second equalizer circuit 222 can amplify the high-frequency components of the first output signal PRE_F and the second output signal PRE_FB.

[0031] The level conversion circuit 230 can be connected to the fifth output signal (AMP_O) line and the sixth output signal (AMP_OB) line, amplify the voltage difference between the fifth output signal AMP_O and the sixth output signal AMP_OB, and generate an internal signal INT_SIG having a CMOS level. The internal signal INT_SIG can be provided to internal circuits of a semiconductor device including the receiver 200, and perform operations corresponding to the functions of the input signal SIG.

[0032] The control circuit 240 can be connected to an internal signal (INT_SIG) line, and can generate a pulse type control signal CTRL each time a logic level of the internal signal INT_SIG transitions, i.e., when the logic level of the internal signal INT_SIG transitions from a logic high to a logic low or from a logic low to a logic high. According to an example embodiment, the control circuit 240 can change a logic level of the control signal CTRL in response to a selection signal SEL (see Figure 5 ). Depending on a pulse level or a logic level of the control signal CTRL, a charging operation of a low pass filter (including resistors R5 and R6 and capacitors C5 and C6) of the first equalizer circuit 221 can be selectively turned on or off. Average voltage levels of a third output signal PRE_S and a fourth output signal PRE_SB can be generated by the charging operation of the low pass filter (including resistors R5 and R6 and capacitors C5 and C6), and thus the first feedback signal FB_INB and the second feedback signal FB_IN (see Figure 3 Figure 5 ) can be output. According to an example embodiment, the control circuit 240 can generate a control signal having a logic level to perform the charging operation of the low pass filter (including resistors R5 and R6 and capacitors C5 and C6) in an initial state of the receiver 200, and having a pulse level each time the logic level of the internal signal INT_SIG transitions. Figure 3

[0033] When the receiver 200 determines bits of the received input signal SIG having a CML level and outputs the internal signal INT_SIG having a CMOS level, the receiver 200 can eliminate a common mode offset between an average voltage level of the input signal SIG and a level of the reference voltage VREF in response to the control signal CTRL, and can eliminate crosstalk generated in the internal signal INT_SIG.

[0034] Some examples can be described using the expression "connected" and / or "coupled" along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, a description using the terms "connected" and / or "coupled" can indicate that two or more elements are in direct physical or electrical contact with each other. On the other hand, a description using the terms "connected" and / or "coupled" can indicate that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0035] Figure 3 is a circuit diagram of a receiver circuit 200a which is an implementation example of the receiver 200 of Figure 2 . Hereinafter, a suffix attached to a reference numeral (e.g., a of 200a and a of 240a) is used to distinguish between a plurality of circuits having the same function. ​​

[0036] Referring to Figure 3 The first amplifier circuit 211 can compare a voltage level of the input signal SIG with a level of the reference voltage VREF, amplify a voltage difference between the voltage level of the input signal SIG and the level of the reference voltage VREF, and generate a first output signal PRE_F and a second output signal PRE_FB at the first node N1 and the second node N2. The reference voltage VREF can be provided from an inside of a semiconductor device in which the receiver circuit 200a is implemented, or can be provided from an external device. The first amplifier circuit 211 can include transistors M1 and M2, resistors R1 and R2, and / or a current source CS1. The transistors M1 and M2 can be implemented as N-type metal oxide semiconductor (NMOS) transistors.

[0037] The input signal (SIG) line can be connected to a gate terminal of the transistor M1. A source terminal (e.g., a first terminal) of the transistor M1 can be connected to the current source CS1, and a drain terminal (e.g., a second terminal) of the transistor M1 can be connected to the resistor R1. The transistor M1 can control an amount of current flowing between its drain terminal and source terminal according to a voltage level of the input signal SIG. The reference voltage (VREF) line can be connected to a gate terminal of the transistor M2. A source terminal of the transistor M2 can be connected to the current source CS1, and a drain terminal of the transistor M2 can be connected to the resistor R2.

[0038] The current source CS1 can provide a bias current flowing through the transistors M1 and M2. A gain of the first amplifier circuit 211 can vary according to a size of the bias current. The first amplifier circuit 211 can also be referred to as a variable gain amplifier (VGA). The current source CS1 can be a transistor whose gate terminal is connected to a bias voltage line, whose drain terminal is connected to the transistors M1 and M2, and whose source terminal is connected to a ground voltage VSS.

[0039] The resistor R1 can be connected between a power supply voltage VDD and the drain terminal of the transistor M1. The resistor R2 can be connected between the power supply voltage VDD and the drain terminal of the transistor M2. Each of the resistors R1 and R2 can be implemented using a passive device or a transistor. The transistors M1 and M2 can be implemented to be identical to each other, and the resistors R1 and R2 can be implemented to be identical to each other.

[0040] The first amplifier circuit 211 can be a CML circuit. The first output signal PRE F can be output from a first connection node Nl between a drain terminal of the transistor M2 and the resistor R2, and the second output signal PRE FB can be output from a second connection node N2 between a drain terminal of the transistor Ml and the resistor Rl. In the first amplifier circuit 211, the voltage levels (e.g., swing levels) of the first output signal PRE F and the second output signal PRE FB can be determined according to a voltage difference between the voltage level of the input signal SIG and the level of the reference voltage REF.

[0041] To verify the operation of the receiver circuit 200a, the level of the reference voltage VREF can be scanned in a predetermined or otherwise desired range and step unit. The level of the reference voltage VREF can be determined by a voltage margin, a timing margin, or an eye diagram through which the receiver circuit 200a can effectively determine, sense, or sample the input signal SIG. In some example embodiments of single-ended signaling, the input signal SIG can be received from outside of a semiconductor device including the receiver circuit 200a, and the reference voltage VREF can be generated within the semiconductor device. Due to a transmission environment of the input signal (SIG) line and process voltage temperature (PVT) variations of integrated circuits in the semiconductor device, a common mode offset can occur between the input signal SIG and the reference voltage VREF. The common mode offset refers to a voltage difference between the average voltage level of the input signal SIG and the level of the reference voltage VREF.

[0042] The voltage level of the input signal SIG and the level of the reference voltage VREF input to the first amplifier circuit 211 can be represented as a sum of a differential input and a common mode input. The differential input can correspond to a voltage difference between the voltage level of the input signal SIG and the level of the reference voltage VREF. The common mode input can be common to the voltage level of the input signal SIG and the level of the reference voltage VREF, and can correspond to an average of the voltage level of the input signal SIG and the level of the reference voltage VREF. The first amplifier circuit 211 can amplify the differential input and suppress the common mode input. The performance of the first amplifier circuit 211 can be evaluated by a common mode rejection ratio (CMRR). The common mode offset can reduce the degree to which the differential input is amplified by the first amplifier circuit 211, the degree to which the common mode input is suppressed by the first amplifier circuit 211, the CMRR of the first amplifier circuit 211, and the AC amplification factor of the first amplifier circuit 211. Accordingly, the common mode offset can reduce the voltage margin or the timing margin through which the receiver circuit 200a can effectively sense or sample the input signal SIG.

[0043] The first equalizer circuit 221a can be configured to cancel a common-mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF. In addition, the first equalizer circuit 221a can be configured to cancel crosstalk generated in the internal signal INT_SIG according to a change in the level of the reference voltage VREF.

[0044] The first equalizer circuit 221a can include transistors M3 and M4, resistors R3 and R4, and / or a current source CS2 constituting an amplifier. The amplifier of the first equalizer circuit 221a is a replica circuit of the first amplifier circuit 211, and can be identical or substantially identical to the first amplifier circuit 211. The operations of the components M3, M4, R3, R4, and CS2 of the amplifier of the first equalizer circuit 221a can be identical or substantially identical to the operations of the components M1, M2, R1, R2, and CS1 of the first amplifier circuit 211. The transistors M3 and M4 can be implemented as NMOS transistors.

[0045] The third output signal PRE_S can be output from a third connection node N3 between the drain terminal of the transistor M4 and the resistor R4, and the fourth output signal PRE_SB can be output from a fourth connection node N4 between the drain terminal of the transistor M3 and the resistor R3. The third output signal (PRE_S) line can be selectively connected to the resistor R6 through a first switching element SW1 that is turned on or off in response to a control signal CTRL1. The fourth output signal (PRE_SB) line can be selectively connected to the resistor R5 through a second switching element SW2 that is turned on or off in response to the control signal CTRL1. The control signal CTRL1 can be supplied from the control circuit 240a, and can selectively turn on or off the first switching element SW1 and the second switching element SW2 according to a change in the level of the reference voltage VREF to cancel crosstalk generated in the internal signal INT_SIG. The first switching element SW1 and the second switching element SW2 can be implemented as transmission gates.

[0046] The first equalizer circuit 221a can include a resistor R5, a capacitor C5, a resistor R6, and a capacitor C6, which constitute a low-pass filter. The resistor R6 and the capacitor C6 can constitute a low-pass filter that filters the third output signal PRE_S transmitted through the first switching element SW1 to generate the first feedback signal FB_INB. The resistor R5 and the capacitor C5 can constitute a low-pass filter that filters the fourth output signal PRE_SB transmitted through the second switching element SW2 to generate the second feedback signal FB_IN. The low-pass filter can be referred to as a filter circuit. The capacitors C5 and C6 can be implemented using MOS transistors, metal-insulator-metal (MIM) capacitors, passive devices, or the like.

[0047] Switching, conversion, or transition of the input signal SIG can be directly reflected in the third output signal PRE_S and the fourth output signal PRE_SB. The third output signal PRE_S and the fourth output signal PRE_SB can be switched at a transmission speed of the input signal SIG through an amplifier of the first equalizer circuit 221a. The low-pass filter including the resistors R5 and R6 and the capacitors C5 and C6 can filter high-frequency components of the third output signal PRE_S and the fourth output signal PRE_SB. The first feedback signal FB_INB and the second feedback signal FB_IN can be similar to a direct current (DC) signal. A voltage level of the first feedback signal FB_INB can be an average voltage level of the third output signal PRE_S. A voltage level of the second feedback signal FB_IN can be an average voltage level of the fourth output signal PRE_SB. The average voltage level can be referred to as a common-mode voltage level.

[0048] The first equalizer circuit 221a can include transistors M5 and M6 constituting a current adjustment circuit and a current source CS3. The transistors M5 and M6 can be implemented as NMOS transistors. The second feedback signal (FB_IN) line can be connected to a gate terminal of the transistor M5. A source terminal of the transistor M5 can be connected to the current source CS3, and a drain terminal of the transistor M5 can be connected to the second output signal (PRE_FB) line. The first feedback signal (FB_INB) line can be connected to a gate terminal of the transistor M6. A source terminal of the transistor M6 can be connected to the current source CS3, and a drain terminal of the transistor M6 can be connected to the first output signal (PRE_F) line. The current source CS3 can provide a bias current flowing through the transistors M5 and M6. The current source CS3 can be a transistor that receives a bias voltage through a gate terminal, is connected to the transistors M5 and M6 through a drain terminal, and is connected to a ground voltage VSS through a source terminal.

[0049] The current adjusting circuit (including transistors M5 and M6 and current source CS3) of the first equalizer circuit 221a can eliminate the common mode offset between the first output signal PRE_F and the second output signal PRE_FB of the first amplifier circuit 211 based on the common mode offset between the input signal SIG and the reference voltage VREF. When the common mode offset occurs between the input signal SIG and the reference voltage VREF, a voltage difference or common mode offset can also occur between the average voltage levels of the first output signal PRE_F and the second output signal PRE_FB of the first amplifier circuit 211. Similarly, a voltage difference or common mode offset can also occur between the average voltage levels of the third output signal PRE_S and the fourth output signal PRE_SB of the amplifier of the first equalizer circuit 221a. The voltage level of the first feedback signal FB_INB can be the average voltage level of the third output signal PRE_S, which is generated by a low pass filter including resistor R6 and capacitor C6. The voltage level of the second feedback signal FB_IN can be the average voltage level of the fourth output signal PRE_SB, which is generated by a low pass filter including resistor R5 and capacitor C5. Thus, a voltage difference or common mode offset can also occur between the first feedback signal FB_INB and the second feedback signal FB_IN.

[0050] The transistor M5 in the first equalizer circuit 221a can adjust the amount of current flowing from the second output signal (PRE_FB) line to the ground voltage (VSS) line according to the second feedback signal FB_IN, thereby adjusting the voltage level of the second output signal PRE_FB. The transistor M6 can adjust the amount of current flowing from the first output signal (PRE_F) line to the ground voltage (VSS) line according to the first feedback signal FB_INB, thereby adjusting the voltage level of the first output signal PRE_F.

[0051] For example, assume that the average voltage level of the input signal SIG is higher than the level of the reference voltage VREF. The average voltage level of the fourth output signal PRE_SB is lower than the average voltage level of the third output signal PRE_S. The average voltage level of the second feedback signal FB_IN is lower than the average voltage level of the first feedback signal FB_INB. The amount of current flowing through the transistor M5 according to the second feedback signal FB_IN is less than the amount of current flowing through the transistor M6 according to the first feedback signal FB_INB. Because the amount of current flowing through the transistor M6 is relatively large, the voltage level of the first output signal PRE_F can be relatively significantly reduced compared to the voltage level of the second output signal PRE_FB of the transistor M6. Thus, the first equalizer circuit 221a can reduce or eliminate the common mode offset when the average voltage level of the input signal SIG is higher than the level of the reference voltage VREF.

[0052] In contrast, it is assumed that the average voltage level of the input signal SIG is lower than the level of the reference voltage VREF. The average voltage level of the third output signal PRE_S is lower than the average voltage level of the fourth output signal PRE_SB. The average voltage level of the first feedback signal FB_INB is lower than the average voltage level of the second feedback signal FB_IN. The amount of current flowing through the transistor M6 according to the first feedback signal FB_INB is smaller than the amount of current flowing through the transistor M5 according to the second feedback signal FB_IN. Since the amount of current flowing through the transistor M5 is relatively large, the voltage level of the second output signal PRE_FB can be relatively significantly reduced compared to the voltage level of the first output signal PRE_F of the transistor M5. Accordingly, the first equalizer circuit 221a can cancel the common-mode offset when the average voltage level of the input signal SIG is lower than the level of the reference voltage VREF.

[0053] The first equalizer circuit 221a can adjust the amount of current flowing through the transistors M5 and M6 to cancel or reduce the voltage difference or common-mode offset between the average voltage levels of the first output signal PRE_F and the second output signal PRE_FB, which occurs due to the common-mode offset between the input signal SIG and the reference voltage VREF. The first equalizer circuit 221a can be referred to as a common-mode offset cancellation circuit.

[0054] The second equalizer circuit 222 can amplify, compensate, or restore high-frequency components of the input signal SIG attenuated due to channel loss. The second equalizer circuit 222 can include transistors M7 and M8, a resistor R7, a capacitor C7, and / or current sources CS4 and CS5. The transistors M7 and M8 can be implemented as NMOS transistors. The drain terminal of the transistor M7 and the gate terminal of the transistor M8 can be connected to the second output signal (PRE_FB) line. The gate terminal of the transistor M7 and the drain terminal of the transistor M8 can be connected to the first output signal (PRE_F) line. The source terminal of the transistor M7 can be connected to the current source CS4, one end of the resistor R7, and one end of the capacitor C7. The source terminal of the transistor M8 can be connected to the current source CS5, the other end of the resistor R7, and the other end of the capacitor C7. The transistors M7 and M8 can form a cross-coupled pair.

[0055] The current source CS4 can provide a bias current flowing through the transistor M7. The current source CS5 can provide a bias current flowing through the transistor M8. The current sources CS4 and CS5 can be transistors that respectively receive a bias voltage through a gate terminal, are respectively connected to the transistors M7 and M8 through a drain terminal, and are respectively connected to a ground voltage VSS through a source terminal.

[0056] The second equalizer circuit 222 can be a high-pass filter that enhances high frequency components of the first output signal PRE_F and the second output signal PRE_FB. The transistors M7 and M8 can amplify the first output signal PRE_F and the second output signal PRE_FB in a positive feedback method. The second equalizer circuit 222 can provide a negative impedance or a negative capacitance to the first output signal (PRE_F) line and the second output signal (PRE_FB) line. The second equalizer circuit 222 can be a negative capacitance equalizer (NCE) or a continuous time linear equalizer (CTLE).

[0057] The gain of the first amplifier circuit 211 can be reduced by the common mode offset cancellation operation of the first equalizer circuit 221a. The second amplifier circuit 212 can compensate for the reduced gain of the first amplifier circuit 211 by amplifying the first output signal PRE_F and the second output signal PRE_FB output from the first amplifier circuit 211. The second amplifier circuit 212 can amplify a voltage difference between the first output signal PRE_F and the second output signal PRE_FB to output a fifth output signal AMP_O and a sixth output signal AMP_OB. The second amplifier circuit 212 can include transistors M9 and M10, resistors R9 and R10, and / or a current source CS6. The transistors M9 and M10 can be implemented as NMOS transistors.

[0058] The first output signal (PRE_F) line can be connected to a gate terminal of the transistor M9. A source terminal of the transistor M9 can be connected to the current source CS6, and a drain terminal of the transistor M9 can be connected to the resistor R9. The second output signal (PRE_F) line can be connected to a gate terminal of the transistor M10. A source terminal of the transistor M10 can be connected to the current source CS6, and a drain terminal of the transistor M10 can be connected to the resistor R10. The current source CS6 can provide a bias current flowing through the transistors M9 and M10, and a gain of the second amplifier circuit 212 can vary according to a magnitude of the bias current. The resistor R9 can be connected between the power supply voltage VDD and the drain terminal of the transistor M9, and the resistor R10 can be connected between the power supply voltage VDD and the drain terminal of the transistor M10. The fifth output signal AMP_O can be output from a fifth connection node N5 between the drain terminal of the transistor M10 and the resistor R10, and the sixth output signal AMP_OB can be output from a sixth connection node N6 between the drain terminal of the transistor M9 and the resistor R9.

[0059] The level conversion circuit 230 can receive the fifth output signal AMP_O and the sixth output signal AMP_OB of the second amplifier circuit 212 generated according to the input signal SIG that swings based on the CML level, amplify a voltage difference between the fifth output signal AMP_O and the sixth output signal AMP_OB, and generate an internal signal INT_SIG having a CMOS level. The level conversion circuit 230 can include an operational amplifier 231 and / or a buffer 232. In the operational amplifier 231, the fifth output signal AMP_O can be connected to a non-inverting input terminal (+), and the sixth output signal AMP_OB can be connected to an inverting input terminal (-). The operational amplifier 231 can be implemented as an operational transconductance amplifier (OTA), a differential amplifier, or the like. An output signal of the operational amplifier 231 can be output as the internal signal INT_SIG through the buffer 232. The internal signal INT_SIG can be generated as a digital signal having a logic high level or a logic low level, and can perform an internal operation of the semiconductor device according to a function of the input signal SIG.

[0060] The control circuit 240a can generate the control signal CTRL1 by receiving the internal signal INT_SIG of the level conversion circuit 230. The control circuit 240a can include an exclusive OR (XOR) gate 301, a first inverter 302 and a second inverter 303 connected in series, and / or a third inverter 304. The XOR gate 301 has a first input terminal for receiving the internal signal INT_SIG, a second input terminal for receiving outputs of the first inverter 302 and the second inverter 303 connected in series, and an output terminal for outputting the control signal CTRL1. The third inverter 304 can receive an output of the XOR gate 301 and output an inverted signal of the control signal CTRL1. The control signal CTRL1 can be output as a logic high pulse whenever a logic level of the internal signal INT_SIG transitions, that is, when the logic level of the internal signal INT_SIG transitions from a logic high to a logic low or from a logic low to a logic high. A width of the logic high pulse of the control signal CTRL1 can be determined by a delay time of the first inverter 302 and the second inverter 303 connected in series. The control signal CTRL1 can be provided to the first switching element SW1 and the second switching element SW2 of the first equalizer circuit 221a.

[0061] Figure 4 is a timing diagram illustrating an operation of Figure 3 the receiver circuit 200a. It should be noted that in the timing diagrams described in the inventive concept, a horizontal axis and a vertical axis respectively represent time and a voltage level, and the timing diagrams are not necessarily drawn to scale.

[0062] Referring to Figure 3 and Figure 4The input signal SIG having the CML level can be received by the receiver circuit 200a at the time Ta4. It is assumed that the average voltage level of the input signal SIG is higher than the level of the reference voltage VREF. Some example embodiments will be described in which the level of the reference voltage VREF for determining the voltage level of the input signal SIG is close to the low voltage level of the input signal SIG.

[0063] From the time Ta4 to the time Tb4, the receiver circuit 200a can determine the bits of the input signal SIG having the CML level and output the internal signal INT_SIG having the CMOS level. In the first amplifier circuit 211, the swing levels of the first output signal PRE_F and the second output signal PRE_FB can be determined according to the voltage difference between the voltage level of the input signal SIG and the level of the reference voltage REF. The second equalizer circuit 222 can amplify the high frequency components of the input signal SIG attenuated due to channel loss. The second amplifier circuit 212 can amplify the first output signal PRE_F and the second output signal PRE_FB and output the fifth output signal AMP_O and the sixth output signal AMP_OB, and the level conversion circuit 230 can amplify the voltage difference between the fifth output signal AMP_O and the sixth output signal AMP_OB and generate the internal signal INT_SIG having a logic high level or a logic low level.

[0064] Whenever the logic level of the internal signal INT_SIG transitions, the control circuit 240a can generate the control signal CTRL1 having a logic high pulse, and the control circuit 240a can provide the generated control signal CTRL1 to the first and second switching elements SW1 and SW2 of the first equalizer circuit 221a. The first equalizer circuit 221a can generate the third and fourth output signals PRE_S and PRE_SB, which are identical to the first and second output signals PRE_F and PRE_FB, respectively, according to a voltage difference between the voltage level of the input signal SIG and the level of the reference voltage REF. Only when the pass gates of the first and second switching elements SW1 and SW2 are turned on in response to the logic high pulse of the control signal CTRL1, the first equalizer circuit 221a can generate the average voltage levels of the third and fourth output signals PRE_S and PRE_SB through the low pass filter including the resistors R5 and R6 and the capacitors C5 and C6, and the first equalizer circuit 221a can output the average voltage levels as the first and second feedback signals FB_INB and FB_IN. The first equalizer circuit 221a can adjust the amounts of currents of the first and second output signal (PRE_F) lines and the second and third output signal (PRE_FB) lines according to the first and second feedback signals FB_INB and FB_IN to adjust the voltage levels of the first and second output signal (PRE_F) lines and the second and third output signal (PRE_FB) lines, and thus can eliminate the common mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF.

[0065] From the time Tb4 to the time Tc4, the input signal SIG having a low level can be received by the receiver circuit 200a for a relatively long time. Because the level of the reference voltage VREF approaches the low voltage level of the input signal SIG, when the input signal SIG having the low voltage level is received, the sensing margin of the receiver circuit 200a can decrease, and crosstalk can occur in the internal signal INT_SIG. The crosstalk is due to the waveform X4, which occurs when the first equalizer circuit 221a generates the average voltage levels of the third and fourth output signals PRE_S and PRE_SB and outputs the average voltage levels as the first and second feedback signals FB_INB and FB_IN, the voltage levels of the first and second feedback signals FB_INB and FB_IN are inverted by the charging operation of the low pass filter including the resistors R5 and R6 and the capacitors C5 and C6, and thus the waveform X4 occurs.

[0066] When the internal signal INT_SIG is outputted at a logic low level without a logic level transition, the control signal CTRL1 is outputted at a logic low level to turn off the pass gates of the first switching element SW1 and the second switching element SW2, so that the charging operation of the low-pass filter (including the resistors R5 and R6 and the capacitors C5 and C6) is stopped, the waveform X4 due to the inversion of the first feedback signal FB_INB and the second feedback signal FB_IN can be reduced or prevented. Thus, the first equalizer circuit 221a can eliminate the crosstalk of the internal signal INT_SIG.

[0067] At the time Tc4, similar to the operation between the time Ta4 and the time Tb4, the receiver circuit 200a can determine the bit of the input signal SIG having the CML level and output the internal signal INT_SIG having the CMOS level.

[0068] Even if the level of the reference voltage VREF for determining the voltage level of the input signal SIG is close to the low level of the input signal SIG, the sensing margin of the receiver circuit 200a is small, Figure 3 the receiver circuit 200a of can eliminate the common-mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF and the crosstalk occurring in the internal signal INT_SIG.

[0069] Figure 5 is a circuit diagram of a receiver circuit 200b according to an example embodiment of the inventive concept. Figure 5 The receiver circuit 200b of Figure 3 is a modified example of the receiver circuit 200a of Figure 5 The configuration of the first equalizer circuit 221b and the control circuit 240b in the receiver circuit 200b of Figure 3 is different from the configuration of the first equalizer circuit 221a and the control circuit 240a in the receiver circuit 200a of Figure 3 For ease of description, the description of the configuration that is the same as or substantially the same as the configuration described above with reference to will be omitted.

[0070] With reference to Figure 5 , the first switching element SW1 and the second switching element SW2 of the first equalizer circuit 221b can be implemented as PMOS transistors, instead of the pass gates described above with reference to Figure 3 .

[0071] The control circuit 240b can include an XOR gate 301, a first inverter 302 and a second inverter 303 connected in series, a multiplexer 501, a flip-flop 502, and / or a NOR gate 503. As described above with reference to Figure 3As described, the XOR gate 301 can output a logic high pulse whenever the logic level of the internal signal INT_SIG transitions. The output signal of the XOR gate 301 can be the same as the control signal CTRL1 of the NOR gate 501. The output signal of the XOR gate 301 can be provided to the first input terminal of the NOR gate 503. Figure 3

[0072] The multiplexer 501 has a first input terminal connected to a power voltage (VDD) line, a second input terminal connected to a ground voltage (VSS) line, and an output terminal. The multiplexer 501 can provide the power voltage (VDD) level of the first input terminal of the multiplexer 501 to the data input terminal D of the flip-flop 502 in response to a logic high level of a selection signal SEL, and the multiplexer 501 can provide the ground voltage (VSS) level of the second input terminal of the multiplexer 501 to the data input terminal D of the flip-flop 502 in response to a logic low level of the selection signal SEL. When the semiconductor device including the receiver circuit 200b is implemented as a memory device, the selection signal SEL can be provided by a mode register set (MRS). According to an example embodiment, the selection signal SEL can be provided from the outside of the semiconductor device including the receiver circuit 200b.

[0073] The flip-flop 502 has a data input terminal D for receiving the output of the multiplexer 501, a clock input terminal CK for receiving the internal signal INT_SIG, and an output terminal. When the internal signal INT_SIG transitions from a logic high level to a logic low level, the flip-flop 502 can receive the output of the multiplexer 501 and output the received output to the second input terminal of the NOR gate 503.

[0074] The NOR gate 503 has a first input terminal for receiving the output of the XOR gate 301, a second input terminal for receiving the output of the flip-flop 502, and an output terminal for outputting a control signal CTRL2. The control signal CTRL2 can be output at a logic low level when the selection signal SEL is at a logic high level. The control signal CTRL2 can be output as an inverted signal of the output of the XOR gate 301 when the selection signal SEL is at a logic low level.

[0075] ​The control signal CTRL2 of the control circuit 240b can be supplied to the gates of PMOS transistors which are the first and second switching elements SW1 and SW2 of the first equalizer circuit 221b. When the PMOS transistors of the first and second switching elements SW1 and SW2 are turned on by the control signal CTRL2, average voltage levels of the third and fourth output signals PRE_S and PRE_SB can be generated by a charging operation of a low-pass filter (including resistors R5 and R6 and capacitors C5 and C6) of the first equalizer circuit 221b, and output as the first and second feedback signals FB_INB and FB_IN.

[0076] When the PMOS transistors of the first and second switching elements SW1 and SW2 are turned off by the control signal CTRL2, the charging operation of the low-pass filter (including resistors R5 and R6 and capacitors C5 and C6) of the first equalizer circuit 221b can be stopped, so that crosstalk of the internal signal INT_SIG can be eliminated.

[0077] Figures 6 to 8 is a timing chart illustrating operations of the receiver circuit 200b of Figure 5 . Figure 6 Some example embodiments in which the level of the reference voltage VREF approaches a high voltage level of the input signal SIG are illustrated, Figure 7 Some example embodiments in which the level of the reference voltage VREF approaches a low voltage level of the input signal SIG are illustrated, and Figure 8 Some example embodiments in which the level of the reference voltage VREF approaches an intermediate voltage level of the input signal SIG are illustrated.

[0078] Referring to Figure 5 and Figure 6 , because the level of the reference voltage VREF approaches a high level voltage of the input signal SIG, the sensing margin of the receiver circuit 200b can be reduced when the input signal SIG having a high voltage level is received. At time Ta6, the input signal SIG can be received by the receiver circuit 200b.

[0079] In the receiver circuit 200b, from time Ta6 to time Tb6, the first amplifier circuit 211 can output the first output signal PRE_F and the second output signal PRE_FB according to a voltage difference between a voltage level of the input signal SIG and a level of the reference voltage REF, the second amplifier circuit 212 can amplify the first output signal PRE_F and the second output signal PRE_FB and output the fifth output signal AMP_O and the sixth output signal AMP_OB, and the level conversion circuit 230 can amplify a voltage difference between the fifth output signal AMP_O and the sixth output signal AMP_OB and generate the internal signal INT_SIG having a logic high level or a logic low level.

[0080] When the selection signal SEL is at a logic high (H) level, the control circuit 240b can output the control signal CRTL2 having a logic low (L) level, and when the selection signal SEL is at a logic low (L) level, the control circuit 240b can output the inverted signal of the logic high pulse, i.e., the logic low pulse, every time the logic level of the internal signal INT_SIG transitions. When the PMOS transistors of the first and second switching elements SW1 and SW2 of the first equalizer circuit 221b are turned on in response to the logic low (L) level or the logic low pulse of the control signal CRTL2, the average voltage level of the third output signal PRE_S and the fourth output signal PRE_SB can be generated by the low-pass filter (including the resistors R5 and R6 and the capacitors C5 and C6) and output as the first feedback signal FB_INB and the second feedback signal FB_IN. The first equalizer circuit 221b can adjust the amount of current of the first output signal (PRE_F) line and the second output signal (PRE_FB) line according to the first feedback signal FB_INB and the second feedback signal FB_IN to adjust the voltage level of the first output signal (PRE_F) line and the second output signal (PRE_FB) line, and thus the first equalizer circuit 221b can eliminate the common-mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF.

[0081] From time Tb6 to time Tc6, the input signal SIG having a high level can be received by the receiver circuit 200b for a relatively long time. Because the level of the reference voltage VREF approaches the high voltage level of the input signal SIG, the sensing margin of the receiver circuit 200b can be small.

[0082] The PMOS transistors of the first and second switching elements SW1 and SW2 of the first equalizer circuit 221b can remain on in response to a logic low (L) level of the control signal CTRL2 when the selection signal SEL is at a logic high (H) level. In some example embodiments, when the first equalizer circuit 221b generates average voltage levels of the third and fourth output signals PRE_S and PRE_SB and outputs the average voltage levels as the first and second feedback signals FB_INB and FB_IN, the voltage levels of the first and second feedback signals FB_INB and FB_IN can be inverted like the waveform X6 by a charging operation of a low pass filter including the resistors R5 and R6 and the capacitors C5 and C6. Thus, crosstalk can occur in the internal signal INT_SIG output by the receiver circuit 200b by determining bits of the input signal SIG having a CML level.

[0083] To eliminate the crosstalk of the internal signal INT_SIG, the selection signal SEL can be provided at a logic low (L) level. The control circuit 240b can output the control signal CTRL2 having a logic high level based on the selection signal SEL having a logic low (L) level and the internal signal INT_SIG having a logic high level. When the PMOS transistors of the first and second switching elements SW1 and SW2 of the first equalizer circuit 221b are cut off according to a logic high level of the control signal CTRL2 and the charging operation of the low pass filter including the resistors R5 and R6 and the capacitors C5 and C6 is stopped, the voltage levels of the first and second feedback signals FB_INB and FB_IN are not inverted. By adjusting the amount of current of the first and second output signal (PRE_F) lines and the second and first output signal (PRE_FB) lines to adjust the voltage levels of the first and second output signal (PRE_F) lines without inverting the voltage levels of the first and second feedback signals FB_INB and FB_IN, the common mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF can be eliminated and the crosstalk of the internal signal INT_SIG can be eliminated.

[0084] From the time Tc6 to the time Td6, the receiver circuit 200b can determine bits of the input signal SIG having a CML level and output the internal signal INT_SIG having a CMOS level, similar to the operation between the time Ta6 and the time Tb6.

[0085] From time Td6 to time Te6, the input signal SIG having the low level can be received by the receiver circuit 200b for a relatively long time. Because the level of the reference voltage VREF is sufficiently higher than the voltage level of the input signal SIG, the sensing margin of the receiver circuit 200b can be sufficient. Similar to the operation between time Ta6 and time Tb6, the receiver circuit 200b can determine the bit of the input signal SIG having the CML level and stably output the internal signal INT_SIG having the CMOS level without crosstalk.

[0086] At time Te6, similar to the operation between time Ta6 and time Tb6, the receiver circuit 200b can determine the bit of the input signal SIG having the CML level and output the internal signal INT_SIG having the CMOS level.

[0087] As described with reference to Figure 5 and Figure 6 , even if the level of the reference voltage VREF for determining the voltage level of the input signal SIG approaches the high voltage level of the input signal SIG, the receiver circuit 200b can eliminate the common-mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF and the crosstalk occurring in the internal signal INT_SIG, although the sensing margin of the receiver circuit 200b is small.

[0088] Referring to Figure 5 and Figure 7 , because the level of the reference voltage VREF approaches the low level of the input signal SIG, the sensing margin of the receiver circuit 200b can be reduced when the input signal SIG having the low level is received. At time Ta7, the input signal SIG can be received by the receiver circuit 200b.

[0089] From time Ta7 to time Td7, similar to the operation between time Ta6 and time Tb6 of Figure 6 , the receiver circuit 200b can determine the bit of the input signal SIG having the CML level and stably output the internal signal INT_SIG having the CMOS level.

[0090] From time Td7 to time Te7, the input signal SIG having the low level can be received by the receiver circuit 200b for a relatively long time. Because the level of the reference voltage VREF approaches the low level of the input signal SIG, the sensing margin of the receiver circuit 200b can be small.

[0091] The PMOS transistors of the first and second switching elements SW1 and SW2 of the first equalizer circuit 221b can remain on in response to a logic low (L) level of the control signal CTRL2 when the selection signal SEL is at a logic high (H) level. In some example embodiments, when the first equalizer circuit 221b generates average voltage levels of the third and fourth output signals PRE_S and PRE_SB and outputs the average voltage levels as the first and second feedback signals FB_INB and FB_IN, the voltage levels of the first and second feedback signals FB_INB and FB_IN can be inverted by a charging operation of a low pass filter including resistors R5 and R6 and capacitors C5 and C6 as the waveform X7. Thus, crosstalk can occur in the internal signal INT_SIG output by the receiver circuit 200b by determining bits of the input signal SIG having a CML level.

[0092] To eliminate the crosstalk of the internal signal INT_SIG, the selection signal SEL can be provided at a logic low (L) level. The control circuit 240b can output the control signal CTRL2 having a logic high level based on the selection signal SEL having a logic low level and the internal signal INT_SIG having a logic low level. When the PMOS transistors of the first and second switching elements SW1 and SW2 of the first equalizer circuit 221b are cut off according to a logic high level of the control signal CTRL2 and the charging operation of the low pass filter including the resistors R5 and R6 and the capacitors C5 and C6 is stopped, the voltage levels of the first and second feedback signals FB_INB and FB_IN are not inverted. By adjusting the amount of current of the first and second output signal (PRE_F) lines and the second and first output signal (PRE_FB) lines to adjust the voltage levels of the first and second output signal (PRE_F) lines without inverting the voltage levels of the first and second feedback signals FB_INB and FB_IN, the common mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF can be eliminated and the crosstalk of the internal signal INT_SIG can be eliminated.

[0093] At time Te7, similar to the operation between time Ta6 and time Tb6, the receiver circuit 200b can determine bits of the input signal SIG having a CML level and output the internal signal INT_SIG having a CMOS level.

[0094] As described with reference to Figure 5 and Figure 7That is, even if the level of the reference voltage VREF used to determine the voltage level of the input signal SIG is close to the low voltage level of the input signal SIG, and the sensing margin of the receiver circuit 200b is small, the receiver circuit 200b can eliminate the common-mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF, and the crosstalk occurring in the internal signal INT_SIG.

[0095] Referring to Figure 5 and Figure 8 Because the level of the reference voltage VREF is close to the middle level of the input signal SIG, the sensing margin of the receiver circuit 200b can be sufficient regardless of the high level or the low level of the received input signal SIG. At time Ta8, the input signal SIG can be received by the receiver circuit 200b.

[0096] From time Ta8 to time Te8, similar to the operation between time Ta6 and time Tb6 of Figure 6 the receiver circuit 200b can determine the bit of the input signal SIG having the CML level and output the internal signal INT_SIG having the CMOS level. Because the level of the reference voltage VREF is close to the middle level of the input signal SIG, the receiver circuit 200b can ensure a sufficient sensing margin.

[0097] In the receiver circuit 200b, the first amplifier circuit 211 can output the first output signal PRE_F and the second output signal PRE_FB according to a voltage difference between a voltage level of the input signal SIG and a level of the reference voltage REF regardless of the control signal CTRL2 generated by the control circuit 240 in response to a logic high (H) level or a logic low (L) level of the selection signal SEL. In addition, the first equalizer circuit 221b can generate the third output signal PRE_S and the fourth output signal PRE_SB according to the voltage difference between the voltage level of the input signal SIG and the level of the reference voltage REF, can generate average voltage levels of the third output signal PRE_S and the fourth output signal PRE_SB to output the average voltage levels as the first feedback signal PRE_S and the second feedback signal PRE_SB, and can adjust amounts of current of the first output signal (PRE_F) line and the second output signal line (PRE_FB) line according to voltage levels of the first feedback signal FB_INB and the second feedback signal FB_IN to adjust voltage levels of the first output signal (PRE_F) line and the second output signal line (PRE_FB) line. Furthermore, the second amplifier circuit 212 can amplify the first output signal PRE_F and the second output signal PRE_FB and output the fifth output signal AMP_O and the sixth output signal AMP_OB, and the level conversion circuit 230 can amplify a voltage difference between the fifth output signal AMP_O and the sixth output signal AMP_OB and stably output the internal signal INT_SIG having a logic high level or a logic low level.

[0098] Figure 9 is a circuit diagram of a receiver circuit 200c according to an example embodiment of the inventive concept, and Figure 10 is a timing chart illustrating an operation of the receiver circuit 200c of Figure 9 . Figure 9 The receiver circuit 200c of Figure 3 is a modified example of the receiver circuit 200a of Figure 9 . The configuration of the control circuit 240c in the receiver circuit 200c of Figure 3 is different from the configuration of the control circuit 240a in the receiver circuit 200a of Figure 3 and Figure 4 described above with reference to will be omitted.

[0099] Referring to Figure 9 , the control circuit 240c can include an XOR gate 301, a first inverter 302 and a second inverter 303 connected in series, a flip-flop 901, and / or an OR gate 902. As Figure 3As described, the XOR gate 301 can output a logic high pulse whenever the logic level of the internal signal INT_SIG transitions. The output signal of the XOR gate 301 can be provided to a first input terminal of the OR gate 902.

[0100] The flip-flop 901 has a data input terminal D connected to a ground voltage (VSS) line, a clock input terminal CK connected to an internal signal (INT_SIG) line, and an output terminal. As Figure 10 shown, the output of the flip-flop 901 can be at a logic high level at a power supply voltage (VDD) level in an initial state, and can be output at a logic low level according to a ground voltage (VSS) level on the data input terminal D when the internal signal INT_SIG transitions from a logic high level to a logic low level. The output of the flip-flop 901 can be provided to a second input terminal of the OR gate 902.

[0101] The OR gate 902 has a first input terminal for receiving the output of the XOR gate 301, a second input terminal for receiving the output of the flip-flop 901, and an output terminal for outputting a control signal CTRL3. The third inverter 903 can receive the output of the OR gate 902 and output an inverted signal of the control signal CTRL3. As Figure 10 shown, as a result of performing an "OR" operation on the output of the XOR gate 301 and the output of the flip-flop 502, the control signal CTRL3 can be output. According to the output of the flip-flop 901, the control signal CTRL3 can be output at a logic high level in an initial state, and then when the internal signal INT_SIG transitions from a logic high level to a logic low level, the control signal CTRL3 can be output according to the output of the XOR gate 301 having a logic high pulse. The control signal CTRL3 of the control circuit 240c can be provided to pass gates of the first switching element SW1 and the second switching element SW2 as the first equalizer circuit 221a.

[0102] Referring to Figure 10 , from time T1 to time T2, when the pass gates of the first switching element SW1 and the second switching element SW2 are turned on by the control signal CTRL3 having a logic high level, a charging operation of a low-pass filter (including resistors R5 and R6 and capacitors C5 and C6) of the first equalizer circuit 221a can be performed.

[0103] At time T2, the transmission gates of the first switching element SW1 and the second switching element SW2 can be selectively turned on or off using the control signal CTRL3 with a logic high pulse. When the transmission gates of the first switching element SW1 and the second switching element SW2 are turned off, the charging operation of the low-pass filter (including resistors R5 and R6 and capacitors C5 and C6) of the first equalizer circuit 221a can be stopped. The first equalizer circuit 221a can selectively turn on or off the charging operation of the low-pass filter (including resistors R5 and R6 and capacitors C5 and C6), thereby generating the average voltage level of the third output signal PRE_S and the fourth output signal PRE_SB, and outputting the average voltage level as the first feedback signal FB_INB and the second feedback signal FB_IN.

[0104] Figure 11 This is a circuit diagram of a receiver circuit 200d according to an exemplary embodiment of the present invention. Figure 11 The receiver circuit 200d is Figure 9 Example of modification of receiver circuit 200c.

[0105] Reference Figure 11 The configuration of the first amplifier circuit 211a, the second amplifier circuit 212a, the first equalizer circuit 221c, and the second equalizer circuit 222a in the receiver circuit 200d is similar to... Figure 9 The configurations of the first amplifier circuit 211, the second amplifier circuit 212, the first equalizer circuit 221a, and the second equalizer circuit 222 in the receiver circuit 200c are different. Specifically, compared with... Figure 9 Compared to the first equalizer circuit 221a, the first equalizer circuit 221c includes switching elements SW1a and SW2a formed by NMOS transistors. Therefore, the configuration of the first amplifier circuit 211a, the second amplifier circuit 212a, the first equalizer circuit 221c, and the second equalizer circuit 222a is determined according to the characteristics of the NMOS transistors.

[0106] The first amplifier circuit 211a may include transistors M1a and M2a, resistors R1a and R2a, and / or a current source CS1a. Transistors M1a and M2a may be implemented as P-type metal-oxide-semiconductor (PMOS) transistors.

[0107] An input signal (SIG) line can be connected to a gate terminal of a transistor Mla. A source terminal of the transistor Mla can be connected to a current source CSla, and a drain terminal of the transistor Mla can be connected to a resistor Rla. The transistor Mla can control an amount of current flowing between its drain terminal and source terminal according to a voltage level of the input signal SIG. A reference voltage (VREF) line can be connected to a gate terminal of a transistor M2a. A source terminal of the transistor M2a can be connected to the current source CSla, and a drain terminal of the transistor M2a can be connected to a resistor R2a. The current source CSla can be connected to a power supply voltage VDD, and can provide a bias current flowing through the transistors Mla and M2a. The resistor Rla can be connected between a ground voltage VSS and the drain terminal of the transistor Mla. The resistor R2a can be connected between the ground voltage VSS and the drain terminal of the transistor M2a. A first output signal PRE_F can be output from a connection node between the drain terminal of the transistor M2a and the resistor R2a, and a second output signal PRE_FB can be output from a connection node between the drain terminal of the transistor Mla and the resistor Rla.

[0108] The first equalizer circuit 221c can include transistors M3a and M4a constituting an amplifier, resistors R3a and R4a, and / or a current source CS2a. The transistors M3a and M4a can be implemented as PMOS transistors. The amplifier of the first equalizer circuit 221c can be identical or substantially identical to the first amplifier circuit 211a. A third output signal PRE_S can be output from a connection node between a drain terminal of the transistor M4a and the resistor R4a, and a fourth output signal PRE_SB can be output from a connection node between a drain terminal of the transistor M3a and the resistor R3a. A third output signal (PRE_S) line can be selectively connected to the resistor R6a through an NMOS transistor of a first switching element SWla that turns on or off in response to a control signal CTRL4. A fourth output signal (PRE_SB) line can be selectively connected to the resistor R5a through an NMOS transistor of a second switching element SW2a that turns on or off in response to the control signal CTRL4. The control signal CTRL4 can be provided by the control circuit 240c.

[0109] The first equalizer circuit 221c can include a resistor R5a, a capacitor C5a, a resistor R6a, and / or a capacitor C6a that constitute a low pass filter. The resistor R6a and the capacitor C6a can filter the third output signal PRE_S transmitted through the NMOS transistor of the first switching element SW1a to generate the first feedback signal FB_INB, and the resistor R5a and the capacitor C5a can filter the fourth output signal PRE_SB transmitted through the NMOS transistor of the second switching element SW2a to generate the second feedback signal FB_IN.

[0110] The first equalizer circuit 221a can include transistors M5a and M6a and / or a current source CS3a that constitute a current adjusting circuit. The transistors M5a and M6a can be implemented as PMOS transistors. The transistor M5a can have a gate terminal connected to the second feedback signal (FB_IN) line, a source terminal connected to the current source CS3a, and a drain terminal connected to the second output signal (PRE_FB) line. The transistor M6a can have a gate terminal connected to the first feedback signal (FB_INB) line, a source terminal connected to the current source CS3a, and a drain terminal connected to the first output signal (PRE_F) line. The current source CS3a can be connected to the power supply voltage VDD and can provide a bias current flowing through the transistors M5a and M6a.

[0111] The second amplifier circuit 212a can amplify the first output signal PRE_F and the second output signal PRE_FB output from the first amplifier circuit 211a to compensate for the reduced gain of the first amplifier circuit 211a. The second amplifier circuit 212a can amplify a voltage difference between the first output signal PRE_F and the second output signal PRE_FB to output a fifth output signal AMP_O and a sixth output signal AMP_OB. The second amplifier circuit 212a can include transistors M9a and M10a, resistors R9a and R10a, and / or a current source CS6a. The transistors M9a and M10a can be implemented as PMOS transistors. The transistor M9a can have a gate terminal connected to the first output signal (PRE_F) line, a source terminal connected to the current source CS6a, and a drain terminal connected to the resistor R9a. The transistor M10a can have a gate terminal connected to the second output signal (PRE_FB) line, a source terminal connected to the current source CS6a, and a drain terminal connected to the resistor R10a. The current source CS6a can be connected to the power supply voltage VDD and can provide a bias current flowing through the transistors M9a and M10a. The resistor R9a can be connected between the ground voltage VSS and the drain terminal of the transistor M9a, and the resistor R10a can be connected between the ground voltage VSS and the drain terminal of the transistor M10a. The fifth output signal AMP_O can be output from a connection node between the drain terminal of the transistor M10a and the resistor R10a, and the sixth output signal AMP_OB can be output from a connection node between the drain terminal of the transistor M9a and the resistor R9a.

[0112] The second equalizer circuit 222a can include transistors M7a and M8a, a resistor R7a, a capacitor C7a, and / or current sources CS4a and CS5a. The transistors M7a and M8a can be implemented as PMOS transistors. The drain terminal of the transistor M7a and the gate terminal of the transistor M8a can be connected to the second output signal (PRE_FB) line, and the gate terminal of the transistor M7a and the drain terminal of the transistor M8a can be connected to the first output signal (PRE_F) line. The source terminal of the transistor M7a can be connected to the current source CS4a, one end of the resistor R7a, and one end of the capacitor C7a. The source terminal of the transistor M8a can be connected to the current source CS5a, the other end of the resistor R7a, and the other end of the capacitor C7a.

[0113] The receiver circuit 200d can be described with reference to the timing diagram of FIG. 13. Figure 10 The receiver circuit 200d can be described with reference to the timing diagram of FIG. 13. Figure 9The receiver circuit 200c is similarly operated. In the receiver circuit 200d, the NMOS transistors of the first and second switching elements SW1a and SW2a can be initially turned on by the control signal CTRL4 having a logic high level, and thus a charging operation of the low-pass filter (including the resistors R5a and R6a and the capacitors C5a and C6a) of the first equalizer circuit 221c can be performed. Thereafter, when the internal signal INT_SIG transitions from a logic high level to a logic low level, the NMOS transistors of the first and second switching elements SW1a and SW2a can be selectively turned on or turned off by the control signal CTRL4 having a logic high pulse. When the NMOS transistors of the first and second switching elements SW1a and SW2a are turned off, the charging operation of the low-pass filter (including the resistors R5a and R6a and the capacitors C5a and C6a) of the first equalizer circuit 221c can be stopped. The first equalizer circuit 221c can selectively turn on or turn off the charging operation of the low-pass filter (including the resistors R5a and R6a and the capacitors C5a and C6a), thereby generating an average voltage level of the third and fourth output signals PRE_S and PRE_SB and outputting the average voltage level as the first and second feedback signals FB_INB and FB_IN.

[0114] By using the NMOS transistors of the first and second switching elements SW1a and SW2a in response to the control signal CTRL4, the receiver circuit 200d can eliminate a common-mode offset between the average voltage level of the input signal SIG and the level of the reference voltage VREF and crosstalk occurring in the internal signal INT_SIG.

[0115] Figure 12 is a block diagram of a system 1000 to which a receiver according to an example embodiment of the inventive concept is applied.

[0116] Referring to Figure 12 , the system 1000 can include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, dynamic random access memories (DRAMs) 1500a and 1500b, flash devices 1600a and 1600b, input / output (I / O) devices 1700a and 1700b, and / or an application processor 1800 (hereinafter, referred to as "AP"). The system 1000 can be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. In addition, the system 1000 can be implemented as a server or a personal computer.

[0117] Any of the above-disclosed elements can be included in, or implemented with, a processing circuit, such as hardware including logic circuitry, a hardware / software combination, such as a processor executing software, or combinations thereof. For example, processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0118] The camera 1100 can capture still images or moving images according to a user's control, and can store or transmit the captured images / image data to the display 1200. The audio processor 1300 can process audio data included in the flash memory devices 1600a and 1600b or network content. The modem 1400 can modulate a signal to perform wired / wireless data transmission and reception, and can demodulate a modulated signal at a reception side to restore an original signal. The I / O devices 1700a and 1700b can include devices that provide digital input and / or output functions, such as a universal serial bus (USB) or storage device, a digital camera, a secure digital (SD) card, a digital versatile disk (DVD), a network adapter, and a touch screen.

[0119] The AP 1800 can control the overall operation of the system 1000. The AP 1800 can control the display 1200 so that a part of content stored in the flash memory devices 1600a and 1600b is displayed on the display 1200. When a user input is received through the I / O devices 1700a and 1700b, the AP 1800 can perform a control operation corresponding to the user input. The AP 1800 can include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data operation, or the AP 1800 can include an accelerator chip 1820 separate from the AP 1800. The AP 1800 can include a controller 1810 and an interface 1830. The DRAM 1500b can be additionally mounted on the accelerator block or the accelerator chip 1820. The accelerator block is a functional block that specifically performs a specific function of the AP 1800, and can include a graphic processing unit (GPU) that specifically processes graphic data, a neural processing unit (NPU) that specifically performs AI calculation and inference, and a data processing unit (DPU) that specifically performs data processing.

[0120] The system 1000 can include a plurality of DRAMs 1500a and 1500b. The AP 1800 can control the DRAMs 1500a and 1500b through command and mode register settings (MRSs) conforming to Joint Electron Device Engineering Council (JEDEC) standards, or can set a DRAM interface protocol so as to use company-specific functions, such as low voltage, high speed and reliability, and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 1800 can communicate with the DRAMs 1500a through an interface conforming to JEDEC standards, such as low power double data rate 4 (LPDDR4) and LPDDR5, and the accelerator block or accelerator chip 1820 can set a new DRAM interface protocol to control the DRAMs 1500b (having higher bandwidth than the DRAMs 1500a) for the accelerator.

[0121] In Figure 12 In the above-described embodiments, only the DRAMs 1500a and 1500b are illustrated. However, the inventive concept is not limited thereto, and any memory, such as a phase change memory (PRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), or a hybrid RAM, can be used when the AP 1800 or the accelerator chip 1820 satisfies bandwidth, response speed, and voltage conditions. The DRAMs 1500a and 1500b can have lower latency and bandwidth compared to the I / O devices 1700a and 1700b or the flash memory devices 1600a and 1600b. The DRAMs 1500a and 1500b can be initialized when the system 1000 is powered on. Operating system and application data can be loaded from outside of the system 1000, and the DRAMs 1500a and 1500b can be used as a temporary storage place for the operating system and application data, or can be used as an execution space for various software codes.

[0122] In the DRAMs 1500a and 1500b, add / subtract / multiply / divide operations, vector operations, address operations, or fast Fourier transform (FFT) operations can be performed. In addition, in the DRAMs 1500a and 1500b, functions for inference can be performed. In some example embodiments, inference can be performed using an artificial neural network in a deep learning algorithm. The deep learning algorithm can include a training operation of learning a model through various data, and an inference operation of recognizing data using the learned model. As an example, an image captured by a user through the camera 1100 can be signal-processed and stored in the DRAM 1500b, and the accelerator block or accelerator chip 1820 can perform an AI data operation of recognizing data using the data stored in the DRAM 1500b and the functions for inference.

[0123] The system 1000 can include a plurality of memory devices or flash memory devices 1600a and 1600b having a capacity greater than the capacity of the DRAMs 1500a and 1500b. The accelerator block or accelerator chip 1820 can use the flash memory devices 1600a and 1600b to perform training operations and AI data operations. The flash memory devices 1600a and 1600b can include memory controllers 1610a and 1610b and flash memories 1620a and 1620b. In an example embodiment, the flash memory devices 1600a and 1600b can efficiently perform training operations and inferencing AI data operations performed by the AP 1800 and / or the accelerator chip 1820 by using computing devices disposed in the memory controllers 1610a and 1610b. The flash memory devices 1600a and 1600b can store pictures taken by the camera 1100 or can store data transmitted through a data network. For example, the flash memory devices 1600a and 1600b can store augmented reality (AR) / virtual reality (VR) content as well as high definition (HD) or ultra-high definition (UHD) content.

[0124] The system 1000 can transmit or receive CML level signals for high speed operations between components. The camera 1100, the display 1200, the audio processor 1300, the modem 1400, the DRAMs 1500a and 1500b, the flash memory devices 1600a and 1600b, the I / O devices 1700a and 1700b, and / or the AP 1800 in the system 1000 can include one or more of the receiver circuits 200a to 200d described with reference to Figures 2 to 11 one or more of the receiver circuits 200a to 200d described.

[0125] While the present inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. A receiver, comprising: A first circuit is configured to receive an input signal, amplify the voltage difference between the voltage level of the input signal and the level of a reference voltage to generate a first output signal and a second output signal, and output an internal signal based on the voltage difference between the first output signal and the second output signal, the internal signal being a digital signal corresponding to a bit of the input signal. The second circuit is configured to receive the input signal, amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage to generate a third output signal and a fourth output signal, generate the average voltage level of the third output signal through a first switching element in response to a control signal to output the average voltage level of the third output signal as a first feedback signal, and generate the average voltage level of the fourth output signal through a second switching element in response to the control signal to output the average voltage level of the fourth output signal as a second feedback signal; as well as The control circuit is configured to output a pulse-type control signal whenever the logic level of the internal signal changes, wherein the first switching element and the second switching element are selectively turned on or off according to the logic pulse level of the control signal.

2. The receiver according to claim 1, wherein, The first circuit includes: A first amplifier circuit is configured to amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage, so as to output the first output signal to a first node line and output the second output signal to a second node line; A second amplifier circuit is configured to amplify the voltage difference between the first output signal and the second output signal to output a fifth output signal and a sixth output signal. The second amplifier circuit is connected to the first node line and the second node line. The level conversion circuit is configured to amplify the first swing width of the fifth output signal and the sixth output signal to a second swing width greater than the first swing width, and generate the internal signal.

3. The receiver according to claim 1, wherein, The second circuit includes: A first equalizer circuit is configured to adjust the voltage level of the first output signal based on the voltage level of the first feedback signal, and to adjust the voltage level of the second output signal based on the voltage level of the second feedback signal; and The second equalizer circuit is configured to amplify the high-frequency components of the first output signal and the second output signal. The first equalizer circuit includes: An amplifier circuit is configured to receive the input signal and amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage, so as to output the third output signal to the third node line and the fourth output signal to the fourth node line; A first low-pass filter is configured to generate the average voltage level of the third output signal and output the average voltage level of the third output signal as the first feedback signal. The second low-pass filter is configured to generate the average voltage level of the fourth output signal and output the average voltage level of the fourth output signal as the second feedback signal; The first switching element is configured to, in response to the control signal, transmit the third output signal of the third node line to the first low-pass filter or block the third output signal of the third node line; and The second switching element is configured to transmit the fourth output signal of the fourth node line to the second low-pass filter or block the fourth output signal of the fourth node line in response to the control signal.

4. The receiver according to claim 1, wherein, The control circuit includes: A first inverter and a second inverter are connected in series to receive the internal signal; An XOR gate receives the internal signal and the outputs of the first inverter and the second inverter connected in series, and outputs the control signal; and The third inverter receives the output of the XOR gate and outputs the inverted signal of the control signal.

5. The receiver according to claim 4, wherein, The first switching element and the second switching element include a transmission gate, which is turned on or off in response to the control signal and the inverted signal of the control signal.

6. The receiver according to claim 1, wherein, The control circuit is also configured to generate a control signal with a logic level that connects the first switching element and the second switching element from the initial state of the receiver until the output of a control signal with the logic pulse level.

7. The receiver according to claim 6, wherein, The control circuit includes: A first inverter and a second inverter are connected in series to receive the internal signal; An XOR gate receives the internal signal and the outputs of the first inverter and the second inverter connected in series. A trigger with a data input connected to a ground voltage line and a clock input connected to an internal signal line; An OR gate that receives the output of the XOR gate and the output of the flip-flop, and outputs the control signal; and The third inverter receives the output of the OR gate and outputs the inverted signal of the control signal.

8. The receiver according to claim 7, wherein, The first switching element and the second switching element include a transmission gate, which is turned on or off in response to the control signal and the inverted signal of the control signal.

9. A receiver, comprising: A first circuit is configured to receive an input signal, amplify the voltage difference between the voltage level of the input signal and the level of a reference voltage to generate a first output signal and a second output signal, and output an internal signal based on the voltage difference between the first output signal and the second output signal, the internal signal being a digital signal corresponding to a bit of the input signal. The second circuit is configured to receive the input signal, amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage to generate a third output signal and a fourth output signal, generate the average voltage level of the third output signal through a first switching element in response to a control signal to output the average voltage level of the third output signal as a first feedback signal, and generate the average voltage level of the fourth output signal through a second switching element in response to the control signal to output the average voltage level of the fourth output signal as a second feedback signal; as well as The control circuit is configured to output a pulse-type control signal or a control signal with a fixed logic level, based on a selection signal, whenever the logic level of the internal signal changes.

10. The receiver according to claim 9, wherein, The control circuit is also configured to control the first switching element and the second switching element. The first switching element and the second switching element are selectively turned on or off according to the logic pulse level of the control signal, and selectively turned on according to the fixed logic level of the control signal.

11. The receiver according to claim 9, wherein, The first circuit includes: A first amplifier circuit is configured to amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage, so as to output the first output signal to a first node line and output the second output signal to a second node line; A second amplifier circuit is configured to amplify the voltage difference between the first output signal and the second output signal to output a fifth output signal and a sixth output signal. The second amplifier circuit is connected to the first node line and the second node line. The level conversion circuit is configured to amplify the first swing width of the fifth output signal and the sixth output signal to a second swing width greater than the first swing width, and generate the internal signal.

12. The receiver according to claim 9, wherein, The second circuit includes: A first equalizer circuit is configured to adjust the voltage level of the first output signal based on the voltage level of the first feedback signal, and to adjust the voltage level of the second output signal based on the voltage level of the second feedback signal; and The second equalizer circuit is configured to amplify the high-frequency components of the first output signal and the second output signal. The first equalizer circuit includes: An amplifier circuit is configured to receive the input signal and amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage, so as to output the third output signal to the third node line and the fourth output signal to the fourth node line; A first low-pass filter is configured to generate the average voltage level of the third output signal and output the average voltage level of the third output signal as the first feedback signal. The second low-pass filter is configured to generate the average voltage level of the fourth output signal and output the average voltage level of the fourth output signal as the second feedback signal; The first switching element is configured to, in response to the control signal, transmit the third output signal of the third node line to the first low-pass filter or block the third output signal of the third node line; and The second switching element is configured to transmit the fourth output signal of the fourth node line to the second low-pass filter or block the fourth output signal of the fourth node line in response to the control signal.

13. The receiver according to claim 9, wherein, The control circuit includes: A first inverter and a second inverter are connected in series to receive the internal signal; An XOR gate receives the internal signal and the outputs of the first inverter and the second inverter connected in series. A multiplexer has a first input connected to a power supply voltage line and a second input connected to a ground voltage line, outputs the power supply voltage level of the first input in response to a first logic level of the selection signal, and outputs the ground voltage level of the second input in response to a second logic level of the selection signal; A trigger having a data input connected to the output line of the multiplexer and a clock input connected to an internal signal line; and The NOR gate receives the output of the XOR gate and the output of the flip-flop, and outputs the control signal.

14. The receiver according to claim 13, wherein, The first switching element and the second switching element include P-type metal-oxide-semiconductor transistors that are turned on or off in response to the control signal.

15. The receiver according to claim 9, wherein, The selection signal is provided from the mode register group of the memory device including the receiver.

16. The receiver according to claim 9, wherein, The selection signal is provided from outside the semiconductor device including the receiver.

17. A receiver for receiving an input signal and outputting an internal signal, said internal signal being a digital signal corresponding to bits of the input signal. The receiver includes: A first amplifier circuit is configured to amplify the voltage difference between the voltage level of the input signal and the level of a reference voltage, so as to output a first output signal to a first node line and output a second output signal to a second node line. A second amplifier circuit is configured to amplify the voltage difference between the first output signal and the second output signal to output a fifth output signal and a sixth output signal. The second amplifier circuit is connected to the first node line and the second node line. A level conversion circuit is configured to amplify the first swing width of the fifth output signal and the sixth output signal to a second swing width greater than the first swing width, and generate the internal signal; A first equalizer circuit is configured to receive the input signal, amplify the voltage difference between the voltage level of the input signal and the level of the reference voltage to generate a third output signal and a fourth output signal, generate the average voltage level of the third output signal through a first switching element in response to a control signal to output the average voltage level of the third output signal as a first feedback signal, and generate the average voltage level of the fourth output signal through a second switching element in response to the control signal to output the average voltage level of the fourth output signal as a second feedback signal, and adjust the voltage difference between the first output signal and the second output signal based on the voltage difference between the first feedback signal and the second feedback signal; as well as The control circuit is configured to output a pulse-type control signal whenever the logic level of the internal signal changes, wherein the first switching element and the second switching element are selectively turned on or off according to the logic pulse level of the control signal.

18. The receiver according to claim 17, wherein, The first amplifier circuit includes: The first transistor has a gate terminal connected to an input signal line and a source terminal connected to a current source connected to a power supply voltage line; The second transistor has a gate terminal connected to a reference voltage line and a source terminal connected to the current source; A first resistor is connected between the drain terminal of the first transistor and the ground voltage line; and A second resistor is connected between the drain terminal of the second transistor and the ground voltage line. The first transistor and the second transistor include PMOS transistors. The first output signal is output from a first connection node between the drain terminal of the second transistor and the second resistor, and the second output signal is output from a second connection node between the drain terminal of the first transistor and the first resistor.

19. The receiver according to claim 17, wherein, The second amplifier circuit includes: The first transistor has a gate terminal connected to a first output signal line and a source terminal connected to a current source connected to a power supply voltage line; The second transistor has a gate terminal connected to a reference voltage line and a source terminal connected to the current source; A first resistor is connected between the drain terminal of the first transistor and the ground voltage line; and A second resistor is connected between the drain terminal of the second transistor and the ground voltage line. Wherein, the first transistor and the second transistor include PMOS transistors, the fifth output signal is output from the connection node between the drain terminal of the second transistor and the second resistor, and the sixth output signal is output from the connection node between the drain terminal of the first transistor and the first resistor.

20. The receiver according to claim 17, wherein, The first equalizer circuit includes: The first transistor has a gate terminal connected to an input signal line, a source terminal connected to a current source connected to a power supply voltage line, and a drain terminal connected to a fourth output signal line. The second transistor has a gate terminal connected to a reference voltage line, a source terminal connected to the current source, and a drain terminal connected to a third output signal line; A first resistor is connected between the drain terminal of the first transistor and the ground voltage line; A second resistor is connected between the drain terminal of the second transistor and the ground voltage line; A first low-pass filter is configured to generate the average voltage level of the third output signal and output the average voltage level of the third output signal as the first feedback signal. The second low-pass filter is configured to generate the average voltage level of the fourth output signal and output the average voltage level of the fourth output signal as the second feedback signal; The first switching element is configured to, in response to the control signal, transmit the third output signal to the first low-pass filter or block the third output signal; and The second switching element is configured to transmit the fourth output signal to the second low-pass filter or block the fourth output signal in response to the control signal.

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