Support flushing victim cache of write-miss entries

Abstract

A cache system comprising a first sub-cache and a second sub-cache (700) in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; line type bits (708) configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller (714) configured to flush the stored write miss data based on the line type bits (708).

Description

Background Art

[0001] In a multi-core coherent system, multiple processors and system components share the same memory resources, such as on-chip and off-chip memory. A memory cache (e.g., a cache) can provide a certain amount of high-speed memory that is operably located near (e.g., close to) the processor (compared to main memory). Generally speaking, the closer the cache is operably located to the processor, the lower the latency, i.e., fewer processor clock cycles are used to fulfill memory requests. Generally speaking, the cache memory closest to the processor includes a Level 1 (L1) cache, which is typically directly on the die with the processor. Many processors also include a larger Level 2 (L2) cache. This L2 cache is typically slower than the L1 cache, but can still be on the die with the processor core. The L2 cache can be a per-processor core cache or shared across multiple cores. Typically, a larger, slower L3 cache, either on the die as a separate component or as another part of a single-chip system (SoC), is also available for the processor core.

[0002] Memory systems, such as caches, may be susceptible to data corruption, for example due to electronic or magnetic interference from cosmic rays, solar particles, or malicious memory accesses. As processors are increasingly used in critical and / or other fault-tolerant systems, such as self-driving vehicles and autonomous systems, techniques for protecting memory systems from data corruption are increasingly being applied to memory systems. One such technique is the use of error correction codes (ECC) to detect and correct memory corruption. Implementing ECC in high-speed cache memories is challenging because ECC may introduce additional timing overhead that needs to be accounted for. For example, a high-speed cache memory system may have a five-stage memory pipeline for determining whether an accessed memory address is in the cache and retrieving the contents of the cache memory. Each stage may take one clock cycle, which at 1 GHz is approximately 1 nanosecond. Error checking the contents of the cache memory may essentially take up one full clock cycle. What is needed is a technique for improving the cache performance of fault-tolerant caches. Summary of the Invention

[0003] This description relates to a cache system. More particularly, and not by way of limitation, aspects of this description relate to a cache system comprising a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to flush stored write miss data based on the line type bit.

[0004] Another aspect of this description relates to a method for caching data, comprising: receiving, by a cache system, a write memory request for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache; storing data associated with the write memory request in the second sub-cache; storing an indication that the stored data corresponds to a write miss in a line type bit of the second sub-cache; and flushing the stored data based on the indication.

[0005] Another aspect of this description relates to a device comprising a first sub-cache and a second sub-cache in parallel with the first sub-cache; wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to flush the stored write miss data based on the line type bit.

[0006] Another aspect of this description relates to a cache system comprising a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; line type bits configured to store an indication that a corresponding line in the set of cache lines is configured to store write miss data; and an eviction controller configured to evict a cache line of the second sub-cache storing write miss data based on an indication that the cache line has been completely written.

[0007] Another aspect of this description relates to a method for caching data, comprising: receiving, by a cache system, a write memory request for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache; storing data associated with the write memory request in the second sub-cache; storing an indication in line type bits of the second sub-cache that the stored data corresponds to a write miss; and evicting a cache line of the second sub-cache storing the write miss based on an indication that the cache line has been completely written.

[0008] Another aspect of this description relates to a device comprising: a processor; a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to store an indication that a corresponding line in the set of cache lines is configured to store write miss data; and an eviction controller configured to evict a cache line of the second sub-cache storing write miss data based on an indication that the cache line is completely written.

[0009] Another aspect of this description relates to a cache system comprising: a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands that are not cached in the first sub-cache, and wherein the second sub-cache comprises: a color tag bit configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag; and an eviction controller configured to evict a cache line of the second sub-cache storing write miss data based on the color tag associated with the cache line.

[0010] Another aspect of this description relates to a method for caching data, comprising: receiving, by a cache system, a write memory command for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and the write memory command not cached in the first sub-cache in parallel with the first sub-cache; storing data associated with the write memory command in the second sub-cache; storing a color tag bit associated with the data in the second sub-cache; and evicting the stored data based on the color tag bit.

[0011] Another aspect of this description relates to a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, and wherein the second sub-cache comprises: a color tag bit configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag; and an eviction controller configured to evict the cache line of the second sub-cache storing write miss data based on the color tag associated with the cache line.

[0012] Another aspect of this description relates to techniques for caching data by a cache system, the cache system comprising: a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: a color tag bit configured to store an indication that a corresponding line of the second sub-cache is associated with a color tag; and an eviction controller configured to evict a cache line of the second sub-cache storing write memory data based on the color tag associated with the line, and wherein the second sub-cache is further configured to: receive a first write memory command to a memory address, the write memory command associated with a first color tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first color tag in the second sub-cache; receive a second write memory command for the cache line, the write memory command associated with a second color tag; merge the second color tag with the first color tag; store the merged color tag; and evict the cache line based on the merged color tag.

[0013] Another aspect of this description relates to a method for caching data, comprising: receiving, by a cache system, a write memory command for a memory address, the write memory command being associated with a first color tag; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache in parallel with the first sub-cache; storing first data associated with the first write memory command in a cache line of the second sub-cache; storing the first color tag in the second sub-cache; receiving a second write memory command for the cache line, the write memory command being associated with a second color tag; merging the second color tag with the first color tag; storing the merged color tag; and evicting the cache line based on the merged color tag.

[0014] Another aspect of this description relates to a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: a color tag bit configured to store an indication that a corresponding line of the second sub-cache is associated with a color tag; and an eviction controller configured to evict a cache line of the second sub-cache storing write memory data based on the color tag associated with the line, and wherein the second sub-cache is further configured to: receive a first write memory command to a memory address, the write memory command associated with a first color tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first color tag in the second sub-cache; receive a second write memory command for the cache line, the write memory command associated with a second color tag; merge the second color tag with the first color tag; store the merged color tag; and evict the cache line based on the merged color tag.

[0015] Another aspect of this description relates to a cache system comprising: a first sub-cache; a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a privilege level, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address, the first write memory command being associated with a first privilege level; store first data associated with the first write memory command in a cache line of the second sub-cache; store the privilege level associated with the cache line in the second sub-cache; receive a second write memory command for the cache line, the second write memory command being associated with a second privilege level; merge the first privilege level with the second privilege level; store the merged privilege level; and output the merged privilege level with the cache line.

[0016] Another aspect of this description relates to a method for caching data, comprising: receiving, by a cache system, a first write memory command for a memory address, the first write memory command being associated with a first privilege level; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache in parallel with the first sub-cache; storing first data associated with the first write memory command in a cache line of the second sub-cache; storing the first privilege level in the second sub-cache; receiving a second write memory command for the cache line, the second write memory command being associated with a second privilege level; merging the first privilege level with the second privilege level; storing the merged privilege level; and outputting the merged privilege level with the cache line.

[0017] Another aspect of this description relates to a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a privilege level, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address, the first write memory command being associated with a first privilege level; store first data associated with the first write memory command in a cache line of the second sub-cache; store the privilege level associated with the cache line in the second sub-cache; receive a second write memory command for the cache line, the second write memory command being associated with a second privilege level; merge the first privilege level with the second privilege level; store the merged privilege level; and output the merged privilege level with the cache line.

[0018] Another aspect of this description relates to a cache system comprising a first sub-cache and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache comprises a line type bit configured to store an indication that a corresponding line of the second sub-cache is configured to store write miss data.

[0019] Another aspect of this description relates to a method for caching data, comprising: receiving, by a cache system, a write memory request for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in a second sub-cache, the second sub-cache being coupled in parallel with the first sub-cache; storing data associated with the write memory request in the second sub-cache; and storing an indication that the stored data corresponds to a write miss in a line type bit of the second sub-cache.

[0020] Another aspect of this description relates to a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache comprises a line type bit configured to store an indication that a corresponding line of the second sub-cache is configured to store write miss data.

[0021] Another aspect of this description relates to a cache system comprising: a first sub-cache; a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache; and a cache controller configured to: receive two or more cache commands; determine that a conflict exists between the two or more received cache commands; determine a conflict resolution between the two or more received cache commands; and send the two or more cache commands to the first sub-cache and the second sub-cache.

[0022] Another aspect of this description relates to a method for caching data, comprising: receiving two or more cache commands; determining that a conflict exists between the two or more cache commands; determining a conflict resolution between the received two or more cache commands; and sending the two or more cache commands to a first sub-cache and a second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache in parallel with the first sub-cache.

[0023] Another aspect of this description relates to a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache; and a cache controller configured to: receive two or more cache commands; determine that a conflict exists between the two or more received cache commands; determine a conflict resolution between the two or more received cache commands; and send the two or more cache commands to the first sub-cache and the second sub-cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0025] Figure 1 It is a block diagram of a computer system.

[0026] Figure 2 is a block diagram illustrating a simplified cache memory pipeline for processing read requests.

[0027] Figure 3 is a block diagram of a cache memory pipeline with a store queue according to aspects described herein.

[0028] Figure 4 is a block diagram illustrating a cache architecture including a victim cache.

[0029] Figure 5 is a block diagram illustrating a cache architecture including a parallel victim cache according to aspects described herein.

[0030] Figure 6 is a block diagram illustrating a victim cache memory pipeline according to aspects described herein.

[0031] Figure 7 is a block diagram illustrating a victim cache pipeline including a write miss buffer according to aspects described herein.

[0032] Figure 8 is a block diagram of a MESI RAM according to aspects described herein.

[0033] Figure 9 is an architectural block diagram of a cache system including a write miss buffer according to aspects described herein.

[0034] Figures 10 to 16 is a flow chart illustrating a technique for caching data according to aspects of this description. DETAILED DESCRIPTION

[0035] Figure 1 1 is a block diagram of a computer system 100. Computer system 100 includes a data cache 102, such as a level 1 (L1) data cache. Data cache 102 stores a subset of system data to reduce the time to access (e.g., read and / or write) the cached subset. By efficiently caching the most frequently used data, data cache 102 can significantly improve system performance.

[0036] Data cache 102 may be coupled to one or more processing resources 104 (e.g., processor cores) and extended memory 106. Extended memory 106 includes other levels of the memory hierarchy, such as L2 cache, storage devices, and the like. Data cache 102 may be incorporated into the same die as processing resource 104 (e.g., an on-die cache) or may be on a separate die. In either case, cache 102 is coupled to each processing resource 104 via one or more interfaces for exchanging data between cache 102 and the processing resource. In this example, cache 102 is coupled to each processing resource 104 via a scalar interface and a vector interface. In examples with more than one interface, if one interface is busy, the command may be serviced using another interface. For example, when a scalar read command is received by the cache via the scalar interface, the associated data may be provided to the processing resource 104 via the vector interface based on interface utilization, data size, and / or other considerations. Similarly, cache 102 may also be coupled to extended memory 106 via one or more interfaces. Where there is more than one interface, the interface may be selected based on utilization, data size, and / or other considerations.

[0037] Each interface can have any suitable width. The width of the interfaces can be different from each other, although in many examples, they are integer multiples of the narrowest interface. In one such example, the scalar interface is 64 bits wide, the vector interface is 512 bits wide, and the extended memory interface is 1024 bits wide.

[0038] The interface can be bidirectional or unidirectional. A bidirectional interface can include two independent unidirectional interfaces, allowing data to be transmitted and received simultaneously. In one such example, the vector interface includes two 512-bit unidirectional buses, one for receiving data and operations from processing resource 104 and one for sending data to processing resource 104.

[0039] Data cache 102 may include several pipelines for processing operations received via these interfaces. Figure 2is a block diagram illustrating a simplified cache memory pipeline 200 for processing read requests. As shown in cache memory pipeline 200, processor 202 sends a memory request to cache memory 204. Although cache memory 204 is described in the context of an L1 cache, the concepts described herein are applicable to any type of cache memory. In certain cases, the memory request may be sent through a cache or memory controller, not shown in the figure. In this example, the cache memory pipeline includes five stages, E1, E2, E3, E4, and E5. Each cache memory pipeline stage may be allocated a specific number of clock cycles to complete, and in some examples, each stage is allocated one clock cycle, so that cached data can be returned to processor 202 after the E5 memory pipeline stage in five clock cycles. In the E1 memory pipeline stage, the memory request is received by cache memory 204. The memory request includes the memory address from which data is to be retrieved. In the E2 pipeline stage, tag random access memory (RAM) 206 is read to determine which memory addresses are currently stored in cache memory. Tag RAM 206 stores a table that records which entries in memory 208 correspond to which memory addresses in extended memory. Tag RAM may be a group or portion of memory used to hold a table of memory addresses. In certain cases, the cache may be an N-way associative cache, where each cache group may hold N rows of memory addresses. As N increases, the number of addresses searched also increases, which in turn increases the amount of time required to determine whether the requested memory address is in the tag RAM. In the E3 memory pipeline stage, the received memory address is compared to the stored address read from the tag RAM to determine whether there is a cache hit or miss. A cache hit occurs when the data associated with the requested memory address is stored in the cache, and a cache miss occurs when the data associated with the requested memory address is not stored in the cache. In the E4 memory pipeline stage, the portion of memory 208 associated with the requested memory address is read, and at the E5 memory pipeline stage, the requested memory address is provided to the processor 202. Memory 208 can be any type of memory suitable for cache memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), registers, etc. The pipeline stages illustrate how the memory pipeline can be configured and, therefore, omit certain sub-steps and features. In certain embodiments, the stages in which specific activities, such as memory accesses, are performed can be different.

[0040] Figure 33 is a block diagram illustrating a cache pipeline 300 that supports read-modify-write with an error correction code store queue architecture according to aspects of this description. Pipeline 300 includes a read path (having a read path latch 302, a tag RAM 306, a memory 308, etc.) and a write path (a write path latch 304, a store queue 314, etc.).

[0041] Regarding the read path, pipeline 300 includes tag RAM 306 and memory 308 (e.g., DRAM or other suitable memory). The cache can have any degree of associativity, and in the example, the cache is a direct-mapped cache such that each extended memory address corresponds to exactly one entry in cache memory 308.

[0042] In certain cases, the cache pipeline 300 may include support for ECC, and the memory 308 may be coupled to error detection and correction circuitry 310. In the ECC example, the memory 308 stores data in blocks and a set of ECC syndrome bits corresponding to the blocks. When a read operation is received, the memory 308 may provide the stored data block and the corresponding ECC syndrome bits to the error detection and correction circuitry 310. The error detection and correction circuitry 310 may regenerate the ECC syndrome bits based on the data block as read from the memory 208 and compare the regenerated ECC syndrome bits with the previously stored ECC syndrome bits. Any discrepancy may indicate that the data block has been read incorrectly, and the ECC syndrome bits may be used to correct errors in the data block. The ability to detect and correct errors makes caches well-suited for mission-critical applications.

[0043] An arbitration unit 312 may be coupled to the memory 308 to arbitrate between conflicting accesses to the memory 308. When multiple operations attempt to access the memory 308 in the same cycle, the arbitration unit 312 may select which operation(s) are granted access to the memory 308 based on a priority scheme. Many different priority schemes may be used. As an example of a priority scheme, arbitration prioritizes read operations over write operations because write data in the pipeline 300 may be available for use by subsequent operations even before the write data is written to the memory 308, for example, via the data forwarding multiplexer 318 of the storage queue 314, as will be described in more detail below. Thus, there is minimal performance impact when allowing write data to wait in the pipeline 300. However, as the pipeline 300 fills with write data that has not yet been written back, the priority of the write operation may increase until it takes precedence over the completed read operation.

[0044] The read path may extend in parallel with the store queue 314. Because a read operation may refer to data from a write operation that may not have yet completed, the pipeline 300 may include write forwarding functionality that allows the read path to obtain data from the store queue 314 that has not yet been written back to the memory 308. In an example, the pipeline 300 includes a pending store address table 316 that records the addresses of operations at each stage of the store queue 314; a data forwarding multiplexer 318 that selects data from one stage of the store queue 314 for forwarding; and a store queue hit multiplexer 320 that selects between the output of the memory 308 (via the error detection and correction circuit 310) and the forwarded store queue 314 data from the data forwarding multiplexer 318.

[0045] An example flow of a read operation through pipeline 300 will now be described. In the first cycle, indicated by stage E1, the cache retrieves the record associated with the address of the read operation from tag RAM 306 to determine whether the data is stored in cached memory 308. In a direct-mapped example, the cache does not need to wait for a tag RAM comparison before requesting data from memory 308, and therefore, the tag RAM comparison between the address of the read operation and the record of the cached address does not need to extend to the second (E2) or third (E3) cycles.

[0046] In the second cycle, in stage E2, the cache may request data and ECC syndrome bits from memory 308 if granted by arbitration unit 312. In this cycle, the cache may also determine whether newer data is available in store queue 314 by comparing the read address to pending store address table 316. If so, data forwarding multiplexer 318 is set to forward the appropriate data from store queue 314.

[0047] Data and ECC syndrome bits may be provided by memory 308 in the third cycle in stage E3. However, this data may or may not correspond to the memory address specified by the read operation because the cache may allocate multiple extended memory addresses to the same entry in cached memory 308. Therefore, in the third cycle, the cache determines whether the provided data and ECC from memory 308 correspond to the memory address based on a comparison of the tag RAM record in the read operation (e.g., a cache hit). In the event of a cache hit, the data and ECC bits are received by error detection and correction circuitry 310, which corrects any errors in the data in the fourth cycle in stage E4.

[0048] As described above, newer data that has not yet been written to memory 308 may be present in store queue 314 and may be forwarded from store queue 314 by data forwarding multiplexer 318. If so, store queue hit multiplexer 320 selects the forwarded data instead of the corrected data from memory 308.

[0049] Corrected data from memory 308 or forwarded data from store queue 314 is provided to the requesting processor in the fifth cycle in stage E5. In this way, the example cache can provide data to the processor with full ECC checking and correction in the case of a cache hit in approximately 5 cycles.

[0050] In the event that the data and ECC bits are not present in memory 308 (e.g., a cache miss), pipeline 300 may be stalled until the data can be retrieved from expansion memory, at which point the data may be written to memory 308 and tag RAM 306 may be updated so that subsequent reads of the data hit in cache.

[0051] A cache may also support several operations that read data from the cache and make changes to the data before rewriting it. For example, a cache may support a read-modify-write (RMW) operation. A RMW operation reads existing data, modifies at least a portion of the data, and rewrites that portion of the data. In an ECC embodiment, an RMW operation may be performed when writing less than a full group width. Since the write is not to the full group width, performing an ECC operation on only a portion of the written data will result in an incorrect ECC syndrome. Therefore, because the portion of the data in the group that will not be rewritten still contributes to the ECC syndrome bits, the read functionality of the RMW is used.

[0052] RMW operations can be divided into write operations and read operations, and pipeline 300 can be structured so that read operations in the read path are synchronized with write operations in store queue 314. The read and write operations remain synchronized until read-modify-write merge circuit 322 overwrites at least a portion of the read data with the write data to generate merged data. The merged data is provided to ECC generation circuit 324, which generates new ECC syndrome bits for the merged data. Then, the merged data and the ECC syndrome bits can be provided to arbitration unit 312 for storage in memory 308.

[0053] An example flow of an RMW operation through pipeline 300 will now be described. The read portion of the operation proceeds essentially as described above in stages E1 through E4, with the cache comparing the address of the read operation to the record in tag RAM 306 and requesting data and ECC syndrome bits from memory 308 and / or store queue 314. Because the RMW operation will modify the data, in the example of tracking the MESI (Modified, Exclusive, Shared, and Invalid) state of entries in memory 308, a cache hit that is not in the Modified or Exclusive state may be considered a cache miss. When the data is obtained in the correct state and any errors are corrected, it is provided to read-modify-write merging circuitry 322 in cycle E4 (or later in the case of a cache miss). In this same cycle, read-modify-write merging circuitry 322 may overwrite at least a portion of the corrected data with the write data to produce merged data. ECC generation circuitry 324 generates new ECC syndrome bits for the merged data in stage E5 (or later in the event of a cache miss). The merged data and ECC syndrome bits are provided to arbitration unit 312 for writing to cache memory 308.

[0054] In some examples, sequential RMW operations involving the same address are received. Instead of waiting for the merged data from the previous RMW operation to be written to the memory 308, the storage queue 314 may include an address comparator 326 for write forwarding, which can feed the merged data back to the previous stage of the storage queue 314 for use by the next RMW operation. This may be called "piggybacking." The data can be fed back before or after the ECC generation circuit 324. Because the feedback effectively merges the RMW operations, the final RMW operation has a complete set of data and ECC syndrome bits. Therefore, the RMW operation that precedes it in time can be canceled before it is written back to the memory 308. This can avoid pausing other operations due to writing outdated data.

[0055] In certain cases, memory 308 may represent the entire data cache. By way of example only, in this embodiment, the data cache (which may be an L1 data cache) is associated with a single store queue structure 314. As an example, the data cache may include 256 lines, with each line having 1024 bits (1 Kb) per line.

[0056] In other examples, the cache may be divided into multiple independently addressable groups, and each individual group may have its own corresponding store queue structure 314. For example, consider an embodiment in which the data cache described above has 256 lines, each with a line width of 1024 bits, but is divided into 16 groups, with each line in a given group having 64 bits. In this embodiment, there would be 16 store queues, one for each group of the data cache. Thus, read and write operations can be sent to the groups in parallel, and each group arbitrates its own process in response to read and / or write operations. By allowing each group in the multiple-group cache to operate independently, the cache operates more efficiently because the entire cache line is not locked when a request is received. Rather, only the portion of the cache line assigned to the group receiving the request is locked. Of course, the cache size described above is merely an example, and the description is not limited to any specific cache line width, number of groups, or rows.

[0057] The above example also facilitates writing and / or reading vector data. For example, the vector data may be 512 bits wide. For a multi-set cache, a write request containing vector data that is a cache hit may be processed as eight parallel writes to eight sets (e.g., 8 x 64 bits = 512 bits). Similarly, a read request to this multi-set cache may be performed as eight parallel reads from the eight sets.

[0058] Another feature that may be present in contemplated embodiments of the cache system is support for in-transit forwarding and invalidation. For example, assume in one example that the cache is a two-way set associative cache. In a two-way set associative implementation, each cache line within the cache can be mapped to two different addresses in higher-level memory, such as, for example, an L2 cache or main system memory.

[0059] Consider the following case where a given cache line, referred to in this example as "line 1," is a cache line in a two-way set associative cache and maps to two different addresses in memory, referred to as "address A" and "address B." Now, assume that the cache receives a first request that is a partial write (e.g., a write to less than the entire cache line) and follows a read request like this:

[0060] Write(Address A):Data 1 / / Write Data 1 to the cache line corresponding to address A

[0061] Read(Address B) / / Read the data contained in the cache line corresponding to / / Address B

[0062] In this example, let's assume the write request is a hit, which means the cache line corresponding to address A (in this example we'll assume it's row 1) is in the cache. In response, the cache system will begin the process of writing data 1 to row 1.

[0063] Next, let's assume the read request is a miss. In other words, while row 1 could be mapped to either address A or address B in this two-way set-associative cache, in this example, it is currently mapped to address A. A miss therefore occurs because address B is not found in tag RAM 306. In response to a miss, the cache system will service the miss by retrieving data from a higher-level memory, such as the L2 cache, and when the data, referred to as "data 2" in this example, is returned, the data currently in row 1 will be evicted in favor of data 2. This can occur before the previous write has completed. In this case, there is no need to complete the write operation because row 1 would have been evicted anyway. Therefore, the write can fail before it completes (referred to as "in transit").

[0064] Atomic operations such as atomic compare and swap are further examples of memory operations that include reads. An atomic compare and swap operation can provide an address, a key value, and a set of new data to be written. The current data at the address is compared to the key, and if they match, the current data at the address is overwritten with the new data. Therefore, in some examples, pipeline 300 includes atomic compare and swap circuitry 328 to perform a comparison and forward the new data for writing if the current data matches the key value. Atomic compare and swap circuitry 328 can be coupled in parallel with read-modify-write merge circuitry 322, and function multiplexer 330 can be used to determine which output is provided to ECC generation circuitry 324.

[0065] An example flow of atomic and swap operations through pipeline 300 will now be described. The read portion of the operation proceeds essentially as described above in stages E1 through E4, with the cache comparing the address of the read operation to the record in tag RAM 306 and the cache requesting data and ECC syndrome bits from memory 308 and / or store queue 314. Because the atomic compare and swap operation can modify data, in the example of tracking the MESI state of entries in memory 308, a cache hit that is not in the modified or exclusive state can be considered a cache miss. When the data is obtained in the correct state, it is provided to atomic compare and swap circuitry 328 in stage E4 (or later in the case of a cache miss). During these cycles, the new data and key can be stored in write path latch 304. During stage E4, atomic compare and swap circuitry 328 can receive the corrected read data, the key, and the new data. If the corrected read data matches the key, the atomic compare and swap circuit 328 provides the new data to the ECC generation circuit 324. If the read data matches the key, the atomic compare and swap circuit 328 may also change the state of the new data to modified. The ECC generation circuit 324 generates new ECC syndrome bits for the new data in stage E5 (or later in the case of a cache miss). The new data and ECC syndrome bits are provided to the arbitration unit 312 for writing to the cache memory 308.

[0066] When a sequential atomic compare and swap operation is received, pipeline 300 may also perform write forwarding using address comparator 326, similar to as described in the context of RMW operations.

[0067] Further examples of memory operations that read existing data include histogram operations. Histogram operations can specify values to be added to or subtracted from existing data. To support histogram operations, pipeline 300 can include an arithmetic unit 332 coupled in parallel with the read-modify-write merge circuit 322 and / or the atomic compare and swap circuit 328. Arithmetic unit 332 can support operands of any size, and in one such example, arithmetic unit 332 supports addition and subtraction of 16-bit values from 64-bit groups. Multiplexer 330 can be used to select between arithmetic unit 332, read-modify-write merge circuit 322, and atomic compare and swap circuit 328.

[0068] An example flow of a histogram operation through pipeline 300 will now be described. The read portion of the operation proceeds essentially as described above in stages E1 through E4, with the cache comparing the address of the read operation to the record in tag RAM 306 and requesting data and ECC syndrome bits from memory 308 and / or store queue 314. Because the histogram operation modifies the data, in the example of tracking the MESI state of entries in memory 308, a cache hit that is not in the Modified or Exclusive state may be considered a cache miss. When the data is obtained in the correct state, it is provided to arithmetic unit 332 in stage E4 (or later in the case of a cache miss). During these cycles, the value to be added to the corrected data may be stored in write path latch 304. During stage E4, arithmetic unit 332 may receive the corrected read data and the value to be added to or subtracted from the read data. Arithmetic unit 332 performs the specified addition or subtraction and provides the new data to ECC generation circuit 324. ECC generation circuit 324 generates new ECC syndrome bits for the new data in stage E5 (or later in the case of a cache miss). The new data and ECC syndrome bits are provided to arbitration unit 312 for writing to cache memory 308.

[0069] When a sequential histogram operation is received, pipeline 300 may also perform write forwarding using address comparator 326 similar to that described in the context of RMW operations.

[0070] Although Figure 3 A single pipeline 300 is illustrated with a single instance of a store queue 314, latches 302 and 304, error detection and correction circuitry 310, and the like. However, as described above, memory 308 can be arranged to support more than one independent copy of pipeline 300. Thus, pipeline 300 can be replicated multiple times. In one such example, memory 308 entries are 1024-bit blocks based on the width of the extended memory interface, and memory 308 is arranged into 16 parallel groups, where each 1024-bit block in each of the 16 groups contains 64 bits. In this particular example, each of the 16 groups has its own independent pipeline 300. Read or write operations from the processor are divided into several group-level operations, and each is provided to its corresponding pipeline 300 so that they can be processed simultaneously. For example, a 512-bit vector read operation can be divided into eight 64-bit read operations provided to eight independent pipelines 300 for parallel processing. At the same time, another operation may be received via the scalar or vector interface of another processor and divided into operations that are provided to the remaining pipelines 300. Thus, the data cache can service multiple independent operations simultaneously, with each operation being allocated a subset of the pipelines 300.

[0071] In certain cases, the cache pipeline 300 may be coupled to a victim cache. The victim cache may help improve cache miss rates, such as those due to conflict misses. In certain cases, the victim cache may have an impact on cache performance similar to increasing the N-way associativity (e.g., a cache associativity program). This benefit is more pronounced in cases where a victim cache is added to a direct-mapped cache, as direct-mapped caches typically have the highest conflict miss rates. The addition of a victim cache may help improve the overall cache hit rate.

[0072] Figure 4 is a block diagram illustrating a cache architecture 400 including a victim cache. Here, the cache architecture 400 includes a primary cache 404 coupled to a victim cache 402, where the victim cache 402 resides behind the primary cache 404. When a line of data is evicted from the primary cache 404, instead of moving the line of data to the next level of cache (e.g., L2), the line of data is moved to the victim cache 402 and held there until there is a reason to evict it, such as due to capacity or other reasons. In this cache architecture 400, in the event of a cache miss from the primary cache 404, the victim cache 402 can service the miss and return the line to the processor 414, thereby reducing the overall latency experienced on a read miss.

[0073] As an example, assume that the processor 414 attempts to access address A in both the primary cache 404 and the victim cache 402, resulting in a cache miss. The primary cache 404 may then evict address B from the primary cache 404 and create a victim cache (address B) line in the victim cache 402. The read miss for address B then goes 406 to higher-level memory 412, such as an L2 cache, another cache, and / or other memory, to be serviced. Once address A is accessed, the contents of address A may be transferred back 410 and stored in the primary cache 404.

[0074] If a subsequent access attempt is made to address B, the primary cache 404 is checked to see if address B is cached, resulting in a cache miss. Next, the victim cache 402 is checked 408, which returns a hit if address B is stored in the victim cache 402 after being evicted from the primary cache 404. Address B can then be restored 410 to the primary cache 404 and returned to the processor 414 as a result. The read latency in this system, while faster than if the address had to be fetched from higher-level memory 414 (e.g., L2 cache, main memory, etc.), is still greater than the latency when there is a cache hit in the primary cache 404.

[0075] To help address delays experienced in cache architectures that place a victim cache after a primary cache, in certain cases the victim cache may be placed in parallel with the primary cache. Figure 5 is a block diagram illustrating a cache architecture 500 including a parallel victim cache according to aspects of this description. Cache architecture 500 can be viewed as having multiple parallel sub-caches. Each of primary cache 504 and victim cache 502 has its own independent associativity, and the overall cache system 500 can have the appearance of a mixed-way cache system. In certain cases, either primary cache 504 or victim cache 502 can be n-way associative, while the other can be fully associative. In this example, primary cache 504 can be a direct-mapped (1-way associative) cache, and victim cache 502 can be fully associative.

[0076] In this example, if processor 514 issues a read to address A that misses in primary cache 504, the miss request goes to higher-level cache 512 for servicing, and the victim line (here, address B) is moved to victim cache 502. Next, let's assume processor 514 wants to read address B. In this example, the read address is checked in parallel against primary cache 504 and victim cache 502. This results in a read miss in primary cache 504, but a hit in victim cache 502. The read result for address B can then be transferred directly from victim cache 502 back to processor 514. Because both caches are checked in parallel, the read latency remains the same, as if the read request were a hit in primary cache 504. The overall effect of having a victim cache in parallel with the primary cache is that in the event that a subsequent CPU access hits in the victim cache, we get the benefit of reduced cache miss rate while also not affecting latency.

[0077] Figure 66 is a block diagram illustrating a victim cache memory pipeline 600 according to aspects of this description. As described above, the victim cache can be a fully associative cache, meaning that there are no mappings between addresses and cache lines. Specifically, any address can be stored in any cache line of the victim cache. Therefore, for an address received at block 602 in the E1 stage, the received address is checked against the address stored in each location in the victim cache tag RAM 604 in the E2 stage. In certain cases, these locations in the victim cache tag RAM 604 correspond to lines of the victim cache 606. For example, if address A is received at block 602, address A is compared to the addresses in the victim cache tag RAM 604 to see if there is a match. If, for example, location 5 of the victim cache tag RAM 604 corresponds to address A, the data corresponding to address A is stored in address 5 of the victim cache 606. This data is ultimately transferred back to the processor at block 608.

[0078] In cases where the victim cache operates in parallel with the primary cache, it may be desirable for the victim cache to support certain features of the primary cache, such as ECC and RMW operations. In certain cases, the victim cache may also include a store queue 610 structure to facilitate parallel operation similar to that of the primary cache. Figure 3 The described approach to store queue 314 provides support for RMW and ECC operations.

[0079] In certain cases, a cache may include a write miss buffer. A write miss may occur when a memory write is issued to the cache against a memory address that is not in the cache. Memory writes may be atomic operations, and the processor issuing the memory write may be paused until a memory write completion message is returned to the processor. Instead of pausing the processor until the write to a higher-level memory is complete, the cache may store the memory write in a write miss buffer and return an indication that the memory write is complete. The write miss buffer buffers this information and then outputs (e.g., flushes) the memory write to the target memory address. Once the memory write output to the target memory address is complete, the memory write is removed from the write miss buffer. To output the memory write, the write miss buffer may include three pieces of information for each memory write: the memory address to be written, the corresponding data, and a byte enable (byteization) mask for the memory write. Typically, the byte enable defines a logic or mask of the portion of the memory row to be written to. Typically, the write miss buffer is implemented as a first-in-first-out (FIFO) buffer using dedicated buffer circuitry. However, FIFO write miss buffers are frequently configured to flush to higher level memory more or less continuously and do not support features such as write merging.In certain cases, write miss buffers can be allocated to the cache system using a victim cache.

[0080] Figure 7 is a block diagram illustrating a victim cache pipeline 700 including a write-miss buffer according to aspects of this description. As described above, the write-miss buffer may store the memory address for a write, the data to be written, and byte-wise logic. In this example victim cache pipeline 700, the memory address of a write-miss buffer entry may be stored in the victim cache tag RAM 704, and the corresponding data may be stored in the victim cache RAM 706. A byte-enable memory 702 may also be added to the victim cache to store the byte-wise logic associated with the write-miss buffer line. In certain cases, the MESI RAM 732 may be modified to include an additional bit indicating a line type 708 associated with an entry in the victim cache RAM 706. The line type 708 indicates whether a particular line of the victim cache RAM 706 is a cache line or a write-miss buffer line. In certain cases, the line type 708 may be added to another memory, such as the victim cache tag RAM 704, rather than the MESI RAM 718.

[0081] Moreover, for example, in combination Figure 6The described victim cache system can be configured as a write miss buffer by adding control logic to the read and write miss state machines to address the allocation of write miss entries within the victim cache, logic to support handling of various address hazards in the case of reads to the same row as a write miss entry within the victim cache, and logic to support resolution of same-address loads / stores in the victim cache's data path. A store queue 710 structure can also be provided to implement support for RMW and ECC support for write misses. In certain cases, the store queue 710 can be used to implement support for RMW and ECC support for write miss operations as well as cache operations.

[0082] As an example of performing a write-miss buffer operation in a cache, when a write is received at block 712, the address of the write is checked against the memory address stored in each location in the victim cache tag RAM 704. A write miss occurs when the address of the write is not found in the victim cache tag RAM 704. When operating as a write-miss cache, a determination is made as to the location in the victim cache where the write miss is stored. In certain cases, this determination may be made based on an entry in the victim cache tag RAM 704. If there is an empty location in the victim cache tag RAM 704, the address of the write miss is stored in the empty location in the victim cache tag RAM 704. If there is no empty location, the line may be evicted based on an eviction scheme to allocate write-miss buffer space. In other cases, the line may have previously been used as a write-miss buffer or cache line. The line type 708 of the location in the victim cache tag RAM 704 corresponding to the write miss may be updated to indicate that the location is being used as a write-miss buffer. For example, a 0 in line type 708 may indicate that the corresponding line is a cache entry, while a 1 in line type 708 may indicate that the corresponding line is a write-miss buffer entry. In certain cases, line type 708 may be stored in another memory location, such as MESI RAM 732, or in a dedicated memory space, such as a set of registers. The data for the write miss is stored in the line of victim cache RAM 706 corresponding to the used victim cache tag RAM 704 location. Byte enable logic may be stored in the corresponding slot of byte enable memory 702. In certain cases, byte enable memory 702 may include bits indicating which locations of byte enable memory 702 are valid. The line type bit facilitates storing write-miss entries in a line of victim cache RAM 706 without dedicating a portion of victim cache RAM 706 as a write buffer.

[0083] According to aspects of this description, for example, the victim cache eviction logic in the eviction controller 714 can be updated to handle write miss entries stored in the victim cache to prioritize evicting write miss entries in favor of store cache entries. Furthermore, the control logic for the read and write state machines of the victim cache controller 734 can be configured to determine that an incoming read request may hit a cache line of the victim cache that is configured to store write misses. In such a case, the victim cache controller 734 can be configured to treat this read hit like a read miss and evict the stored write miss command to higher-level memory and then send the read miss out to the higher-level memory. Furthermore, cache systems are typically configured to pause on a miss, whereas a write miss buffer typically does not pause the processor when it buffers a write miss. To help resolve this discrepancy, the victim cache controller 734 may be configured to allocate write miss entries to the victim cache without stalling the CPU by speculatively reading incoming write data so that if the data is a write miss then the data can be stored directly into the victim cache without stalling.

[0084] In certain cases, by placing the write miss in the cache system, the write miss can remain cached until it is necessary to evict it to higher-level memory. In certain cases, a write miss stored in the victim cache can remain in the cache system until a defined condition is met, a fence operation is requested, or there is an address / hardware conflict that requires eviction of the particular write miss entry.

[0085] Maintaining the write miss buffer until a barrier operation is explicitly requested can be problematic, for example, if the barrier operation is not raised at the end of the operation, and any write misses stored in the victim cache can be stuck inside the victim cache. Furthermore, barrier operations can present latency issues, as simply flushing (e.g., evicting all) the write miss buffer stores in response to a barrier operation can result in delays, as the cache needs to flush the stored write misses to the appropriate memory and then wait for an acknowledgement to be returned. In certain cases, automatic flushing or clearing of write miss entries stored in the victim cache can be provided. Automatic flushing can be implemented to facilitate clearing write miss entries from the victim cache while reducing potential delays that may be incurred during the clearing process. In certain cases, the eviction controller 714 can monitor activity on the processor interface. If the eviction controller 714 detects idle activity on the processor interface, the eviction controller 714 can proceed to initiate clearing of write miss entries from the victim cache. For example, if the eviction controller 714 detects that the processor has not issued any commands for N clock cycles, the eviction controller 714 may internally initiate an automatic flush process to begin clearing the cached memory within the victim cache. In certain cases, N may be predetermined. In other cases, N may be configurable. In certain cases, the automatic flush process may traverse (e.g., sequentially check) the VTag RAM, looking for write-miss entries and flushing the entries corresponding to the write-miss entries. In other cases, the automatic flush process may include logic that flushes entries based on a FIFO, least recently used (LRU), random, or other basis.

[0086] When automatically flushing a write miss entry, the eviction controller 714 may send an eviction trigger request to the victim cache controller 734 of the selected write buffer cache line. The victim cache controller 734 checks the store queue to see if there are any entries in the store queue corresponding to the write buffer cache line to be flushed. If a corresponding entry exists in the store queue, the victim cache controller 734 may wait for the store queue to complete. Once the store queue is empty, the victim cache controller 734 may evict the selected cache line. The victim cache controller 734 then sets up the creation of store miss packets to be sent to a higher-level cache or other memory. These store miss packets may include the corresponding memory address stored in the victim cache tag RAM 704, the byte enable logic in the byte enable memory 702, and the data in the victim cache RAM 706. The victim cache may then send the store miss packets, for example, to the cache controller of the higher-level cache or other memory. When flushing a write-miss entry, the write-miss packet can be sent out to other memories and the corresponding entries in the victim cache RAM 706, victim cache tag RAM 704, and byte enable memory 702 can be invalidated. The write-miss packet can be temporarily placed in the flush buffer 716 until the write-miss packet is accepted (e.g., acknowledged) by the other memories. Once the write-miss buffer cache line is invalidated, the eviction controller 714 can select the next write-miss buffer cache line to be evicted and proceed to evict the next write-miss buffer cache line. If activity is subsequently detected on the processor interface, this automatic flush operation can be canceled. In this way, the victim cache can take advantage of idle cycles and avoid impacting processor performance when there is activity on the interface by attempting to flush the write-miss buffer entries.

[0087] In certain cases, write misses stored in the victim cache can be evicted based on the state of the write-miss line storing the particular write miss (rather than based on a FIFO, LRU, random, or other scheme based on the order in which the cache lines were allocated). In cases where the cache is configured to merge data in the cache, a cache write from a processor to a memory line does not imply that the processor needs to read from other portions of the memory line. Furthermore, in cases where the processor has written out a large portion of a memory line (e.g., half a memory line or the entire memory line), the processor is less likely to need to access that portion of the memory line again (e.g., to merge additional data into) compared to cases where the processor has written out only a small portion of the memory line. Because the processor is less likely to need to access a given write-miss cache line after writing out half or a full write-miss cache line, this write-miss cache line can be evicted with less potential impact on performance. Thus, once a write-miss cache line is fully or half written and a write has been initiated on the next entry in the victim cache on another write-miss cache line, the full or partially full cache line can be evicted. This helps resolve situations where the processor is issuing a stream of cache write misses that are collectively larger than the victim cache. Furthermore, aggressively evicting full or half-full write-miss cache lines helps avoid performance issues that arise when a large number of write miss entries stored in the victim cache are flushed all at once due to a fence operation at the end of the operation.

[0088] To help support the removal of cache lines that are full or half-full write misses, the byte enable memory 702 may include two status bits: a half-full line status bit 718 and a full line status bit 720. Each line of the byte enable memory 702 corresponds to a cache line in the victim cache RAM 206, and each line of the byte enable memory 702 may include a half-full line status bit 718 and a full line status bit 720. These status bits may be updated during each write cycle, in which bits are written to a cache line configured as a write miss buffer, and the status bits may be calculated based on bits already stored in the corresponding line of the victim cache RAM 706 and bits written to the victim cache RAM 706 during the write cycle. In certain cases, this update may be performed for each cache line of the byte enable memory 702 during each cycle, and the update may be omitted when there is no write cycle. As indicated above, each line of the byte enable memory 702 may include a bit mask indicating which locations (e.g., bytes) of the byte enable memory 702 are valid (e.g., written to). Determining which lines are full or half-full can be performed using an XOR of corresponding portions of the bitmask. Half-full line status bit 718 can be set to the least significant bit or most significant bit when half of a given cache line has been written. Similarly, full line status bit 720 can be set when the entire cache line has been written. The cache lines can then be traversed (e.g., checked sequentially) to determine which addresses are returned with full or half-full cache lines. In certain cases, the address corresponding to a full cache line is selected first, and if no full cache line exists, the address corresponding to a half-full cache line is returned. If multiple cache lines are full (or, if no full cache line exists, half-full), the first cache line found to be full (or half-full) when traversing the cache lines can be selected. If no cache line is full or half-full, the write-miss cache line can be selected based on a FIFO, LRU, or other logic that can be used to determine which cache line to select when multiple lines are available.

[0089] Evicting a write miss entry can operate similarly to an automatic flush, except that the store queue is not checked to see if there are any entries corresponding to the full or partial write miss cache line being evicted, since this operation is initiated by a read or write miss and is performed after the line has been written. Once a full or partial write miss cache line has been selected for eviction, the eviction controller 714 instructs the victim cache controller 734 to evict the selected cache line. The victim cache controller 734 sets up the creation of store miss packets to be sent to a higher-level cache or other memory. These store miss packets may include the corresponding memory address stored in the victim cache tag RAM 704, the byte enable logic in the byte enable memory 702, and the data in the victim cache RAM 706. The store miss packets are sent, for example, to the cache controller of the higher-level cache or other memory and may invalidate the corresponding entries in the victim cache RAM 706, the victim cache tag RAM 704, and the byte enable memory 702. The store miss packet may be temporarily placed in the flush buffer 716 until the store miss packet is accepted (eg, acknowledged) by other memory.

[0090] Once a write-miss cache line has been invalidated, the address of the cache line may be sent to the replacement policy logic 722 during each write cycle. Available cache line addresses may be fed into the mux 724 in the replacement address line 726. The address generation line 728 may contain the address assigned to the received write instruction. If the hit / miss logic 730 determines that the address of the received write instruction is a hit, the address is stored in a line of the victim cache and the data from the write instruction is merged into that line. If the hit / miss logic 730 determines that the address of the received write instruction is a miss, the address from the replacement address line 728 may be used to write the write-miss command to the victim cache / write-miss buffer. If there are no empty cache lines in the victim cache / write-miss buffer to allocate the write miss, an eviction process may be triggered. During the eviction process, the centralized controller may detect that a write miss has been received that needs to be stored in the victim cache. The centralized controller may instruct the victim cache controller 734 to ensure that an available cache line exists. This cache line may be based on the location provided by the replacement address 726 or the address generation 728. If there is already a write miss stored in the identified location, the write miss may be evicted.

[0091] Figure 88 is a block diagram of a MESI RAM 800 according to aspects of this description. MESI RAM 800 may be a memory (e.g., SRAM) or a set of registers (e.g., a register file) for tracking the MESI state of a corresponding cache line. As an example, in certain cases, a victim cache may track the MESI state in MESI state bits 802 in MESI RAM 800 for a cache entry as part of write data. In certain cases, MESI RAM 800 includes a line corresponding to each line of a corresponding cache (here, the victim cache). A primary cache may include a corresponding MESI RAM. In certain cases, a single MESI RAM may be shared by both the primary and victim caches. MESI RAM 800 may have a set of bits for tracking the MESI state of each cache line stored in the victim cache. In certain cases, MESI RAM 800 may be extended with additional bits to track other states of cache lines in the victim cache. MESI RAM 800 may be extended to track additional states by including additional columns for additional states. In this example, the MESI RAM has been extended to include status bits in bit fields to track each cache line's privilege level 804, red tag 806, blue tag 808, whether the line is valid or not 810, and whether the line is written to the miss buffer or a victim cache line 812. It should be noted that while shown as part of the MESI RAM, in other embodiments the status bits may be placed within other memory, such as the tag RAM 704, or in a separate memory altogether. The MESI RAM may be configured to track additional states not shown here.

[0092] In certain cases, it may be useful to flush all write miss entries of a particular type stored in the victim cache. As described below, entries in the write miss buffer may be associated with a "color" label. This color label may be represented by one or more bits, such that when a bit is set for a write miss buffer entry, the color associated with the write miss buffer entry may be "blue," and when the bit is not set or another bit is set, the write miss buffer entry may be "red." Tagging helps allow specific write miss buffer entries to be associated with a particular process running on the processor, while other write miss buffer entries may be associated with another process running on the processor. In certain cases, a processor may wish to flush all write miss buffer entries associated with a particular process (e.g., a selective fence operation), but not flush write miss buffer entries associated with another process.

[0093] To perform a selective fence operation, the processor may assert the clear signal. Along with the asserted clear signal, the processor may provide an indication that a particular tag should be cleared first (red or blue tag). Return to Reference Figure 7 , a flush signal is passed to the eviction controller 714. The eviction controller 714 may check the availability of a higher-level cache or memory to see if it is busy. If the higher-level cache or memory is not available, the eviction controller 714 may pause the processor. If the higher-level cache or memory is available, the eviction controller 714 may send an eviction trigger request indicating a priority tag to the victim cache controller 734. The victim cache controller 734 may then check the store queue to see if there are any outstanding entries in the store queue of any bank of the victim cache RAM 706. The victim cache controller 734 may also instruct the store queue 710 to upgrade its priority to flush the store queue. If, for example, there is data in the store queue that has not yet been stored to the victim cache, the eviction controller 714 may wait for the store queue 710 to complete. Once the store queue 710 is empty, the eviction controller 714 instructs the victim cache controller to evict the selected cache line. The victim cache controller 734 then sets up the creation of a store miss packet to be sent to the higher-level cache or other memory. These store miss packets may include the corresponding memory addresses stored in victim cache tag RAM 704, the byte enable logic in byte enable memory 702, and the data in victim cache RAM 706. The victim cache may then send the store miss packets, for example, to a cache controller of a higher-level cache or other memory. When flushing write miss entries, the write miss packets may be sent out to other memory and may invalidate the corresponding entries in victim cache RAM 706, victim cache tag RAM 704, and byte enable memory 702. The write miss packets may be temporarily placed in flush buffer 716 until the write miss packets are accepted (e.g., acknowledged) by other memory. This flushing continues until the processor stops asserting the flush signal. If the processor stops asserting the flush signal before all write miss buffer entries of the indicated color have been flushed, then flushing of the write miss buffer ceases at any point in the victim cache flushing process when the flush signal stops being asserted. Once all write miss buffer entries for the indicated color tag have been cleared, the idle signal is asserted back to the processor. If the processor continues to assert the clear signal, other write miss buffer entries associated with another color tag may be cleared.

[0094] Placing write misses in the cache system helps provide an opportunity to merge additional write misses into write misses already in the cache system. Since write misses can be held longer in the cache, the cache has the advantage of merging any future write misses into the write misses already in the cache system, thereby reducing the amount of write miss traffic going to higher-level memories. Reducing the number of write misses sent to higher-level memories reduces the pressure on those memories and helps improve overall performance.

[0095] Write merging may occur when the processor issues a second store or write command to a particular address at block 712. In the case where the victim cache is fully associative, the address of the second write may be checked by the hit / miss logic 730 against a set of memory addresses stored in each location in the victim cache tag RAM 704. Replacement policy 722 logic concurrently determines where write transactions within the victim cache may be assigned in the event of a write miss. Typically, when a write miss is stored in the victim cache, the write miss is assigned an entire cache line, even if the data in the write miss does not require an entire cache line. Thus, a set of memory addresses may be associated with each write miss stored in the victim cache (including the memory address in the write miss) along with a set of memory addresses that precede, follow, or both precede and follow the memory address in the write miss. If the address of the second write is determined to be within the set of memory addresses associated with the write miss stored in the victim cache, a cache hit is detected and the hit / miss logic returns the location in the victim cache where the write miss is currently stored. In the E3 pipe stage, the color type and privilege level associated with the second write are merged with the currently stored color type and privilege level, for example, by the victim cache controller 734, and the MESI RAM 732 is updated. In certain cases, merging privilege levels may be performed with reference to the privilege merge table 736. The data of the second write may also be merged into the corresponding line of the victim cache 706 and the corresponding entry of the byte enable memory 702 updated based on the byte enable logic associated with the second write, for example, by the victim cache controller 734. In certain cases, the store queue 710 may also include write-merging functionality. For example, when back-to-back writes are issued to the same address, the store queue 710 may internally merge them to help minimize the number of writes issued to the victim cache RAM 706.

[0096] In certain cases, write merging can be performed across privilege levels. Merging privilege levels can be performed when performing a write merge. For example, a first write miss stored in a victim cache can be associated with a first privilege level. A second write associated with a second privilege level can be merged with the stored first write miss. In order to perform the merge, the privilege levels should also be merged. In certain cases, privilege levels can be merged by merging the privilege level into a lower privilege level. For example, in an embodiment, a write operation can be associated with two privilege levels (e.g., root / guest user / supervisor). A first write miss can be received at the privilege level of the root user. This first write miss can be written to a write miss buffer in the victim cache. A second write with the privilege level of the guest supervisor can be received, and the second write is directed to an address within the set of addresses associated with the first write miss. When merging the privilege levels of two writes, the lower privilege level can be used, resulting in a merged privilege level of the guest user. In certain cases, merging privilege levels can operate in the same manner when performing a merge for multiple data paths. In certain cases, privilege level merges may be encoded in a privilege merge table 736, indicating how different privilege levels may be merged. In certain cases, the privilege merge table 736 may be predefined. An example of a predefined privilege merge table 736 is shown in Table 1. In certain cases, the privilege merge table 736 is configurable.

[0097] Table 1

[0098]

[0099]

[0100] In certain cases, write merging may be performed for color tags. For example, the first write miss stored in the victim cache may be associated with the first color tag, such as red. Figure 8, the first write miss may be associated with an entry in MESI RAM 800 having a bit set in bitfield red tag 806. A second write associated with a second color tag may be merged with the stored first write miss. To perform the merge, the color tags should also be merged. In certain cases, the color tags can be merged by combining the color tags of the writes. For example, if both writes are tagged red, the merged write remains tagged red. Similarly, if both writes are tagged blue, the merged write will be tagged blue. If one write is tagged red and the other is tagged blue, the merged write is tagged both red and blue. Therefore, if the second write to be merged is associated with a blue tag, the merged write may have a bit set in bitfield red tag 806 and a bit set in bitfield blue tag 808. In certain cases, if a flush operation is then performed, for example, on the blue tag, the merged write will be flushed. Similarly, if a flush operation is performed for the red tag, the merged write will also be flushed since the merged write is tagged both red and blue.

[0101] Figure 9 is an architectural block diagram of a cache system 900 including a write miss buffer according to aspects of this description. As shown, cache 902 can receive cache requests from processor 904 via processor interface 906. In certain cases, cache 902 can be configured to handle scalar or vector data, or both. Cache 902 is logically divided into parallel sub-caches including a primary cache 908 and a victim cache 910. Although a single primary cache 908 and victim cache 910 are shown, certain embodiments may include multiple primary cache 908 and victim cache 910 pairs. In certain cases, there may be a different number of primary caches 908 and victim caches 910. With respect to primary cache 908, primary cache tag RAM access controller 912 accesses primary cache tag RAM 914 and checks the primary cache tag RAM 914 against the memory address included in the cache request to determine whether the memory address is stored in primary cache 908. The primary cache controller 916 directs the appropriate allocation, eviction, arbitration, merging, etc., and read / write processes to the primary cache memory 918. Figure 3 The depicted primary cache store queue structure 920 provides features such as RMW, ECC, write merging, and the like.

[0102] The overall architecture of the victim cache 910 is similar to that of the primary cache 908. For example, for a received memory request, the victim cache tag RAM access controller 922 accesses the victim cache tag RAM 924 and checks the victim cache tag RAM 924 against the memory address included in the cache request to determine whether the memory address is stored in the victim cache 910. The victim cache controller 926 similarly directs the appropriate allocation, eviction, arbitration, merging, etc. processes and read / writes to the victim cache memory 928. The victim cache store queue 930 provides RMW, ECC, and other features, such as in conjunction with Figure 3 910 and primary cache 908. Although shown separately, victim cache logic 932 may be integrated with or part of other components, such as victim cache controller 926. In certain cases, victim cache 908 includes specific components that help enable victim cache 908 to support write-miss buffering functionality. For example, auto-flush logic 934 may monitor processor interface 906 and direct the flushing of portions of victim cache memory 928 allocated for write-miss buffering, such as to higher-level caches and memories, via one or more memory interfaces 936. As another example, MESI RAM 938 or victim cache tag RAM may be configured to include one or more bit fields to store status information about write-miss buffering entries stored in victim cache 910.

[0103] In certain cases, the victim cache and the primary cache may comprise multiple data paths configured as parallel caches that appear to the processor as a single cache. Each data path is configured to process specific commands in parallel with the other data paths. For example, the first data path 910 may be processing read commands to the primary cache, while the second data path 942 is processing write misses to the victim cache. In an embodiment with two data paths for the victim cache, four combinations of cache commands may exist for the first data path 940 and the second data path 942: read / read, read / write, write / read, and write / write. Furthermore, each command combination may result in a cache hit / hit, hit / miss, miss / hit, or miss / miss. Furthermore, two commands may potentially be addressed to the same memory address with different privilege levels and colors. In certain cases, to facilitate control of the parallel caches, a centralized controller 944 may help coordinate the processing of read and write requests between the primary cache 908 and the victim cache 910. In certain cases, the centralized controller 944 may be configured to handle coordination between the primary cache 908 and the victim cache 910 and delegate the management of the primary cache 908 and the victim cache 910 to the primary cache controller 916 and the victim cache controller 926, respectively. The centralized controller 944 may also detect and handle potential conflicts. For example, when a read request is received from a processor, the centralized controller 944 may check the primary cache 908 and the victim cache 910 to determine that the addressed memory location of the read request is not stored in either the primary cache 908 or the victim cache 910 and is therefore a read miss. The centralized controller 944 may also check the victim cache 910 to determine that the addressed memory location has not been stored in the victim cache 910 as a write miss or flushed from the victim cache 910. If the addressed memory location is stored in the victim cache 910 as a write miss, the centralized controller 944 may suspend flushing the read request for the addressed memory location. The centralized controller 944 may then issue a request for the addressed memory location to a higher level cache or memory.

[0104] In certain cases, if a read or write request is a hit in the primary cache 908, the result in the victim cache 910 can be ignored. In the case where the primary cache 908 is configured as a single-way associative cache, cache request conflicts for multiple data paths are clear. Cache request conflicts from multiple data paths can be a problem in the victim cache 910, which is fully associative and can store write miss entries as well as cache entries. Cache request conflicts for two data paths can be handled as described in the following examples. It is worth noting that in the following examples, cache operations are described in the context of specific data paths. However, the examples involve combinations of specific cache operations, and it does not matter which data path a specific cache operation is performed on.

[0105] In the first example, there is a cache read miss for the first data path, and a cache write hit for the second data path, with two different memory addresses. In the specific case where the victim cache 910 is fully associative, the cache request can reach any location within the victim cache 910. Figure 7 Address generation 928 for the location within the victim cache occurs in the E2 pipe stage, along with an address lookup in the victim cache tag RAM 904. Therefore, address generation 728 for the location within the victim cache is performed before it is known whether the address of the cache request is a hit or a miss. Once the centralized controller 944 determines that there has been a read miss on the primary cache 908, a request is issued to a higher-level cache or memory to obtain the memory address of the read request. If the primary cache 908 is single-way associative, the memory address of the read request from the first data path maps to a single location in the primary cache 908. If data already cached exists in the single location, the already cached data is evicted from the primary cache 908 to the victim cache 910 to a pre-generated location within the victim cache 910. If this pre-generated location is the same as the location where a cache write hit occurred for the second data path, a conflict occurs. This conflict can be detected by the centralized controller 944. As indicated above, the generation of the address for the location within the victim cache 910 occurs before it is known whether the cache request address is a hit or a miss, so there is an address generated for the second location within the victim cache 910 for the cache write of the second data path before it is determined that the cache write is a hit. Based on the detection of a conflict, this second location within the victim cache can be used to store data evicted from the primary cache 908 due to the read miss.

[0106] In another example, as in the first example, there may be a cache read miss for the first data path and a cache write hit for the second data path, but in this example, the cache read misses in the primary cache and the cache write also hits in the primary cache. In a specific case, the primary cache is a single-way associative cache (e.g., a direct-mapped cache), where a particular memory address is mapped to a particular location within the primary cache. In this example with a direct-mapped cache, the cache read and cache write are mapped to the same location in the primary cache. In this example, due to the read miss, a request is issued to a higher-level cache or memory to obtain the memory address of the read request, and the already cached data is evicted from the primary cache 908 to the victim cache 910 to a pre-generated location within the victim cache 910, here, location A. In this example, the cache write for the second data path hits the same location in the primary cache that was evicted. One possible solution to this conflict is to load the requested read miss directly from a higher-level cache or memory into a separate location in the victim cache. Another solution to the conflict is to have the centralized controller 944 pause the read miss so that already cached data is not evicted to the victim cache 910 until the cache write of the second data path completes to location A in the primary cache and then location A is evicted to the victim cache. In certain cases, the pause can occur while waiting for the memory write and eviction to complete.

[0107] As another example, a first cache write may be received on a first data path for the victim cache 910, and a second cache write may also be received on a second data path for the victim cache 910. If the first cache write and the second cache write are addressed to different memory addresses, then both cache writes may proceed in parallel with the victim cache 910. If both the first cache write and the second cache write are addressed to the same memory address and both are cache misses, then the victim cache controller 926 allocates a single location in the victim cache write miss memory 928 and merges the first cache write and the second cache write in the victim cache store queue 930. The merged data may then be written to the victim cache write miss memory 928 along with the merged byte enable, privilege, and color tag information. If both the first cache write and the second cache write are addressed to the same memory address and both are cache hits, then both the first cache write and the second cache write are merged into the hit location in the cache.

[0108] As another example, a cache read may be received on a first data path for the victim cache 910, and a cache write may be received on a second data path for the victim cache 910. In the case where the cache read is a hit and the cache write is a hit for different locations in the victim cache 910, the cache read and cache write proceed in parallel without conflicts. In the case where the cache read is a hit and the cache write is a miss for different locations in the victim cache 910, the cache read and cache write also proceed in parallel without conflicts. In the case where the cache read is a miss and the cache write is a hit for different locations in the victim cache 910, the cache read may use the address generated for the location within the victim cache 910 for the cache write as described above. In the case where the cache read is a miss and the cache write is a miss for different locations in the victim cache 910, both the cache read and cache write use the address generated for the location within the victim cache 910.

[0109] In another example, a cache read may be received on a first data path for primary cache 908, and a cache write may be received on a second data path for primary cache 908. In certain cases, a cache read may be a hit against a location (e.g., a cache line or slot) in primary cache 908. A cache write may also be a hit against the same location in primary cache 908. In this case, the cache read and cache write may proceed in parallel without conflict, because the cache read may be executed relatively quickly and complete before the cache write needs to access the primary cache location as the cache write proceeds through the store queue. In another case, a cache read may be a hit against a location in primary cache 908. A cache write may be a miss against the same location in primary cache 908. In this case, cache commands generally proceed in parallel, because the cache read may complete before the cache write needs to access the cache location. In another case, a cache read may be a miss against a location in primary cache 908. The cache write may be a hit to the same location in the primary cache 910. In this case, similar to what is described above, the cache read may be suspended until the cache write of the second data path completes to the location in the main memory 908 and is evicted to the victim cache 908. The cache read then proceeds to read a set of addresses from a higher-level cache or memory into the primary cache 910. In another case, the cache read may be a miss to the first location in the primary cache 908. The cache write may also be a miss to the same location in the primary cache 908. In this case, the cache read and cache write may proceed in parallel without conflict.

[0110] In another example, a cache read may be received on a first data path for victim cache 910, and a cache write may be received on a second data path for victim cache 910. In certain cases, a cache read may be a hit for an address stored in victim cache 910. A cache write may also be a hit for the same address stored in victim cache 910. In this case, the cache read may proceed first, and the cache write may be paused until the cache read completes. Alternatively, the order of the cache write and cache read may be based on the data path on which the cache write and cache read are received, where a cache command arriving on a lower (or higher) numbered data path completes before another cache command. In certain cases, a cache read may be a miss for an address stored in victim cache 910. A cache write may also be a miss for the same address stored in victim cache 910. In this case, the cache write command may be forwarded to a higher level cache or memory, and then a cache read may obtain the data from the higher level cache or memory after the cache write command completes storage in the victim cache 910 .

[0111] In another example, a first cache read may be received on a first data path for victim cache 910, and a second cache read may be received on a second data path for victim cache 910. If the first cache read and the second cache read are for different memory addresses, then there is no conflict in hits or misses. In certain cases, the first cache read may be a miss for a first address in a set of addresses. The second cache read may also be a miss for a second address in the same set of addresses. If the first cache read and the second cache read have different priorities, then a higher-level cache or memory is accessed based on the higher of the different priorities. Otherwise, the higher-level cache or memory is accessed and a set of memory addresses is obtained for storage in victim cache 910. Cases where the first cache read and the second cache read are for the same address are handled identically.

[0112] Figure 101000 is a flow chart illustrating a technique for caching data 1000 according to aspects of this description. In block 1002, a cache system receives a write memory request for a memory address. For example, a cache system, such as an L1 cache, may receive the write request from a processor via a processor interface. In block 1004, a first sub-cache of the cache system determines that the memory address is not cached in the first sub-cache. For example, the cache system may include two parallel caches: a primary cache and a victim cache. The memory address of the cache request may be checked against both the primary cache and the victim cache in parallel. A write miss occurs when a write request is received for a memory address not contained within the cache system. In block 1006, a second sub-cache of the cache system determines that the memory address is not cached in the second sub-cache. In block 1008, data associated with the write memory request is stored in the second sub-cache. For example, the data of the write memory request may have been stored in the victim cache. Furthermore, the address associated with the write memory request may be stored in the tag RAM of the victim cache, and the byte enable logic associated with the write memory request may be stored in the byte enable memory of the victim cache. At block 1010, an indication that the stored data corresponds to a write miss is stored in the line type bits of the second sub-cache. For example, the victim cache includes a line type bit associated with a line of the victim cache. A bit may be set in the line type bits to indicate that a particular line of the victim cache received a write miss. At block 1012, the stored data may be flushed based on the indication. For example, the stored write miss data may be flushed from the victim cache to a higher level memory by checking the line type bit of the cache line and flushing the line associated with the write miss.

[0113] Figure 111 is a flow chart illustrating a technique for caching data 1100 according to aspects of this description. In block 1102, a cache system receives a write memory request for a memory address. For example, a cache system, such as an L1 cache, may receive the write request from a processor via a processor interface. In block 1104, a first sub-cache of the cache system determines that the memory address is not cached in the first sub-cache. For example, the cache system may include two parallel caches: a primary cache and a victim cache. The memory address of the cache request may be checked against both the primary cache and the victim cache in parallel. A write miss occurs when a write request is received for a memory address not contained within the cache system. In block 1106, a second sub-cache of the cache system determines that the memory address is not cached in the second sub-cache. In block 1108, data associated with the write memory request is stored in the second sub-cache. For example, the data of the write memory request may have been stored in the victim cache. Furthermore, the address associated with the write memory request may be stored in the tag RAM of the victim cache, and the byte enable logic associated with the write memory request may be stored in the byte enable memory of the victim cache. At block 1110, an indication that the stored data corresponds to a write miss is stored in the line type bits of the second sub-cache. For example, the victim cache includes a line type bit associated with a line of the victim cache. A bit may be set in the line type bits to indicate that a particular line of the victim cache received a write miss. At block 1112, the line of the second sub-cache storing the write miss is evicted based on an indication that the line has been completely written. For example, the line may be calculated based on byte enable logic indicating that all or half of the bytes of the cache line have been filled with write data. A filled or partially filled cache line may be evicted from the victim cache based on the bit.

[0114] Figure 1212 is a flow chart illustrating a technique for caching data 1200 according to aspects of this description. In block 1202, a cache system receives a write memory command to a memory address, the write memory command being associated with a first privilege level. For example, a cache system, such as an L1 cache, may receive a write request from a processor via a processor interface. In block 1204, a first sub-cache of the cache system determines that the memory address is not cached in the first sub-cache. For example, the cache system may include two parallel caches: a primary cache and a victim cache. The memory address of the cache request may be checked against both the primary cache and the victim cache in parallel. A write miss occurs when a write request is received to a memory address that is not in either the primary cache or the victim cache. In block 1206, a second sub-cache of the cache system determines that the memory address is not cached in the second sub-cache, and the second sub-cache is configured to store cache data evicted from the first sub-cache and the write memory command not cached in the first sub-cache in parallel with the first sub-cache. At block 1208, data associated with the write memory command is stored in the second sub-cache. At block 1210, the color tag bits associated with the data are stored in the second sub-cache. For example, the color tag bits may be stored in a bit field of a memory in the second sub-cache, such as MESI RAM. At block 1212, the stored data is evicted based on the color tag bits. For example, a cache line storing write miss data associated with a particular color tag bit may be evicted when the processor asserts a flush signal and the color tag priority indication. After all cache lines with a particular color tag bit have been flushed, the cache system may assert an idle signal. If the processor continues to assert the flush signal, other cache lines storing write miss data associated with other color tags may also be evicted.

[0115] Figure 13is a flow chart illustrating a technique for caching data 1300 according to aspects of this description. In block 1302, a cache system receives a write memory command to a memory address, the write memory command being associated with a first color tag. For example, a cache system, such as an L1 cache, may receive a write request from a processor via a processor interface. The write request may include an indication of the color tag associated with the write request. In block 1304, a first sub-cache of the cache system determines that the memory address is not cached in the first sub-cache. For example, the cache system may include two parallel caches: a primary cache and a victim cache. The memory address of the cache request may be checked against both the primary cache and the victim cache in parallel. A write miss occurs when a write request is received to a memory address not contained within the cache system. In block 1306, a second sub-cache of the cache system determines that the memory address is not cached in the second sub-cache. In block 1308, data associated with the write memory command is stored in a cache line of the second sub-cache. For example, the data of the write request may be stored in a cache line of the victim cache. Furthermore, the address associated with the write memory request may be stored in the tag RAM of the victim cache, and the byte enable logic associated with the write memory request may be stored in the byte enable memory of the victim cache. At block 1310, a first color tag is stored in the second sub-cache. For example, the color tag may be stored using two bits within a bit field of memory in the second sub-cache, such as MESI RAM. At block 1312, a second write memory command for a cache line is received, the write memory command being associated with a second color tag. For example, a second write request may be received for a memory address targeting the same cache line as the first write request. The second write request is associated with a second color tag. The second color tag may be the same as or different from the first color tag. At block 1314, the second color tag is merged with the first color tag. For example, if the first and second color tags represent the same color, merging the two tags continues to set that color tag. If the two color tags are different, merging may set both color tags. At block 1316, the merged color tag is stored. At block 1318, cache lines may be evicted based on the merged color tag. For example, if the first color tag and the second color tag represent the same color, eviction may be based on that color tag. If the two color tags are different, eviction may be based on either color tag.

[0116] Figure 1414 is a flow chart illustrating a technique for caching data 1400 according to aspects of this description. In block 1402, a cache system receives a first write memory command to a memory address, the first write memory command being associated with a first privilege level. For example, a cache system, such as an L1 cache, may receive a write request from a processor via a processor interface. In block 1404, a first sub-cache of the cache system determines that the memory address is not cached in the first sub-cache. For example, the cache system may include two parallel caches: a primary cache and a victim cache. The memory address of the cache request may be checked against both the primary cache and the victim cache in parallel. A write miss occurs when a write request is received to a memory address that is not in either the primary cache or the victim cache. In block 1406, a second sub-cache of the cache system determines that the memory address is not cached in the second sub-cache, and the second sub-cache is configured to store cache data evicted from the first sub-cache and the write memory command not cached in the first sub-cache in parallel with the first sub-cache. At block 1408, first data associated with the first write memory command is stored in a cache line of the second sub-cache. At block 1410, a first privilege level is stored in the second sub-cache. For example, the first privilege level may include two partial privilege levels, such as root / guest user / supervisor. These two partial privilege levels may be stored using two bits within a bit field of memory in the second sub-cache, such as MESI RAM. At block 1412, a second write memory command for a cache line is received, the second write memory command being associated with a second privilege level. For example, a second write request may be received for a memory address targeting the same cache line as the first write request. The second write request is associated with a second privilege level, which may be the same as or different from the first write request. At block 1414, the first privilege level and the second privilege level are merged. For example, the privilege levels may be merged based on a privilege merge table or by selecting a lower privilege level from the merged privilege levels. At block 1416, the merged privilege level is stored. At block 1418, the merged privilege level is output with the cache line. For example, a cache line including the merged first and second write requests may be evicted to a higher level cache or memory in a store miss data packet including the merged privilege level.

[0117] Figure 1515 is a flow chart illustrating a technique for caching data 1500 according to aspects of this description. In block 1502, a cache system receives a write memory request for a memory address. For example, a cache system, such as an L1 cache, may receive the write request from a processor via a processor interface. In block 1504, a first sub-cache of the cache system determines that the memory address is not cached in the first sub-cache. For example, the cache system may include two parallel caches: a primary cache and a victim cache. The memory address of the cache request may be checked against both the primary cache and the victim cache in parallel. A write miss occurs when a write request is received for a memory address not contained within the cache system. In block 1506, a second sub-cache of the cache system determines that the memory address is not cached in the second sub-cache. In block 1508, data associated with the write memory request is stored in the second sub-cache. For example, the data of the write memory request may have been stored in the victim cache. Furthermore, the address associated with the write memory request may be stored in the tag RAM of the victim cache, and the byte enable logic associated with the write memory request may be stored in the byte enable memory of the victim cache. At block 1510, an indication that the stored data corresponds to a write miss is stored in the line type bits of the second sub-cache. For example, the victim cache includes line type bits associated with a line of the victim cache. A bit may be set in the line type bits to indicate that a particular line of the victim cache contains a write miss.

[0118] Figure 16 is a flow chart illustrating a technique for caching data 1600 according to aspects of the present description. At block 1602, a cache system receives two or more cache commands. For example, a cache system, such as an L1 cache, may receive multiple cache commands via a processor interface using, for example, two or more data paths. At block 1604, a determination is made that a conflict exists between the two or more cache commands. For example, a cache controller may determine that a cache conflict exists between two cache commands. A conflict may occur when two cache commands result in a conflicting change to the same cache location. At block 1606, a conflict resolution is determined between the two or more received cache commands. At block 1608, the two or more cache commands are sent to a first sub-cache and a second sub-cache, and the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache in parallel with the first sub-cache.

[0119] Examples:

[0120] In the following paragraphs, further exemplary embodiments are provided.

[0121] Example 1 includes a cache system comprising: a first sub-cache; and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: a set of cache lines; a line type bit configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to flush the stored write miss data based on the line type bit.

[0122] Example 2 includes the cache system of Example 1, wherein the second sub-cache further comprises: a tag random access memory (RAM) configured to store a memory address associated with the stored write miss data; and a byte enable memory configured to store byte enable logic associated with the stored write miss data, and wherein the eviction controller is configured to flush the stored write miss data by transmitting a memory write request to a higher-level memory based on the stored memory address and the stored byte enable logic.

[0123] Example 3 includes the cache system of example 1, wherein the cache system further comprises a processor interface, and wherein the eviction controller is further configured to: monitor activity on the processor interface; and flush stored write miss data based on the monitored activity.

[0124] Example 4 includes the cache system of example 3, wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.

[0125] Example 5 includes the cache system of example 4, wherein detecting idle activity comprises determining whether a memory request has been received within a predetermined number of clock cycles.

[0126] Example 6 includes the cache system of example 4, wherein the eviction controller is further configured to: determine that activity on the processor interface has resumed; and cancel a flush of the stored write miss data.

[0127] Example 7 includes the cache system of example 6, wherein determining that activity on the processor interface has resumed comprises detecting receipt of a cache request from a processor.

[0128] Example 8 includes a method for caching data, comprising: receiving, by a cache system, a write memory request for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache; storing data associated with the write memory request in the second sub-cache; storing an indication that the stored data corresponds to a write miss in a line type bit of the second sub-cache; and flushing the stored data based on the indication.

[0129] Example 9 includes the method of example 8, wherein flushing the stored data comprises transmitting, by the second sub-cache, a memory write request to a higher level memory.

[0130] Example 10 includes the method of example 8, further comprising monitoring activity on a processor interface, and wherein flushing the stored data is further based on the monitored activity.

[0131] Example 11 includes the method of example 10, wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.

[0132] Example 12 includes the method of example 11, wherein detecting idle activity comprises determining that a memory request has not been received within a predetermined number of clock cycles.

[0133] Example 13 includes the method of example 11, further comprising: determining that activity on the processor interface has resumed; and canceling the flushing of the stored write miss data.

[0134] Example 14 includes the method of example 13, wherein determining that activity on the processor interface has resumed comprises detecting receipt of a cache request.

[0135] Example 15 includes a device comprising: a processor; a first sub-cache; and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to flush the stored write miss data based on the line type bit.

[0136] Example 16 includes the device of example 15, wherein the second sub-cache further comprises: a tag random access memory (RAM) configured to store a memory address associated with the stored write miss data; and a byte enable memory configured to store byte enable logic associated with the stored write miss data, and wherein the eviction controller is configured to flush the stored write miss data by transmitting a memory write request to a higher level memory based on the stored memory address and the stored byte enable logic.

[0137] Example 17 includes the device of example 15, wherein the cache system further comprises a processor interface, and wherein the eviction controller is further configured to: monitor activity on the processor interface; and flush stored write miss data based on the monitored activity.

[0138] Example 18 includes the apparatus of example 17, wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.

[0139] Example 19 includes the apparatus of example 18, wherein detecting idle activity comprises determining whether a memory request has been received within a predetermined number of clock cycles.

[0140] Example 20 includes the device of example 18, wherein the eviction controller is further configured to: determine that activity on the processor interface has resumed; and cancel a flush of the stored write miss data.

[0141] Example 21 includes a cache system comprising: a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: a color tag bit configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag; and an eviction controller configured to evict a cache line of the second sub-cache storing write miss data based on the color tag associated with the cache line.

[0142] Example 22 includes the cache system of example 21, wherein the second sub-cache includes a bit field configured to store a state of the color tag.

[0143] Example 23 includes the cache system of example 22, wherein the bit field includes a bit that stores the state of each color tag.

[0144] Example 24 includes the cache system of example 23, wherein the bit field is stored in a memory that tracks a modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache.

[0145] Example 25 includes the cache system of example 24, wherein the MESI memory is configured to store an indication that the corresponding cache line of the second sub-cache is storing write miss data.

[0146] Example 26 includes the cache system of example 21, wherein the cache system further comprises a processor interface, and wherein the eviction controller is further configured to: receive a color tag priority indication on the processor interface; and evict a cache line of the second sub-cache storing write miss data based on the received color tag priority indication.

[0147] Example 27 includes the cache system of example 6, wherein the eviction controller is further configured to: assert an idle signal on the processor interface after all cache lines of the second sub-cache storing write miss data having color tag bits corresponding to the color tag priority indication have been evicted.

[0148] Example 28 includes a method for caching data, comprising: receiving, by a cache system, a write memory command for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and the write memory command that is not cached in the first sub-cache in parallel with the first sub-cache; storing data associated with the write memory command in the second sub-cache; storing a color tag bit associated with the data in the second sub-cache; and evicting the stored data based on the color tag bit.

[0149] Example 29 includes the method of example 28, further comprising: receiving a color tag priority indication from a processor; receiving a clear signal from the processor; and wherein evicting the stored data is based on the received color tag priority indication.

[0150] Example 30 includes the method of example 29, further comprising asserting an idle signal after all cache lines of the second sub-cache storing write miss data having color tag bits corresponding to the color tag priority indication have been evicted.

[0151] Example 31 includes the method of example 30, further comprising: continuing to receive the clear signal from the processor; and evicting stored data having color tag bits that do not correspond to the color tag priority indication.

[0152] Example 32 includes the method of example 39, further comprising: determining that storing the data has not completed; and waiting until the data has been stored.

[0153] Example 33 includes the method of Example 38, further comprising storing the color scale bit in a bit field associated with a corresponding color scale bit.

[0154] Example 34 includes a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, and wherein the second sub-cache includes: a color tag bit configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag; and an eviction controller configured to evict the cache line of the second sub-cache storing write miss data based on the color tag associated with the cache line.

[0155] Example 35 includes the device of example 34, wherein the second sub-cache comprises a bit field configured to store a state of the color patch.

[0156] Example 36 includes the device of example 35, wherein the bit field comprises a bit storing the state of each color patch.

[0157] Example 37 includes the device of example 36, wherein the bit field is stored in a memory that tracks a modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache.

[0158] Example 38 includes the device of example 37, wherein the MESI memory is configured to store an indication that the corresponding cache line of the second sub-cache is storing write miss data.

[0159] Example 39 includes the device of example 34, wherein the cache system further comprises a processor interface, and wherein the eviction controller is further configured to: receive a color-tag priority indication on the processor interface; and evict a cache line of the second sub-cache storing write-miss data based on the received color-tag priority indication.

[0160] Example 40 includes the device of example 39, wherein the eviction controller is further configured to assert an idle signal on the processor interface after all cache lines of the second sub-cache storing write miss data having color tag bits corresponding to the color tag priority indication have been evicted.

[0161] Example 41 includes a cache system comprising: a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: a color tag bit configured to store an indication that a corresponding line of the second sub-cache is associated with a color tag; and an eviction controller configured to evict a cache line of the second sub-cache storing write memory data based on the color tag associated with the line, and wherein the second sub-cache is further configured to: receive a first write memory command to a memory address, the write memory command associated with a first color tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first color tag in the second sub-cache; receive a second write memory command for the cache line, the write memory command associated with a second color tag; merge the second color tag with the first color tag; store the merged color tag; and evict the cache line based on the merged color tag.

[0162] Example 42 includes the cache system of example 41, wherein the first color code and the second color code represent the same color code.

[0163] Example 43 includes the cache system of example 41, wherein the first color tag and the second color tag represent different color tags, and wherein the merged color tag includes a first bit representing the first color tag and a second bit representing the second color tag.

[0164] Example 44 includes the cache system of example 43, wherein the second sub-cache is further configured to evict the cache line based on the first color scale.

[0165] Example 45 includes the cache system of example 44, wherein the second sub-cache is further configured to evict the cache line based on the second color scale.

[0166] Example 46 includes the cache system of example 41, wherein the first color tag and the second color tag are stored in bit fields in memory that track modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache data.

[0167] Example 47 includes the cache system of example 46, wherein the bit field includes a bit that stores a state of each color tag.

[0168] Example 48 includes a method for caching data, comprising: receiving, by a cache system, a write memory command for a memory address, the write memory command being associated with a first color tag; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands that are not cached in the first sub-cache in parallel with the first sub-cache; storing first data associated with the first write memory command in a cache line of the second sub-cache; storing the first color tag in the second sub-cache; receiving a second write memory command for the cache line, the write memory command being associated with a second color tag; merging the second color tag with the first color tag; storing the merged color tag; and evicting the cache line based on the merged color tag.

[0169] Example 49 includes the method of example 48, wherein the first color scale and the second color scale represent the same color scale.

[0170] Example 50 includes the method of example 48, wherein the first color scale and the second color scale represent different color scales, and wherein the merged color scale includes a first digit representing the first color scale and a second digit representing the second color scale.

[0171] Example 51 includes the method of example 50, wherein the evicting is based on the first color scale.

[0172] Example 52 includes the method of example 51, wherein the evicting is based on the second color scale.

[0173] Example 53 includes the method of example 48, wherein the first color tag and the second color tag are stored in bit fields in memory that track modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache data.

[0174] Example 54 includes the method of example 53, wherein the bit field includes a bit that stores a state of each color patch.

[0175] Example 55 includes a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: a color tag bit configured to store an indication that a corresponding line of the second sub-cache is associated with a color tag; and an eviction controller configured to evict a cache line of the second sub-cache storing write memory data based on the color tag associated with the line, wherein the second sub-cache is further configured to: receive a first write memory command to a memory address, the write memory command associated with a first color tag; store first data associated with the first write memory command in a cache line of the second sub-cache; store the first color tag in the second sub-cache; receive a second write memory command for the cache line, the write memory command associated with a second color tag; merge the second color tag with the first color tag; store the merged color tag; and evict the cache line based on the merged color tag.

[0176] Example 56 includes the device of example 55, wherein the first color scale and the second color scale represent the same color scale.

[0177] Example 57 includes the device of example 55, wherein the first color scale and the second color scale represent different color scales, and wherein the merged color scale includes a first digit representing the first color scale and a second digit representing the second color scale.

[0178] Example 58 includes the device of example 57, wherein the second sub-cache is further configured to evict the cache line based on the first color scale.

[0179] Example 59 includes the device of example 58, wherein the second sub-cache is further configured to evict the cache line data based on the second color scale.

[0180] Example 60 includes the device of example 55, wherein the first color tag and the second color tag are stored in bit fields in memory that track modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache data.

[0181] Example 61 includes a cache system comprising: a first sub-cache; a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a privilege level, and wherein the second sub-cache is further configured to: receive a first write memory command for a memory address, the first write memory command being associated with a first privilege level; store first data associated with the first write memory command in a cache line of the second sub-cache; store the privilege level associated with the cache line in the second sub-cache; receive a second write memory command for the cache line, the second write memory command being associated with a second privilege level; merge the first privilege level with the second privilege level; store the merged privilege level; and output the merged privilege level with the cache line.

[0182] Example 62 includes the cache system of example 61, wherein privilege level information is stored in a bit field in memory that tracks a modified, exclusive, shared, and invalid (MESI) state of entries in the second sub-cache data.

[0183] Example 63 includes the cache system of example 62, wherein the privilege level comprises a two-part privilege level.

[0184] Example 64 includes the cache system of example 63, wherein the bit field comprises 2 bits for storing the privilege level.

[0185] Example 65 includes the cache system of example 61, wherein the second sub-cache includes a privilege merge table indicating how different privilege levels are merged.

[0186] Example 66 includes the cache system of example 65, wherein the privilege merge table is predefined.

[0187] Example 67 includes the cache system of example 61, wherein merging the first privilege level and the second privilege level comprises selecting a lower privilege level.

[0188] Example 68 includes a method for caching data, comprising: receiving, by a cache system, a first write memory command for a memory address, the first write memory command being associated with a first privilege level; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache in parallel with the first sub-cache; storing first data associated with the first write memory command in a cache line of the second sub-cache; storing the first privilege level in the second sub-cache; receiving a second write memory command for the cache line, the second write memory command being associated with a second privilege level; merging the first privilege level with the second privilege level; storing the merged privilege level; and outputting the merged privilege level with the cache line.

[0189] Example 69 includes the method of example 67, wherein the privilege level comprises a two-part privilege level.

[0190] Example 70 includes the method of example 69, wherein the second sub-cache includes 2 bits in a bit field for storing the privilege level.

[0191] Example 71 includes the method of example 68, wherein the merging is based on a privilege merge table that indicates how different privilege levels are merged.

[0192] Example 72 includes the method of example 71, wherein the privilege merge table is predefined.

[0193] Example 73 includes the method of example 68, wherein merging the first privilege level and the second privilege level comprises selecting a lower privilege level.

[0194] Example 74 includes a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache to store cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache, the second sub-cache comprising: privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a privilege level, and wherein the second sub-cache is further configured to: receive a first write memory command for a memory address, the first write memory command being associated with a first privilege level; store first data associated with the first write memory command in a cache line of the second sub-cache; store the privilege level associated with the cache line in the second sub-cache; receive a second write memory command for the cache line, the second write memory command being associated with a second privilege level; merge the first privilege level with the second privilege level; store the merged privilege level; and output the merged privilege level with the cache line.

[0195] Example 75 includes the device of example 74, wherein privilege level information is stored in a bit field in memory that tracks a modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache data.

[0196] Example 76 includes the device of example 75, wherein the privilege level comprises a two-part privilege level.

[0197] Example 77 includes the device of example 76, wherein the bit field comprises 2 bits for storing the privilege level.

[0198] Example 78 includes the apparatus of example 75, wherein the second sub-cache includes a privilege merge table indicating how different privilege levels are merged.

[0199] Example 79 includes the device of example 78, wherein the privilege merge table is predefined.

[0200] Example 80 includes the device of example 75, wherein merging the first privilege level and the second privilege level comprises selecting a lower privilege level.

[0201] Example 81 includes a cache system comprising a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes a line type bit configured to store an indication that a corresponding line of the second sub-cache is configured to store write miss data.

[0202] Example 82 includes the cache system of example 81, wherein the second sub-cache further comprises a tag random access memory (RAM) configured to store a memory address associated with the stored write miss data.

[0203] Example 83 includes the cache system of example 81, wherein the second sub-cache further comprises a byte enable memory configured to store byte enable logic associated with the stored write miss data.

[0204] Example 84 includes the cache system of example 83, wherein the byte enable memory includes memory locations corresponding to each cache line of the second sub-cache.

[0205] Example 85 includes the cache system of example 81, wherein the stored indication indicates whether the corresponding cache line of the second sub-cache is storing a write miss entry or a cache entry.

[0206] Example 86 includes the cache system of example 81, wherein the line type bit is stored in a memory that tracks a modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache.

[0207] Example 87 includes the cache system of example 81, wherein the first sub-cache is an n-way set associative cache and wherein the second sub-cache is a fully associative cache.

[0208] Example 88 includes a method for caching data, comprising: receiving, by a cache system, a write memory request for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in a second sub-cache, the second sub-cache being coupled in parallel with the first sub-cache; storing data associated with the write memory request in the second sub-cache; and storing an indication that the stored data corresponds to a write miss in a line type bit of the second sub-cache.

[0209] Example 89 includes the method of example 88, further comprising storing a memory address associated with the stored write miss data in a tag random access memory (RAM).

[0210] Example 90 includes the method of example 88, further comprising storing byte enable logic associated with the stored write miss data in a byte enable memory.

[0211] Example 91 includes the method of example 88, wherein the line type bits are stored in a memory that tracks modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache.

[0212] Example 92 includes the method of example 88, further comprising evicting a cache entry from a line of the second sub-cache, and wherein storing data associated with the write memory request comprises storing the data in the line.

[0213] Example 93 includes the method of example 88, wherein the stored indication indicates whether the corresponding cache line of the second sub-cache is storing a write miss entry or a cache entry.

[0214] Example 94. A device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes a line type bit configured to store an indication that a corresponding line of the second sub-cache is configured to store write miss data.

[0215] Example 95 includes the device of example 94, wherein the second sub-cache further comprises a tag random access memory (RAM) configured to store a memory address associated with the stored write miss data.

[0216] Example 96 includes the device of example 94, wherein the second sub-cache further comprises a byte enable memory configured to store byte enable logic associated with the stored write miss data.

[0217] Example 97 includes the device of example 96, wherein the byte enable memory includes memory locations corresponding to each cache line of the second sub-cache.

[0218] Example 98 includes the device of example 94, wherein the stored indication indicates whether the corresponding cache line of the second sub-cache is storing a write miss entry or a cache entry.

[0219] Example 99 includes the device of example 94, wherein the line type bits are stored in a memory that tracks modified, exclusive, shared, and invalid (MESI) status of entries in the second sub-cache.

[0220] Example 100 includes the device of example 94, wherein the first sub-cache is an n-way set associative cache and wherein the second sub-cache is a fully associative cache.

[0221] Example 101 includes a cache system comprising: a first sub-cache; and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: a set of cache lines; a line type bit configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to evict a cache line of the second sub-cache storing write miss data based on an indication that the cache line has been completely written.

[0222] Example 102 includes the cache system of example 101, wherein the eviction controller is further configured to evict a cache line of the second sub-cache storing write miss data based on an indication that half of the cache line has been written.

[0223] Example 103 includes the cache system of example 102, wherein the eviction controller is configured to determine, based on the indication that half of the cache line has been written, that no cache line in the second sub-cache storing write miss data is fully written before evicting the cache line.

[0224] Example 104 includes the cache system described in Example 102, wherein the second sub-cache further includes a byte enable memory configured to store byte enable logic associated with the stored write miss data, and wherein the byte enable memory includes a first bit that stores the indication that the cache line has been completely written.

[0225] Example 105 includes the cache system of example 104, wherein the byte enable memory includes a second bit storing the indication that half of the cache line has been written.

[0226] Example 106 includes the cache system of example 105, wherein the first and second bits are determined based on the byte enable logic associated with the stored write miss data.

[0227] Example 107 includes the cache system of example 106, wherein the first and second bits are determined based on the byte enable logic each time write miss data is stored in the second sub-cache.

[0228] Example 108 includes a method for caching data, comprising: receiving, by a cache system, a write memory request for a memory address; determining, by a first sub-cache of the cache system, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the cache system, that the memory address is not cached in the second sub-cache; storing data associated with the write memory request in the second sub-cache; storing an indication that the stored data corresponds to a write miss in line type bits of the second sub-cache; and evicting a cache line of the second sub-cache storing the write miss based on an indication that the cache line has been completely written.

[0229] Example 109 includes the method of example 108, further comprising evicting a cache line of the second sub-cache storing write miss data based on an indication that half of the cache line has been written.

[0230] Example 110 includes the method of example 109, further comprising determining, based on the indication that half of the cache line has been written, that no cache line in the second sub-cache storing write miss data is fully written before evicting the cache line.

[0231] Example 111 includes the method of Example 109, further comprising storing a first bit in a byte enable memory of the second sub-cache indicating that the cache line has been completely written.

[0232] Example 112 includes the method of Example 111, further comprising storing a second bit in the byte enable memory of the second sub-cache indicating that the cache line half is written.

[0233] Example 113 includes the method of Example 112, wherein the first and second bits are determined based on the byte enable logic associated with the stored write miss data.

[0234] Example 114 includes the method of example 113, wherein the first and second bits are determined based on the byte enable logic each time write miss data is stored in the second sub-cache.

[0235] Example 115 includes a device comprising: a processor; a first sub-cache; and a second sub-cache in parallel with the first sub-cache; wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to store an indication that a corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to evict a cache line of the second sub-cache storing write miss data based on an indication that the cache line has been completely written.

[0236] Example 116 includes the device of example 115, wherein the eviction controller is further configured to evict a cache line of the second sub-cache storing write miss data based on an indication that half of the cache line has been written.

[0237] Example 117 includes the device of example 116, wherein the eviction controller is configured to determine, based on the indication that half of the cache line has been written, that no cache line in the second sub-cache storing write miss data is fully written before evicting the cache line.

[0238] Example 118 includes the device of Example 118, wherein the second sub-cache further includes a byte enable memory configured to store byte enable logic associated with the stored write miss data, and wherein the byte enable memory includes a first bit storing the indication that the cache line has been completely written.

[0239] Example 119 includes the device of example 118, wherein the byte enable memory includes a second bit storing the indication that half of the cache line has been written.

[0240] Example 120 includes the device of example 119, wherein the first and second bits are determined based on the byte enable logic associated with the stored write miss data.

[0241] Example 121 includes a cache system comprising: a first sub-cache; a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands that are not cached in the first sub-cache; and a cache controller configured to: receive two or more cache commands; determine a conflict between the two or more received cache commands; determine a conflict resolution between the two or more received cache commands; and send the two or more cache commands to the first sub-cache and the second sub-cache.

[0242] Example 122 includes the cache system described in Example 121, wherein the cache command is a read command, and wherein the cache controller is further configured to: determine, based on a memory address of the read command, that the memory address is not cached in the first sub-cache; determine, based on the memory address, that the memory address is stored in the second sub-cache as a write memory command; and suspend the read command until the write memory command is flushed from the second sub-cache.

[0243] Example 123 includes the cache system of example 121, wherein the cache controller is further configured to receive two or more cache commands in parallel.

[0244] Example 124 includes the cache system described in Example 123, wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to: determine a first cache location in the first sub-cache based on a first memory address of the read command; determine that the first memory address is not cached at the first cache location in the first sub-cache; receive a second cache location in the second sub-cache associated with the read command; determine that the second memory address is stored as a write memory command at the second cache location in the second sub-cache based on a second memory address of the write command; receive a third cache location in the second sub-cache associated with the write command; and evict a cached memory item from the first cache location in the first sub-cache to the third cache location in the second sub-cache.

[0245] Example 125 includes the cache system described in Example 123, wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to: determine a first cache location in the first sub-cache based on a first memory address of the read command; determine that the first memory address is not cached at the first cache location in the first sub-cache; determine that the second memory address is stored at the first location in the first sub-cache based on a second memory address of the write command; pause the read command; execute the write command; evict the executed write command to the second sub-cache; and resume the read command after the eviction.

[0246] Example 126 includes the cache system described in Example 123, wherein the two or more cache commands include a first write command and a second write command, and wherein the cache controller is further configured to: determine that a first memory address of the first write command is not cached in the first sub-cache; determine that a second memory address of the second write command is not cached in the first sub-cache; determine that the first memory address matches the second memory address; merge the first write command with the second write command; and store the merged command to the second sub-cache.

[0247] Example 127 includes the cache system described in Example 123, wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to: determine that a first memory address of the read command is not cached in the first sub-cache; determine that a second memory address of the write command is cached in the first sub-cache; determine that the first memory address matches the second memory address; suspend the write command until the read command is completed; and resume the write command.

[0248] Example 128 includes a method for caching data, comprising: receiving two or more cache commands; determining that a conflict exists between the two or more cache commands; determining a conflict resolution between the received two or more cache commands; and sending the two or more cache commands to a first sub-cache and a second sub-cache, wherein the second sub-cache is configured to store cache data evicted from the first sub-cache and write memory commands that are not cached in the first sub-cache in parallel with the first sub-cache.

[0249] Example 129 includes the method of Example 8, wherein the cache command is a read command and the method further includes: determining based on a memory address of the read command that the memory address is not cached in the first sub-cache; determining based on the memory address that the memory address is stored as a write memory command in the second sub-cache; and pausing the read command until the write memory command is flushed from the second sub-cache.

[0250] Example 130 includes the method of example 128, wherein the two or more cache commands are received in parallel.

[0251] Example 131 includes the method described in Example 130, wherein the two or more cache commands include a read command and a write command and the method further includes: determining a first cache location in the first sub-cache based on a first memory address of the read command; determining that the first memory address is not cached at the first cache location in the first sub-cache; receiving a second cache location in the second sub-cache associated with the read command; determining that the second memory address is stored as a write memory command at the second cache location in the second sub-cache based on the second memory address of the write command; receiving a third cache location in the second sub-cache associated with the write command; and evicting a cached memory item from the first cache location in the first sub-cache to the third cache location in the second sub-cache.

[0252] Example 132 includes the method of Example 130, wherein the two or more cache commands include a read command and a write command and the method further includes: determining a first cache location in the first sub-cache based on a first memory address of the read command; determining that the first memory address is not cached at the first cache location in the first sub-cache; determining that the second memory address is stored at the first location in the first sub-cache based on a second memory address of the write command; pausing the read command; executing the write command; evicting the executed write command to the second sub-cache; and resuming the read command after the eviction.

[0253] Example 133 includes the method described in Example 130, wherein the two or more cache commands include a first write command and a second write command, and wherein the cache controller is further configured to: determine that a first memory address of the first write command is not cached in the first sub-cache; determine that a second memory address of the second write command is not cached in the first sub-cache; determine that the first memory address matches the second memory address; merge the first write command with the second write command; and store the merged command to the second sub-cache.

[0254] Example 134 includes the method of Example 130, wherein the two or more cache commands include a read command and a write command and the method further includes: determining that a first memory address of the read command is not cached in the first sub-cache; determining that a second memory address of the write command is cached in the first sub-cache; determining that the first memory address matches the second memory address; pausing the write command until the read command is completed; and resuming the write command.

[0255] Example 135 includes a device comprising: a processor; a first sub-cache; and a second sub-cache coupled in parallel with the first sub-cache for storing cache data evicted from the first sub-cache and write memory commands not cached in the first sub-cache; and a cache controller configured to: receive two or more cache commands; determine that a conflict exists between the two or more received cache commands; determine a conflict resolution between the two or more received cache commands; and send the two or more cache commands to the first sub-cache and the second sub-cache.

[0256] Example 136 includes the device of Example 135, wherein the cache command is a read command, and wherein the cache controller is further configured to: determine, based on a memory address of the read command, that the memory address is not cached in the first sub-cache; determine, based on the memory address, that the memory address is stored in the second sub-cache as a write memory command; and suspend the read command until the write memory command is flushed from the second sub-cache.

[0257] Example 137 includes the device of example 135, wherein the cache controller is further configured to receive two or more cache commands in parallel.

[0258] Example 138 includes the device described in Example 137, wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to: determine a first cache location in the first sub-cache based on a first memory address of the read command; determine that the first memory address is not cached at the first cache location in the first sub-cache; receive a second cache location in the second sub-cache associated with the read command; determine that the second memory address is stored as a write memory command at the second cache location in the second sub-cache based on a second memory address of the write command; receive a third cache location in the second sub-cache associated with the write command; and evict a cached memory item from the first cache location in the first sub-cache to the third cache location in the second sub-cache.

[0259] Example 139 includes the device described in Example 137, wherein the two or more cache commands include a read command and a write command, and wherein the cache controller is further configured to: determine a first cache location in the first sub-cache based on a first memory address of the read command; determine that the first memory address is not cached at the first cache location in the first sub-cache; determine that the second memory address is stored at the first location in the first sub-cache based on a second memory address of the write command; pause the read command; execute the write command; evict the executed write command to the second sub-cache; and resume the read command after the eviction.

[0260] Example 140 includes the device described in Example 137, wherein the two or more cache commands include a first write command and a second write command, and wherein the cache controller is further configured to: determine that a first memory address of the first write command is not cached in the first sub-cache; determine that a second memory address of the second write command is not cached in the first sub-cache; determine that the first memory address matches the second memory address; merge the first write command with the second write command; and store the merged commands to the second sub-cache.

[0261] The term "coupled" is used throughout this specification. The term encompasses connections, communications, or signal paths that achieve a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, then in the first instance, device A is coupled to device B. Alternatively, in the second instance, if intermediary component C does not substantially alter the functional relationship between device A and device B, then device A is coupled to device B through intermediary component C, such that device B is controlled by device A via the control signal generated by device A.

[0262] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A cache system comprising: The first-level cache, which contains: a first sub-cache; and A second sub-cache is provided in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to indicate a line type of a corresponding cache line in the set of cache lines, wherein a first line type is an indication that the cache line in the set of cache lines is configured to store a row of data evicted from the first sub-cache, and wherein a second line type is an indication that the corresponding cache line in the set of cache lines is configured to store write miss data; and an eviction controller configured to flush stored write miss data based on the line type bit; and Second level cache.

2. The cache system according to claim 1, wherein the second sub-cache further comprises: a tag random access memory (RAM) configured to store a memory address associated with the stored write miss data; and a byte enable memory configured to store byte enable logic associated with the stored write miss data, and Wherein the eviction controller is configured to flush stored write miss data by transmitting a memory write request to a higher level memory based on the stored memory address and stored byte enable logic.

3. The cache system of claim 1 , wherein the cache system further comprises a processor interface, and wherein the eviction controller is further configured to: monitoring activity on the processor interface; and The stored write miss data is flushed based on the monitored activity.

4. The cache system of claim 3, wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.

5. The cache system of claim 4, wherein detecting idle activity comprises determining whether a memory request has been received within a predetermined number of clock cycles.

6. The cache system of claim 4, wherein the eviction controller is further configured to: determining that activity on the processor interface has resumed; and Flushing of the stored write miss data is canceled.

7. The cache system of claim 6, wherein determining that activity on the processor interface has resumed comprises detecting receipt of a cache request from a processor.

8. A method for caching data, comprising: receiving, by the first level cache, a write memory request for a memory address; determining, by a first sub-cache of the first level cache, that the memory address is not cached in the first sub-cache; determining, by a second sub-cache of the first level cache, that the memory address is not cached in the second sub-cache; storing data associated with the write memory request in the second sub-cache; storing an indication that the stored data corresponds to a write miss in a line type bit of the second sub-cache; monitoring processor activity on a processor interface; as well as The stored data is flushed based on the indication and the activity of the processor being at or below a threshold.

9. The method of claim 8, wherein flushing the stored data comprises transmitting, by the second sub-cache, a memory write request to a higher level memory.

10. The method of claim 8, wherein the threshold is idle activity on the processor interface. The method of claim 10 , wherein detecting idle activity comprises determining that a memory request has not been received within a predetermined number of clock cycles.

12. The method according to claim 10, further comprising: determining that activity on the processor interface has resumed; and Flushing of the stored write miss data is canceled.

13. The method of claim 12, wherein determining that activity on the processor interface has resumed comprises detecting receipt of a cache request.

14. An apparatus comprising: A processor comprising a first level cache, wherein the first level cache comprises: a first sub-cache; and A second sub-cache is provided in parallel with the first sub-cache, wherein the second sub-cache comprises: a set of cache lines; a line type bit configured to indicate a line type of a corresponding cache line in the set of cache lines, wherein a first line type is an indication that the cache line in the set of cache lines is configured to store a row of data evicted from the first sub-cache, and wherein a second line type is an indication that the corresponding cache line in the set of cache lines is configured to store write miss data; and An eviction controller is configured to flush stored write miss data based on the line type bit.

15. The apparatus of claim 14, wherein the second sub-cache further comprises: a tag random access memory (RAM) configured to store a memory address associated with the stored write miss data; and a byte enable memory configured to store byte enable logic associated with the stored write miss data, and Wherein the eviction controller is configured to flush stored write miss data by transmitting a memory write request to a higher level memory based on the stored memory address and stored byte enable logic.

16. The apparatus of claim 14, wherein the cache system further comprises a processor interface, and wherein the eviction controller is further configured to: monitoring activity on the processor interface; and The stored write miss data is flushed based on the monitored activity.

17. The apparatus of claim 16, wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.

18. The apparatus of claim 17, wherein detecting idle activity comprises determining whether a memory request has been received within a predetermined number of clock cycles.

19. The device of claim 17, wherein the eviction controller is further configured to: determining that activity on the processor interface has resumed; and Flushing of the stored write miss data is canceled.

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