IO command processing method and solid-state storage device

Abstract

The present application provides an IO command processing method and a solid-state storage device. The disclosed method includes: obtaining a LUN number and / or a block address from an IO command; wherein the LUN number is used to indicate a virtual LUN or a logical LUN, the virtual LUN includes multiple physical LUNs, and the logical LUN includes one or more physical LUNs from different virtual LUNs or multiple physical blocks provided by one or more physical LUNs from different virtual LUNs; selecting one or more processing units from multiple processing units according to the LUN number; each processing unit determines the physical LUN accessed by the IO command and the physical block address on the physical LUN according to the block address; sending a valid chip enable signal to the CE port that provides the physical LUN accessed by the IO command; and sending an NVM interface command to the accessed physical LUN, wherein each processing unit executes multiple IO commands in parallel; or multiple processing units execute one or more IO commands in parallel.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to an IO command processing method and a solid-state storage device. Background Art

[0002] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), etc. are common NVM (Non-Volatile Memory).

[0003] A memory target is one or more logic units (Logic Unit) that share a chip enable (CE) signal within a flash memory particle package, and each logic unit has a logic unit number (LUN, Logic Unit Number). A NAND flash memory package may include one or more tube cores (DIE). Typically, a logic unit corresponds to a single tube core. A logic unit may include multiple planes (Plane). Multiple planes within a logic unit can be accessed in parallel, and multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other. In the "Open NAND Flash Interface Specification (Revision 3.2)" obtained from http: / / www.onfi.org / ~ / media / ONFI / specs / ONFI_3_2%20Gold.pdf, the meanings of targets, logic units, LUNs, and planes are provided, as well as commands for operating NVM chips.

[0004] The solid-state drive controller includes a flash memory interface controller (or media interface controller, flash memory channel controller), which is coupled to the NVM chip and issues commands to the NVM chip in a manner that complies with the interface protocol of the NVM chip to operate the NVM chip and receive command execution results output from the NVM chip. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0005] In the Chinese patent application with publication number CN1414468A, a scheme for processing CPU (Central Processing Unit) instructions by executing a microinstruction sequence is provided. When the CPU is to process a specific instruction, the conversion logic circuit converts the specific instruction into a microinstruction sequence corresponding thereto, and implements the function of the specific instruction by executing the microinstruction sequence. The microinstruction sequence or the template of the microinstruction sequence is stored in a ROM (Read Only Memory). In the process of converting the specific instruction into the microinstruction sequence, the microinstruction sequence template can be filled to correspond to the specific instruction.

[0006] In Chinese patent applications CN201610009789.6 and CN201510253428.1, a microinstruction execution method and device for a flash memory interface controller are provided, and in Chinese patent application CN 201610861793.5, a microinstruction sequence scheduling method and device are provided, and the entire text thereof is incorporated herein. A flash memory interface controller is usually coupled to multiple NVM chips, and the NVM chip includes multiple LUNs (Logic Units) or tube cores. Multiple LUNs and tube cores can respond to and access NVM commands in parallel. Since each LUN or tube core can have multiple NVM commands to be processed, the NVM controller needs to schedule multiple NVM commands or multiple microinstruction sequences to maintain multiple NVM commands in process or to be processed, or to maintain multiple microinstruction sequences for generating NVM commands.

[0007] In a large-capacity SSD, the controller needs to connect more NVM chips. Multiple dies or targets may also be included in a single NVM chip. Since each die or target on the NVM chip has a chip enable (CE) pin, and when operating each die or target, a separate CE signal must be applied to it to distinguish it from the operation of other NVM chips / dies / targets in the SSD. However, the numerous CE signals consume a large number of IO pin resources of the controller.

[0008] Figure 1 This is a schematic diagram of a storage system with chip enable signal extension according to Chinese patent CN201632269U. Figure 1 The storage system shown includes a memory controller 101 (also called a solid state drive controller) and flash memory channels 1 (102) to m (103), each of which includes one or more flash memory chips (not shown). Figure 1The storage system further includes a CE expander 104. The CE expander 104 is connected to the memory controller 101. The connection between the CE expander 104 and the memory controller 101 can be through, for example, a CE data signal line and a CE control signal line. Data can also be transmitted between the CE expander 104 and the memory controller 101 through communication protocols such as IIC (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver / Transmitter), and LIN (Local Interconnect Network). Figure 1 In the embodiment of the present invention, the flash channels 102 and 103 share data signal lines and control signal lines except chip enable. It should be understood that the memory controller 101 and the CE expander 104 can be coupled using a single signal line.

[0009] The CE expander 104 is connected to the chip enable (CE) ports of multiple flash memory chips or flash memory dies on the flash memory channel 1 (102) to the flash memory channel m (103) through multiple chip enable (CE) signal lines. Figure 1 The flash channels are indicated by “flash channel 1-CE1”, “flash channel 1-CEn”, “flash channel m-CE1” and “flash channel m-CEn”.

[0010] exist Figure 1 In the embodiment of the present invention, there are m flash memory channels in the storage system, each flash memory channel has 1 flash memory chip, each flash memory chip includes n dies and n chip enable (CE) ports corresponding to the n dies, so a total of n*m CE signal lines are needed. These n*m ​​CE signal ports are all connected to the CE expander 104, and the CE expander 104 communicates with the memory controller 201 through fewer signal lines (for example, Figure 1 For example, the memory controller 101 indicates to the CE expander 104 that the first die of the first flash memory chip on the flash channel 103 is to be enabled, and the CE expander 104 generates a valid enable signal on the corresponding “flash channel m-CE1” chip enable signal line, but does not generate a valid enable signal on other chip enable signal lines.

[0011] It is still understandable that multiple CE expanders can be provided to enable the memory controller to access more flash memory chips. And the technology provided by Chinese patent CN201632269U can be applied to access other NVM chips. Summary of the invention

[0012] The purpose of the present application includes providing an IO command processing method and an NVM interface controller to support the application of a CE expander and an expansion mechanism to access more NVM chips.

[0013] According to a first aspect of the present invention, a first IO command processing method according to the first aspect of the present invention is provided, the method comprising: obtaining an IO command from a command queue; obtaining a virtual LUN number and / or a virtual block address from the IO command; selecting a processing unit according to the virtual LUN number; the processing unit determining a physical LUN accessed by the IO command and a physical block address on the physical LUN according to the virtual block address; issuing a valid chip enable signal to a CE port providing the physical LUN accessed by the IO command; and issuing an NVM interface command to the accessed physical LUN.

[0014] According to the first IO command processing method of the first aspect of the present invention, a second IO command processing method according to the first aspect of the present invention is provided, in which blocks of the virtual LUN are addressed according to the virtual block address, and the number of blocks of the virtual LUN is equal to the sum of the numbers of blocks of multiple physical LUNs included in the virtual LUN.

[0015] According to the second IO command processing method according to the first aspect of the present invention, a third IO command processing method according to the first aspect of the present invention is provided, wherein the virtual LUN includes multiple physical LUNs.

[0016] According to the first to third IO command processing methods of the first aspect of the present invention, a fourth IO command processing method according to the first aspect of the present invention is provided, providing a processing unit for each virtual LUN so as to select a corresponding processing unit according to the virtual LUN number when processing an IO command.

[0017] According to the fourth IO command processing method of the first aspect of the present invention, there is provided a fifth IO command processing method according to the first aspect of the present invention, wherein the processing unit is coupled to a plurality of physical LUNs.

[0018] According to the fifth IO command processing method of the first aspect of the present invention, a sixth IO command processing method according to the first aspect of the present invention is provided, wherein the processing unit is coupled to the multiple physical LUNs through a CE expander; and the CE expander, under the control of the processing unit, sends a valid chip enable signal to the CE port of the physical LUN accessed by the IO command.

[0019] According to the fifth or sixth IO command processing method of the first aspect of the present invention, a seventh IO command processing method according to the first aspect of the present invention is provided, wherein the CE expander also sends an invalid chip enable signal to the CE ports corresponding to each physical LUN other than the accessed physical LUN in the virtual LUN to which the physical LUN accessed by the IO command belongs under the control of the processing unit.

[0020] According to the fourth to seventh IO command processing methods of the first aspect of the present invention, there is provided an eighth IO command processing method according to the first aspect of the present invention, wherein the processing unit performs its function by executing a microinstruction sequence.

[0021] According to the eighth IO command processing method of the first aspect of the present invention, a ninth IO command processing method according to the first aspect of the present invention is provided, wherein the microinstruction sequence has multiple execution contexts, and the microinstruction sequence utilizes one of the multiple execution contexts each time it is executed.

[0022] According to the first to ninth IO command processing methods of the first aspect of the present invention, there is provided a tenth IO command processing method according to the first aspect of the present invention, further comprising: obtaining a type of the IO command.

[0023] According to the tenth IO command processing method of the first aspect of the present invention, an eleventh IO command processing method according to the first aspect of the present invention is provided. If the IO command is a reset command, all physical LUNs corresponding to the virtual LUNs are obtained, and a valid chip enable signal is sent to the CE ports providing all these physical LUNs; a reset command is sent to all these physical LUNs; and the reset command is processed until it is confirmed that the reset command is executed on all physical LUNs.

[0024] According to the tenth IO command processing method of the first aspect of the present invention, a twelfth IO command processing method according to the first aspect of the present invention is provided, if the IO command is a reset command, all physical LUNs corresponding to the virtual LUNs are obtained, a reset command is issued to one of these physical LUNs each time, and the reset command is repeatedly issued to each physical LUN, and a chip enable signal is issued to the corresponding CE ports providing these physical LUNs; and the reset command is processed until all physical LUNs in the virtual LUNs are reset.

[0025] According to the tenth IO command processing method of the first aspect of the present invention, a thirteenth IO command processing method according to the first aspect of the present invention is provided. If the IO command is a programming command, the physical LUN to be accessed and the physical block address on the physical LUN are determined based on the accessed virtual block address, and a chip enable signal is sent to the CE port providing the physical LUN; and a programming command is sent to the physical LUN; and the programming command is processed and the execution status of the programming command is obtained until the execution of the programming command is completed.

[0026] According to the first to thirteenth IO command processing methods of the first aspect of the present invention, a fourteenth IO command processing method according to the first aspect of the present invention is provided, further comprising: recording a status of command execution in a to-be-processed command set.

[0027] According to the fourteenth IO command processing method of the present invention, a fifteenth IO command processing method according to the first aspect of the present invention is provided, which also includes: selecting one of the pending commands from the pending command set, obtaining the status of the selected command, and continuing to process the selected command based on the status of the selected command, wherein each execution of the command can be a stage of executing the command.

[0028] According to the fourteenth or fifteenth IO command processing method of the first aspect of the present invention, there is provided a sixteenth IO command processing method according to the first aspect of the present invention, which, in response to receiving a programming command, processes the programming command on the corresponding physical LUN; and suspends the processing of the programming command, and records the status of the indicating command processing progress of the programming command in the set of commands to be processed; and in response to resuming the processing of the programming command, queries the processing progress of the programming command on the corresponding physical LUN; if the processing of the programming command has not been completed, continues the processing of the programming command; and suspends the processing of the programming command again.

[0029] According to the fourteenth to sixteenth IO command processing methods of the first aspect of the present invention, a seventeenth IO command processing method according to the first aspect of the present invention is provided, which includes processing a first programming command if there are at least two programming commands accessing the same virtual LUN in the command queue; pausing the processing of the first programming command, and recording the status of the indicating command processing progress of the first programming command in the set of commands to be processed; and processing the second programming command if there are other second programming commands on the virtual LUN that have not yet started to be executed.

[0030] According to the seventeenth IO command processing method of the first aspect of the present invention, an eighteenth IO command processing method according to the first aspect of the present invention is provided, which comprises the following steps: if there is no other second command that has not yet started to be executed on the virtual LUN, selecting a first programming command from the set of commands to be processed, and obtaining the status of the first programming command; if the execution status of the first programming command indicates that it is incomplete, processing the first programming command; and continuously obtaining the execution status of the first programming command from the physical LUN accessed by the first programming command until the execution status of the first programming command indicates that the processing is complete.

[0031] According to the eighth IO command processing method of the first aspect of the present invention, a nineteenth IO command processing method according to the first aspect of the present invention is provided, if the execution status of the first programming command indicates that the processing is completed, continue to select a third programming command from the set of commands to be processed.

[0032] According to a second aspect of the present invention, a first IO command processing method according to the second aspect of the present invention is provided, comprising: obtaining an IO command from a command queue; obtaining a logical LUN number and / or a logical block address from the IO command; obtaining a virtual LUN number corresponding to the logical LUN based on the logical LUN number and / or the logical block address; selecting a processing unit and a physical LUN accessed by the IO command based on the virtual LUN number; issuing a valid chip enable signal to a CE port that provides the physical LUN accessed by the IO command; and issuing an NVM interface command to the accessed physical LUN.

[0033] According to the first IO command processing method of the second aspect of the present invention, a second IO command processing method according to the second aspect of the present invention is provided, wherein the virtual LUN includes multiple physical LUNs; and one or more physical LUNs coupled to different virtual LUNs, or multiple physical blocks provided by one or more physical LUNs coupled to different virtual LUNs are organized as logical LUNs.

[0034] According to the second IO command processing method of the second aspect of the present invention, a third IO command processing method according to the second aspect of the present invention is provided, wherein the logical LUN is mapped to multiple virtual LUNs.

[0035] According to the second IO command processing method of the second aspect of the present invention, a fourth IO command processing method according to the second aspect of the present invention is provided, wherein the logical LUN corresponds to the physical LUN one by one.

[0036] According to the second IO command processing method of the second aspect of the present invention, a fifth IO command processing method according to the second aspect of the present invention is provided, wherein multiple logical blocks with consecutive logical block addresses within the same logical LUN are mapped to different virtual LUNs.

[0037] According to the second IO command processing method of the second aspect of the present invention, a sixth IO command processing method according to the second aspect of the present invention is provided, wherein multiple logical blocks with the same logical block addresses in different logical LUNs are mapped to different virtual LUNs.

[0038] According to the first to sixth IO command processing methods of the second aspect of the present invention, a seventh IO command processing method according to the second aspect of the present invention is provided, wherein a processing unit is provided for each virtual LUN so that a corresponding processing unit is selected according to the virtual LUN number when processing an IO command.

[0039] According to a third aspect of the present invention, a first NVM interface controller according to the third aspect of the present invention is provided, the NVM interface controller includes a command queue and an NVM command processing unit, the NVM command processing unit is coupled to multiple NVM chips, the command queue is used to receive IO commands, the NVM command processing unit is used to obtain IO commands from the command queue, and send NVM interface commands to the NVM chip or receive data or status from the NVM chip according to the instructions of the IO commands, the NVM command processing unit includes multiple processing units, which are used to access the corresponding NVM chip, the NVM command processing unit is coupled to the CE port of the NVM chip through one or more CE expanders, and the NVM command processing unit is also used to send a chip enable signal to the specified NVM chip by setting the CE expander to access the corresponding NVM chip.

[0040] According to the first NVM interface controller of the third aspect of the present invention, a second NVM interface controller according to the third aspect of the present invention is provided, wherein a CE expander is coupled to chip enable (CE) ports of multiple NVM chips, and an NVM command processing unit sends a chip enable or chip disable signal to one of the multiple NVM chips by setting the CE expander.

[0041] According to the first NVM interface controller of the third aspect of the present invention, a third NVM interface controller according to the third aspect of the present invention is provided, wherein a plurality of processing units are coupled to CE ports of a plurality of NVM chips through a plurality of CE expanders, and the plurality of processing units send a chip enable signal or a chip disable signal to a designated NVM chip by setting corresponding CE expanders.

[0042] According to the first to third NVM interface controllers of the third aspect of the present invention, a fourth NVM interface controller according to the third aspect of the present invention is provided, wherein the IO command obtained from the command queue indicates a virtual LUN number, the virtual LUN number is used to indicate a virtual LUN, and the virtual LUN includes multiple physical LUNs.

[0043] According to the first to fourth NVM interface controllers of the third aspect of the present invention, a fifth NVM interface controller according to the third aspect of the present invention is provided, wherein the NVM processing unit is coupled to multiple physical LUNs, and the NVM interface controller is also used to select one of the multiple processing units to process IO commands according to the virtual LUN number.

[0044] According to the first to fifth NVM interface controllers of the third aspect of the present invention, a sixth NVM interface controller according to the third aspect of the present invention is provided, wherein each NVM chip includes multiple physical LUNs, the processing unit is coupled to the multiple physical LUNs through a CE expander; and the CE expander, under the control of the processing unit, sends a valid chip enable signal to the CE port of the physical LUN accessed by the IO command.

[0045] According to the sixth NVM interface controller of the third aspect of the present invention, there is provided a seventh NVM interface controller of the third aspect of the present invention, wherein the CE expander also sends an invalid chip enable signal to the CE ports corresponding to the other physical LUNs among the multiple physical LUNs coupled to the CE expander, except the physical LUN accessed by the IO command, under the control of the processing unit.

[0046] According to the first to seventh NVM interface controllers of the third aspect of the present invention, there is provided an eighth NVM interface controller according to the third aspect of the present invention, wherein the processing unit performs its functions by executing a microinstruction sequence.

[0047] According to the eighth NVM interface controller of the third aspect of the present invention, there is provided a ninth NVM interface controller of the third aspect of the present invention, wherein the microinstruction sequence has multiple execution contexts, and the microinstruction sequence utilizes one of the multiple execution contexts each time it is executed.

[0048] According to the first to ninth NVM interface controllers of the third aspect of the present invention, a tenth NVM interface controller according to the third aspect of the present invention is provided, and the NVM command processing unit is also used to obtain the virtual LUN number and / or virtual block address from the IO command; and select a processing unit according to the virtual LUN number, and the processing unit determines the physical LUN accessed by the IO command and the physical block address on the physical LUN according to the virtual block address.

[0049] According to the tenth NVM interface controller of the third aspect of the present invention, there is provided an eleventh NVM interface controller according to the third aspect of the present invention, wherein the NVM command processing unit accesses blocks of the virtual LUN through the virtual block address, and the number of blocks of the virtual LUN is equal to the sum of the numbers of blocks of multiple physical LUNs included in the virtual LUN.

[0050] According to the first to eleventh NVM interface controllers of the third aspect of the present invention, there is provided a twelfth NVM interface controller according to the third aspect of the present invention, and the NVM command processing unit is further used to obtain the type of the IO command.

[0051] According to the twelfth NVM interface controller of the third aspect of the present invention, a thirteenth NVM interface controller of the third aspect of the present invention is provided. If the IO command is a reset command, the NVM command processing unit is also used to obtain all physical LUNs indicated by the virtual LUN numbers, and send a chip enable signal to all CE ports providing these physical LUNs by setting a CE expander; and send a reset command to these physical LUNs; and process the reset command until it is confirmed that the reset command has been executed on all physical LUNs.

[0052] According to the twelfth NVM interface controller of the third aspect of the present invention, a fourteenth NVM interface controller according to the third aspect of the present invention is provided, and if the IO command is a reset command, the NVM command processing unit is also used to obtain all physical LUNs indicated by the virtual LUN numbers, issue a reset command to one of these physical LUNs each time, and repeatedly issue a reset command to each physical LUN, and issue a chip enable signal to the corresponding CE ports providing these physical LUNs; and process the reset command until all physical LUNs in the virtual LUNs are reset.

[0053] According to the twelfth NVM interface controller of the third aspect of the present invention, a fifteenth NVM interface controller of the third aspect of the present invention is provided, and if the IO command is a programming command, the NVM command processing unit is further used to determine the physical LUN to be accessed and the physical block address on the physical LUN based on the accessed virtual block address, and send a chip enable signal to the CE port providing the physical LUN; and send a programming command to the physical LUN; and process the programming command and obtain the execution status of the programming command until the execution of the programming command is completed.

[0054] According to the first to fifteenth NVM interface controllers of the third aspect of the present invention, there is provided a sixteenth NVM interface controller according to the third aspect of the present invention, the NVM interface controller further storing a set of commands to be processed for recording the status of command execution.

[0055] According to the sixteenth NVM interface controller of the third aspect of the present invention, a seventeenth NVM interface controller according to the third aspect of the present invention is provided, and the NVM command processing unit is also used to select one of the pending commands from the pending command set, obtain the status of the selected command, and execute the selected command, wherein each execution of the command can be a stage of executing the command.

[0056] According to the sixteenth or seventeenth NVM interface controller of the third aspect of the present invention, there is provided an eighteenth NVM interface controller according to the third aspect of the present invention, and the NVM command processing unit is further used for, in response to receiving a programming command, processing the programming command on the corresponding physical LUN; and pausing the execution of the programming command, and recording the status of the indicating command processing progress of the programming command in the pending command set; and in response to resuming the execution of the programming command, querying the processing progress of the programming command on the corresponding physical LUN; if the processing of the programming command has not been completed, continuing the processing of the programming command; and pausing the processing of the programming command again.

[0057] According to the sixteenth to eighteenth NVM interface controllers of the third aspect of the present invention, there is provided a nineteenth NVM interface controller according to the third aspect of the present invention, wherein if there are at least two programming commands for accessing the first virtual LUN in the command queue, the NVM command processing unit is further used to process the first programming command; and to suspend the processing of the first programming command, and to record the status of the indicating command processing progress of the first programming command in the set of commands to be processed; and if there are other second programming commands on the first virtual LUN that have not yet started to be executed, to process the second programming command.

[0058] According to the nineteenth NVM interface controller of the third aspect of the present invention, there is provided a twentieth NVM interface controller according to the third aspect of the present invention, wherein if there are no other second commands that have not yet started to be executed on the first virtual LUN, the NVM command processing unit is further used to select a first programming command from the set of commands to be processed, and obtain the status of the first programming command; if the execution status of the first programming command indicates that it is incomplete, process the first programming command; and query the execution status of the first programming command from the first physical LUN accessed by the first programming command until the execution status of the first programming command indicates that the processing is completed.

[0059] According to the nineteenth NVM interface controller of the third aspect of the present invention, a twenty-first NVM interface controller according to the third aspect of the present invention is provided, and if the execution status of the first programming command indicates that the processing is completed, the NVM command processing unit is also used to select a third programming command from the set of commands to be processed.

[0060] According to the first to fourth NVM interface controllers of the third aspect of the present invention, a twenty-second NVM interface controller according to the third aspect of the present invention is provided, wherein an IO command obtained from a command queue indicates a logical LUN number, and wherein one or more physical LUNs coupled to different virtual LUNs, or multiple physical blocks provided by one or more physical LUNs coupled to different virtual LUNs, are organized into logical LUNs.

[0061] According to the twenty-second NVM interface controller of the third aspect of the present invention, there is provided a twenty-third NVM interface controller according to the third aspect of the present invention, wherein the NVM media interface controller maps a logical LUN to a plurality of virtual LUNs.

[0062] According to the twenty-second NVM interface controller of the third aspect of the present invention, there is provided a twenty-fourth NVM interface controller according to the third aspect of the present invention, wherein the logical LUN corresponds one-to-one to the physical LUN.

[0063] According to the twenty-second NVM interface controller of the third aspect of the present invention, a twenty-fifth NVM interface controller according to the third aspect of the present invention is provided, wherein the NVM media interface controller maps multiple logical blocks with consecutive logical block addresses within the same logical LUN to different virtual LUNs.

[0064] According to the twenty-second NVM interface controller of the third aspect of the present invention, a twenty-sixth NVM interface controller according to the third aspect of the present invention is provided, wherein the NVM media interface controller maps multiple logical blocks with the same logical block addresses within different logical LUNs to different virtual LUNs.

[0065] According to the twelfth to twenty-sixth NVM interface controllers of the third aspect of the present invention, a twenty-seventh NVM interface controller of the third aspect of the present invention is provided, and the NVM command processing unit is also used to obtain the logical LUN number and / or logical block address from the IO command; obtain the number of the virtual LUN corresponding to the logical LUN based on the logical LUN number and / or logical block address; select a processing unit based on the number of the virtual LUN; the selected processing unit is used to send a valid chip enable signal to the CE port of the physical LUN accessed by the IO command through the CE expander; and send an NVM interface command to the accessed physical LUN.

[0066] According to a fourth aspect of the present invention, a solid-state storage device according to the fourth aspect of the present invention is provided, the solid-state storage device comprising a control component and a plurality of NVM chips, the control component being used to access the plurality of NVM chips, the NVM chips comprising one or more physical LUNs, the control component comprising an NVM interface controller as described in any one to seventeen of the third aspect of the present invention, and one or more CE expanders, wherein the NVM interface controller is coupled to the plurality of NVM chips via the one or more CE expanders, and is used to send a chip enable signal to the CE port of the NVM chip providing the accessed physical LUN.

[0067] According to a fifth aspect of the present invention, a program including instruction codes is provided according to the fifth aspect of the present invention. When loaded into a solid-state storage device and executed on a controller of the solid-state storage device, the program enables the controller to execute the IO command processing method as described in the first to nineteenth aspects of the first aspect of the present invention and the first to seventh aspects of the second aspect of the present invention.

[0068] According to a sixth aspect of the present invention, a solid-state storage device according to the sixth aspect of the present invention is provided, the solid-state storage device comprising one or more processors and a memory, the one or more processors executing the IO command processing method as described in items 1 to 19 of the first aspect of the present invention and items 1 to 7 of the second aspect of the present invention by running a program in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0070] Figure 1 A schematic diagram of a storage system with chip enable signal extension in the prior art;

[0071] Figure 2 A block diagram of an NVM interface controller of a solid state drive controller according to an embodiment of the present invention;

[0072] Figure 3 is a block diagram of an NVM interface controller of a solid state drive controller according to yet another embodiment of the present invention;

[0073] Figure 4 is a schematic diagram of a virtual LUN according to an embodiment of the present invention;

[0074] Figure 5 is a block diagram of an NVM interface controller of a solid state drive controller according to another embodiment of the present invention;

[0075] Figure 6 is a flowchart of a NVM command processing unit processing a command according to an embodiment of the present invention;

[0076] Figure 7 is a flowchart of a NVM command processing unit processing a command according to another embodiment of the present invention;

[0077] Figure 8 is a flowchart of a thread processing command of an NVM command processing unit according to yet another embodiment of the present invention;

[0078] Fig. 9 is a block diagram of an NVM interface controller of a solid state drive controller according to still another embodiment of the present invention;

[0079] Fig.10 Schematic diagram of a mapping table from a logical LUN (and a block) to a virtual LUN and a physical LUN according to an embodiment of the present invention.

[0080] Fig.11 A block diagram of an NVM interface controller of a solid state drive controller according to still another embodiment of the present invention; and

[0081] Fig.12 FIG. 4 is a schematic diagram of a mapping table from a logical LUN (and a block) to a virtual LUN and a physical LUN according to another embodiment of the present invention. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0083] Embodiment 1

[0084] Figure 2 is a block diagram of an NVM interface controller of a solid state drive controller according to an embodiment of the present invention. Figure 2 The NVM interface controller in the system includes a command queue 201 and an NVM command processing unit 202. According to an embodiment of the present invention, the command queue 201 is used to receive commands from a user or an upper system. The commands from the user or the upper system may include commands such as read, write, delete, mark as invalid, etc., and may also include commands such as reading the NVM chip status, reading or setting the NVM chip features (Feature), and may also include user-defined commands. The NVM command processing unit 202 is used to obtain commands from the command queue 201, and send NVM interface commands that comply with the NVM chip interface standard to the NVM chip according to the instructions of the commands, or receive data or status from the NVM in accordance with the NVM chip interface standard. The NVM command processing unit 202 is coupled to multiple NVM chips. In Figure 2 In the embodiment, the NVM command processing unit 202 is coupled to four NVM chips through two channels, and each NVM chip includes two LUNs. The NVM chip in channel 1 provides LUN0-LUN3, and the NVM chip in channel 2 provides LUN4-LUN7. It can be understood that the NVM interface controller can be coupled with more channels and access more NVM chips and more LUNs.

[0085] According to an embodiment of the present invention, a plurality of processing units are provided in the NVM command processing unit 202, and the plurality of processing units access the corresponding NVM chip by executing a microinstruction sequence. Among them, the executable microinstruction sequence is called a thread. Since the same microinstruction sequence has its own execution state each time it is executed, multiple threads can be created based on the same microinstruction sequence. The execution state is also stored for each thread in the NVM command processing unit 202. According to an embodiment of the present invention, a thread is created or used based on the LUN to be accessed. For example, thread 1 is used to access LUN1, and / or thread 2 is used to access LUN2.

[0086] Embodiment 2

[0087] Figure 3 is a block diagram of an NVM interface controller of a solid state drive controller according to yet another embodiment of the present invention. Figure 3 The NVM interface controller in the embodiment includes a command queue 201 and an NVM command processing unit 202. The NVM processing unit 202 includes multiple processing units (not shown), and the multiple processing units access the corresponding NVM chip by executing a microinstruction sequence. The executable microinstruction sequence is called a thread. Figure 3 Also shown in FIG. 2 are multiple threads that can be scheduled for execution in the NVM interface controller. When the threads are scheduled for execution, the NVM processing unit 202 accesses multiple NVM chips by setting a CE expander.

[0088] In one example, see Figure 3 , the NVM interface controller is coupled to the CE ports of multiple NVM chips through a CE expander, and by executing microinstructions, the CE expander is set to generate a chip enable signal or a chip disable signal to any one of the multiple NVM chips (or one of the targets), and other similar ports (e.g., DQ, DQS, ALE, CLE, etc.) of these multiple NVM chips share signal lines. For example, by executing the Set_CE microinstruction, the CE expander is informed of the NVM chip to be accessed. For example, to access LUN3, thread 1 executes the Set_CE microinstruction, so that the CE expander sends a valid chip enable signal to the CE port of the NVM 1 chip, and generates an invalid chip signal to the CE ports of NVM 0, NVM2 and NVM3, so that the command issued by thread 1 to access the NVM chip is effective for the NVM1 chip. In this way, the thread can access multiple NVM chips, multiple LUNs or multiple targets.

[0089] As another example, the NVM interface controller is coupled to multiple NVM chips through multiple CE expanders, and executes microinstructions to set each CE expander to send a chip enable signal or a chip disable signal to a designated NVM chip (or, LUN or target).

[0090] Embodiment 3

[0091] Figure 4 is a schematic diagram of a virtual LUN according to an embodiment of the present invention. As an example, thread 2 is coupled to two NVM chips through a CE expander, each NVM chip includes two LUNs (for the purpose of clarity, they are referred to as "physical LUNs"), so that thread 2 can access four physical LUNs. Figure 4 , each physical LUN includes 1024 physical blocks for storing data, and a virtual LUN is provided to represent the four physical LUNs that can be accessed by thread 2 through the CE expander, so that the virtual LUN includes 4096 physical blocks provided by the four physical LUNs. In an embodiment according to the present invention, the virtual LUN is accessed in an address space with a block address range of 0-4095, and thread 2 obtains the physical LUN (e.g., physical LUN3) providing the block according to the block address (e.g., 4000) of the virtual LUN, and instructs the CE expander to send an enable signal to the CE port of the NVM chip (e.g., NVM chip 1) where the physical LUN3 is located, and sends a disable signal to other CE ports.

[0092] Embodiment 4

[0093] Figure 5 1 is a block diagram of an NVM interface controller of a solid state drive controller according to another embodiment of the present invention. According to an embodiment of the present invention, the NVM interface controller receives a command (e.g., User_CMD_Post(LUN, block)) from a user or an upper layer system through a command queue, and the command indicates a LUN and a block to be accessed. The LUN indicated in the command is a virtual LUN, and the block is a block provided by the virtual LUN. For example, the command accesses block 2047 of virtual LUN 3.

[0094] According to an embodiment of the present invention, in response to receiving an IO command indicating a virtual LUN to be accessed, the NVM command processing unit provides a thread for each virtual LUN, and when processing the command, the NVM command processing unit selects a corresponding thread according to the number of the virtual LUN. For example, a command to access virtual LUN3 is processed by thread 3. Thread 3 determines the block to be accessed by physical LUN 3-2 (see FIG. 10 ) according to the block accessed by the command (address 2047). Figure 5) to provide the accessed block, provide a valid chip enable signal to the NVM chip or target providing the physical LUN 3-2 by setting (for example, executing the Set_CE microinstruction) the CE expander, and issue an NVM interface command to the physical LUN 3-2.

[0095] As described above, according to an embodiment of the present invention, by organizing multiple physical LUNs into virtual LUNs, the NVM interface controller can access more physical LUNs without increasing the number of threads (each thread manages access to one virtual LUN), thereby realizing a larger capacity solid state drive. In addition, from the perspective of the upper layer system of the NVM interface controller, the access method of the NVM interface controller has not changed, but the number of blocks included in the virtual LUN has increased, thereby obtaining the ability to access more NVM chips without changing the upper layer system or with very little change.

[0096] Embodiment 5

[0097] Figure 6 1 is a flowchart of a NVM command processing unit processing a command according to an embodiment of the present invention, and is used to process the IO command in Embodiment 4. According to an embodiment of the present invention, the command processing unit of the NVM interface controller obtains an IO command from a command queue, and the command indicates the command type, the virtual LUN number to be accessed, and / or the information of the block address. The command types include programming, erasing, reading, resetting, etc.

[0098] In one example, the command processing unit obtains an IO command from a command queue, the command indicating that the type of the IO command is a reset command, and the command also indicates the virtual LUN number to be accessed (e.g., LUN3). Optionally, the reset command does not include block address information (601). Next, the NVM command processing unit determines the type of the IO command (602), and determines that the IO command is a reset command (613). In response to receiving the reset command, the NVM command processing unit selects the corresponding thread 4 according to the virtual LUN number (614). Thread 4 is designated to process the command to access virtual LUN3.

[0099] Next, the NVM command processing unit obtains all physical LUNs indicated by the virtual LUN numbers (615), and sends an enable signal to the CE pins of the NVM chips or targets providing all these physical LUNs by setting (e.g., executing the Set_CE microinstruction) the CE expander, and sends a reset command to all these physical LUNs (616). The reset command is processed on these physical LUNs, and it is confirmed that the reset command execution is completed (617).

[0100] Optionally, the NVM command processing unit issues a reset command to one of the physical LUNs at a time, and repeatedly issues a reset command to each physical LUN, and sends an enable signal on the corresponding CE pins providing the physical LUNs by setting (e.g., executing a Set_CE microinstruction) the CE expander, and processes the reset command on each physical LUN until all physical LUNs in the virtual LUN are reset.

[0101] In another example, the command processing unit obtains an IO command from a command queue, the command indicating that the type of the IO command is a programming command, and the command also indicating the virtual LUN number (e.g., LUN3) and the block to be accessed, wherein the block is a block provided by the virtual LUN (601). Next, the NVM command processing unit determines the type of the IO command (602), and determines that the IO command is a reset command (623). In response to receiving the programming command, the NVM command processing unit selects the corresponding thread 4 according to the virtual LUN number (624). Thread 4 determines the physical LUN accessed by the programming command according to the block accessed by the command, as well as the physical block address on the physical LUN, and the CE port corresponding to the NVM chip or die (625) that provides the physical LUN.

[0102] Next, thread 4 sends an enable signal to the CE pin of the NVM chip or die providing the physical LUN by setting (e.g., executing the Set_CE microinstruction) the CE expander (626), and issues a programming command to the physical LUN. In response to receiving the programming command, the NVM command processing unit processes the programming command on the corresponding physical LUN and obtains the execution status of the programming command until the execution of the programming command is completed (627).

[0103] Embodiment 6

[0104] Figure 7 The flowchart of the NVM command processing unit processing a command according to another embodiment of the present invention is used to process an IO command. Since a virtual LUN includes multiple physical LUNs, and multiple physical LUNs can be accessed in parallel, it is necessary to provide parallel processing capabilities for commands accessing different physical LUNs on the virtual LUN. A set of pending commands is provided to record the status of the processing progress of the IO commands that do not need to occupy the flash channel temporarily.

[0105] According to an embodiment of the present invention, the command processing unit of the NVM interface controller obtains an IO command from a command queue (701), wherein the IO command indicates the command type, virtual LUN number and / or block address information of the IO command. The NVM command processing unit also records the status of the command indicating the command processing progress in the pending command set (702), selects one of the pending commands from the pending command set (703), obtains the status of the selected command, and executes the selected command. Each execution of the command may be a stage of executing the command (704).

[0106] For example, the command processing unit obtains an IO command from the command queue, and the command indicates that the type of the IO command is a programming command. The command also indicates the virtual LUN number (e.g., LUN3) and the block to be accessed, where the block is a block provided by the virtual LUN. In response to receiving the programming command, the NVM command processing unit selects the corresponding thread 5 according to the virtual LUN number. Thread 5 determines the physical LUN accessed by the programming command, the physical block address on the physical LUN, and the NVM chip or die providing the physical LUN based on the block accessed by the command. Next, thread 5 sends an enable signal to the CE pin of the NVM chip or die providing the physical LUN by setting (e.g., executing the Set_CE microinstruction) the CE expander, and issues a programming command to the physical LUN.

[0107] When executing the first stage of the programming command, the NVM command processing unit sends the address of the programming command and / or the data to be written to the physical LUN corresponding to the programming command, and then records the status of the programming command (for example, processing progress, accessed address and / or storage location of the data to be written) in the pending command set. And when executing the programming command, the programming command is obtained from the pending command set, and the second stage of the command to be executed is determined by using the status of the programming command provided by the pending command set, and then the physical LUN is queried whether the processing of the programming command is completed.

[0108] Between the first stage and the second stage of executing the programming command, the NVM command processing unit may obtain one or more IO commands from the command queue for processing, or may obtain one or more IO commands from the pending command set for processing, thereby providing multiple IO commands to the virtual LUN.

[0109] Preferably, each physical LUN processes only one IO command at a time. The NVM command processing unit also records whether an IO command has been issued to a physical LUN, and selects to process an IO command accessing a physical LUN for which no IO command is being processed.

[0110] Embodiment 7

[0111] Figure 8 The present invention is a flowchart of a thread processing command of an NVM command processing unit according to another embodiment of the present invention, which is used to process IO commands in a queue and process two or more programming commands appearing in the command queue for accessing the same virtual LUN.

[0112] In one example, the command processing unit of the NVM interface controller obtains an IO command from a command queue (801), the command indicating that the IO command is a programming command, and the command also indicates a virtual LUN number and a block to be accessed, wherein the block is a block provided by the virtual LUN. In response to receiving the programming command, the NVM command processing unit selects the corresponding thread 6 according to the virtual LUN number. Thread 6 determines the physical LUN accessed by the programming command and the physical block address on the physical LUN according to the block accessed by the command. Next, thread 6 sends an enable signal to the CE pin of the NVM chip or target where the physical LUN to be accessed is located by setting (e.g., executing the Set_CE microinstruction) the CE expander, and sends a programming command and / or data to the physical LUN to be accessed. And the programming command is processed on the corresponding physical LUN (802).

[0113] Next, the NVM command processing unit suspends processing of the current command (e.g., sends a programming pause command to the accessed physical LUN), and records the status of the current command indicating the command processing progress in the pending command set (803). And it is determined whether there are other commands that have not yet been executed on the current virtual LUN (804). If there are other IO commands that have not yet been executed on the current virtual LUN, the above processing process is repeated to obtain IO commands, process IO commands on the corresponding physical LUN, and optionally, suspend the processed IO commands.

[0114] If there are no other IO commands that have not yet been executed on the current virtual LUN, the NVM command processing unit selects one of the programming commands in the pending command set (805), and obtains the status of the programming command (e.g., extracts information indicating the command type, virtual LUN number and / or block address), and then selects the corresponding thread 7 according to the virtual LUN number accessed by the programming command. Thread 7 determines the physical LUN accessed by the programming command and the physical block address on the physical LUN according to the block accessed by the command (806). Next, thread 7 sets (e.g., executes the Set_CE microinstruction) the CE expander, sends an enable signal to the CE pin of the NVM chip or target where the physical LUN to be accessed is located, sends a query status command to the physical LUN to be accessed, and determines whether the current programming command has been processed (807). If the query status command indicates that the corresponding command (e.g., programming command) has been executed, continue to select other commands in the pending command set until all commands in the pending command set have been processed (808). If the query status command indicates that the corresponding command (eg, programming command) has not been completed, the query status command is again issued to the physical LUN to be accessed according to the status information of the corresponding command.

[0115] Embodiment 8

[0116] Fig. 9 is a block diagram of an NVM interface controller of a solid state drive controller according to still another embodiment of the present invention. According to an embodiment of the present invention, the NVM interface controller receives a command from a user or an upper layer system through a command queue, and the command indicates a LUN and a block to be accessed. The LUN indicated in the command is a logical LUN, and the block is a block provided by the logical LUN. For example, the command accesses block 2047 of logical LUN 3.

[0117] exist Fig. 9 In the embodiment, the logical LUN is composed of physical LUNs coupled to different CE expanders, thereby facilitating the simultaneous execution of multiple commands accessing the same logical LUN on multiple physical LUNs.

[0118] exist Fig. 9 In the embodiment of FIG. 1 , the logical LUN is composed of four physical LUNs. Each physical LUN provides 1024 blocks, so that the block 2047 of the logical LUN3 can be provided by the second physical LUN (referred to as logical LUN 3-1) that constitutes the logical LUN3. See also Fig.10, logical LUN 0 includes physical LUNs (respectively recorded as physical LUN 0-0, physical LUN 1-0, physical LUN 2-0 and physical LUN 3-0) respectively coupled to four CE expanders (respectively recorded as virtual LUN0, virtual LUN1, virtual LUN2 and virtual LUN3), and logical LUN 3 includes physical LUNs (respectively recorded as physical LUN 0-3, physical LUN 1-3, physical LUN 2-3 and physical LUN 3-3) respectively coupled to four CE expanders (respectively recorded as virtual LUN0, virtual LUN1, virtual LUN2 and virtual LUN3). According to an embodiment of the present invention, the NVM command processing unit maintains such Fig.10 In response to obtaining a command from the command queue, the command processing unit processes the command according to the logical LUN number and block address indicated in the command, such as Fig.10 The mapping table shown obtains the virtual LUN (or the thread for accessing the virtual LUN) providing the accessed block and the physical LUN, and instructs the thread associated with the virtual LUN to process the command.

[0119] As an example, in response to a received IO command indicating the block address 2047 of the logical LUN3 to be accessed, the NVM command processing unit determines that thread 8 (see Fig. 9 , the physical LUN3 associated with the virtual LUN1) provides the accessed block; and if the received IO command indicates access to the block 1023 of the logical LUN3, the NVM command processing unit determines that thread 9 (see Fig. 9 , the physical LUN3 associated with the virtual LUN0) provides the accessed block. According to the embodiment of the present invention, thread 8 and thread 9 process the command at the same time. According to the physical LUN accessed, thread 8 and thread 9 provide a valid CE enable signal to the NVM chip or target providing the physical LUN by setting (for example, executing the Set_CE microinstruction) the CE expander, and issue an NVM interface command to the corresponding physical LUN. Since thread 8 accesses the CE expander corresponding to virtual LUN1, and thread 9 accesses the CE expander corresponding to virtual LUN0, there is no conflict in resources (for example, CE expander, physical LUN, etc.) when threads 8 and 9 process IO commands, and they can be processed simultaneously.

[0120] As still another example, the NVM media interface controller maps logical LUNs (and blocks) to virtual LUNs (and physical LUNs) in different ways, such that access to consecutive blocks of the logical LUN is mapped to different virtual LUNs, thereby further improving the parallelism of command processing.

[0121] As still another example, the NVM media interface controller maps commands accessing consecutive blocks within a logical LUN to different virtual LUNs, or maps commands accessing blocks with the same address of multiple logical LUNs to different virtual LUNs.

[0122] As described above, by providing a logical LUN, the NVM command processing unit distributes commands to different threads according to the logical LUN number and the block address. Multiple threads process commands in parallel, which enhances the parallelism of the NVM interface controller's access to the NVM chip.

[0123] Embodiment 9

[0124] Fig.11 is a block diagram of an NVM interface controller of a solid state drive controller according to yet another embodiment of the present invention. According to an embodiment of the present invention, the NVM interface controller receives commands from a user or an upper layer system through a command queue, and the command indicates the LUN and block to be accessed. The LUN indicated in the command is a logical LUN. Fig.11 In an embodiment, the logical LUN has the same size as the physical LUN, and each logical LUN is provided by one physical LUN.

[0125] exist Fig.11 In an embodiment of the present invention, a logical LUN is composed of physical LUNs coupled to different CE expanders, thereby facilitating multiple commands accessing the same logical LUN to be executed on multiple physical LUNs simultaneously. Fig.12 , logical LUN 0 to logical LUN 3 are provided by each physical LUN 0 of virtual LUN 0 to virtual LUN 3 (respectively denoted as physical LUN 0-0, physical LUN 1-0, physical LUN 2-0 and physical LUN 3-0, where the a in front of the mark "ab" indicates the virtual LUN number and the b in the back indicates the physical LUN number in the virtual LUN), and logical LUN 4 to logical LUN 7 are provided by each physical LUN 2 of virtual LUN 0 to virtual LUN 3 (respectively denoted as physical LUN 0-2, physical LUN 1-2, physical LUN 2-2 and physical LUN 3-2). As an example, each NVM chip provides two physical LUNs, and it is advantageous for the NVM interface controller to map multiple consecutive logical LUNs to physical LUNs from different NVM chips, because this can reduce the risk of data being unrecoverable when the NVM chip fails. And mapping the continuous multiple logical LUNs to the NVM chip physical pages coupled to different CE expanders, so that commands to access the continuous multiple logical LUNs can be processed simultaneously without resource (such as CE expander, physical LUN, etc.) conflicts.

[0126] According to an embodiment of the present invention, the NVM command processing unit maintains Fig.12 In response to obtaining a command from the command queue, the command processing unit processes the command according to the logical LUN number indicated in the command through methods such as Fig.12 The mapping table shown obtains the virtual LUN (or the thread for accessing the virtual LUN) and the physical LUN that provide the accessed block, and instructs the thread 10 associated with the accessed virtual LUN to process the command. According to an embodiment of the present invention, the thread 10 processes the command, and the thread 10 provides a valid CE enable signal to the NVM chip or target that provides the physical LUN by setting (for example, executing the Set_CE microinstruction) the CE expander according to the accessed physical LUN, and issues an NVM interface command to the physical LUN.

[0127] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for processing IO commands for a solid-state storage device, characterized in that: include: Get IO commands from the command queue; Obtaining a LUN number and a block address from an IO command; wherein the LUN number is used to indicate a virtual LUN or a logical LUN, the virtual LUN includes a plurality of physical LUNs, the logical LUN includes a plurality of physical blocks provided by one or more physical LUNs from different virtual LUNs or one or more physical LUNs from different virtual LUNs; and wherein a plurality of processing units are provided, a processing unit is provided for each virtual LUN, and the processing unit is coupled to the plurality of physical LUNs via a CE expander; Selecting one or more processing units from the plurality of processing units according to the LUN number, wherein the corresponding processing unit is selected according to the LUN number indicating the virtual LUN; Each processing unit determines the physical LUN accessed by the IO command and the physical block address on the physical LUN according to the block address; sends a valid chip enable signal to the CE port providing the physical LUN accessed by the IO command; and sends an NVM interface command to the accessed physical LUN, wherein: Multiple processing units execute one or more IO commands in parallel.

2. The IO command processing method according to claim 1, characterized in that: If the LUN number indicates a logical LUN, the number of the virtual LUN corresponding to the logical LUN is obtained according to the logical LUN number and / or the logical block address; a processing unit and a physical LUN accessed by the IO command are selected according to the number of the virtual LUN; a valid chip enable signal is sent to the CE port that provides the physical LUN accessed by the IO command; and an NVM interface command is sent to the accessed physical LUN.

3. The IO command processing method according to claim 2, wherein: Each processing unit executes multiple IO commands in parallel, including: Each processing unit records the status of the indicated processing progress of the IO command in the command queue in the pending command set; when executing the IO command, the status of the IO command is obtained from the pending command set, and the selected IO command is executed according to the status of the IO command, wherein each execution of the IO command is a stage of executing the command, and one or more IO commands can be obtained from the command queue between two adjacent stages for processing, and the one or more IO commands are provided to the virtual LUN corresponding to the virtual LUN number.

4. The IO command processing method according to any one of claims 1 to 3, characterized in that: Map a logical LUN to multiple virtual LUNs; or map multiple logical blocks with consecutive logical block addresses in the same logical LUN to different virtual LUNs; or map multiple logical blocks with the same logical block addresses in different logical LUNs to different virtual LUNs.

5. The IO command processing method according to claim 4, characterized in that: If a logical LUN is mapped to multiple virtual LUNs, multiple processing units execute one or more IO commands in parallel, including: In response to the received multiple IO commands indicating access to different logical blocks of the same logical LUN, and the different logical blocks correspond to different virtual LUNs, the multiple processing units corresponding to the different virtual LUNs execute the multiple IO commands in parallel.

6. The IO command processing method according to claim 4 or 5, characterized in that: If multiple logical blocks with consecutive logical block addresses in the same logical LUN are mapped to different virtual LUNs; or multiple logical blocks with the same logical block addresses in different logical LUNs are mapped to different virtual LUNs, multiple processing units execute one or more IO commands in parallel, including: In response to a received IO command indicating access to consecutive logical blocks within the same logical LUN or indicating access to multiple logical blocks with the same logical block address within different logical LUNs, the IO command is mapped to different virtual LUNs, and multiple processing units corresponding to the different virtual LUNs execute the IO command in parallel.

7. A solid-state storage device, comprising a control component and a plurality of NVM chips, wherein the control component is used to access the plurality of NVM chips, the NVM chips comprising one or more physical LUNs, characterized in that: The control component includes an NVM interface controller and one or more CE expanders, wherein the NVM interface controller is coupled to multiple NVM chips through the one or more CE expanders, and is used to send a chip enable signal to the CE port of the NVM chip providing the accessed physical LUN; and send an NVM interface command to the accessed physical LUN; wherein, The NVM interface controller includes an NVM command processing unit, the NVM command processing unit includes a plurality of processing units, a processing unit is provided for each virtual LUN, the processing unit is coupled to the plurality of physical LUNs via a CE expander; In response to receiving one or more IO commands, the NVM command processing unit obtains a virtual LUN number and a block address from the IO command; and selects one or more processing units from the plurality of processing units according to the LUN number indicating the virtual LUN; wherein the LUN number is used to indicate a virtual LUN or a logical LUN, the virtual LUN includes a plurality of physical LUNs, the logical LUN includes one or more physical LUNs from different virtual LUNs or a plurality of physical blocks provided by one or more physical LUNs from different virtual LUNs; Each processing unit determines the physical LUN accessed by the IO command and the physical block address on the physical LUN based on the block address; sends a valid chip enable signal to the CE port that provides the physical LUN accessed by the IO command, and sends an NVM interface command to the accessed physical LUN, wherein multiple processing units execute one or more IO commands in parallel.

8. The solid-state storage device according to claim 7, wherein: The NVM interface controller also stores a pending command set for recording the status of command execution; selects one of the pending commands from the pending command set, obtains the status of the selected command, and executes the selected command, wherein each execution of the command may be a stage of executing the command, and one or more IO commands may be obtained from the command queue for processing between two adjacent stages.

9. A solid-state storage device, comprising one or more processors and a memory, wherein the one or more processors execute the IO command processing method according to any one of claims 1 to 6 by running a program in the memory.

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