Integrated computing devices, integrated circuit chips, circuit boards, and computing methods

Abstract

This disclosure discloses an integrated computing device, an integrated circuit chip, a circuit board, and a method for performing computational operations using the aforementioned integrated computing device. The integrated computing device may be included in a combined processing unit, which may further include a general interconnect interface and other processing units. The integrated computing device interacts with other processing units to jointly complete user-specified computational operations. The combined processing unit may also include a storage device connected to the device and other processing units respectively, for storing data from the device and other processing units. The solution disclosed herein can improve the operational efficiency of computations in various data processing fields, including, for example, artificial intelligence, thereby reducing the overall overhead and cost of computation.

Description

Technical Field

[0001] This disclosure generally relates to the field of data processing. More specifically, this disclosure relates to an integrated computing device, an integrated circuit chip, a circuit board, and a method for performing computational operations using the aforementioned integrated computing device. Background Technology

[0002] Current artificial intelligence computations often involve a large amount of data processing, such as convolution operations and image processing. As the amount of data increases, the computational and storage requirements for data operations, such as matrix operations, increase dramatically due to the larger data scale. Current computational methods typically utilize general-purpose processors such as central processing units ("CPUs") or graphics processing units ("GPUs"). However, general-purpose processors often have high power consumption due to their versatility and high component redundancy, thus limiting their performance.

[0003] Furthermore, existing processing circuits typically employ a single hardware architecture, limiting their ability to handle operations within a specific architecture and preventing the flexible selection of suitable processing circuits based on actual needs. Additionally, for some fixed hardware architectures using hard-wired connections, as data volume increases or data format changes, not only may certain types of operations become unsupportable, but their performance may be severely limited during computation, even rendering them inoperable. Summary of the Invention

[0004] To at least address the shortcomings of the existing technology described above, this disclosure provides a solution that supports multiple types of operations and operating modes, improves computational efficiency, and saves computational costs and overhead. Specifically, this disclosure provides the aforementioned solution in the following aspects.

[0005] In a first aspect, this disclosure provides an integrated computing device, including a main control circuit, a first main processing circuit, and a second main processing circuit, wherein:

[0006] The main control circuit is configured to acquire calculation instructions, parse the calculation instructions to obtain operation instructions, and send the operation instructions to at least one of the first main processing circuit and the second main processing circuit.

[0007] The first main processing circuit includes one or more sets of pipelined operation circuits, wherein each set of pipelined operation circuits is configured to perform pipelined operations based on received data and the operation instructions; and

[0008] The second main processing circuit includes multiple sub-processing circuits, each of which is configured to perform multi-threaded operations based on the received data and the arithmetic instructions.

[0009] In a second aspect, this disclosure provides an integrated circuit chip including an integrated computing device comprising the foregoing and several embodiments described below.

[0010] In a third aspect, this disclosure provides a board including the aforementioned integrated circuit chip.

[0011] In a fourth aspect, this disclosure provides a method for performing computational operations using an integrated computing device, wherein the integrated computing device includes a main control circuit, a first main processing circuit, and a second main processing circuit, the method comprising:

[0012] The main control circuit is used to acquire calculation instructions and parse the calculation instructions to obtain operation instructions, and the operation instructions are sent to at least one of the first main processing circuit and the second main processing circuit;

[0013] Utilizing one or more sets of pipelined operation circuits included in the first main processing circuit to perform pipelined operations based on the received data and the operation instructions; and

[0014] Multiple sub-processing circuits included in the second main processing circuit are used to perform multi-threaded operations based on the received data and the operation instructions.

[0015] By utilizing the integrated computing devices, integrated circuit chips, boards, and methods disclosed herein, operational limitations under a single type of hardware architecture can be overcome, improving the operational efficiency of various data processing fields, including, for example, artificial intelligence, in data processing and computation, reducing data computation time and power consumption, and lowering computational overhead and cost. Attached Figure Description

[0016] The above and other objects, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0017] Figure 1 This is a general architecture diagram of an integrated computing device according to embodiments of the present disclosure;

[0018] Figure 2 This is an example specific architecture diagram illustrating an integrated computing device according to embodiments of this disclosure;

[0019] Figure 3 This is an example structural diagram illustrating a first main processing circuit according to an embodiment of the present disclosure;

[0020] Figure 4a4b and 4c are schematic diagrams illustrating matrix transformations performed by a data conversion circuit according to an embodiment of this disclosure;

[0021] Figure 5a 5b, 5c and 5d are schematic diagrams illustrating various connection relationships of a plurality of sub-processing circuits according to embodiments of the present disclosure;

[0022] Figure 6a 6b, 6c and 6d are schematic diagrams illustrating various additional connection relationships of a plurality of sub-processing circuits according to embodiments of the present disclosure;

[0023] Figure 7a and Figure 7b These are schematic diagrams showing different loop structures of the sub-processing circuits according to embodiments of this disclosure;

[0024] Figure 8a and Figure 8b These are schematic diagrams illustrating different loop structures of the sub-processing circuits according to embodiments of this disclosure;

[0025] Figure 9 This is a schematic architecture diagram showing an integrated computing device and a processing circuit according to an embodiment of the present disclosure;

[0026] Figure 10 This is a simplified flowchart illustrating a method for performing computational operations using an integrated computing device according to an embodiment of this disclosure;

[0027] Figure 11 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

[0028] Figure 12 This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation

[0029] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a general architecture diagram illustrating an integrated computing device 100 according to an embodiment of this disclosure. Figure 1As shown, the integrated computing device 100 disclosed herein may include a main control circuit 102, a first main processing circuit 104, and a second main processing circuit 106. In various arithmetic operations, such as computational operations, the main control circuit may be configured to acquire computational instructions, parse the computational instructions to obtain arithmetic instructions, and send the arithmetic instructions to at least one of the first and second main processing circuits. According to the scheme disclosed herein, the computational instructions may be a form of hardware instruction and include one or more opcodes, each opcode representing one or more specific operations to be performed by the first or second main processing circuit. These operations may include different types of operations depending on the application scenario, such as arithmetic operations like addition or multiplication, logical operations, comparison operations, or table lookup operations, or any combination of the aforementioned types of operations. Accordingly, in this disclosure, the arithmetic instructions may be one or more microinstructions executed internally by the processing circuit after parsing the computational instructions. Specifically, an arithmetic instruction may include one or more microinstructions corresponding to an opcode in the computational instruction to complete one or more operations.

[0032] In one embodiment, during the parsing of the calculation instruction, the main control circuit 102 can be configured to acquire instruction identification information in the calculation instruction and send the operation instruction to at least one of the first main processing circuit and the second main processing circuit according to the instruction identification information. It can be seen that, with the help of the aforementioned instruction identification information, the main control circuit can selectively send operation instructions to the first main processing circuit and / or the second main processing circuit identified in the instruction identification information. Furthermore, depending on the application scenario, the operation instruction obtained after parsing the calculation instruction can be an operation instruction decoded by the main control circuit or an operation instruction not decoded by the main control circuit. When the operation instruction is an operation instruction not decoded by the main control circuit, the first and second main processing circuits can include corresponding decoding circuits to perform the decoding of the operation instruction, for example, to obtain multiple microinstructions.

[0033] In another embodiment, during the parsing of the calculation instructions, the main control circuit can be configured to decode the acquired calculation instructions, and then, based on the decoding result and the operating states of the first and second main processing circuits, send the calculation instructions to at least one of the first and second main processing circuits. In this embodiment, both the first and second main processing circuits support non-specific operations of the same type. Therefore, to improve the utilization rate of the main processing circuits and increase computational efficiency, the calculation instructions can be sent to the main processing circuits with low utilization or in an idle state.

[0034] In one or more embodiments, the first main processing circuit 104 may include one or more sets of pipelined operation circuits, wherein each set of pipelined operation circuits can be configured to perform pipelined operations based on received data and operation instructions. In some application scenarios, each set of pipelined operation circuits may include at least one arithmetic unit (e.g., one or more adders) to perform a single-level pipelined operation. Further, when the arithmetic units included in each set of pipelined operation circuits need to be hierarchical or include multiple types of arithmetic units, the set of pipelined operation circuits can form a multi-level operation pipeline and can be configured to perform multi-level pipelined operations. For example, the structure of a set of pipelined operation circuits may include a three-level pipeline consisting of a first-level adder, a second-level multiplier, and a third-level adder to perform addition and multiplication operations. As another example, the structure of a set of pipelined operation circuits may include a three-level pipeline consisting of a multiplier, an adder, and a nonlinear arithmetic unit for pipelined completion of addition, multiplication, and activation operations.

[0035] In some embodiments, the second main processing circuit 106 may include multiple sub-processing circuits, each of which can be configured to perform multi-threaded operations based on received data and processing instructions. In different application scenarios, the connection between the multiple sub-processing circuits can be either a hard connection via hardwired routing or a logical connection configured according to, for example, microinstructions, to form a topology of various sub-processing circuit arrays. For example, the aforementioned multiple sub-processing circuits can be connected and arranged in a one-dimensional or multi-dimensional array topology (as shown in Figures 5 and 6), and each sub-processing circuit can be connected to other sub-processing circuits within a certain range, in a specified direction, and at predetermined intervals. Furthermore, the multiple sub-processing circuits can be cascaded through the connections to form one or more closed loops (as shown in Figures 7 and 8).

[0036] Figure 2 This is an example specific architecture diagram illustrating an integrated computing device 200 according to an embodiment of this disclosure. From Figure 2 As can be seen from this, the integrated computing device 200 not only includes Figure 1 The integrated computing device 100 includes a main control circuit 102, a first main processing circuit 104, and a second main processing circuit 106. Further illustrations show multiple circuits included in the first main processing circuit 104 and the second main processing circuit 106. Therefore, regarding... Figure 1 The described technical details also apply to Figure 2 The content shown is as described above. Given that the preceding text has already incorporated... Figure 1 The functions of the main control circuit, the first main processing circuit, and the second main processing circuit have been described in detail, and will not be repeated below.

[0037] like Figure 2As shown, the first main processing circuit 104 may include multiple sets of pipelined operation circuits 109, wherein each set of pipelined operation circuits may include one or more arithmetic units, and when each set of pipelined operation circuits includes multiple arithmetic units, the multiple arithmetic units may be configured to perform multi-level pipelined operations, that is, to form a multi-level operation pipeline.

[0038] In some application scenarios, the pipelined computation circuit disclosed herein can support unary operations (i.e., operations with only one input data). Taking the operation at the scale layer + ReLU layer in a neural network as an example, suppose the computation instruction to be executed is expressed as result = relu(a*ina + b), where ina is the input data (e.g., a vector or matrix), and a and b are computational constants. For this computation instruction, a three-stage pipelined computation circuit, including a multiplier, an adder, and a nonlinear operator, disclosed herein can be used to perform the operation. Specifically, the multiplier of the first-stage pipeline can be used to calculate the product of the input data ina and a to obtain the first-stage pipelined computation result. Next, the adder of the second-stage pipeline can be used to perform an addition operation on the first-stage pipelined computation result (a*ina) and b to obtain the second-stage pipelined computation result. Finally, the ReLU activation function of the third-stage pipeline can be used to activate the second-stage pipelined computation result (a*ina + b) to obtain the final computation result result.

[0039] In some application scenarios, the pipelined arithmetic circuit disclosed herein can support binary operations (e.g., the convolution calculation instruction result = conv(ina, inb)) or ternary operations (e.g., the convolution calculation instruction result = conv(ina, inb, bias)). The input data inina, inb, and bias can be vectors (e.g., integer, fixed-point, or floating-point data) or matrices. Taking the convolution calculation instruction result = conv(ina, inb) as an example, the convolution operation expressed by this calculation instruction can be executed using multiple multipliers, at least one adder tree, and at least one nonlinear arithmetic unit included in the three-stage pipelined arithmetic circuit structure. The two input data inina and inb can be, for example, neuron data. Specifically, the first-stage pipelined multiplier in the three-stage pipelined arithmetic circuit can first be used for calculation, thereby obtaining the first-stage pipelined operation result product = inina * inb (considered a micro-instruction in the arithmetic instruction, corresponding to the multiplication operation). Then, the addition tree in the second-stage pipelined circuit can be used to perform a summation operation on the first-stage pipelined result "product" to obtain the second-stage pipelined result "sum". Finally, the nonlinear arithmetic unit in the third-stage pipelined circuit is used to perform an activation operation on "sum" to obtain the final convolution result.

[0040] In one application scenario, each pipelined arithmetic circuit includes one or more arithmetic units that can perform the aforementioned four arithmetic operations, as well as various other operations such as table lookup and data type conversion. For example, in data type conversion operations, when the input data ina is a 32-bit floating-point data (represented as float32), it can be converted into the required data type such as a 16-bit floating-point data (represented as float16), a 32-bit fixed-point data (represented as fix32), or an 8-bit integer data (represented as int8) according to the actual operation requirements. Depending on the operational requirements, the pipelined arithmetic circuit disclosed herein can not only support the above-mentioned conversion operations of various data types, but also support functions such as absolute value calculation and hardening operations of various data types.

[0041] In one embodiment, the first main processing circuit 104 may further include an arithmetic processing circuit 111, which may be configured to preprocess data (e.g., input neurons) before the pipelined arithmetic circuit performs arithmetic operations or postprocess data (e.g., output neurons) after the arithmetic operations according to arithmetic instructions. In some embodiments, the arithmetic processing circuit 111 may also be connected to... Figure 9 The processing circuit 112 shown in the diagram works in conjunction with the circuit to complete the expected computational operations. In some application scenarios, the aforementioned preprocessing and postprocessing may include, for example, data splitting and / or data concatenation operations. In the scenario of performing a data splitting operation, assuming that before performing operations on a data N of a specified bit width, arranged in rows (e.g., arranged in a matrix), the computational processing circuit can split the data N into even-numbered rows (denoted as N_2i, where i can be a natural number greater than or equal to 0) and odd-numbered rows (denoted as N_2i+1). Further, in the scenario of performing a data concatenation operation, the lower 256 bits of the even-numbered rows "N_2i" of the split data N in the previous example can be concatenated with the lower 256 bits of the odd-numbered rows "N_2i+1" as the higher bits, according to predetermined requirements, thereby forming a new data with 512 bits.

[0042] In other application scenarios, when processing the data M obtained after performing operations (e.g., in matrix arrangement), the processing circuit can first split the lower 256 bits of the even-numbered rows of data M into 8-bit units to obtain 32 even-numbered rows of data units (represented as M_2i0 to M_2i respectively). 31 Similarly, the lower 256 bits of the odd-numbered rows of data M can also be split into 8-bit units to obtain 32 odd-numbered rows of data units (represented as M_(2i+1)0 to M_(2i+1) respectively). 31Furthermore, the 32 odd-numbered row units and 32 even-numbered row units are arranged alternately according to the data bit order from low to high, with even-numbered rows preceding odd-numbered rows. Specifically, even-numbered row unit 0 (M_2i0) is placed in the low position, followed by odd-numbered row unit 0 (M_(2i+1)0). Then, even-numbered row unit 1 (M_2i1) is arranged, and so on, until odd-numbered row unit 31 (M_(2i+1)0) is completed. 31 When arranging the data, 64 units of data are spliced ​​together to form a new 512-bit data.

[0043] In one embodiment, the first main processing circuit 104 may further include a data conversion circuit 113, which may be configured to perform a data conversion operation according to the arithmetic instructions. In some arithmetic operations, when the data is a matrix, the data conversion operation may be a transformation of the arrangement of matrix elements. This transformation may, for example, include matrix transpose and mirroring (to be discussed later). Figures 4a-4c Description), matrix rotation at predetermined angles (e.g., 90 degrees, 180 degrees, or 270 degrees) and matrix dimension transformation.

[0044] Furthermore, the second main processing circuit 106 may include multiple sub-processing circuits 115. Each sub-processing circuit may include a logic operation circuit 1151, which can be configured to perform logical operations according to operation instructions and received data, such as performing logical operations like AND, OR, NOT, shift operations, or comparison operations on the received data. Furthermore, each sub-processing circuit may also include an arithmetic operation circuit 1153, which can be configured to perform arithmetic operations, such as linear operations like addition, subtraction, or multiplication.

[0045] In one embodiment, each sub-processing circuit may include a storage circuit 1152, which includes a data storage circuit and / or a predicate storage circuit. The data storage circuit may be configured to store at least one of the computational data (e.g., pixels) and intermediate computation results of the sub-processing circuit. Further, the predicate storage circuit may be configured to store the predicate storage circuit number and predicate information of each sub-processing circuit obtained using the computational instructions. In specific storage applications, the storage circuit 1152 may be implemented using registers or static random access memory (SRAM) as needed.

[0046] In one application scenario, the predicate storage circuit may include *a* 1-bit registers for storing predicate information. Further, the sequence numbers of the *a* 1-bit registers can be represented by *b* binary numbers, where *b* >= log₂(a). For example, suppose the predicate storage circuit in a sub-processing circuit may include 32 1-bit registers numbered sequentially from 00000 to 11111. Thus, the sub-processing circuit can read the predicate information from the register with sequence number "00101" according to the register sequence number "00101" specified in the received arithmetic instruction.

[0047] In one embodiment, the predicate storage circuit can be configured to update the predicate information according to the operation instructions. For example, the predicate information can be updated directly according to the configuration information in the operation instructions, or the configuration information can be obtained according to the storage address of the configuration information provided in the operation instructions to update the predicate information. During the operation of the sub-processing circuit, the predicate storage circuit can also update the predicate information according to the comparison result of each sub-processing circuit (which is a form of operation result in the context of this disclosure). For example, the predicate information can be updated by comparing the input data received by the sub-processing circuit with the stored data in its data storage circuit. When the input data is greater than the stored data, the predicate information of the sub-processing circuit is set to 1. Conversely, when the input data is less than the stored data, the predicate information is set to 0, or its original value is maintained.

[0048] Before executing the operation, each sub-processing circuit can determine whether to execute the operation instruction based on the information in the operation instruction. Furthermore, each sub-processing circuit can be configured to obtain the predicate information corresponding to the predicate storage circuit according to the predicate storage circuit number in the operation instruction, and determine whether to execute the operation instruction based on the predicate information. For example, if the value obtained by the sub-processing circuit from reading the predicate information according to the predicate storage circuit number specified in the operation instruction is 1, it indicates that the sub-processing circuit executes the operation instruction (e.g., it can instruct the sub-processing circuit to read the data pointed to in the instruction and store the read data in the data storage circuit of the sub-processing circuit). Conversely, if the value obtained by the sub-processing circuit from reading the predicate information according to the predicate storage circuit number specified in the operation instruction is 0, it indicates that the sub-processing circuit does not execute the operation instruction.

[0049] In one embodiment, the second main processing circuit 106 may further include a data processing circuit 117, which may include at least one of a pre-processing circuit and a post-processing circuit. The pre-processing circuit may be configured to perform pre-processing operations on the computational data before the sub-processing circuit performs the computation (to be discussed later). Figure 7b (Description), for example, performing data splicing or data placement operations. The post-processing circuit can be configured to perform post-processing operations on the calculation results after the sub-processing circuit performs the calculations, such as performing data restoration or data compression.

[0050] To enable data transmission and storage, the integrated computing device 200 disclosed herein may further include a main storage circuit 108, which can receive and store data from the main control circuit as input data for the first and / or second main processing circuits. Specifically, the main storage circuit can be further divided according to the storage method or the characteristics of the stored data. The main storage circuit 108 may include at least one of a main storage module 119 and a main cache module 121. The main storage module 119 may be configured to store data to be performed in the first and / or second main processing circuits (e.g., neuron or pixel data in a neural network) and the results of the operations (e.g., convolution results in a neural network). The main cache module 121 may be configured to cache intermediate operation results after at least one of the first and second main processing circuits has performed an operation.

[0051] In the interaction between the main memory circuit and the first main processing circuit, the pipelined operation circuit in the first main processing circuit can also perform corresponding operations using a mask stored in the main memory circuit. For example, during the execution of an operation, the pipelined operation circuit can read a mask from the main memory circuit and use the mask to indicate whether the data for the operation performed in the pipelined operation circuit is valid. The main memory circuit can not only perform internal storage applications, but also has the function of interacting with storage devices outside the integrated computing device disclosed herein, for example, by exchanging data with external storage devices through direct memory access (“DMA”).

[0052] The above text combined Figures 1-2 The architecture and functions of the integrated computing device have been described in detail below, which will be combined with... Figure 3 , Figures 4a to 4c An exemplary description is provided for the specific application of the first main processing circuit.

[0053] Figure 3 This is an example structural diagram illustrating a first main processing circuit according to an embodiment of this disclosure. Given the detailed description of the functionality of the first main processing circuit architecture above, the following will further explain the collaborative relationships between multiple sets of pipelined operation circuits and between multiple pipeline stages within the first main processing circuit.

[0054] like Figure 3As shown, the first main processing circuit 104 may include one or more sets of pipelined operation circuits 109 (two sets shown in the figure). Each set of pipelined operation circuits may include one or more levels of pipelined operation circuits (from the first level to the Nth level pipelined operation circuit shown in each set in the figure). The one or more levels of pipelined operation circuits can execute one or more levels of pipelined operations according to the received data and operation instructions. In the application of multi-level pipelined operation, the structure of a set of pipelined operation circuits may include one or more types of multiple arithmetic units such as counters, adders, multipliers, addition trees, accumulators, and nonlinear arithmetic units to perform multi-level pipelined operations. Furthermore, depending on the application scenario, multi-level pipelined operations can be executed serially or in parallel. As those skilled in the art will understand, an operation instruction disclosed herein can be executed by a set of multi-level pipelined operation circuits. The operation instruction includes multiple serial operations, and one operation can be executed by the first level, second level, or Nth level pipelined operation circuit in a set of pipelined operation circuits to complete the operation instruction. For example, in conjunction with the foregoing Figure 2 The convolution operation performed by the three-stage pipelined arithmetic circuit is described as a serial pipelined arithmetic. Furthermore, when multiple sets of pipelined arithmetic circuits 109 are performing arithmetic operations, they can execute multiple arithmetic instructions simultaneously, that is, parallel operations between multiple instructions.

[0055] In some applications, unused stages of pipelined computation can be bypassed. This means that only one or more stages of a multi-stage pipelined computation can be used as needed, without requiring the computation to go through all stages. For example, in calculating Euclidean distance, assuming the instruction is dis = sum((ina - inb)^2), only a few stages of pipelined computation consisting of adders, multipliers, adder trees, and accumulators can be used to obtain the final result. Unused stages can be bypassed before or during the pipelined computation.

[0056] In the aforementioned pipelined operation, each pipelined circuit can execute the pipelined operation independently. However, multiple pipelined circuits can also execute the pipelined operation collaboratively. For example, the output of the first and second stages of the first pipelined circuit, after performing serial pipelined operations, can be used as the input to the third stage of another pipelined circuit. As another example, the first and second stages of the first pipelined circuit can perform parallel pipelined operations and output their respective pipelined operation results as the input to the first and / or second stage pipelined operations of another pipelined circuit.

[0057] Figure 4aFigures 4b and 4c are schematic diagrams illustrating matrix transformations performed by the data conversion circuit according to an embodiment of this disclosure. To better understand the transformation operations performed by the data conversion circuit 113 in the first main processing circuit, the transpose and horizontal mirroring operations of the original matrix will be described further below as examples.

[0058] like Figure 4a As shown, the original matrix is ​​an (M+1) row × (N+1) column matrix. Depending on the application requirements, the data conversion circuit can... Figure 4a The original matrix shown is transformed by transposing it to obtain, as shown below. Figure 4b The matrix shown is an example. Specifically, the data conversion circuit can swap the row and column indices of elements in the original matrix to form a transpose matrix. Figure 4a The coordinates of the element "10" in the 1st row and 0th column of the original matrix shown are... Figure 4b The coordinates in the transpose matrix shown are in row 0, column 1. And so on, in... Figure 4a The coordinates of the element "M0" in the (M+1)th row and 0th column of the original matrix are shown. Figure 4b The coordinates in the transpose matrix shown are in row 0 and column M+1.

[0059] like Figure 4c As shown, the data conversion circuit can... Figure 4a The original matrix shown is horizontally mirrored to form a horizontally mirrored matrix. Specifically, the data conversion circuit can use the horizontal mirroring operation to convert the order of elements in the original matrix from the first row to the last row to the first row, while keeping the column numbers of the elements in the original matrix unchanged. Figure 4a The coordinates in the original matrix shown are the element "00" in the 0th row and 0th column and the element "10" in the 1st row and 0th column, respectively. Figure 4c The coordinates in the horizontal mirror matrix shown are respectively at row M+1, column 0 and row M, column 0. And so on, in... Figure 4a The coordinates of the element "M0" in the (M+1)th row and 0th column of the original matrix are shown. Figure 4c The coordinates shown in the horizontal mirror matrix are in row 0 and column 0.

[0060] Figure 5aImages 5b, 5c, and 5d are schematic diagrams illustrating various connection relationships of multiple sub-processing circuits according to embodiments of the present disclosure. The multiple sub-processing circuits of the present disclosure can be connected in a one-dimensional or multi-dimensional array topology. When the multiple sub-processing circuits are connected in a multi-dimensional array, the multi-dimensional array can be a two-dimensional array, and the sub-processing circuit located in the two-dimensional array can be connected to one or more other sub-processing circuits in the same row, column, or diagonal in at least one direction, with a predetermined two-dimensional spacing pattern. The predetermined two-dimensional spacing pattern can be associated with the number of sub-processing circuits spaced apart in the connection. Figures 5a to 5c Examples are shown of various forms of two-dimensional array topologies among multiple sub-processing circuits.

[0061] like Figure 5a As shown, five sub-processing circuits are connected to form a simple two-dimensional array. Specifically, with one sub-processing circuit as the center of the two-dimensional array, one sub-processing circuit is connected to each of the four horizontal and vertical directions relative to that sub-processing circuit, thus forming a two-dimensional array with three rows and three columns. Furthermore, since the sub-processing circuit located at the center of the two-dimensional array is directly connected to the sub-processing circuits adjacent to the preceding and following columns in the same row, and to the sub-processing circuits adjacent to the preceding and following rows in the same column, the number of intervening sub-processing circuits (referred to as the "interval number") is 0.

[0062] like Figure 5b As shown, four rows and four columns of sub-processing circuits can be connected to form a two-dimensional Torus array. Each sub-processing circuit is connected to its adjacent preceding and following rows and columns, respectively, meaning the number of intervals between adjacent sub-processing circuits is 0. Furthermore, the first sub-processing circuit in each row or column of this two-dimensional Torus array is also connected to the last sub-processing circuit in that row or column, with the number of intervals between the first and last connected sub-processing circuits in each row or column being 2.

[0063] like Figure 5c As shown, the four rows and four columns of sub-processing circuits can also be connected to form a two-dimensional array where the interval between adjacent sub-processing circuits is 0 and the interval between non-adjacent sub-processing circuits is 1. Furthermore, in this two-dimensional array, adjacent sub-processing circuits in the same row or column are directly connected, i.e., the interval is 0, while non-adjacent sub-processing circuits in the same row or column are connected to sub-processing circuits with an interval of 1. It can be seen that when multiple sub-processing circuits are connected to form a two-dimensional array, Figure 5b and Figure 5cThe sub-processing circuits shown in the same row or column can have different numbers of intervals. Similarly, in some scenarios, sub-processing circuits in the diagonal direction can also be connected with different numbers of intervals.

[0064] like Figure 5d As shown, using four such Figure 5b The illustrated two-dimensional Torus array can be arranged into four layers at predetermined intervals and connected to form a three-dimensional Torus array. This three-dimensional Torus array, based on the two-dimensional Torus array, utilizes an interval pattern similar to that between rows and columns for inter-layer connections. For example, firstly, sub-processing circuits in adjacent layers in the same row and column are directly connected, i.e., the interval number is 0. Next, the sub-processing circuits in the same row and column of the first and last layers are connected, i.e., the interval number is 2. Ultimately, a four-layer, four-row, four-column three-dimensional Torus array can be formed.

[0065] Through the examples above, those skilled in the art will understand that the connection relationships of other multidimensional arrays of sub-processing circuits can be formed on the basis of a two-dimensional array by adding new dimensions and increasing the number of sub-processing circuits. In some application scenarios, the solution disclosed herein can also configure logical connections of sub-processing circuits using configuration instructions. In other words, although there may be hardwired connections between sub-processing circuits, the solution disclosed herein can also selectively connect some sub-processing circuits or selectively bypass some sub-processing circuits through configuration instructions to form one or more logical connections. In some embodiments, the aforementioned logical connections can also be adjusted according to the actual computational needs (e.g., data type conversion). In summary, for different computing scenarios, the solution disclosed herein can configure the connections of sub-processing circuits, including, for example, configuring them as matrices or as one or more closed computational loops.

[0066] Figure 6a Figures 6b, 6c, and 6d are schematic diagrams illustrating various additional connection relationships of multiple sub-processing circuits according to embodiments of the present disclosure. As can be seen from the figures, Figures 6a to 6d Is Figures 5a to 5d This is another exemplary connection relationship of the multidimensional array formed by the multiple sub-processing circuits shown, in view of which, combined with Figures 5a to 5d The described technical details also apply to Figures 6a to 6d The content shown.

[0067] like Figure 6a As shown, the sub-processing circuits of the two-dimensional array include a central sub-processing circuit located at the center of the two-dimensional array and three sub-processing circuits connected in four directions (row and column) to the central sub-processing circuit. Therefore, the number of intervals between the central sub-processing circuit and the remaining sub-processing circuits are 0, 1, and 2, respectively. Figure 6bAs shown, the sub-processing circuit of the two-dimensional array includes a central sub-processing circuit located at the center of the two-dimensional array, three sub-processing circuits in two opposite directions in the same row as the central sub-processing circuit, and one sub-processing circuit in two opposite directions in the same column as the central sub-processing circuit. Therefore, the number of intervals between the central sub-processing circuit and the sub-processing circuits in the same row are 0 and 2, respectively, and the number of intervals between the central sub-processing circuit and the sub-processing circuits in the same column are both 0.

[0068] As Figure 5d As shown, the multidimensional array formed by multiple sub-processing circuits can be a three-dimensional array composed of multiple layers. Each layer of the three-dimensional array can include a two-dimensional array of multiple sub-processing circuits arranged along its row and column directions. Further, the sub-processing circuits located in the three-dimensional array can be connected to one or more other sub-processing circuits in the same row, column, diagonal, or different layers in at least one of the row, column, diagonal, and layer directions with a predetermined three-dimensional spacing pattern. Further, the predetermined three-dimensional spacing pattern and the number of sub-processing circuits spaced apart in the connection can be related to the number of layers. The following will combine... Figure 6c and Figure 6d The connection method of the three-dimensional array is further described.

[0069] Figure 6c This diagram illustrates a multi-layered, multi-row, multi-column three-dimensional array formed by connecting multiple sub-processing circuits. Taking a sub-processing circuit located in the l-th layer, r-th row, and c-th column (denoted as (l, r, c)) as an example, it is positioned at the center of the array and is connected to sub-processing circuits in the preceding column (l, r, c-1) and following column (l, r, c+1) of the same layer and row, sub-processing circuits in the preceding row (l, r-1, c) and following row (l, r+1, c) of the same layer and column, and sub-processing circuits in the preceding layer (l-1, r, c) and following layer (l+1, r, c) of different layers within the same row and column. Furthermore, the number of intervals between the sub-processing circuit at (l, r, c) and other sub-processing circuits in the row, column, and layer directions is zero.

[0070] Figure 6dThis diagram illustrates a three-dimensional array where the number of intervals between multiple sub-processing circuits connected in the row, column, and layer directions is all 1. Taking the sub-processing circuit located at the center of the array (l, r, c) as an example, it is connected to sub-processing circuits at positions (l, r, c-2) and (l, r, c+2) that are one column apart in the same row and at different columns within the same layer, and to sub-processing circuits at positions (l, r-2, c) and (l, r+2, c) that are one row apart in the same column and at different rows within the same layer. Furthermore, it is connected to sub-processing circuits at positions (l-2, r, c) and (l+2, r, c) that are one layer apart in the same row and at different layers within the same row. Similarly, the remaining sub-processing circuits at positions (l, r, c-3) and (l, r, c-1) that are one column apart in the same row and at the same layer are connected to each other, while the sub-processing circuits at positions (l, r, c+1) and (l, r, c+3) are connected to each other. Next, the sub-processing circuits at (l, r-3, c) and (l, r-1, c) on the same layer and column, separated by one row, are connected to each other, and the sub-processing circuits at (l, r+1, c) and (l, r+3, c) are connected to each other. Additionally, the sub-processing circuits at (l-3, r, c) and (l-1, r, c) on the same row and column, separated by one layer, are connected to each other, and the sub-processing circuits at (l+1, r, c) and (l+3, r, c) are connected to each other.

[0071] The above text provides an exemplary description of the connection relationship of a multidimensional array formed by multiple sub-processing circuits. The following text will provide a further exemplary description of the loop structure formed by the sub-processing circuits in conjunction with Figures 7 and 8.

[0072] Figure 7a and Figure 7b These are schematic diagrams illustrating different loop structures of the sub-processing circuits according to embodiments of this disclosure. For example... Figure 7a As shown, the four adjacent sub-processing circuits 115 are sequentially numbered "0, 1, 2, and 3". Then, starting with sub-processing circuit 0, these four sub-processing circuits are connected sequentially in a clockwise direction, and sub-processing circuit 3 is connected to sub-processing circuit 0, so that the four sub-processing circuits are connected in series to form a closed loop (referred to as "loop"). It can be seen from this loop that... Figure 7a The number of intervals between the sub-processing circuits shown is 0 or 2. For example, the interval between sub-processing circuits 0 and 1 is 0, while the interval between sub-processing circuit 3 and 0 is 2. Furthermore, the physical addresses of the four sub-processing circuits in the loop shown can be 0-1-2-3, and their logical addresses are also 0-1-2-3. It should be noted that... Figure 7a The connection order shown is merely exemplary and not restrictive. Those skilled in the art may also connect the four sub-processing circuits in series in a counterclockwise direction to form a closed loop, depending on actual computational needs.

[0073] In some practical scenarios, when the data bit width supported by a single sub-processing circuit cannot meet the bit width requirements of the processed data, multiple sub-processing circuits can be combined into a sub-processing circuit group to represent a single data point. For example, suppose a single sub-processing circuit can process 8-bit data. When processing 32-bit data, four sub-processing circuits can be combined into a sub-processing circuit group to connect four 8-bit data points to form a 32-bit data point. Furthermore, the aforementioned sub-processing circuit group formed by four 8-bit sub-processing circuits can act as... Figure 7b The diagram shows a sub-processing circuit 115, which can support higher bit-width operations.

[0074] from Figure 7b As can be seen from this, the layout of the sub-processing circuit shown is similar to... Figure 7a Similar to what is shown, but Figure 7b The number of intervals between neutron processing circuits and Figure 7a Different. For example... Figure 7b As shown, the four sub-processing circuits, numbered 0, 1, 2, and 3 in sequence, are connected clockwise, starting with sub-processing circuit 0, then sub-processing circuit 1, sub-processing circuit 3, and sub-processing circuit 2. Sub-processing circuit 2 is also connected to sub-processing circuit 0, thus forming a closed loop in series. From this loop, it can be seen that... Figure 7b The number of intervals between the sub-processing circuits shown is either 0 or 1. For example, the interval between sub-processing circuits 0 and 1 is 0, while the interval between sub-processing circuits 1 and 3 is 1. Furthermore, the physical addresses of the four sub-processing circuits in the closed loop shown can be 0-1-2-3, while the logical addresses are 0-1-3-2. Therefore, when it is necessary to split high-bit-width data to allocate it to different sub-processing circuits, the data order can be rearranged and allocated according to the logical addresses of the sub-processing circuits.

[0075] The above-mentioned splitting and rearranging operations can be performed by combining... Figure 2 The preprocessing circuit described is used for execution. Specifically, this preprocessing circuit can rearrange the input data according to the physical and logical addresses of multiple sub-processing circuits to meet the requirements of data operations. Assume four sequentially arranged sub-processing circuits 0 to 3 as follows: Figure 7a The connections shown, since both their physical and logical addresses are 0-1-2-3, allow the preprocessing circuit to sequentially transmit input data (e.g., pixel data) aa0, aa1, aa2, and aa3 to their corresponding sub-processing circuits. However, when the aforementioned four sub-processing circuits are... Figure 7bWhen the connection is shown, the physical address remains unchanged at 0-1-2-3, while the logical address changes to 0-1-3-2. At this time, the pre-processing circuit needs to rearrange the input data aa0, aa1, aa2, and aa3 into aa0-aa1-aa3-aa2 to transmit it to the corresponding sub-processing circuit. Based on the above input data rearrangement, the disclosed scheme can guarantee the correctness of the data operation order. Similarly, if the order of the four operation output results (e.g., pixel data) obtained above is bb0-bb1-bb3-bb2, it can be combined with... Figure 2 The described post-processing circuit restores the order of the operation output results to bb0-bb1-bb2-bb3 to ensure the consistency between the input data and the output data.

[0076] Figure 8a and Figure 8b These are schematic diagrams illustrating further different loop structures of the sub-processing circuits according to embodiments of the present disclosure, wherein more sub-processing circuits are arranged and connected in different ways to form closed loops.

[0077] like Figure 8a As shown, 16 sub-processing circuits 115, numbered sequentially from 0 to 15, are connected and combined in pairs to form a sub-processing circuit group. For example, as shown, sub-processing circuit 0 is connected to sub-processing circuit 1 to form a sub-processing circuit group… and so on. Sub-processing circuit 14 is connected to sub-processing circuit 15 to form a sub-processing circuit group, ultimately forming eight sub-processing circuit groups. Furthermore, these eight sub-processing circuit groups can also be connected in a manner similar to the aforementioned sub-processing circuit connections, including connecting them according to, for example, predetermined logical addresses to form a closed loop of a sub-processing circuit group.

[0078] like Figure 8b As shown, multiple sub-processing circuits 115 are connected in an irregular or non-uniform manner to form a closed loop. Specifically, in Figure 8b The diagram shows that sub-processing circuits can form closed loops with intervals of 0 or 3. For example, sub-processing circuit 0 can be connected to sub-processing circuit 1 (interval of 0) and sub-processing circuit 4 (interval of 3), respectively.

[0079] Based on the above combination Figure 7a , 7bAs described in 8a and 8b, the sub-processing circuits disclosed herein can have varying numbers of sub-processing circuits spaced apart to form a closed loop. When the total number of sub-processing circuits changes, any number of intermediate intervals can be dynamically configured to form a closed loop. Multiple sub-processing circuits can also be combined into a sub-processing circuit group and connected to form a closed loop of the sub-processing circuit group. Furthermore, the connection of multiple sub-processing circuits can be a hard connection constructed in hardware or a soft connection configured in software.

[0080] Figure 9 This is a schematic architectural diagram illustrating an integrated computing device and slave processing circuitry according to embodiments of the present disclosure. It should be noted that the architectural diagrams of the integrated computing device and slave processing circuitry disclosed herein are merely illustrative and not restrictive. In addition to performing pipelining and multithreaded operations, the solutions disclosed herein can also cooperate with slave processing circuitry to perform other types of data operations.

[0081] like Figure 9 As shown, with Figures 1-2 Similar integrated computing devices include a main control circuit 102, a first main processing circuit 104, and a second main processing circuit 106. Further, at least one of the first and second main processing circuits can communicate with at least one slave processing circuit 112 via an interconnect circuit 110. The interconnect circuit 110 can be used to forward data, computation instructions, or intermediate computation results transmitted between the first or second main processing circuit and the at least one slave processing circuit. In one embodiment, the at least one slave processing circuit can be configured to receive data and computation instructions transmitted from at least one of the first and second main processing circuits via the interconnect circuit to perform intermediate computations in parallel, obtaining multiple intermediate computation results. The multiple intermediate computation results can also be transmitted to at least one of the first or second main processing circuits via the interconnect circuit. In another embodiment, the first main processing circuit can be configured to receive and execute the computation instructions in a Single Instruction Multiple Data (SIMD) manner, while the second main processing circuit can be configured to receive and execute the computation instructions in a Single Instruction Multiple Thread (SIMT) manner.

[0082] Figure 10 This is a simplified flowchart illustrating a method 1000 for performing computational operations using an integrated computing device according to an embodiment of this disclosure. The integrated computing device can be applied to, for example... Figures 1-2 The architecture shown is shown.

[0083] like Figure 10As shown, in step 1010, method 1000 can utilize the main control circuit to obtain calculation instructions and can parse the calculation instructions to obtain operation instructions. Furthermore, the operation instructions can be sent to at least one of the first main processing circuit and the second main processing circuit. In one embodiment, the main control circuit can determine the first and / or second main processing circuit to perform the operation based on the instruction identification information in the calculation instructions, and send the operation instructions to at least one of the first main processing circuit and the second main processing circuit to execute the corresponding operation specified by the operation instructions.

[0084] In one or more embodiments, during the parsing of calculation instructions, the main control circuit can perform a decoding operation on the calculation instructions and send the calculation instructions to at least one of the first main processing circuit and the second main processing circuit based on the decoding result. When both the first and second main processing circuits support non-specific operations of the same type, the main control circuit can send the calculation instructions to the main processing circuit with low utilization or in an idle state, based on the load status of the first and second main processing circuits. Furthermore, depending on the application scenario, the calculation instructions obtained after parsing the calculation instructions may also be calculation instructions that have not been decoded by the main control circuit. The first or second main processing circuit may include a corresponding decoding circuit to decode the received calculation instructions, for example, to generate multiple micro-instructions, so that the first or second main processing circuit can perform subsequent operations based on the micro-instructions.

[0085] Next, the process can proceed to steps 1020 and / or 1030 based on at least one of the first and second main processing circuits determined at step 1010 for executing the next operation. Specifically, when executing step 1020, method 1000 can utilize one or more sets of pipelined operation circuits included in the first main processing circuit, and perform pipelined operations based on received data (e.g., neuron data) and computation instructions. In one embodiment, each set of pipelined operation circuits can perform the pipelined operation independently or collaboratively. Specifically, the multiple sets of pipelined operation circuits disclosed herein support independent completion of their respective pipelined operations and can execute these pipelined operations in parallel with each other. Furthermore, these parallel pipelined operations can involve the same or different computational operations. In contrast, in the collaborative execution of the pipelined operations, the multiple sets of pipelined operation circuits can, for example, cooperate with each other, wait for or pass intermediate or result data to complete computations when performing pipelined operations on different sets according to computation instructions or control signals. In another embodiment, each pipeline circuit may include a single-level pipeline operation (e.g., may include one or more arithmetic units) or a multi-level pipeline operation (e.g., may be executed serially or in parallel).

[0086] At step 1030, method 1000 may utilize multiple sub-processing circuits included in the second main processing circuit to perform multi-threaded operations based on received data (e.g., pixel data) and arithmetic instructions. In one embodiment, the multiple sub-processing circuits may be connected in a one-dimensional or multi-dimensional array topology, and the array of multiple sub-processing circuits connected in series may form one or more closed loops. In another embodiment, the multiple sub-processing circuits may determine whether to execute the operation of the arithmetic instruction based on information (e.g., predicate information) in the received arithmetic instruction.

[0087] Figure 11 This is a structural diagram illustrating a combined processing apparatus 1100 according to an embodiment of this disclosure. Figure 11 As shown, the combined processing device 1100 includes a computing processing device 1102, an interface device 1104, other processing devices 1106, and a storage device 1108. Depending on the application scenario, the computing processing device may include one or more computing devices 1110, which can be configured to perform the operations described herein. Figures 1-10 The described operation.

[0088] In different embodiments, the computing processing apparatus disclosed herein can be configured to perform user-specified operations. In exemplary applications, the computing processing apparatus can be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within the computing processing apparatus can be implemented as an artificial intelligence processor core or a portion of the hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or portions of the hardware structure of artificial intelligence processor cores, the computing processing apparatus disclosed herein can be considered to have a single-core structure or a homogeneous multi-core structure.

[0089] In exemplary operation, the computing processing device disclosed herein can interact with other processing devices through an interface device to jointly complete user-specified operations. Depending on the implementation, the other processing devices disclosed herein may include one or more types of processors such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and an artificial intelligence processor, both general-purpose and / or special-purpose processors. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing processing device disclosed herein can be considered to have a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, they can be considered to form a heterogeneous multi-core structure.

[0090] In one or more embodiments, the other processing device may serve as an interface between the computing processing device disclosed herein (which may be specifically embodied in artificial intelligence, such as neural network operations) and external data and control, performing basic controls including but not limited to data transfer, starting and / or stopping the computing device. In another embodiment, the other processing device may also cooperate with the computing processing device to jointly complete computational tasks.

[0091] In one or more embodiments, the interface device can be used to transfer data and control commands between a computing processing device and other processing devices. For example, the computing processing device can obtain input data from other processing devices via the interface device and write it to on-chip storage (or memory) of the computing processing device. Further, the computing processing device can obtain control commands from other processing devices via the interface device and write them to on-chip control cache of the computing processing device. Alternatively or optionally, the interface device can also read data from the storage device of the computing processing device and transmit it to other processing devices.

[0092] Additionally or optionally, the combined processing apparatus disclosed herein may further include a storage device. As shown in the figures, the storage device is connected to both the computing processing device and the other processing device. In one or more embodiments, the storage device may be used to store data from the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage of the computing processing device or other processing device.

[0093] In some embodiments, this disclosure also discloses a chip (e.g. Figure 12 The chip shown is 1202. In one implementation, the chip is a system-on-chip (SoC) and integrates one or more such... Figure 11 The combined processing unit shown is illustrated. This chip can be connected to external interface devices (such as...). Figure 12 The external interface device 1206 shown is connected to other related components. These related components may be, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. In some applications, the chip may integrate other processing units (e.g., video codecs) and / or interface modules (e.g., DRAM interfaces). In some embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip. In some embodiments, this disclosure also discloses a board that includes the aforementioned chip package structure. The following will be combined with... Figure 12 This board is described in detail.

[0094] Figure 12 This is a schematic diagram illustrating the structure of a board 1200 according to an embodiment of this disclosure. For example... Figure 12 As shown, the board includes a storage device 1204 for storing data, which includes one or more storage cells 1210. This storage device can be connected and transmit data with the controller 1208 and the aforementioned chip 1202 via, for example, a bus. Furthermore, the board also includes an external interface device 1206, configured for data relay or switching between the chip (or a chip in a chip package) and an external device 1212 (e.g., a server or computer). For example, data to be processed can be transferred from the external device to the chip via the external interface device. Alternatively, the calculation results of the chip can be transmitted back to the external device via the external interface device. Depending on the application scenario, the external interface device can have different interface forms, such as a standard PCIe interface.

[0095] In one or more embodiments, the controller in the disclosed board can be configured to regulate the state of the chip. Therefore, in one application scenario, the controller may include a microcontroller (MCU) for regulating the operating state of the chip.

[0096] Based on the above combination Figure 11 and Figure 12 Based on the description, those skilled in the art will understand that this disclosure also discloses an electronic device or apparatus that may include one or more of the aforementioned boards, one or more of the aforementioned chips, and / or one or more of the aforementioned combined processing apparatus.

[0097] Depending on the application scenario, the electronic devices or apparatus disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablets, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus disclosed herein can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus disclosed herein can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal applications. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present disclosure can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0098] It should be noted that, for the sake of brevity, this disclosure describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solutions disclosed herein are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of this document, those skilled in the art will understand that some steps can be performed in a different order or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this disclosure can be considered optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions disclosed herein. In addition, depending on the solution, the description of some embodiments in this disclosure may have different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this disclosure can also be referred to the relevant descriptions of other embodiments.

[0099] In terms of specific implementation, based on the disclosure and teachings of this document, those skilled in the art will understand that several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or apparatus embodiments described above, this document divides them based on logical functions, but in actual implementation, there may be other division methods. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationships between different units or components, the connections discussed above in conjunction with the accompanying drawings can be direct or indirect couplings between units or components. In some scenarios, the aforementioned direct or indirect couplings involve communication connections utilizing interfaces, where the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0100] In this disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this disclosure. Additionally, in some scenarios, multiple units in the embodiments of this disclosure may be integrated into one unit or each unit may exist physically independently.

[0101] In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage device (CMSDD). Therefore, when the disclosed solution is embodied in a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, server, or network device) to execute some or all of the steps of the method described in the embodiments of this disclosure. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0102] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0103] The foregoing can be better understood in accordance with the following terms:

[0104] Clause 1. An integrated computing device, comprising a main control circuit, a first main processing circuit, and a second main processing circuit, wherein:

[0105] The main control circuit is configured to acquire calculation instructions, parse the calculation instructions to obtain operation instructions, and send the operation instructions to at least one of the first main processing circuit and the second main processing circuit.

[0106] The first main processing circuit includes one or more sets of pipelined operation circuits, wherein each set of pipelined operation circuits is configured to perform pipelined operations based on received data and operation instructions; and

[0107] The second main processing circuit includes multiple sub-processing circuits, each of which is configured to perform multi-threaded operations based on received data and arithmetic instructions.

[0108] Clause 2. The integrated computing device according to Clause 1, wherein in parsing the computing instructions, the main control circuit is configured to:

[0109] Obtain the instruction identification information from the calculation instructions; and

[0110] The operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit according to the instruction identification information.

[0111] Clause 3. The integrated computing device according to Clause 1, wherein in parsing the computing instructions, the main control circuit is configured to:

[0112] Decode the computation instructions; and

[0113] Based on the decoding result and the operating states of the first main processing circuit and the second main processing circuit, the operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit.

[0114] Clause 4. The integrated computing device according to Clause 1, wherein each of the plurality of pipeline circuits performs the pipeline operation independently or collaboratively.

[0115] Clause 5. The integrated computing device according to Clause 4, wherein each pipeline circuitry includes one or more arithmetic units, and when each pipeline circuitry includes multiple arithmetic units, the multiple arithmetic units are configured to perform multi-stage pipeline operations.

[0116] Clause 6. The integrated computing device according to Clause 1, wherein the first main processing circuit further includes an arithmetic processing circuit configured to preprocess data before the pipelined arithmetic circuit performs arithmetic operations or postprocess data after the arithmetic operations according to arithmetic instructions.

[0117] Clause 7. The integrated computing device according to Clause 1, wherein the first main processing circuit further includes a data conversion circuit configured to perform a data conversion operation according to the arithmetic instructions.

[0118] Clause 8. The integrated computing device according to Clause 1, wherein the plurality of subprocessing circuits are connected in a topology of a one-dimensional or multi-dimensional array.

[0119] Clause 9. The integrated computing device according to Clause 8, wherein the multidimensional array is a two-dimensional array, and the sub-processing circuit located in the two-dimensional array is connected to one or more other sub-processing circuits in the same row, column, or diagonal in at least one of its row, column, or diagonal directions in a predetermined two-dimensional spacing pattern.

[0120] Clause 10. The integrated computing device according to Clause 9, wherein the predetermined two-dimensional spacing pattern is associated with the number of sub-processing circuits spaced in the connection.

[0121] Clause 11. The integrated computing device according to Clause 8, wherein the multidimensional array is a three-dimensional array consisting of multiple layers, wherein each layer comprises a two-dimensional array of multiple said sub-processing circuits arranged along the row and column directions, wherein:

[0122] The sub-processing circuit located in the three-dimensional array is connected to one or more other sub-processing circuits in the same row, column, diagonal, or different layer in at least one of its row, column, diagonal, and layer directions in a predetermined three-dimensional spacing pattern.

[0123] Clause 12. The integrated computing device according to Clause 11, wherein the predetermined three-dimensional spacing pattern is related to the number of sub-processing circuits spaced apart from each other in the connection and the number of spacing layers.

[0124] Clause 13. An integrated computing device according to any one of Clauses 8-12, wherein a plurality of subprocessing circuits connected in series via the said connection form one or more closed loops.

[0125] Clause 14. The integrated computing device according to Clause 1, wherein the plurality of subprocessing circuits are configured to determine whether to participate in the computation based on the computation instructions.

[0126] Clause 15. The integrated computing device according to Clause 1, wherein each of the sub-processing circuits comprises:

[0127] Logic operation circuits configured to perform logical operations according to operation instructions and data; and

[0128] A storage circuit includes a data storage circuit, wherein the data storage circuit is configured to store at least one of the computational data and intermediate computation results of the sub-processing circuit.

[0129] Clause 16. The integrated computing device according to Clause 15, wherein the storage circuitry further includes a predicate storage circuitry, wherein the predicate storage circuitry is configured to store a predicate storage circuitry number and predicate information for each of the subprocessing circuits acquired using the arithmetic instructions.

[0130] Clause 17. The integrated computing device according to Clause 16, wherein the predicate storage circuitry is further configured to:

[0131] Update the predicate information according to the operation instructions; or

[0132] The predicate information is updated based on the computation results of each of the sub-processing circuits.

[0133] Clause 18. The integrated computing device according to Clause 16, wherein each of the sub-processing circuits is configured to:

[0134] The predicate information corresponding to the predicate storage circuit is obtained according to the predicate storage circuit number in the operation instruction; and

[0135] The sub-processing circuit is determined to execute the operation instruction based on the predicate information.

[0136] Clause 19. The integrated computing device according to Clause 1, wherein each of the subprocessing circuits includes an arithmetic operation circuit configured to perform arithmetic operations.

[0137] Clause 20. The integrated computing device according to Clause 1, wherein the second main processing circuit further includes a data processing circuit, the data processing circuit including at least one of a pre-processing circuit and a post-processing circuit, wherein the pre-processing circuit is configured to preprocess the computation data before the sub-processing circuit performs the computation, and the post-processing circuit is configured to postprocess the computation result after the sub-processing circuit performs the computation.

[0138] Clause 21. The integrated computing device according to Clause 1, wherein the integrated computing device further includes a main storage circuit, the main storage circuit including at least one of a main storage module and a main cache module, wherein the main storage module is configured to store data for performing operations in the main processing circuit and the results of the operations performed, and the main cache module is configured to cache intermediate results of operations performed by at least one of the first main processing circuit and the second main processing circuit.

[0139] Clause 22. The integrated computing device according to any one of Clauses 1-12 or 14-21 further includes:

[0140] At least one slave processing circuit is configured to perform intermediate operations in parallel based on data and arithmetic instructions transmitted from at least one of the first master processing circuit and the second master processing circuit to obtain a plurality of intermediate results, and to transmit the plurality of intermediate results to at least one of the first master processing circuit and the second master processing circuit.

[0141] Clause 23. The integrated computing device according to Clause 22, wherein the first main processing circuit is configured to receive and execute the arithmetic instructions in a SIMD manner.

[0142] Clause 24. The integrated computing device according to Clause 22, wherein the second main processing circuit is configured to receive and execute the arithmetic instructions in a SIMT manner.

[0143] Clause 25. An integrated circuit chip comprising an integrated computing device according to any one of Clauses 1-24.

[0144] Clause 26. A board including an integrated circuit chip as described in Clause 25.

[0145] Clause 27. A method for performing computational operations using an integrated computing device, wherein the integrated computing device includes a main control circuit, a first main processing circuit, and a second main processing circuit, the method comprising:

[0146] The main control circuit is used to acquire calculation instructions and parse the calculation instructions to obtain operation instructions, and the operation instructions are sent to at least one of the first main processing circuit and the second main processing circuit;

[0147] Utilizing one or more sets of pipelined operation circuits included in the first main processing circuit to perform pipelined operations based on received data and operation instructions; and

[0148] Multiple sub-processing circuits included in the second main processing circuit are used to perform multi-threaded operations based on the received data and arithmetic instructions.

[0149] Clause 28. The method according to Clause 27, wherein in parsing the calculation instructions, the method utilizes the main control circuit to perform the following steps:

[0150] Obtain the instruction identification information from the calculation instructions; and

[0151] The operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit according to the instruction identification information.

[0152] Clause 29. The method according to Clause 27, wherein in parsing the calculation instructions, the method utilizes a main control circuit to perform the following steps:

[0153] Decode the computation instructions; and

[0154] Based on the decoding result and the operating states of the first main processing circuit and the second main processing circuit, the operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit.

[0155] Clause 30. The method according to Clause 27, wherein the pipeline operation is performed independently or collaboratively by each of the multiple sets of pipeline circuits.

[0156] Clause 31. The method according to Clause 30, wherein each set of pipeline circuits includes one or more arithmetic units, and when each set of pipeline circuits includes multiple arithmetic units, the method utilizes multiple arithmetic units to perform multi-stage pipeline operations.

[0157] Clause 32. The method according to Clause 27, wherein the first main processing circuit further includes an arithmetic processing circuit, and the method further includes using the arithmetic processing circuit to preprocess the data before the pipeline arithmetic circuit performs the arithmetic operation or to postprocess the data after the arithmetic operation according to the arithmetic instruction.

[0158] Clause 33. The method according to Clause 27, wherein the first main processing circuit further includes a data conversion circuit, and the method further includes using the data conversion circuit to perform a data conversion operation according to the arithmetic instructions.

[0159] Clause 34. The method according to Clause 27, wherein the plurality of subprocessing circuits are connected in a topology of a one-dimensional or multi-dimensional array.

[0160] Clause 35. The method according to Clause 34, wherein the multidimensional array is a two-dimensional array, and the sub-processing circuit located in the two-dimensional array is connected to one or more other sub-processing circuits in the same row, column, or diagonal in at least one of its row, column, or diagonal directions in a predetermined two-dimensional spacing pattern.

[0161] Clause 36, the method according to Clause 35, wherein the predetermined two-dimensional spacing pattern is associated with the number of sub-processing circuits spaced in the connection.

[0162] Clause 37. The method according to Clause 34, wherein the multidimensional array is a three-dimensional array consisting of multiple layers, wherein each layer comprises a two-dimensional array of multiple said sub-processing circuits arranged along the row and column directions, wherein the method includes:

[0163] The sub-processing circuits located in the three-dimensional array are connected such that the sub-processing circuits are connected to one or more other sub-processing circuits in the same row, column, diagonal, or different layer in at least one of the row, column, diagonal, and layer directions in a predetermined three-dimensional spacing pattern.

[0164] Clause 38. The method according to Clause 37, wherein the predetermined three-dimensional spacing pattern is related to the number of sub-processing circuits spaced apart from each other in the connection and the number of layers spaced apart.

[0165] Clause 39. The method according to any one of Clauses 34-38, wherein the plurality of sub-processing circuits connected in series via the said connection form one or more closed loops.

[0166] Clause 40. The method according to Clause 27, wherein it is determined whether the plurality of sub-processing circuits participate in the operation based on the operation instruction.

[0167] Clause 41. The method according to Clause 27, wherein each of the sub-processing circuits includes a logic operation circuit and a storage circuit, wherein the storage circuit includes a data storage circuit, the method comprising using the logic operation circuit to perform a logic operation according to an operation instruction and data, and using the data storage circuit to store at least one of the operation data and intermediate operation results of the sub-processing circuit.

[0168] Clause 42. The method according to Clause 41, wherein the storage circuit further includes a predicate storage circuit, wherein the method includes using the predicate storage circuit to store the predicate storage circuit number and predicate information of each of the sub-processing circuits obtained by the operation instructions.

[0169] Clause 43. The method according to Clause 42, wherein the following steps are performed using the predicate storage circuit:

[0170] Update the predicate information according to the operation instructions; or

[0171] The predicate information is updated based on the computation results of each of the sub-processing circuits.

[0172] Clause 44. The method according to Clause 42, wherein the following steps are performed using each of the sub-processing circuits:

[0173] The predicate information corresponding to the predicate storage circuit is obtained according to the predicate storage circuit number in the operation instruction; and

[0174] The sub-processing circuit is determined to execute the operation instruction based on the predicate information.

[0175] Clause 45. The method according to Clause 27, wherein each of the sub-processing circuits includes an arithmetic operation circuit, and the method utilizes the arithmetic operation circuit to perform arithmetic operations.

[0176] Clause 46. The method according to Clause 27, wherein the second main processing circuit further includes a data processing circuit, the data processing circuit including at least one of a pre-processing circuit and a post-processing circuit, wherein the method includes performing a pre-processing operation on the computation data using the pre-processing circuit before the sub-processing circuit performs the operation, and performing a post-processing operation on the computation result using the post-processing circuit after the sub-processing circuit performs the operation.

[0177] Clause 47. The method according to Clause 27, wherein the integrated computing device further includes a main storage circuit, the main storage circuit including at least one of a main storage module and a main cache module, wherein the method includes using the main storage module to store data for performing operations in the main processing circuit and the results of the operations performed thereon, and using the main cache module to cache intermediate results of the operations performed by at least one of the first main processing circuit and the second main processing circuit.

[0178] Clause 48. The method according to any one of Clauses 27-38 or 40-47, wherein the integrated computing device further comprises at least one slave processing circuit, the method comprising using the at least one slave processing circuit to perform intermediate operations in parallel based on data and arithmetic instructions transmitted from at least one of the first main processing circuit and the second main processing circuit to obtain a plurality of intermediate results, and transmitting the plurality of intermediate results to at least one of the first main processing circuit and the second main processing circuit.

[0179] Clause 49. The method according to Clause 48, wherein the first main processing circuit is configured to receive and execute the arithmetic instructions in a SIMD manner.

[0180] Clause 50, the method according to Clause 48, wherein the second main processing circuit is configured to receive and execute the arithmetic instructions in a SIMT manner.

[0181] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. An integrated computing device, comprising a main control circuit, a first main processing circuit, and a second main processing circuit, wherein: The main control circuit is configured to acquire calculation instructions, parse the calculation instructions to obtain operation instructions, and send the operation instructions to at least one of the first main processing circuit and the second main processing circuit. The first main processing circuit includes one or more sets of pipelined operation circuits, wherein each set of pipelined operation circuits is configured to perform pipelined operations based on received data and operation instructions; the first main processing circuit is further configured to bypass one or more stages of pipelined operation circuits that are not used in the operation; wherein, when multiple sets of pipelined operation circuits are performing operation operations, they simultaneously execute multiple operation instructions; and The second main processing circuit includes multiple sub-processing circuits, each of which is configured to perform multi-threaded operations based on received data and arithmetic instructions. The sub-processing circuits are connected at different intervals to form a closed loop, wherein the number of intervals between the sub-processing circuits is dynamically configured. The second main processing circuit further includes a data processing circuit, which includes a pre-processing circuit. The pre-processing circuit is configured to preprocess the data before the sub-processing circuit performs the operation. When it is necessary to split the high bit width data, the pre-processing circuit is configured to rearrange the data according to the physical address and logical address of multiple sub-processing circuits to meet the requirements of data operation. The integrated computing device further includes: At least one slave processing circuit is configured to perform intermediate operations in parallel based on data and arithmetic instructions transmitted from at least one of the first master processing circuit and the second master processing circuit to obtain a plurality of intermediate results, and to transmit the plurality of intermediate results to at least one of the first master processing circuit and the second master processing circuit.

2. The integrated computing device according to claim 1, wherein in parsing the computing instructions, the main control circuit is configured to: Obtain the instruction identification information from the calculation instructions; and The operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit according to the instruction identification information; or The main control circuit is configured to: Decode the computation instructions; and Based on the decoding result and the operating states of the first main processing circuit and the second main processing circuit, the operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit.

3. The integrated computing device according to claim 1, wherein each set of pipeline circuits includes one or more arithmetic units, and when each set of pipeline circuits includes multiple arithmetic units, the multiple arithmetic units are configured to perform multi-level pipeline operations.

4. The integrated computing device according to claim 1, wherein the first main processing circuit further includes an arithmetic processing circuit and / or a data conversion circuit, wherein the arithmetic processing circuit is configured to preprocess the data before the pipeline arithmetic circuit performs the arithmetic operation or postprocess the data after the arithmetic operation according to the arithmetic instruction, and the data conversion circuit is configured to perform a data conversion operation according to the arithmetic instruction.

5. The integrated computing device according to claim 1, wherein the plurality of sub-processing circuits are connected in a one-dimensional or multi-dimensional array structure.

6. The integrated computing device of claim 5, wherein the multidimensional array is a two-dimensional array, and the sub-processing circuit located in the two-dimensional array is connected to one or more other sub-processing circuits in the same row, column, or diagonal in at least one of its row, column, or diagonal directions in a predetermined two-dimensional spacing pattern, wherein the predetermined two-dimensional spacing pattern is associated with the number of sub-processing circuits spaced apart in the connection.

7. The integrated computing device according to claim 5, wherein the multidimensional array is a three-dimensional array composed of multiple layers, wherein each layer comprises a two-dimensional array of multiple sub-processing circuits arranged along the row direction, column direction, and diagonal direction, wherein: The sub-processing circuit located in the three-dimensional array is connected to one or more other sub-processing circuits in the same row, column, diagonal, or different layers in at least one of its row, column, diagonal, and layer directions in a predetermined three-dimensional spacing pattern, wherein the predetermined three-dimensional spacing pattern is related to the number of spacings and the number of spacing layers between the processing circuits to be connected.

8. The integrated computing device according to claim 1, wherein the plurality of sub-processing circuits are configured to determine whether the plurality of sub-processing circuits participate in the operation according to the operation instructions.

9. The integrated computing device of claim 1, wherein each of the sub-processing circuits comprises: A logic operation circuit configured to perform logical operations based on operation instructions and data; as well as The storage circuit includes a data storage circuit and a predicate storage circuit. The data storage circuit is configured to store at least one of the computational data and intermediate computation results of the sub-processing circuit. The predicate storage circuit is configured as follows: The predicate storage circuit number and predicate information of each of the sub-processing circuits obtained using the operation instructions are stored; Update the predicate information according to the operation instructions; or The predicate information is updated based on the computation results of each of the sub-processing circuits.

10. The integrated computing device of claim 9, wherein each of the sub-processing circuits is configured to: The predicate information corresponding to the predicate storage circuit is obtained according to the predicate storage circuit number in the operation instruction; and The sub-processing circuit is determined to execute the operation instruction based on the predicate information.

11. The integrated computing device of claim 1, wherein each of the subprocessing circuits includes an arithmetic operation circuit configured to perform arithmetic operations.

12. The integrated computing device according to claim 1, wherein the data processing circuit further includes a post-processing circuit, wherein the post-processing circuit is configured to perform post-processing operations on the calculation results after the sub-processing circuit performs the calculation.

13. The integrated computing device according to claim 1, wherein the integrated computing device further comprises a main storage circuit, the main storage circuit comprising at least one of a main storage module and a main cache module, wherein the main storage module is configured to store data for performing operations in the main processing circuit and the operation results after the operations are performed, and the main cache module is configured to cache intermediate operation results after at least one of the first main processing circuit and the second main processing circuit performs operations.

14. The integrated computing device of claim 1, wherein the first main processing circuit is configured to receive and execute the arithmetic instructions in a SIMD manner and the second main processing circuit is configured to receive and execute the arithmetic instructions in a SIMT manner.

15. An integrated circuit chip, comprising an integrated computing device according to any one of claims 1-14.

16. A board comprising the integrated circuit chip according to claim 15.

17. A method for performing computational operations using an integrated computing device, wherein the integrated computing device includes a main control circuit, a first main processing circuit, and a second main processing circuit, the method comprising: The main control circuit is used to acquire calculation instructions and parse the calculation instructions to obtain operation instructions, and the operation instructions are sent to at least one of the first main processing circuit and the second main processing circuit; The system utilizes one or more sets of pipelined operation circuits included in the first main processing circuit to perform pipelined operations based on received data and the operation instructions; it also utilizes one or more sets of pipelined operation circuits in the first main processing circuit to perform bypass operations on one or more stages of pipelined operation circuits that will not be used in the operation; wherein, when multiple sets of pipelined operation circuits are performing operation operations, they simultaneously execute multiple operation instructions; and Multiple sub-processing circuits included in the second main processing circuit are used to perform multi-threaded operations based on the received data and the operation instructions, wherein the sub-processing circuits are connected at different intervals to form a closed loop, and the number of intervals between the sub-processing circuits is dynamically configured. The preprocessing circuit included in the data processing circuit of the second main processing circuit performs preprocessing operations on the operation data before the sub-processing circuit performs the operation. When it is necessary to split the high bit width data, the preprocessing circuit is configured to rearrange the data according to the physical address and logical address of multiple sub-processing circuits to meet the requirements of data operation. The integrated computing device further includes at least one slave processing circuit, and the method further includes using the at least one slave processing circuit to perform intermediate operations in parallel according to data and operation instructions transmitted from at least one of the first main processing circuit and the second main processing circuit to obtain multiple intermediate results, and transmitting the multiple intermediate results to at least one of the first main processing circuit and the second main processing circuit.

18. The method of claim 17, wherein in parsing the calculation instructions, the method utilizes the main control circuit to perform the following steps: Obtain the instruction identification information from the calculation instructions; and The operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit according to the instruction identification information; or The method utilizes the main control circuit to perform the following steps: Decode the computation instructions; and Based on the decoding result and the operating states of the first main processing circuit and the second main processing circuit, the operation instruction is sent to at least one of the first main processing circuit and the second main processing circuit.

19. The method of claim 17, wherein each pipeline circuit includes one or more arithmetic units, and when each pipeline circuit includes multiple arithmetic units, the method utilizes the multiple arithmetic units to perform multi-level pipeline operations.

20. The method according to claim 17, wherein the first main processing circuit further includes an arithmetic processing circuit and / or a data conversion circuit, wherein the method utilizes the arithmetic processing circuit to preprocess the data before the pipeline arithmetic circuit performs the arithmetic operation or to postprocess the data after the arithmetic operation according to the arithmetic instruction, and utilizes the data conversion circuit to perform a data conversion operation according to the arithmetic instruction.

21. The method of claim 17, wherein the plurality of sub-processing circuits are connected in a one-dimensional or multi-dimensional array structure.

22. The method of claim 21, wherein the multidimensional array is a two-dimensional array, and the sub-processing circuits located in the two-dimensional array are connected to one or more other sub-processing circuits in the same row, column, or diagonal direction in at least one of their row, column, or diagonal directions in a predetermined two-dimensional spacing pattern, wherein the predetermined two-dimensional spacing pattern is associated with the number of sub-processing circuits spaced apart in the connection.

23. The method of claim 21, wherein the multidimensional array is a three-dimensional array composed of multiple layers, wherein each layer comprises a two-dimensional array of multiple said sub-processing circuits arranged along the row direction, column direction, and diagonal direction, wherein the method includes: The sub-processing circuits located in the three-dimensional array are connected such that the sub-processing circuits are connected to one or more other sub-processing circuits in the same row, column, diagonal, or different layer in at least one of the row, column, diagonal, and layer directions in a predetermined three-dimensional spacing pattern, wherein the predetermined three-dimensional spacing pattern is related to the number of spacings and the number of spacing layers between the processing circuits to be connected.

24. The method according to claim 17, wherein the determination of whether the plurality of sub-processing circuits participate in the operation is based on the operation instruction.

25. The method of claim 17, wherein each of the sub-processing circuits includes a logic operation circuit and a storage circuit, the storage circuit including a data storage circuit and a predicate storage circuit, wherein the method includes using the logic operation circuit to perform a logic operation according to an operation instruction and data, using the data storage circuit to store at least one of the operation data and intermediate operation results of the sub-processing circuit, and using the predicate storage circuit to perform the following steps: The predicate storage circuit number and predicate information of each of the sub-processing circuits obtained using the operation instructions are stored; Update the predicate information according to the operation instructions; or The predicate information is updated based on the computation results of each of the sub-processing circuits.

26. The method of claim 25, wherein each of the sub-processing circuits is used to perform the following steps: The predicate information corresponding to the predicate storage circuit is obtained according to the predicate storage circuit number in the operation instruction; and The sub-processing circuit is determined to execute the operation instruction based on the predicate information.

27. The method of claim 17, wherein the data processing circuit further includes a post-processing circuit, and the method further includes using the post-processing circuit to perform post-processing operations on the calculation results after the sub-processing circuit performs the calculation.

28. The method of claim 17, wherein the first main processing circuit is configured to receive and execute the arithmetic instructions in a SIMD manner and the second main processing circuit is configured to receive and execute the arithmetic instructions in a SIMT manner.

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