A BIOS-based FPGA encryption method, apparatus, device, and medium

Abstract

This application discloses a BIOS-based FPGA encryption method, apparatus, device, and medium. The method includes: using the BIOS to access the FPGA's loading connection channel via a hardware link; the loading connection channel is a connection channel for copying a program from FLASH memory to static random access memory; encrypting the FLASH memory through the loading connection channel using encryption rules stored in the BIOS to achieve write protection; monitoring the FPGA's refresh link, and when the FPGA receives a target image file for refresh, performing security authentication on the target new image file to filter out risky image files with anomalies. This avoids the increased cost associated with using high-end FPGAs and the cost and design complexity issues caused by adding redundant MCU devices when using low-end FPGAs, thus improving FPGA encryption efficiency.

Description

Technical Field

[0001] This invention relates to the field of FPGA encryption, and in particular to a BIOS-based FPGA encryption method, apparatus, device, and medium. Background Technology

[0002] Currently, there are two types of FPGA (Field Programmable Gate Array) encryption methods. One is FPGAs with built-in encryption functionality. This method is simple and practical, but it is limited to high-end FPGA chips, resulting in extremely high costs and uncertainties. Existing technologies also involve adding an MCU (Microcontroller Unit) chip with encryption capabilities to the FPGA encryption system. However, this method is complex and increases hardware costs. Therefore, how to achieve large-scale and simple FPGA encryption is a pressing problem that needs to be solved. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a BIOS-based FPGA encryption method, apparatus, device, and medium that avoids the increased cost associated with using high-end FPGAs and the cost and design complexity issues caused by adding redundant MCU devices when using low-end FPGAs, thereby improving FPGA encryption efficiency. The specific solution is as follows:

[0004] In a first aspect, this application discloses a BIOS-based FPGA encryption method, comprising:

[0005] The BIOS is used to access the FPGA's loading connection channel via a hardware link; the loading connection channel is the connection channel through which the program is copied from the FLASH memory to the static random access memory.

[0006] The FLASH memory is encrypted using the encryption rules stored in the BIOS through the loading connection channel to achieve write protection;

[0007] The refresh link of the FPGA is monitored, and when the FPGA receives a target image file for refresh, the target new image file is security authenticated to filter out risky image files with abnormalities.

[0008] Optionally, the step of using the BIOS to enter the FPGA loading connection channel via a hardware link includes:

[0009] The BIOS is used to access the FPGA's loading connection channel through the hardware link between the BIOS's ROM memory and the CPU, and the hardware link between the CPU and the FPGA.

[0010] Optionally, the security authentication of the target new image file includes:

[0011] Extract the parameter information of the target new image file; the parameter information includes the encrypted public key and name corresponding to the target image file;

[0012] Based on the parameter information and the pre-built image file authentication rules, the target new image file is subjected to security authentication.

[0013] Optionally, the BIOS-based FPGA encryption method further includes:

[0014] If the BIOS detects a reverse FPGA program attack in the FPGA's storage content, it provides pseudocode to the reverse FPGA program attack according to a preset protection mechanism to protect the FPGA's legitimate program code.

[0015] Optionally, the BIOS-based FPGA encryption method further includes:

[0016] The BIOS monitors the FPGA's refresh process and access operations, and locks the FPGA when illegal behavior is detected; illegal behavior includes attacks and malicious tampering.

[0017] Optionally, after locking the FPGA upon detecting illegal behavior, the method further includes:

[0018] Stop the current refresh or access operation and clear the data content already stored in the FPGA corresponding to the current refresh or access operation.

[0019] Optionally, after locking the FPGA upon detecting illegal behavior, the method further includes:

[0020] Record the parameter information corresponding to the illegal behavior;

[0021] Based on the parameter information, update the image file authentication rules corresponding to the security authentication operation for the target new image file.

[0022] Secondly, this application discloses a BIOS-based FPGA encryption device, comprising:

[0023] The channel access module is used to access the FPGA's loading connection channel via the hardware link using the BIOS; the loading connection channel is the connection channel through which the program is copied from the FLASH memory to the static random access memory.

[0024] The FLASH encryption module is used to encrypt the FLASH memory through the loading connection channel using the encryption rules stored in the BIOS to achieve write protection;

[0025] The security authentication module is used to monitor the refresh link of the FPGA, and when it detects that the FPGA has received a target image file for refresh, it performs security authentication on the target new image file to filter out risky image files with abnormalities.

[0026] Thirdly, this application discloses an electronic device, comprising:

[0027] Memory, used to store computer programs;

[0028] A processor is used to execute the computer program to implement the aforementioned BIOS-based FPGA encryption method.

[0029] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned BIOS-based FPGA encryption method.

[0030] In this application, the BIOS is used to access the FPGA's loading connection channel via a hardware link. This loading connection channel is the channel through which the program copies data from FLASH memory to static random access memory (SRAM). The FLASH memory is encrypted using encryption rules stored in the BIOS via this loading connection channel to achieve write protection. The FPGA's refresh link is monitored, and when the FPGA receives a target image file for refresh, the new target image file undergoes security authentication to filter out any abnormal or risky image files. Therefore, by using the server's BIOS software to encrypt the FPGA, accessing the FPGA's refresh loading connection channel via a hardware link, and then encrypting the FPGA, the data loaded into the FPGA's SRAM is guaranteed not to be tampered with. Furthermore, by performing security authentication on the target image file received by the FPGA for refresh, abnormal and risky image files are filtered out, ensuring the FPGA's security. This avoids the increased cost associated with using high-end FPGAs and the cost and design complexity issues caused by adding redundant MCU devices with low-end FPGAs, thus improving FPGA encryption efficiency. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 A flowchart of a BIOS-based FPGA encryption method provided for this application;

[0033] Figure 2 A flowchart of a specific BIOS-based FPGA encryption method provided for this application;

[0034] Figure 3 A flowchart of a specific BIOS-based FPGA encryption method provided for this application;

[0035] Figure 4 A schematic diagram of a BIOS-based FPGA encryption device provided in this application;

[0036] Figure 5 This application provides a structural diagram of an electronic device. Detailed Implementation

[0037] In existing technologies, FPGA encryption is performed using FPGAs with built-in encryption capabilities. However, this is limited to high-end FPGA chips, resulting in extremely high costs and uncertainties. Other existing technologies involve adding an MCU chip with encryption capabilities to the FPGA encryption system, but this method is complex and increases hardware costs. To overcome these technical problems, this application proposes a BIOS-based FPGA encryption method. This method avoids the increased costs associated with using high-end FPGAs and the cost and design complexity associated with adding redundant MCU devices to low-end FPGAs, thereby improving FPGA encryption efficiency.

[0038] This application discloses a BIOS-based FPGA encryption method, see [link to relevant documentation]. Figure 1 As shown, the method may include the following steps:

[0039] Step S11: Use the BIOS to enter the FPGA's loading connection channel through the hardware link; the loading connection channel is the connection channel through which the program is copied from the FLASH memory to the static random access memory.

[0040] In this embodiment, the BIOS (Basic Input Output System) is first used to access the FPGA's loading connection channel through a hardware link. The loading connection channel is the connection channel through which the program is copied from the FLASH memory to the Static Random-Access Memory (SRAM). That is, the FPGA copies the image file required for the upgrade from the FLASH memory to the internal SRAM. The FLASH memory can be a NandFLASH memory.

[0041] In this embodiment, the step of using the BIOS to enter the FPGA loading connection channel via a hardware link can include: using the BIOS to enter the FPGA loading connection channel via the hardware link between the ROM memory where the BIOS resides and the CPU, and the hardware link between the CPU and the FPGA. It is understood that there is a hardware link between the ROM memory where the BIOS resides and the server CPU, and the CPU and the FPGA are also connected via a hardware link; therefore, the server's BIOS system can enter the FPGA loading connection channel via this hardware link.

[0042] Step S12: Encrypt the FLASH memory through the loading connection channel using the encryption rules stored in the BIOS to achieve write protection.

[0043] In this embodiment, the FLASH memory corresponding to the FPGA is encrypted using the encryption rules stored in the BIOS through the aforementioned loading connection channel to achieve write protection. In other words, by designing the BIOS, the FPGA is encrypted using BIOS software. Before the FPGA program runs to the FLASH, the BIOS enters the FPGA's loading connection channel through a hardware link. Then, the BIOS uses its own special encryption to encrypt the FPGA's Flash memory, ensuring that the program loaded into the FPGA's Flash is encrypted before entering the FPGA's internal SRAM and being restored. This ensures that the program is not tampered with during the loading process into the Flash.

[0044] Step S13: Monitor the refresh link of the FPGA, and when the FPGA receives the target image file for refresh, perform security authentication on the target new image file to filter out risky image files with abnormalities.

[0045] In this embodiment, by monitoring the FPGA's refresh link, and when the FPGA receives the target image file for refresh, the target new image file is security authenticated to filter out risky image files with abnormalities; that is, before the FPGA refreshes using the target new image file, the target new image file is first security authenticated to filter out risky image files with abnormalities.

[0046] In this embodiment, the security authentication of the target new image file may include: extracting parameter information of the target new image file; the parameter information includes the encrypted public key and name corresponding to the target image file; and performing security authentication on the target new image file according to the parameter information and pre-built image file authentication rules. Specifically, security authentication can be performed based on the encrypted public key and name carried by the target image file, and the image file authentication rules can store basic information corresponding to abnormal image files in a blacklist manner. Since FPGA programs are generally refreshed online through FLASH memory, when an external image file is detected, an image file authentication mechanism is triggered to verify and authenticate the external image file, thereby protecting the FPGA.

[0047] The BIOS-based FPGA encryption method provided in this embodiment can be applied to the FT2000+ ARM server. On an ARM CPU (FT2000+) architecture server platform, where the ARM architecture CPU system platform refers to the AARC BIOS system, the FPGA is encrypted using the server's BIOS. Therefore, for large electronic devices such as servers, this embodiment provides a BIOS-based FPGA encryption method that can achieve secure, efficient, and practical FPGA encryption. It also helps ARM servers meet the security and trust requirements of FPGAs, enhancing the hardware security performance of ARM servers.

[0048] As can be seen from the above, this embodiment utilizes the BIOS to enter the FPGA's loading connection channel via a hardware link. This loading connection channel is the connection channel through which the program copies data from the FLASH memory to the static random access memory (SRAM). The FLASH memory is encrypted using encryption rules stored in the BIOS via this loading connection channel to achieve write protection. The FPGA's refresh link is monitored, and when the FPGA receives a target image file for refresh, the new target image file undergoes security authentication to filter out any abnormal or risky image files. Therefore, by using the server's BIOS software to encrypt the FPGA, entering the loading connection channel used for FPGA refresh via a hardware link, and then encrypting the FPGA, the data loaded into the FPGA's SRAM is ensured not to be tampered with. Furthermore, by performing security authentication on the target image file received by the FPGA for refresh, abnormal and risky image files are filtered out, ensuring the FPGA's security. This avoids the increased cost associated with using high-end FPGAs and the cost and design complexity issues caused by adding redundant MCU devices with low-end FPGAs, thus improving FPGA encryption efficiency.

[0049] Based on the above embodiments, this application discloses a specific BIOS-based FPGA encryption method, see [link to relevant documentation]. Figure 2 As shown, the method may include the following steps:

[0050] Step S21: Monitor the FPGA refresh process and access operations to the FPGA through the BIOS, and lock the FPGA when illegal behavior is detected.

[0051] In this embodiment, the BIOS monitors the FPGA refresh process and the access operations to the FPGA. When it detects that the refreshed data is illegal or the access operation is an illegal intrusion, such as an attack or malicious tampering, the FPGA is locked, that is, the internal program of the FPGA's SRAM is locked to ensure the security and reliability of the FPGA program.

[0052] In this embodiment, the method may further include: if the BIOS detects a reverse engineering attack targeting the FPGA's stored content, then according to a preset protection mechanism, pseudo-code is provided to the reverse engineering attack to protect the FPGA's legitimate program code. It is understood that if, despite the above protection, some attack viruses still manage to enter the FPGA, when these attacks attempt to obtain and tamper with the FPGA's internal program, pseudo-code is provided to the attack according to a preset protection mechanism to protect the FPGA's legitimate program code.

[0053] Step S22: Stop the current refresh or access operation and clear the data content already stored in the FPGA corresponding to the current refresh or access operation.

[0054] In this embodiment, while locking the FPGA, the current refresh or access operation is stopped, and the data content already stored in the FPGA corresponding to the current refresh or access operation is cleared. That is, the refresh or access that poses a risk is blocked in time, and the data content already stored in the FPGA corresponding to the current refresh or access operation is cleared, thus ensuring the security of the FPGA.

[0055] Step S23: Record the parameter information corresponding to the illegal behavior.

[0056] Step S24: Update the image file authentication rules corresponding to the security authentication operation for the target new image file based on the parameter information.

[0057] In this embodiment, after detecting illegal behavior, the parameter information corresponding to the illegal behavior is recorded. Then, based on the parameter information of the illegal behavior, the image file authentication rules corresponding to the security authentication operation for the target new image file are updated. That is, these illegal data can be identified and blocked directly before they enter the FPGA refresh step.

[0058] For example Figure 3 The diagram illustrates a specific FPGA encryption flowchart based on BIOS. The FPGA's original program is burned, the server boots up and runs, and then the BIOS enters the FPGA's loading connection channel via a hardware link, automatically encrypting and protecting the link. When a flash is detected, the authentication function of the target image file of the FPGA program is triggered. Simultaneously, it monitors for unauthorized intrusion of unknown information. Upon detecting illegal activity, the FPGA is locked. Furthermore, pseudocode is provided for the BIOS encryption protection mechanism against already flashed attacks. This illegal information is recorded. If similar information is detected in the loading connection channel next time, it will not be allowed to enter the FPGA's SRAM; the entry channel is directly encrypted and locked. Through cyclical identification and verification of illegal information, the secure operation of the FPGA is protected from damage.

[0059] As can be seen from the above, this embodiment monitors the FPGA's refresh process and access operations on the FPGA through the BIOS, and locks the FPGA when illegal behavior is detected. Simultaneously, the current refresh or access operation is stopped, and the data content already stored in the FPGA corresponding to the current refresh or access operation is cleared. Furthermore, the parameter information corresponding to the illegal behavior is recorded. Based on the parameter information, the image file authentication rules corresponding to the security authentication operation for the target new image file are updated. This further enhances the detection and protection measures when the FPGA is illegally intruded upon, and continuously improves the protection capability of the FPGA by updating the image file authentication rules corresponding to the security authentication operation for the target new image file based on illegal behavior.

[0060] Accordingly, this application also discloses a BIOS-based FPGA encryption device, see [link to relevant documentation]. Figure 4 As shown, the device includes:

[0061] The channel access module 11 is used to access the FPGA's loading connection channel via the hardware link using the BIOS; the loading connection channel is the connection channel through which the program is copied from the FLASH memory to the static random access memory.

[0062] The FLASH encryption module 12 is used to encrypt the FLASH memory through the loading connection channel using the encryption rules stored in the BIOS to achieve write protection;

[0063] The security authentication module 13 is used to monitor the refresh link of the FPGA, and when it detects that the FPGA has received a target image file for refresh, it performs security authentication on the target new image file to filter out risky image files with abnormalities.

[0064] As can be seen from the above, this embodiment utilizes the BIOS to enter the FPGA's loading connection channel via a hardware link. This loading connection channel is the connection channel through which the program copies data from the FLASH memory to the static random access memory (SRAM). The FLASH memory is encrypted using encryption rules stored in the BIOS via this loading connection channel to achieve write protection. The FPGA's refresh link is monitored, and when the FPGA receives a target image file for refresh, the new target image file undergoes security authentication to filter out any abnormal or risky image files. Therefore, by using the server's BIOS software to encrypt the FPGA, entering the loading connection channel used for FPGA refresh via a hardware link, and then encrypting the FPGA, the data loaded into the FPGA's SRAM is ensured not to be tampered with. Furthermore, by performing security authentication on the target image file received by the FPGA for refresh, abnormal and risky image files are filtered out, ensuring the FPGA's security. This avoids the increased cost associated with using high-end FPGAs and the cost and design complexity issues caused by adding redundant MCU devices with low-end FPGAs, thus improving FPGA encryption efficiency.

[0065] In some specific embodiments, the channel access module 11 may specifically include:

[0066] The loading connection channel access unit is used to access the loading connection channel of the FPGA by utilizing the BIOS through the hardware link between the ROM memory where the BIOS is located and the CPU, and the hardware link between the CPU and the FPGA.

[0067] In some specific embodiments, the security authentication module 13 may specifically include:

[0068] A parameter information acquisition unit is used to extract parameter information of the target new image file; the parameter information includes the encrypted public key and name corresponding to the target image file;

[0069] The authentication unit is used to perform security authentication on the target new image file based on the parameter information and pre-built image file authentication rules.

[0070] In some specific embodiments, the FPGA encryption device may specifically include:

[0071] The pseudocode providing unit is used to provide pseudocode to the reverse FPGA program attack according to a preset protection mechanism if the BIOS detects a reverse FPGA program attack in the storage content of the FPGA, so as to protect the legitimate program code of the FPGA.

[0072] In some specific embodiments, the FPGA encryption device may specifically include:

[0073] The monitoring unit is used to monitor the refresh process of the FPGA and access operations to the FPGA through the BIOS, and to lock the FPGA when illegal behavior is detected; the illegal behavior includes attacks and malicious tampering.

[0074] In some specific embodiments, the FPGA encryption device may specifically include:

[0075] The pause unit is used to stop the current refresh or access operation and clear the data content already stored in the FPGA corresponding to the current refresh or access operation.

[0076] In some specific embodiments, the FPGA encryption device may specifically include:

[0077] A recording unit is used to record parameter information corresponding to the illegal behavior;

[0078] The update unit is used to update the image file authentication rules corresponding to the security authentication operation for the target new image file based on the parameter information.

[0079] Furthermore, this application also discloses an electronic device, see [link to relevant documentation]. Figure 5 As shown, the content in the figure should not be considered as any limitation on the scope of use of this application.

[0080] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the BIOS-based FPGA encryption method disclosed in any of the foregoing embodiments.

[0081] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0082] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon include operating system 221, computer program 222 and data 223 including target new image file, etc. The storage method can be temporary storage or permanent storage.

[0083] The operating system 221 manages and controls the various hardware devices on the electronic device 20 and the computer program 222 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the BIOS-based FPGA encryption method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.

[0084] Furthermore, this application also discloses a computer storage medium storing computer-executable instructions. When the computer-executable instructions are loaded and executed by a processor, they implement the steps of the BIOS-based FPGA encryption method disclosed in any of the foregoing embodiments.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0086] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0087] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0088] The foregoing has provided a detailed description of a BIOS-based FPGA encryption method, apparatus, device, and medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A BIOS-based FPGA encryption method, characterized in that, include: The BIOS is used to access the FPGA's loading connection channel via a hardware link. The loading connection channel is the connection channel through which the FPGA copies files from the FLASH memory into the static random access memory. The FLASH memory is encrypted using the encryption rules stored in the BIOS through the loading connection channel to achieve write protection; The refresh link of the FPGA is monitored, and when the FPGA receives a target image file for refresh, the target image file is security authenticated to filter out risky image files with abnormalities. The method of using the BIOS to enter the FPGA loading connection channel via a hardware link includes: The BIOS is used to access the FPGA's loading connection channel through the hardware link between the BIOS and the CPU in the ROM memory, and the hardware link between the CPU and the FPGA. The security authentication of the target image file includes: Extract parameter information from the target image file; the parameter information includes the encrypted public key and name corresponding to the target image file; Based on the parameter information and the pre-built image file authentication rules, the target image file is subjected to security authentication. This also includes: If the BIOS detects a reverse FPGA program attack in the FPGA's storage content, it provides pseudocode to the reverse FPGA program attack according to a preset protection mechanism to protect the FPGA's legitimate program code.

2. The FPGA encryption method based on BIOS according to claim 1, characterized in that, Also includes: The BIOS monitors the FPGA's refresh process and access operations, and locks the FPGA when illegal behavior is detected; illegal behavior includes attacks and malicious tampering.

3. The FPGA encryption method based on BIOS according to claim 2, characterized in that, After locking the FPGA upon detecting illegal activity, the method further includes: Stop the current refresh or access operation and clear the data content already stored in the FPGA corresponding to the current refresh or access operation.

4. The FPGA encryption method based on BIOS according to claim 2, characterized in that, After locking the FPGA upon detecting illegal activity, the method further includes: Record the parameter information corresponding to the illegal behavior; Based on the parameter information, update the image file authentication rules corresponding to the security authentication operation for the target image file.

5. A BIOS-based FPGA encryption device, characterized in that, include: The channel access module is used to access the FPGA's loading connection channel via the hardware link using the BIOS; The loading connection channel is the connection channel through which the FPGA copies files from the FLASH memory into the static random access memory. The FLASH encryption module is used to encrypt the FLASH memory through the loading connection channel using the encryption rules stored in the BIOS to achieve write protection; The security authentication module is used to monitor the refresh link of the FPGA, and when it detects that the FPGA has received a target image file for refresh, it performs security authentication on the target image file to filter out risky image files with abnormalities. The channel access module is used to access the FPGA's loading connection channel by utilizing the BIOS through the hardware link between the BIOS's ROM memory and the CPU, and the hardware link between the CPU and the FPGA. The security authentication module is used to extract parameter information of the target image file; the parameter information includes the encryption public key and name corresponding to the target image file; and to perform security authentication on the target image file according to the parameter information and pre-built image file authentication rules. The device is further configured to, if the BIOS detects a reverse FPGA program acquisition attack in the storage content of the FPGA, provide pseudo-code to the reverse FPGA program acquisition attack according to a preset protection mechanism to protect the legitimate program code of the FPGA.

6. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the BIOS-based FPGA encryption method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein the computer programs, when executed by a processor, implement the BIOS-based FPGA encryption method as described in any one of claims 1 to 4.

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