Failure analysis method for tube core and stacked package chip

Abstract

The present invention discloses a method for analyzing a die failure and a method for analyzing a stacked packaged chip failure. The die includes a substrate and a device layer located on the substrate. The failure analysis method includes: locating a hotspot of a defect in the die from the back side of the die, i.e., the side where the substrate is located; removing the substrate from the back side of the die to expose the target circuit; and performing electrical measurements on the back side of the die to obtain defect information. The stacked packaged chip includes a lead frame, multiple dies stacked on the lead frame, and a packaging material covering the lead frame and the multiple dies. The failure analysis method includes: performing electrical measurements on the stacked packaged chip to determine the faulty die; if a faulty die that has not been subjected to failure analysis exists, repeating the failure analysis steps; the failure analysis steps include: removing a portion of the lead frame, the packaging material, and / or the die until the substrate of the first faulty die that has not been subjected to failure analysis is exposed; and performing failure analysis on the faulty die using the die failure analysis method.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a tube die failure analysis method and a stacked package chip failure analysis method. Background Art

[0002] 3D NAND memory, for example, is a stacked packaged chip, in which multiple dies are stacked and bonded together to form a multi-layer structure to provide greater storage capacity. As market demand for higher storage capacity per memory chip continues to increase, stacked dies can be stacked in up to 16 layers or even more. Using stacked packaging not only increases storage density but also offers improved lifespan, performance, and stability.

[0003] However, it becomes difficult to perform failure analysis on stacked packaged chips. When performing failure analysis on a single die, hotspot location is usually performed from the back of the die, that is, the side where the substrate is located. With the improvement of chip integration, a hotspot on the imaging contains hundreds or even more transistors. It is difficult to accurately locate the failure point by simply locating the hotspot from the back of the die. Therefore, after locating the hotspot from the back of the die, the existing technology needs to remove the layer from the front of the die to the target position to further locate the failure point. Therefore, when performing failure analysis on stacked packaged chips, it is necessary to grind from the back of the stacked packaged chip where the lead frame is located until the substrate of the faulty die is exposed, and grind from the front of the stacked packaged chip until the device layer of the faulty die is exposed, and then perform failure analysis according to the above-mentioned single die failure analysis method.

[0004] Existing failure analysis methods for single-die failure analysis require a long time to perform front-side layer removal, which can easily damage devices and circuit structures within the device layer, resulting in suboptimal failure analysis results. When performing failure analysis on stacked packaged chips, all dies except the faulty one must be removed to identify the faulty die. If two or more dies in a stacked package fail simultaneously, only one of the dies can be retained as the faulty die, and the remaining dies must be removed. This inevitably results in the loss of relevant defect information, hindering the discovery and correction of design and production defects. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a tube core failure analysis method and a stacked package chip failure analysis method. After preliminarily determining the target area including the failure point by hotspot positioning, the substrate of the target area is thinned to further accurately locate the failure point. The failure analysis can be performed only from the back side of the faulty tube core. Therefore, when there are multiple faulty tube cores in the stacked package chip, the faulty tube cores can be analyzed one by one to obtain more accurate defect information.

[0006] According to one aspect of the present invention, a method for analyzing a tube die failure is provided. The tube die includes a substrate and a device layer located on the substrate. The method comprises: locating a hotspot of a defect in the tube die from the back side of the tube die, i.e., the side where the substrate is located; removing the substrate from the back side of the tube die to expose a target circuit; and performing electrical measurements on the back side of the tube die to obtain defect information.

[0007] Optionally, after the step of locating a hotspot of a defect in the die from the back side of the die, the method further includes: forming a marking point on the substrate surface using a laser according to the hotspot location to determine a first target area.

[0008] Optionally, locating the hotspot of the defect in the die from the back side of the die includes: locating the hotspot of the defect in the die from the back side of the die using any one of a micro-light microscope and a light-induced resistance change, or a combination of the two.

[0009] Optionally, removing the substrate from the back side of the tube core to expose the target circuit includes: using either a focused ion beam or a plasma focused ion beam to cut the substrate material on the first target area, reducing the substrate thickness of the first target area to a preset value; determining a second target area including the target circuit according to the layout diagram, and using either the focused ion beam or the plasma focused ion beam to remove the substrate material of the second target area to form an opening exposing the target circuit; wherein, the second target area is located in the first target area.

[0010] Optionally, performing electrical measurement on the back side of the die to obtain defect information includes: electrically connecting a probe to the target circuit, and obtaining the defect information by electrically induced resistance change.

[0011] Optionally, the electrically induced resistance change used to obtain the defect information includes: using the electrically induced resistance change to locate the failure point, using either a focused ion beam or a plasma focused ion beam to make a sample of the failure point and performing failure analysis to obtain the defect information.

[0012] Optionally, the preset value is 2 microns.

[0013] Optionally, the first target area is a square with a side length of 150 microns.

[0014] According to another aspect of the present invention, a method for failure analysis of stacked packaged chips is provided, wherein the stacked packaged chip comprises a lead frame, a plurality of dies stacked on the lead frame, and a packaging material covering the lead frame and the plurality of dies, the method comprising: performing electrical measurements on the stacked packaged chip to determine a faulty die; if a faulty die that has not been subjected to failure analysis exists in the stacked packaged chip, repeating the failure analysis step; wherein the failure analysis step comprises: removing the lead frame, a portion of the packaging material, and / or the die until the substrate of the first faulty die that has not been subjected to failure analysis is exposed; and performing failure analysis on the faulty die using the failure analysis method as described above.

[0015] Optionally, removing the lead frame, a portion of the packaging material and / or the die includes: removing the lead frame, a portion of the packaging material and / or the die by a grinding process.

[0016] The failure analysis method for a faulty die in an embodiment of the present invention performs failure analysis on the faulty die from the back side where the substrate is located, which can preserve the circuits, devices and other structures in the device layer intact, and avoid the situation where the structure in the device layer is damaged, resulting in poor failure analysis results or even the inability to perform failure analysis.

[0017] Optionally, an embodiment of the present invention first reduces the thickness of the substrate material in the first target area of the substrate to a preset value, and then removes the substrate material on the second target area to expose the target circuit, thereby avoiding the situation where directly removing the substrate to expose the target circuit causes damage to the circuit, device and other structures in the device layer, and further ensures the integrity of the circuit and device in the first target area.

[0018] Optionally, an embodiment of the present invention uses EMMI (Emission Microscope) or OBIRCH (Optical Beam Induced Resistance Change) to locate hot spots with lower resolution. After exposing the target circuit, the probe is electrically connected to the target circuit, and then EBIRCH (Electrical Beam Induced Resistance Change) is used to accurately locate the failure point. The process is time-saving and has high positioning accuracy.

[0019] The failure analysis method for stacked packaged chips provided by an embodiment of the present invention performs failure analysis on all faulty die one by one in order of the distance between the faulty die and the lead frame when the stacked packaged chip includes two or more faulty die. Failure analysis information of multiple die can be obtained, thereby improving the analysis efficiency of the stacked packaged chip, which is conducive to correcting defects in design and production, improving generation efficiency, and improving the reliability and stability of the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A method flow chart showing a method for analyzing die failure according to an embodiment of the present invention;

[0022] Figures 2a to 2d A schematic structural diagram showing various steps of a die failure analysis method according to an embodiment of the present invention;

[0023] Figure 3 A flowchart showing a method for analyzing failure of stacked packaged chips according to an embodiment of the present invention is provided;

[0024] Figures 4a to 4c A structural schematic diagram showing various steps of a stacked package chip failure analysis method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical components or modules are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0027] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0028] In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of manufacturing a memory device, including all formed layers or regions. Numerous specific details of the present invention, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without adherence to these specific details.

[0029] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0030] Figure 1 A flow chart showing a method for analyzing die failure according to an embodiment of the present invention is shown. Figures 2a to 2d The schematic diagram of the structure of each step of the tube core failure analysis method according to the embodiment of the present invention is shown. Figures 2a to 2d ,right Figure 1 The method flow chart is described.

[0031] The die 220 includes a substrate 221 and a device layer 222 located on the substrate 221. The substrate 221 is, for example, a silicon substrate, and the device layer 222 includes, for example, circuits, devices and other structures.

[0032] In step S410 , hotspot location of defects in the die 220 is performed from the back side of the die 220 , that is, the side where the substrate 221 is located.

[0033] like Figure 2a As shown, Figure 2a A cross-sectional view and a bottom view of the die 220 are shown, and a hotspot 223 of the die 220 is located from the back side of the die 220 using either EMMI, OBIRCH, or a combination of both.

[0034] In an optional embodiment, a laser is used to form a plurality of marking points 224 on the surface of the substrate 221 away from the device layer 222 to define a first target area 225 , wherein the hot spot 223 is located within the first target area 225 .

[0035] Step S420: removing the substrate 221 from the back side of the die 220 to expose the target circuit. Step S420 includes:

[0036] Step S421, cutting the substrate material on the first target area. Figure 2b As shown, Figure 2b A cross-sectional view and a bottom view of the tube core 220 are shown, and a PFIB (Plasma focused ion beam) or FIB (Focused ion beam) is used to cut the substrate material on the first target area 225 until the thickness of the substrate 221 within the first target area 225 is reduced to a preset value x1 to form a first opening 226.

[0037] Optionally, the first target area is, for example, selected from a square with a side length of 150 micrometers, and the preset value x1 is, for example, selected from 2 micrometers.

[0038] The use of PFIB or FIB cutting has higher precision and better controllability, and can avoid material deformation caused by the grinding process, maintain the structural strength of the substrate 221, and prevent the tube core 220 from cracking during subsequent processing.

[0039] Step S422: removing the substrate material in the second target area. Figure 2c Shown Figure 2b A partial enlarged view of the first opening 226 in the die 220 is shown. The second target area 227 including the target circuit is determined according to the layout diagram of the die 220, and the substrate material of the second target area 227 is removed by using either PFIB or FIB to obtain the following: Figure 2d The second opening 229 is formed to expose the target line 228. The first opening 226 and the second opening 229 together constitute an opening for exposing the target line 228.

[0040] In step S430, electrical measurements are performed on the back side of the die 220 to obtain defect information. The nanoprobe is electrically connected to the target circuit 228, and EBIRCH is used to further locate the precise failure point 228. Samples are then made and failure analysis is performed to obtain defect information.

[0041] In a feasible embodiment, the failure point 228 is cut and sampled using a PFIB or a FIB for failure analysis, thereby obtaining information on defects of the die 220 .

[0042] The tube core failure analysis method of the embodiment of the present invention performs failure analysis on the tube core 220 from the back side where the substrate 221 is located, which can preserve the circuits, devices and other structures in the device layer 222 intact, and avoid the situation where the structure in the device layer 222 is damaged, resulting in poor failure analysis results or even the inability to perform failure analysis.

[0043] Optionally, an embodiment of the present invention first reduces the thickness of the substrate material of the first target area 225 in the substrate 221 to a preset value x1, and then removes the substrate material on the second target area 227 to expose the target circuit 228, thereby avoiding the situation where directly removing the substrate to expose the target circuit causes damage to the circuit, device and other structures in the device layer 222, and further ensures the integrity of the circuit and device in the first target area 225.

[0044] Optionally, the embodiment of the present invention first uses EMMI / OBIRCH to locate the hotspot with lower resolution, removes the substrate material to expose the target circuit 228, and then electrically connects the probe to the target circuit 228, and then uses EBIRCH to accurately locate the failure point 230. The process is time-saving and has high positioning accuracy.

[0045] Figure 3 A flowchart showing a method for analyzing failure of stacked packaged chips according to an embodiment of the present invention is shown. Figures 4a to 4c The schematic diagram of each step of the stacked package chip failure location method according to an embodiment of the present invention is shown. Figures 4a to 4c ,right Figure 3 The method flow chart is described.

[0046] like Figure 4a As shown, the stacked package chip 200 includes a lead frame 210, die 220-1 to 220-8 stacked on the lead frame 210, a packaging material (not shown) covering the lead frame 210 and the die 220-1 to 220-8, and bonding wires 240 for connecting adjacent die and between the die and the lead frame 210. It should be understood that this embodiment takes the stacked package chip 200 as an example including eight die, two of which are failed die, however, the present invention is not limited thereto, and the stacked package chip 200 may include four or sixteen die, of which the number of failed die may be one or three.

[0047] Step S100 : performing electrical measurements on the stacked packaged chips to determine a faulty die.

[0048] Electrical measurements are performed on the stacked package chip 200 , for example, using EFA (Electrical failure analysis) to determine that the die 220 - 4 and the die 220 - 6 are faulty dies.

[0049] In an alternative embodiment, after the step of determining that die 220-4 and die 220-6 are faulty die using EFA, the faulty die 220-4 and the faulty die 220-6 are marked, for example, by using a probe to mark the pads of the faulty die 220-4 and the faulty die 220-6.

[0050] Step S200 , determining whether there is a faulty die that has not been subjected to failure analysis, if so, executing step S300 ; if not, executing step S500 .

[0051] In the stacked package chip 200 , if the faulty die 220 - 4 and the faulty die 220 - 6 have not been subjected to failure analysis, step S300 is executed.

[0052] Step S300 , removing the lead frame 210 , a portion of the packaging material and / or a portion of the die, until the substrate of the first faulty die that has not been subjected to failure analysis is exposed.

[0053] The lead frame 210, a portion of the packaging material and the tube cores 220-1 to 220-3 are removed by a grinding process until the substrate of the faulty tube core 220-4 is exposed, and the result is as shown in FIG. Figure 4b The semiconductor structure shown.

[0054] Step S400 , performing failure analysis on the die using a die failure analysis method.

[0055] Use Figure 1 The die failure analysis method shown performs failure analysis on the faulty die 220 - 4 from the back side.

[0056] After the failure analysis is completed, step S200 is executed.

[0057] In this embodiment, the faulty die 200 - 6 of the stacked package chip 200 has not yet been subjected to failure analysis, and the above steps are continued:

[0058] The die 220-4 and the die 220-5 are removed by a grinding process until the substrate of the faulty die 220-6 is exposed, and the substrate is obtained as shown in FIG. Figure 4c The semiconductor structure shown in FIG. Figure 1 The die failure analysis method shown in the figure performs a failure analysis on the faulty die 220-6 from the back side. After the analysis is completed, step 200 is executed. At this time, all the faulty dies have completed the failure analysis, and step S500 is executed.

[0059] Step S500 , end. The failure analysis of all faulty dies in the stacked package chip 200 has been completed.

[0060] Optionally, the stacked package chip 200 is selected from a three-dimensional memory, for example.

[0061] The failure analysis method for stacked packaged chips provided by an embodiment of the present invention performs failure analysis on all faulty die one by one in order of the distance between the faulty die and the lead frame when the stacked packaged chip includes two or more faulty die. Failure analysis information of multiple die can be obtained, thereby improving the analysis efficiency of the stacked packaged chip, which is conducive to correcting defects in design and production, improving generation efficiency, and improving the reliability and stability of the manufacturing process.

[0062] To sum up, the failure analysis method of the faulty tube core in the embodiment of the present invention performs failure analysis on the faulty tube core from the back side where the substrate is located, which can preserve the circuits, devices and other structures in the device layer intact, and avoid the situation where the structure in the device layer is damaged, resulting in poor failure analysis results or even the inability to perform failure analysis.

[0063] Optionally, an embodiment of the present invention first reduces the thickness of the substrate material in the first target area of the substrate to a preset value, and then removes the substrate material on the second target area to expose the target circuit, thereby avoiding the situation where directly removing the substrate to expose the target circuit causes damage to the circuit, device and other structures in the device layer, and further ensures the integrity of the circuit and device in the first target area.

[0064] Optionally, the embodiment of the present invention uses EMMI / OBIRCH to locate hot spots with lower resolution, exposes the target circuit, electrically connects the probe to the target circuit, and then uses EBIRCH to accurately locate the failure point. The process is time-saving and has high positioning accuracy.

[0065] The failure analysis method for stacked packaged chips provided by an embodiment of the present invention performs failure analysis on all faulty die one by one in order of the distance between the faulty die and the lead frame when the stacked packaged chip includes two or more faulty die. Failure analysis information of multiple die can be obtained, thereby improving the analysis efficiency of the stacked packaged chip, which is conducive to correcting defects in design and production, improving generation efficiency, and improving the reliability and stability of the manufacturing process.

[0066] It should be noted that one of ordinary skill in the art will understand that the terms "during", "when" and "when..." used herein in connection with circuit operation are not strict terms indicating that an action occurs immediately upon the start of the initiation action, but rather that there may be some small but reasonable delay or delays between the action and the reaction action initiated by the initiation action, such as various transmission delays. The terms "approximately" or "substantially" used herein mean that an element value has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) (for semiconductor doping concentrations, at least twenty percent (20%)) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive logic or negative logic is used.

[0067] The embodiments of the present invention are as described above, but these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A tube die failure analysis method, wherein the tube die comprises a substrate and a device layer located on the substrate, The failure analysis method includes: performing hotspot location of defects in the die from the back side of the die, i.e., the side where the substrate is located; According to the hotspot positioning, a laser is used to form a marking point on the substrate surface to determine a first target area; From the back side of the die, reducing the thickness of the substrate in the first target area to a preset value; determining a second target area including a target line according to the layout diagram, wherein the second target area is located in the first target area; removing the substrate material of the second target area from the back side of the die to form an opening exposing the target circuit; as well as Electrical measurements are performed on the back side of the die to obtain defect information.

2. The die failure analysis method according to claim 1, wherein locating a hotspot of a defect in the die from the back side of the die comprises: Hot spots of defects in the die are located from the back side of the die using either a micro-light microscope or a light-induced resistance change, or a combination of the two.

3. The method for analyzing die failure according to claim 1 , wherein in the step of reducing the thickness of the substrate in the first target area to a preset value, a focused ion beam or a plasma focused ion beam is used to cut the substrate material in the first target area. In the step of removing the substrate material of the second target area to form an opening exposing the target circuit, either the focused ion beam or the plasma focused ion beam is used to remove the substrate material of the second target area.

4. The method for analyzing die failure according to claim 1 , wherein performing electrical measurement on the back side of the die to obtain defect information comprises: The probe is electrically connected to the target circuit, and information about the defect is obtained by using an electrically induced resistance change.

5. The die failure analysis method according to claim 4, wherein obtaining the defect information by using the electrically induced resistance change comprises: The failure point is located by using an electrically induced resistance change, and the failure point is made into a sample by using either a focused ion beam or a plasma focused ion beam and a failure analysis is performed to obtain information about the defect. The tube die failure analysis method according to claim 1 , wherein the preset value is 2 microns. The die failure analysis method according to claim 1 , wherein the first target area is a square with a side length of 150 μm.

8. A method for analyzing failure of a stacked packaged chip, the stacked packaged chip comprising a lead frame, a plurality of dies stacked on the lead frame, and a packaging material covering the lead frame and the plurality of dies. The failure analysis method includes: Performing electrical measurements on the stacked packaged chips to determine a faulty die; If there is a faulty die in the stacked package chip that has not been subjected to failure analysis, the failure analysis step is repeated; wherein, The failure analysis steps include: removing the lead frame, a portion of the encapsulation material, and / or the die until the substrate of a first failed die not subjected to failure analysis is exposed; Failure analysis is performed on the faulty die using the failure analysis method according to any one of claims 1 to 7.

9. The stacked package chip failure analysis method according to claim 8, wherein removing the lead frame, a portion of the packaging material, and / or the die comprises: The lead frame, a portion of the packaging material and / or the die are removed by a grinding process.

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