A silicon carbide MIS device with stacked gate structure and preparation method thereof
By using the stacked gate structure and nitrogen plasma passivation treatment of AlN and Al2O3 materials stacked in SiC-MIS devices, the problem of unsatisfactory connection between SiO2 and SiC is solved, and high dielectric constant and low interface state density are achieved, improving the The reliability and stability of the device.
Patent Information
- Application Number
- CN202110817730.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-07-20
- Publication Date
- 2024-12-24
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
SiC-MIS devices encounter challenges in terms of gate dielectric layer reliability and electron mobility. The interface connection between SiO2 and SiC is not ideal, resulting in an increase in interface state and a high interface state near the conduction band bottom aggravates channel scattering and carriers. Capture, affects device reliability and performance.
AlN and Al2O3 materials are stacked to form a gate dielectric layer, using the advantages of AlN and 4H-SiC lattice mismatch to improve interface quality, reduce leakage current density, and optimize interface connection to AlN surface passivation treatment through nitrogen plasma, combined with The bandwidth-blocking Al2O3 material pushes the interface state to the center of the bandgap.
A stacked gate structure with high dielectric constant, high critical electric field and low interfacial state density is realized, which improves the reliability and stability of SiC-MIS devices and avoids the impact of quantum tunneling effect on the device.
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Figure CN113871468B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of microelectronics technology, and in particular to a stacked gate dielectric silicon carbide MIS device with a high dielectric constant and a preparation method thereof. Background Art
[0002] Silicon carbide (SiC) material is a wide bandgap semiconductor with excellent performance. It not only has high thermal conductivity, high critical breakdown field strength, and high saturated electron drift rate, but also has stable physical and chemical properties, extremely high radiation resistance and mechanical strength. In recent years, it has rapidly developed into a research hotspot in the fields of high-temperature, high-frequency, and high-power electronic devices.
[0003] Despite this, SiC-based metal-insulator-semiconductor (SiC-MIS) devices have encountered great challenges in terms of gate dielectric layer reliability and electron mobility. The commonly used insulating gate dielectric is SiO2, but the interface connection between SiC and SiO2 is not ideal. A large number of interface dangling bond carbon clusters cause high interface states near the bottom of the conduction band, aggravating channel scattering and carrier capture, reducing channel mobility, and affecting device reliability. At the same time, the dielectric constant of SiO2 is lower than that of SiC, making the electric field inside SiO2 stronger and breaking down earlier. The combination of SiC and SiO2 fails to give full play to the advantages of SiC materials. With the development of semiconductor manufacturing processes, the size of devices continues to shrink. When the SiO2 gate dielectric reaches the ideal physical limit thickness (less than 5nm), the quantum tunneling effect may even cause device failure.
[0004] Therefore, it is necessary to find a dielectric layer with high dielectric constant and good interface matching to replace SiO2 in order to improve the reliability of SiC-MIS devices. Summary of the invention
[0005] In response to the problems in the related art, the present invention proposes a SiC-MIS device with a stacked gate structure and a preparation method thereof. AlN and Al2O3 materials are stacked to form a gate dielectric layer, and the advantage of the small lattice mismatch between AlN and 4H-SiC is used to improve the interface quality and reduce the leakage current density. The surface of the AlN film is passivated by nitrogen plasma, and the AlN surface formed by the plasma treatment with strong reaction activity is flat and has no reconstruction, which optimizes the interface connection between the bottom gate dielectric and the upper gate dielectric. Combined with the Al2O3 material with a wider bandgap, the interface state that may appear near the bottom of the 4H-SiC conduction band is pushed to the center of the bandgap. The present invention provides a stacked gate structure dielectric layer with a high dielectric constant, a high critical electric field and a low interface state density and a preparation method thereof to solve the problems raised in the above background technology.
[0006] In order to achieve the above technical objectives, the technical solution of the present invention is as follows:
[0007] A SiC-MIS device is designed, whose structure includes, from bottom to top, a back electrode, an N+ substrate layer, an N-type homoepitaxial layer, a bottom gate dielectric, a dielectric interface passivation layer, an upper gate dielectric, and a gate electrode. The bottom gate dielectric and the upper gate dielectric are stacked to form a gate dielectric layer.
[0008] Furthermore, the N+ substrate layer is doped with a concentration of 5×10 18 cm -3 The N-type 4H-SiC with phosphorus ions, the thickness of the N+ substrate layer is 500 μm.
[0009] Furthermore, the N-type epitaxial layer is doped with a concentration of 8×10 15 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 1 μm to 100 μm.
[0010] Furthermore, the first gate dielectric layer is made of AlN material, the bottom gate dielectric layer has a thickness of about 2 nm, and the surface is passivated by nitrogen plasma.
[0011] Furthermore, the upper gate dielectric is made of Al2O3 material, and the thickness of the upper gate dielectric is 20 nm.
[0012] Furthermore, the back electrode is an Al film with a thickness of about 200 μm.
[0013] Furthermore, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
[0014] A method for preparing a silicon carbide MIS device with a stacked gate structure comprises the following steps:
[0015] Step S1, the thickness is 350 μm and the nitrogen ion doping concentration is 5×10 18 cm -3 The N+ silicon carbide substrate is cleaned by RCA at a temperature of 1600°C, a pressure of 150 mbar, reaction gases of silane and propane, a doping source gas of PH3, and a carrier gas of PH3;
[0016] Step S2, growing an N-type epitaxial layer on the cleaned N+ substrate layer and performing a process, doping ions with phosphorus ions and a doping concentration of 8×10 15 cm -3 N-type 4H-SiC, with a thickness of 1μm to 100μm;
[0017] Step S3, cleaning the 4H-SiC epitaxial substrate substrate, sequentially performing organic solution ultrasonic cleaning, alkali cleaning, and acid cleaning on the sample, soaking in 5% HF solution after each cleaning step, then rinsing in deionized water, and drying with nitrogen;
[0018] Step S4, using a magnetron sputtering process to prepare an underlying gate dielectric AlN film on the N-type epitaxial layer;
[0019] Step S5, passivating the surface using nitrogen plasma to form an ultra-thin dielectric interface passivation layer;
[0020] Step S6, using a magnetron sputtering process to prepare an upper gate dielectric Al2O3 film on the bottom gate dielectric, and annealing the sample formed of the gate dielectric;
[0021] Step S7, depositing Al metal on the back to prepare a back electrode;
[0022] Step S8, depositing Al metal on the front side to prepare the gate electrode, and completing the MIS device manufacturing.
[0023] Furthermore, in step S2, the process conditions are as follows: temperature is 1600° C., pressure is 150 mbar, reaction gases are silane and propane, and doping source gas is PH3.
[0024] Beneficial effects of the present invention:
[0025] 1. The present invention utilizes magnetron sputtering technology to prepare SiC-MIS devices. Compared with the traditional preparation technology, it can avoid the problem of carbon cluster aggregation at the interface of 4H-SiC and gate dielectric, and reduce the thermal budget.
[0026] 2. The present invention adopts stacked gate dielectrics. The two selected materials, AlN and Al2O3, have the advantages of large bandgap width and high dielectric constant. Compared with the traditional SiO2 as the dielectric layer, it can increase the physical thickness of the gate dielectric layer while ensuring the same capacitance, avoid the influence of quantum tunneling effect on the device, and improve the stability of the device.
[0027] 3. The bottom gate dielectric of the present invention is AlN material, which has a similar lattice constant to 4H-SiC and a small lattice mismatch, can improve interface characteristics and effectively alleviate the problem of excessive interface states.
[0028] 4. The present invention uses nitrogen plasma to passivate the surface of the bottom gate dielectric AlN. The AlN surface formed by the highly reactive plasma treatment is flat and has no reconstruction, which optimizes the interface connection between the bottom gate dielectric and the upper gate dielectric. At the same time, some ions passivate the dangling bonds of the SiC substrate, avoiding high-energy particles from directly damaging the silicon carbide surface. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0030] Figure 1 is a schematic structural diagram of a silicon carbide MIS device with a stacked gate structure according to an embodiment of the present invention;
[0031] Figure 2 FIG. 1 is a schematic diagram of step S2 of a process flow of a silicon carbide MIS device having a stacked gate structure according to an embodiment of the present invention. Figure 1 ;
[0032] Figure 3 FIG. 4 is a schematic diagram of step S4 of a process flow of a silicon carbide MIS device having a stacked gate structure according to an embodiment of the present invention. Figure 2 ;
[0033] Figure 4 FIG. 5 is a schematic diagram of step S5 of a process flow of a silicon carbide MIS device having a stacked gate structure according to an embodiment of the present invention. Figure 3 ;
[0034] Figure 5 FIG. 6 is a schematic diagram of step S6 of a process flow of a silicon carbide MIS device having a stacked gate structure according to an embodiment of the present invention. Figure 4 ;
[0035] Figure 6 FIG. 1 is a schematic diagram of step S7 of a process flow of a silicon carbide MIS device having a stacked gate structure according to an embodiment of the present invention. Figure 5 ;
[0036] In the figure: 1, N+ substrate layer; 2, N-type epitaxial layer; 3, bottom gate dielectric; 4, dielectric interface passivation layer; 5, upper gate dielectric; 6, back electrode; 7, gate electrode. DETAILED DESCRIPTION
[0037] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.
[0038] Embodiment 1:
[0039] like Figure 1As shown, a silicon carbide MIS device with a stacked gate structure according to an embodiment of the present invention comprises, from bottom to top, a back electrode 6, an N+ substrate layer 1, an N-type epitaxial layer 2, a bottom gate dielectric 3, a dielectric interface passivation layer 4, an upper gate dielectric 5, and a gate electrode 7. The bottom gate dielectric 3, the dielectric interface passivation layer 4 and the upper gate dielectric 5 are stacked to form a gate dielectric layer.
[0040] In this embodiment, the N+ substrate layer 1 is doped with a concentration of 5×10 18 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 350 μm.
[0041] In this embodiment, the N-type epitaxial layer is doped with a concentration of 8×10 15 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 1 μm to 100 μm.
[0042] In this embodiment, the first gate dielectric layer is made of AlN material, the bottom gate dielectric layer has a thickness of 2 nm, and the surface is passivated by nitrogen plasma.
[0043] In this embodiment, the upper gate dielectric is made of Al2O3 material, and the thickness of the upper gate dielectric is 20 nm.
[0044] In this embodiment, the back electrode is an Al film with a thickness of about 200 nm.
[0045] In this embodiment, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
[0046] like Figure 2-6 As shown, a method for preparing a silicon carbide MIS device with a stacked gate structure comprises the following steps:
[0047] Step S1, taking a thickness of 350 μm and a nitrogen ion doping concentration of 5×10 18 cm -3 The N+ silicon carbide substrate layer 1 is RCA cleaned at a temperature of 1600° C., a pressure of 150 mbar, reaction gases of silane and propane, a doping source gas of PH3, and a carrier gas of PH3;
[0048] Step S2, growing an N-type epitaxial layer 2 on the cleaned N+ substrate layer 1, and performing a process, wherein the doping ions are phosphorus ions, and the doping concentration is 8×10 15 cm -3 N-type 4H-SiC, with a thickness of 1μm to 100μm;
[0049] Step S3, the 4H-SiC epitaxial substrate substrate is cleaned by a wet process to remove organic matter and natural oxides, and the sample is sequentially subjected to organic solution ultrasonic cleaning, alkali cleaning, and acid cleaning. After each cleaning step, it is immersed in a 5% HF solution, then rinsed in deionized water, and dried with nitrogen; finally, after soaking in a 5% HF solution at a temperature of 80° C. for 5 minutes, the substrate is ultrasonically cleaned with deionized water for 20 minutes, then rinsed with deionized water several times, and finally dried with nitrogen;
[0050] Step S4, preparing a bottom gate dielectric 3 on the N-type epitaxial layer 2. In this embodiment, a magnetron sputtering process is used, and the bottom gate matrix 3 is AlN material. The bottom gate dielectric 3 is obtained with a thickness of about 2 nm;
[0051] Step S5, placing the obtained sample into a plasma degumming machine, and passivating the surface of the bottom gate dielectric with nitrogen plasma to obtain an ultra-thin interface passivation layer 4;
[0052] Step S6, prepare an upper gate dielectric 5 on the interface passivation layer 4. In this embodiment, a magnetron sputtering process is used. The upper gate dielectric 5 is made of Al2O3 material. The distance between the target and the substrate is adjusted, the substrate is evacuated and heated, and high-purity oxygen is introduced as a reaction gas. After natural cooling, the upper gate dielectric 5 is obtained, and the thickness is about 20nm. Then, the sample formed of the gate dielectric is placed in an annealing furnace, and high-purity oxygen and nitrogen are introduced for high-temperature annealing;
[0053] Step S7, preparing a back electrode 6, depositing a metal electrode on the back of the sample by a magnetron sputtering process, wherein the material of the back electrode 6 is Al, and the thickness of the back electrode 6 is 200 nm;
[0054] Step S8, prepare the gate electrode 7, and use the magnetron sputtering process to deposit the metal electrode on the front side of the sample. The gate electrode 7 is made of Al, has a cylindrical shape, a diameter of 500 μm, and a thickness of 200 nm, and the SiC-MIS device is manufactured.
[0055] In this embodiment, in step S2, the process conditions are: temperature is 1600° C., pressure is 150 mbar, reaction gases are silane and propane, and doping source gas is PH3.
[0056] In this embodiment, in step S4, the magnetron sputtering process parameters are: argon gas flow rate 30 sccm, ignition power 30 W, background vacuum degree 5×10 -5 Pa, sputtering gas pressure 0.65Pa, sputtering time 60 to 120s.
[0057] In this embodiment, in step S5, the passivation treatment parameters are: power 50W, nitrogen flow rate 1.5L / min, and treatment time 60 to 200s.
[0058] In the present embodiment, in step S6, the magnetron sputtering process parameters are: argon flow rate 30 sccm, oxygen flow rate 5 sccm-15 sccm, ignition power 30 W, background vacuum 5×10 -4 Pa, sputtering gas pressure 0.65Pa, substrate temperature 400℃, sputtering time 40min; annealing treatment is divided into in-situ low-temperature annealing and slow high-temperature annealing, and the in-situ low-temperature annealing parameters are oxygen flow rate 30sccm, temperature 400℃, and gas pressure 7Pa. The slow high-temperature annealing process parameters are to control the oxygen and nitrogen flow ratio to 1:2, and the slow high-temperature annealing includes a heating process, a heat preservation process, and a natural cooling process. The heating process needs to be heated to 1100℃ through two gradient stages.
[0059] Embodiment 2:
[0060] like Figure 1 As shown, a silicon carbide MIS device with a stacked gate structure according to an embodiment of the present invention comprises, from bottom to top, a back electrode 6, an N+ substrate layer 1, an N-type epitaxial layer 2, a bottom gate dielectric 3, a dielectric interface passivation layer 4, an upper gate dielectric 5, and a gate electrode 7. The bottom gate dielectric 3, the dielectric interface passivation layer 4 and the upper gate dielectric 5 are stacked to form a gate dielectric layer.
[0061] In this embodiment, the N+ substrate layer 1 is doped with a concentration of 5×10 18 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 350 μm.
[0062] In this embodiment, the N-type epitaxial layer is doped with a concentration of 8×10 15 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 1 μm to 100 μm.
[0063] In this embodiment, the first gate dielectric layer is made of AlN material, the bottom gate dielectric layer has a thickness of 7 nm, and the surface is passivated by nitrogen plasma.
[0064] In this embodiment, the upper gate dielectric is made of Al2O3 material, and the thickness of the upper gate dielectric is 15 nm.
[0065] In this embodiment, the back electrode is an Al film with a thickness of about 200 nm.
[0066] In this embodiment, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
[0067] like Figure 2-6As shown, a method for preparing a silicon carbide MIS device with a stacked gate structure comprises the following steps:
[0068] Step S1, taking a thickness of 300 μm and a nitrogen ion doping concentration of 5×10 18 cm -3 The N+ silicon carbide substrate layer 1 is RCA cleaned at a temperature of 1600° C., a pressure of 150 mbar, reaction gases of silane and propane, a doping source gas of PH3, and a carrier gas of PH3;
[0069] Step S2, growing an N-type epitaxial layer 2 on the cleaned N+ substrate layer 1, and performing a process, wherein the doping ions are phosphorus ions, and the doping concentration is 8×10 15 cm -3 N-type 4H-SiC, with a thickness of 1μm to 100μm;
[0070] Step S3, the 4H-SiC epitaxial substrate substrate is cleaned by a wet process to remove organic matter and natural oxides, and the sample is sequentially subjected to organic solution ultrasonic cleaning, alkali cleaning, and acid cleaning. After each cleaning step, it is immersed in a 5% HF solution, then rinsed in deionized water, and dried with nitrogen; finally, after soaking in a 5% HF solution at a temperature of 80° C. for 5 minutes, the substrate is ultrasonically cleaned with deionized water for 20 minutes, then rinsed with deionized water several times, and finally dried with nitrogen;
[0071] Step S4, preparing a bottom gate dielectric 3 on the N-type epitaxial layer 2. In this embodiment, a magnetron sputtering process is used, and the bottom gate matrix 3 is AlN material. The bottom gate dielectric 3 is obtained, and the thickness is about 7 nm;
[0072] Step S5, placing the obtained sample into a plasma degumming machine, and passivating the surface of the bottom gate dielectric with nitrogen plasma to obtain an ultra-thin interface passivation layer 4;
[0073] Step S6, prepare an upper gate dielectric 5 on the interface passivation layer 4. In this embodiment, a magnetron sputtering process is used. The upper gate dielectric 5 is made of Al2O3 material. The distance between the target and the substrate is adjusted to evacuate and heat the substrate. High-purity oxygen is introduced as a reaction gas. After natural cooling, the upper gate dielectric 5 is obtained. The thickness is about 15nm. Then, the sample formed of the gate dielectric is placed in an annealing furnace, and high-purity oxygen and nitrogen are introduced for high-temperature annealing;
[0074] Step S7, preparing a back electrode 6, depositing a metal electrode on the back of the sample by a magnetron sputtering process, wherein the material of the back electrode 6 is Al, and the thickness of the back electrode 6 is 200 nm;
[0075] Step S8, prepare the gate electrode 7, and use the magnetron sputtering process to deposit the metal electrode on the front side of the sample. The gate electrode 7 is made of Al, has a cylindrical shape, a diameter of 500 μm, and a thickness of 200 nm, and the SiC-MIS device is manufactured.
[0076] In this embodiment, in step S2, the process conditions are: temperature is 1600° C., pressure is 150 mbar, reaction gases are silane and propane, and doping source gas is PH3.
[0077] In the present embodiment, in step S4, the magnetron sputtering process parameters are: argon gas flow rate 30 sccm, ignition power 30 W, background vacuum degree 9×10 -5 Pa, sputtering gas pressure 0.65Pa, sputtering time 210 ~ 420s.
[0078] In this embodiment, in step S5, the passivation treatment parameters are: power 50W, nitrogen flow rate 1.5L / min, and treatment time 60 to 200s.
[0079] In the present embodiment, in step S6, the magnetron sputtering process parameters are: argon flow rate 30 sccm, oxygen flow rate 5 sccm-15 sccm, ignition power 30 W, background vacuum 5×10 -4 Pa, sputtering gas pressure 0.65Pa, substrate temperature 400℃, sputtering time 40min; annealing treatment is divided into in-situ low-temperature annealing and slow high-temperature annealing, and the in-situ low-temperature annealing parameters are oxygen flow rate 30sccm, temperature 400℃, and gas pressure 7Pa. The slow high-temperature annealing process parameters are to control the oxygen and nitrogen flow ratio to 1:2, and the slow high-temperature annealing includes a heating process, a heat preservation process, and a natural cooling process. The heating process needs to be heated to 1100℃ through two gradient stages.
[0080] Embodiment three:
[0081] like Figure 1 As shown, a silicon carbide MIS device with a stacked gate structure according to an embodiment of the present invention comprises, from bottom to top, a back electrode 6, an N+ substrate layer 1, an N-type epitaxial layer 2, a bottom gate dielectric 3, a dielectric interface passivation layer 4, an upper gate dielectric 5, and a gate electrode 7. The bottom gate dielectric 3, the dielectric interface passivation layer 4 and the upper gate dielectric 5 are stacked to form a gate dielectric layer.
[0082] In this embodiment, the N+ substrate layer 1 is doped with a concentration of 5×10 18 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 350 μm.
[0083] In this embodiment, the N-type epitaxial layer is doped with a concentration of 8×10 15 cm -3 The N-type 4H-SiC with phosphorus ions has a thickness of 1 μm to 100 μm.
[0084] In this embodiment, the first gate dielectric layer is made of AlN material, the bottom gate dielectric layer has a thickness of 2 nm, and the surface is passivated by nitrogen plasma.
[0085] In this embodiment, the upper gate dielectric is made of Al2O3 material, and the thickness of the upper gate dielectric is 20 nm.
[0086] In this embodiment, the back electrode is an Al film with a thickness of about 200 nm.
[0087] In this embodiment, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
[0088] like Figure 2-6 As shown, a method for preparing a silicon carbide MIS device with a stacked gate structure comprises the following steps:
[0089] Step S1, taking a thickness of 350 μm and a nitrogen ion doping concentration of 5×10 18 cm -3 The N+ silicon carbide substrate layer 1 is RCA cleaned at a temperature of 1600° C., a pressure of 150 mbar, reaction gases of silane and propane, a doping source gas of PH3, and a carrier gas of PH3;
[0090] Step S2, growing an N-type epitaxial layer 2 on the cleaned N+ substrate layer 1, and performing a process, wherein the doping ions are phosphorus ions, and the doping concentration is 8×10 15 cm -3 N-type 4H-SiC, with a thickness of 1μm to 100μm;
[0091] Step S3, the 4H-SiC epitaxial substrate substrate is cleaned by a wet process to remove organic matter and natural oxides, and the sample is sequentially subjected to organic solution ultrasonic cleaning, alkali cleaning, and acid cleaning. After each cleaning step, it is immersed in a 5% HF solution, then rinsed in deionized water, and dried with nitrogen; finally, after soaking in a 5% HF solution at a temperature of 80° C. for 5 minutes, the substrate is ultrasonically cleaned with deionized water for 20 minutes, then rinsed with deionized water several times, and finally dried with nitrogen;
[0092] Step S4, preparing a bottom gate dielectric 3 on the N-type epitaxial layer 2. In this embodiment, a magnetron sputtering process is used, and the bottom gate matrix 3 is AlN material. The bottom gate dielectric 3 is obtained with a thickness of about 2 nm;
[0093] Step S5, placing the obtained sample into a plasma degumming machine, and passivating the surface of the bottom gate dielectric with nitrogen plasma to obtain an ultra-thin interface passivation layer 4;
[0094] Step S6, prepare an upper gate dielectric 5 on the interface passivation layer 4. In this embodiment, a magnetron sputtering process is used. The upper gate dielectric 5 is made of Al2O3 material. The distance between the target and the substrate is adjusted, the substrate is evacuated and heated, and high-purity oxygen is introduced as a reaction gas. After natural cooling, the upper gate dielectric 5 is obtained, and the thickness is about 20nm. Then, the sample formed of the gate dielectric is placed in an annealing furnace, and high-purity oxygen and nitrogen are introduced for high-temperature annealing;
[0095] Step S7, preparing a back electrode 6, depositing a metal electrode on the back of the sample by a magnetron sputtering process, wherein the material of the back electrode 6 is Al, and the thickness of the back electrode 6 is 200 nm;
[0096] Step S8, prepare the gate electrode 7, and use the magnetron sputtering process to deposit the metal electrode on the front side of the sample. The gate electrode 7 is made of Al, has a cylindrical shape, a diameter of 500 μm, and a thickness of 200 nm, and the SiC-MIS device is manufactured.
[0097] In this embodiment, in step S2, the process conditions are: temperature is 1600° C., pressure is 150 mbar, reaction gases are silane and propane, and doping source gas is PH3.
[0098] In the present embodiment, in step S4, the magnetron sputtering process parameters are: argon gas flow rate 30 sccm, ignition power 30 W, background vacuum degree 9×10 -5 Pa, sputtering gas pressure 0.65Pa, sputtering time 60 to 120s.
[0099] In this embodiment, in step S5, the passivation treatment parameters are: power 10-50 W, nitrogen flow rate 1.5 L / min, and treatment time 60-200 s.
[0100] In the present embodiment, in step S6, the magnetron sputtering process parameters are: argon flow rate 30 sccm, oxygen flow rate 5 sccm-15 sccm, ignition power 30 W, background vacuum 5×10 -4Pa, sputtering gas pressure 0.65Pa, substrate temperature 400℃, sputtering time 40min; annealing treatment is divided into in-situ low-temperature annealing and slow high-temperature annealing, and the in-situ low-temperature annealing parameters are oxygen flow rate 30sccm, temperature 400℃, and gas pressure 7Pa. The slow high-temperature annealing process parameters are to control the oxygen and nitrogen flow ratio to 1:2, and the slow high-temperature annealing includes a heating process, a heat preservation process, and a natural cooling process. The heating process needs to be heated to 1100℃ through two gradient stages.
[0101] The above specific implementation examples illustrate the efficacy and principle of the present invention, but are not intended to limit the present invention. Any modification or modification completed by researchers in this field under the guidance of the present invention without violating the spirit and principle of the present invention shall be regarded as an equivalent replacement of the present invention, and shall be covered by the claims of the present invention and protected by the present invention.
[0102] In the description of the present invention, it is necessary to understand that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0103] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0104] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for preparing a silicon carbide MIS device with a stacked gate structure, wherein the structure of the silicon carbide MIS device comprises, from bottom to top, a back electrode (6), an N+ substrate layer (1), an N-type epitaxial layer (2), a bottom gate dielectric (3), a dielectric interface passivation layer (4), an upper gate dielectric (5), and a gate electrode (7); the bottom gate dielectric (3), the dielectric interface passivation layer (4) and the upper gate dielectric (5) are stacked to form a gate dielectric layer; The bottom gate dielectric (3) is made of AlN material; The upper gate dielectric (5) is made of Al2O3 material; The material of the N+ substrate layer (1) is doped with a concentration of 5×10 18 cm -3 N-type 4H-SiC with phosphorus ions; The material of the N-type epitaxial layer (2) is doped with a concentration of 8×10 15 cm -3 Phosphorus ion N-type 4H-SiC, characterized in that The following steps are involved: Step S1, the thickness is 350 μm and the nitrogen ion doping concentration is 5×10 18 cm -3 The N+ silicon carbide substrate was cleaned by RCA at a temperature of 1600°C, a pressure of 150 mbar, reaction gases of silane and propane, a doping source gas of PH3, and a carrier gas of PH3; Step S2, growing an N-type epitaxial layer (2) on the cleaned N+ substrate layer (1), and performing a process, wherein the doping ions are phosphorus ions, and the doping concentration is 8×10 15 cm -3 N-type 4H-SiC, with a thickness of 1 μm to 100 μm; Step S3, cleaning the 4H-SiC epitaxial substrate substrate, sequentially performing organic solution ultrasonic cleaning, alkali cleaning, and acid cleaning on the sample, soaking in 5% HF solution after each cleaning step, then rinsing in deionized water, and drying with nitrogen; Step S4, using a magnetron sputtering process to prepare an AlN film as a bottom gate dielectric (3) on the N-type epitaxial layer (2); In step S4, the magnetron sputtering process parameters are: argon gas flow rate 30 sccm, ignition power 30 W, background vacuum degree 9×10 -5 Pa, sputtering gas pressure 0.65Pa, sputtering time 60~120s; Step S5, passivating the surface using nitrogen plasma to form a dielectric interface passivation layer (4); In step S5, the passivation treatment parameters are: power 10-50W, nitrogen flow rate 1.5L / min, and treatment time 60-200s; Step S6, using a magnetron sputtering process to prepare an upper gate dielectric (5) Al2O3 film on the interface passivation layer (4), and performing an annealing treatment on the sample formed into the gate dielectric; In step S6, the magnetron sputtering process parameters are: argon flow rate 30 sccm, oxygen flow rate 5 sccm-15 sccm, ignition power 30 W, background vacuum 5×10 -4 Pa, sputtering gas pressure 0.65Pa, substrate temperature 400℃, sputtering time 40min; annealing treatment is divided into in-situ low-temperature annealing and slow high-temperature annealing, the in-situ low-temperature annealing parameters are oxygen flow rate 30sccm, temperature 400℃, gas pressure 7Pa; the slow high-temperature annealing parameters are to control the oxygen and nitrogen flow ratio to 1:2, the slow high-temperature annealing includes a heating process, a heat preservation process and a natural cooling process, and the heating process needs to be heated to 1100℃ through two gradient stages; Step S7, evaporating Al metal on the back side to prepare a back electrode (6); Step S8, evaporating Al metal on the front side to prepare the gate electrode (7), thus completing the MIS device manufacturing.
2. The preparation method according to claim 1, characterized in that The bottom gate dielectric has a thickness of 2 nm.
3. The preparation method according to claim 1, characterized in that The thickness of the upper gate dielectric is 20 nm.
4. The preparation method according to claim 1, characterized in that The thickness of the N+ substrate layer (1) is 350 μm.
5. The preparation method according to claim 1, characterized in that The thickness of the N-type epitaxial layer (2) is 1 μm to 100 μm.
6. The preparation method according to claim 1, characterized in that The back electrode (6) has a thickness of 200 nm, and the gate electrode (7) is in the shape of a cylinder with a diameter of 500 μm and a thickness of 200 nm.
7. The preparation method according to claim 1, characterized in that In step S2, the process conditions are: temperature of 1600° C., pressure of 150 mbar, reaction gases of silane and propane, and doping source gas of PH3.