Phase change memory and manufacturing method thereof

Abstract

The present invention provides a phase-change memory device and a method for manufacturing the same. A selective process is employed to form a sidewall barrier layer on the sidewalls of a gate layer. This enhances adhesion between the gate layer and film layers such as linear barrier layers and gap-fill layers in the gaps between adjacent phase-change memory cells, preventing elements in the gate layer from diffusing outward and external elements from diffusing into the gate layer, thereby improving device performance. Furthermore, when a plasma surface treatment process is employed as the selective process, the selective process can, on the one hand, cause the loss and / or alteration of corresponding elements in the gate layer. For example, this can increase the band gap Eg of the edge material of a gate tube formed by the gate layer, thereby bringing the conductive filament of the gate tube closer to the center of the device, thereby improving the consistency of device performance. Furthermore, the plasma can chemically react with the gate layer material on the gap sidewalls to form the desired sidewall barrier layer, simplifying the process.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a phase change memory and a manufacturing method thereof. Background Art

[0002] Please refer to Figure 1 The phase change memory cell of the current three-dimensional phase change memory is usually formed at the intersection of the word line WL and the bit line BL. It uses the gate layer to form a dual-threshold gate switch OTS (Ovonic Threshold Switch) to control the current flowing through the phase change memory layer PCM (Phase Change Memory). The function of this dual-threshold gate switch is to remain in the on state during the erase and write operations on the phase change memory layer PCM, and remain in the off state after the erase and write operations are completed, so as to effectively avoid the read and write crosstalk problem between the phase change memory cells in the memory array.

[0003] However, in 3D phase-change memory, due to the different film-forming processes and material properties of different materials, the interface between the sidewalls of the gate layer and the linear barrier layer covering the sidewalls of the gap between adjacent phase-change memory cells is prone to looseness, forming interface defects called gaps, which fail to effectively protect the sidewalls of the gate layer. As a result, elements in the gate layer may diffuse through these interface defects into the adjacent electrodes above and below it and the phase-change memory layer PCM. This will cause changes in the material properties of the gate layer, its adjacent electrodes, and the phase-change memory layer PCM, affecting the performance of the phase-change memory cell. Summary of the Invention

[0004] The object of the present invention is to provide a phase change memory and a manufacturing method thereof, which can avoid element diffusion on the sidewall of a gating layer and improve the performance of a phase change memory unit.

[0005] To achieve the above object, the present invention provides a method for manufacturing a phase change memory, which comprises the following steps:

[0006] forming a phase change memory stack layer, wherein the phase change memory stack layer comprises a bottom electrode layer, a gating layer, an intermediate electrode layer, a phase change memory layer, and a top electrode layer stacked sequentially from bottom to top;

[0007] Etching the phase change memory stack layer from top to bottom to form a stack body, with gaps between adjacent stack bodies, and the gaps exposing the sidewall surface of the gating layer;

[0008] forming a sidewall barrier layer on the sidewall surface of the gate layer by a selective process;

[0009] forming a second linear barrier layer covering an inner surface of the gap including a surface of the sidewall barrier layer;

[0010] A gap-filling layer is formed to fill the gap.

[0011] Optionally, the step of forming a sidewall barrier layer on the sidewall surface of the gating layer by a selective process includes: performing a plasma surface treatment process to form a sidewall barrier layer on the sidewall surface of the gating layer; and / or performing a selective atomic layer deposition process to form a sidewall barrier layer on the sidewall surface of the gating layer.

[0012] Optionally, the step of forming a sidewall barrier layer on the sidewall surface of the gating layer by a selective process includes: first, performing the plasma surface treatment process to form a first sidewall barrier layer on the sidewall surface of the gating layer; then, performing a selective atomic layer deposition process to form a second sidewall barrier layer on the surface of the first sidewall barrier layer, the first sidewall barrier layer and the second sidewall barrier layer together constitute the sidewall barrier layer required on the sidewall surface of the gating layer.

[0013] Optionally, the plasma used in the plasma surface treatment process is a plasma including at least one element of nitrogen, oxygen, carbon, and hydrogen, and the plasma surface treatment process causes the corresponding elements in the gating layer to be lost and / or changed to change the material properties of the gating layer, and the plasma provided by the plasma surface treatment process chemically reacts with the material of the gating layer on the side wall of the gap to form the sidewall barrier layer; and / or, the material of the sidewall barrier layer formed on the side wall surface of the gating layer by the selective atomic layer deposition process includes at least one of silicon nitride, silicon carbide, and silicon oxide.

[0014] Optionally, the gating layer has doping elements, and the doping elements include at least one of Si, As, Ge, V, Mo, Al, Cu, Ag, Au, Cr, Ti, Ta, Ni, Fe, Sc, W, Sn, Bi, As, Ga, and In.

[0015] Optionally, the ratio of the thickness of the sidewall barrier layer to the line width of the gate layer surrounded by the sidewall barrier layer is 1 / 50 to 1 / 3.

[0016] Optionally, the step of etching the phase change memory stack layer from top to bottom to form the stack body includes:

[0017] Performing photolithography and etching on the top electrode layer and the phase change memory layer, and stopping at the top surface of the intermediate electrode layer to form a phase change structure, with gaps between adjacent phase change structures;

[0018] forming a first linear barrier layer on the sidewall of the phase change structure;

[0019] The first linear barrier layer, the middle electrode layer, the gate layer and the bottom electrode layer are etched downward along the gap and stopped on the top surface of the substrate below the bottom electrode layer to form each of the stacked bodies.

[0020] Optionally, the first linear barrier layer is a single-layer film or a composite structure of multiple films stacked in sequence, and the second linear barrier layer is a single-layer film or a composite structure of multiple films stacked in sequence.

[0021] Based on the same inventive concept, the present invention further provides a phase change memory, comprising:

[0022] A phase-change memory stack layer, the phase-change memory stack layer comprising a bottom electrode layer, a gate layer, an intermediate electrode layer, a phase-change memory layer, and a top electrode layer stacked sequentially from bottom to top, wherein the phase-change memory stack layer is divided into a plurality of stack bodies along a top-to-bottom direction by corresponding gaps, wherein the gaps expose sidewall surfaces of the gate layer;

[0023] a sidewall barrier layer selectively formed on the sidewall surface of the gate layer;

[0024] a second linear barrier layer covering an inner surface of the gap including a surface of the sidewall barrier layer;

[0025] A gap-filling layer fills the gap and is located on a surface of the second linear barrier layer.

[0026] Optionally, the sidewall barrier layer is a single-layer film, which is a film layer formed by a chemical reaction between a plasma of at least one element selected from nitrogen, oxygen, carbon, and hydrogen and the material of the gating layer on the sidewall of the gap, or is a film layer formed on the sidewall surface of the gating layer by a selective atomic layer deposition process; or, the sidewall barrier layer is a composite structure formed by stacking multiple films, which includes a first sidewall barrier layer covering the sidewall of the gating layer and a second sidewall barrier layer covering the first sidewall barrier layer, the first sidewall barrier layer is a film layer formed by a chemical reaction between a plasma of at least one element selected from nitrogen, oxygen, carbon, and hydrogen and the material of the gating layer on the sidewall of the gap, and the second sidewall barrier layer is a film layer formed on the sidewall surface of the first sidewall barrier layer by a selective atomic layer deposition process.

[0027] Optionally, the ratio of the thickness of the sidewall barrier layer to the line width of the gate layer surrounded by the sidewall barrier layer is 1 / 50 to 1 / 3.

[0028] Optionally, the stack further includes a first linear barrier layer, which covers the top electrode and the side walls of the phase change memory layer and exposes the side wall surface of the selection layer; wherein the first linear barrier layer is a composite structure of a single film or a multi-layer film stacked in sequence, and the second linear barrier layer is a composite structure of a single film or a multi-layer film stacked in sequence.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] 1. A sidewall barrier layer is formed on the sidewall of the gate layer using a selective process, which can enhance the adhesion between the gate layer and the linear barrier layer, gap filling layer and other film layers in the gap between the adjacent phase change memory cells, and prevent the elements in the gate layer from diffusing outward and the external elements from diffusing into the gate layer, thereby improving device performance.

[0031] 2. When the selective process includes a plasma surface treatment process, the plasma surface treatment process can, on the one hand, cause the corresponding elements in the gating layer to be lost and / or changed as the sidewall barrier layer is formed, so as to change the material properties in the edge area of ​​the gating layer, for example, increase the band gap Eg of the edge material of the gating tube formed by the gating layer, so that the conductive filament of the gating tube is closer to the center of the device, thereby helping to improve the consistency of the working performance of the device; on the other hand, the plasma provided by the plasma can chemically react with the material of the gating layer on the sidewall of the gap between adjacent phase change memory cells to form the required sidewall barrier layer, thereby simplifying the formation process of the sidewall barrier layer.

[0032] 3. When the selective process includes a selective atomic layer deposition process, the selective atomic layer deposition process can accurately control the film thickness and uniformity of the sidewall barrier layer, so that the surface of the gap sidewall between adjacent phase change memory cells is smooth, which is beneficial to enhance the coverage performance of the linear barrier layer subsequently formed on the gap surface and the filling performance of the gap filling layer filled in the gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 The figure is a schematic cross-sectional view of a device structure in an existing method for manufacturing a phase change memory.

[0034] Figure 2 This is a flow chart of a method for manufacturing a phase change memory provided in the first embodiment of the present invention.

[0035] Figures 3A to 3I Schematic diagram of the cross-sectional structure of a device in the method for manufacturing a phase change memory according to the first embodiment of the present invention.

[0036] Figures 4A to 4C Schematic diagram of the cross-sectional structure of a device in a method for manufacturing a phase change memory according to a second embodiment of the present invention.

[0037] Figures 5A to 5C Schematic diagram of the cross-sectional structure of a device in a method for manufacturing a phase change memory according to a third embodiment of the present invention.

[0038] Wherein, the accompanying drawings are marked as follows:

[0039] 100-substrate; 101-bit line; 102-stack; 102a-initial stack; 1021-bottom electrode layer; 1022-selection layer; 1023-intermediate electrode layer; 1024-phase change memory layer; 1025-top electrode layer; 103-gap; 104-first linear barrier layer; 1041-first sub-linear barrier layer; 1042-second sub-linear barrier layer; 105-sidewall barrier layer; 1051-first sidewall barrier layer; 1052-second sidewall barrier layer; 106-second linear barrier layer; 107-gap filling layer; 108-word line. DETAILED DESCRIPTION

[0040] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. Example 1

[0041] Please refer to Figure 2 This embodiment provides a method for manufacturing a phase change memory, which includes the following steps:

[0042] S1, forming a phase change memory stack layer, wherein the phase change memory stack layer includes a bottom electrode layer, a gate layer, an intermediate electrode layer, a phase change memory layer and a top electrode layer stacked in sequence from bottom to top;

[0043] S2, etching the phase change memory stack layer from top to bottom to form a stack body, with gaps between adjacent stack bodies, and the gaps exposing the sidewall surface of the gating layer;

[0044] S3, forming a sidewall barrier layer on the sidewall surface of the gate layer by a selective process;

[0045] S4, forming a second linear barrier layer, wherein the second linear barrier layer covers the inner surface of the gap including the surface of the sidewall barrier layer;

[0046] S5 , forming a gap-filling layer filled in the gap.

[0047] First, please refer to Figure 3AAs shown, in step S1, a substrate 100 is first provided, and a bit line layer (unmarked) and a phase change memory stack layer (unmarked) are sequentially deposited on the substrate 100. The phase change memory stack layer includes a bottom electrode layer 1021, a gating layer 1022, an intermediate electrode layer 1023, a phase change memory layer 1024, a top electrode layer 1025 and a hard mask layer 1026 stacked sequentially from bottom to top.

[0048] The substrate 100 may be a wafer material that has been processed through a series of integrated circuit manufacturing processes. The wafer material may be selected from at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compounds. The wafer material may also be a multi-layer structure or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeO). The substrate 100 may already have active or passive electronic components such as MOS transistors, diodes, and resistors formed therein, and may also have device isolation structures, and may further have multi-layer metal interconnect structures. When the phase-change memory to be formed has two, four, or more stacked layers of phase-change memory cells, the substrate 100 may also have already completed the fabrication of the phase-change memory cells below the phase-change memory stack layer and their electrically connected word lines and / or bit lines.

[0049] The bit line layer 101 can be formed by suitable processes such as chemical vapor deposition, sputtering deposition, electroplating, chemical plating, metal silicide manufacturing, doped polysilicon deposition, etc., and its material may include at least one of Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, Ni metal, P-type doped polysilicon, N-type doped polysilicon, metal silicide, etc.

[0050] The phase change memory stack layer is used to subsequently form a number of phase change memory units spaced apart from each other, each phase change memory unit having a bottom electrode (i.e., layer 1021) and a top electrode (i.e., layer 1025). The materials of the bottom electrode layer 1021, the intermediate electrode layer 1023, and the top electrode layer 1025 may be the same or different, and may be selected from one or more of C, Ta, TiN, TaC, TaN, Co, W, Pt, Au, Ti, Al, Ag, Cu, and Ni. The gate layer 1022 may include an undoped chalcogenide material or a doped chalcogenide material, wherein the chalcogenide material may be, for example, a selenium-based OTS material (including Se and compounds thereof with one or more of Ge, Si, and As), a tellurium-based OTS material (including Te and compounds thereof with one or more of Ge, Si, and Sb), etc. The doping element in the doped chalcogenide material may include at least one of Si, As, Ge, V, Mo, Al, Cu, Ag, Au, Cr, Ti, Ta, Ni, Fe, Sc, W, Sn, Bi, As, Ga, and In. These doping elements may change the properties of the chalcogenide material.

[0051] The material of the phase change memory layer 1024 can be any suitable phase change material, for example, it can include at least one of Ge-Sb-Te based phase change material (also known as GST), Ge-Te based phase change material, Ge-Sb based phase change material, Si-Sb-Te based phase change material, Sb-Te based phase change material, Sb based phase change material, etc., and can be a combination of two phase change materials, a combination of three phase change materials, or a combination of more phase change materials. Among them, the Ge-Sb-Te based phase change material is composed of three elements: Ge, Sb, and Te, and can include but is not limited to Ge3Sb4Te8, Ge2Sb2Te5, Ge2Sb2Te4, GeSb2Te4, etc., and the Ge-Te based phase change material is composed of two elements: Ge and Te. Among them, the Ge-Sb based phase change material is composed of two elements: Ge and Sb, and the Si-Sb-Te based phase change material is composed of three elements: Si, Sb, and Te, and can include but is not limited to: Si 11 Sb 57 Te 32 、Si 18 Sb 52 Te 30 、Si 24 Sb 48 Te 28Etc. Therefore, based on the fact that the phase-change material contained in the phase-change memory layer 1024 can be a single layer or a combination of multiple phase-change materials, the present invention does not impose any specific limitation on the number of layers of the phase-change memory layer 1024. The phase-change material can be a single layer or multiple layers, such as 2 layers, 3 layers, 4 layers, 5 layers, 6 layers, or even more layers. The crystallization temperature and threshold voltage of two adjacent layers of phase-change material can be different. When the phase-change materials with different crystallization temperatures and threshold voltages correspond to different pulse voltages or pulse currents for phase change, under a pulse voltage or pulse current of a specific magnitude, the phase-change materials of all layers of the phase-change memory layer 1024 may be in a low-resistance state, the phase-change materials of all layers of the phase-change memory layer 1024 may be in a high-resistance state, or the phase-change materials of some layers may be in a low-resistance state, while the phase-change materials of other layers may be in a high-resistance state.

[0052] The hard mask layer 1026 may be made of one or more combinations of oxide, nitride, or metal.

[0053] It should be understood that in other embodiments of the present invention, the phase change memory stack layer may further include at least one of a blocking interface layer (also referred to as a diffusion barrier layer) located between the gating layer 1022 and the bottom electrode layer 1021, a blocking interface layer (also referred to as a diffusion barrier layer) located between the gating layer 1022 and the intermediate electrode layer 1023, a blocking interface layer (also referred to as a diffusion barrier layer) located between the phase change memory layer 1024 and the intermediate electrode layer 1023, and a blocking interface layer (also referred to as a diffusion barrier layer) located between the phase change memory layer 1024 and the top electrode layer 1025.

[0054] Please refer to Figures 3B to 3D In step S2 , the phase change memory stack layer is etched from top to bottom to form a stack body, with gaps 103 between adjacent stack bodies, and the gaps 103 expose the sidewall surface of the gate layer 1022 .

[0055] In this embodiment, a single patterning technology or a double patterning technology can be used to etch the bit line layer, the phase change memory layer and the subsequently formed word line layer to form bit lines, phase change memory cells and word lines. Alternatively, a double patterning technology can be used to etch the bit line layer, the phase change memory layer and the subsequently formed word line layer to form bit lines, phase change memory cells and word lines.

[0056] As an example, in step S1, before depositing the bottom electrode layer 1021, the bitline layer is etched from top to bottom along the Y direction to form the required number of bitlines 101 extending along the Y direction. In step S2, the phase-change memory stack is etched to the top surface of the bitlines 101 to form a number of discrete phase-change memory cells. These phase-change memory cells are stacks 102 that expose the sidewalls of the gate layer 1022. These phase-change memory cells are separated by gaps extending along the X direction and along the Y direction. This example uses a single patterning technique.

[0057] As another example, in step S1, the bit line layer is not patterned first. Instead, in step S2, the hard mask layer 1026, the top electrode layer 1025, and the phase change memory layer 1024 are first photolithographically etched from top to bottom along the Y direction. The etching stops on the top surface of the intermediate electrode layer 1023 to form a plurality of initial stacks 102a extending along the Y direction. At this time, the gaps 103 between adjacent initial stacks 102a also extend along the Y direction. Figure 3B Then, a first linear barrier layer 104 may be formed on the sidewall surface and top surface of each initial stack 102a by a suitable process such as chemical vapor deposition, as shown in FIG. Figure 3C As shown. The first linear barrier layer 104 can be subsequently formed as the sidewalls of the initial stack 102a. This protects the sidewalls of the initial stack 102a from damage during subsequent processes. It also improves adhesion between the subsequent gapfill layer and the sidewalls of the initial stack 102a. It also prevents element diffusion between the initial stack 102a and the subsequently formed gapfill layer, preventing changes in the material composition of the various film layers and ensuring device performance. In this embodiment, the first linear barrier layer 104 includes a first sub-linear barrier layer 1041 and a second sub-linear barrier layer 1042, which are sequentially stacked on the sidewall surfaces of each initial stack 102a. The material of the first sub-linear barrier layer 1041 can be a nitride (e.g., silicon nitride), and the material of the second sub-linear barrier layer 1042 can be an oxide (e.g., silicon oxide). Next, the second sub-linear barrier layer 1042, the first sub-linear barrier layer 1041, the intermediate electrode layer 1023, the selection layer 1022 and the bottom electrode layer 1021 are sequentially etched along the gap 103 from top to bottom until the top surface of the bit line layer 101 is exposed, thereby forming a plurality of strip-shaped stacks 102 spaced apart from each other and extending along the Y direction, and the gaps 103 between adjacent stacks 102 extend to the top surface of the bit line 101.

[0058] Please refer to Figure 3EIn step S3, a plasma surface treatment process is used as a selective process to treat the sidewall surfaces of the gate layer 1022 exposed in the gap 103. The plasma used in the plasma surface treatment process is a plasma containing at least one element of N (nitrogen), O (oxygen), C (carbon), and H (hydrogen). The process parameters of the plasma surface treatment process in this step can be set to reduce the loss and / or change (including migration, redistribution, recrystallization, etc.) of the elements (including doped elements) constituting the gate layer 1022, thereby improving the material properties of the gate layer 1022, such as improving the electrical properties (including increasing switching speed, reducing leakage current, etc.) and stability (reducing voids, etc.) of the gate layer 1022. At the same time, the plasma provided by the plasma surface treatment process can chemically react with the material of the gate layer on the sidewall of the gap 103 to form the sidewall barrier layer 105.

[0059] Optionally, the plasma surface treatment process in this step may set the process temperature to 300° C. or higher, and may further set the bias power so that the plasma is applied to the sidewalls of the gating layer 1022 .

[0060] Further optionally, during the implementation of the plasma surface treatment process, an inert gas is used, which may include helium (He), argon (Ar), or a mixture of He and Ar. The inert gas can transport the plasma that needs to react with the gating layer 1022 to the side wall surface of the gating layer 1022.

[0061] As an example, when the gating layer 1022 formed in step S1 is an undoped sulfur compound, the plasma surface treatment process in step S3 can cause the sulfur compound at the side wall of the gating layer 1022 to be nitrided, oxidized, carbonized or hydrogenated, and can change the material properties of the sulfur compound inside the gating layer 1022 (for example, change its grain structure, size, etc.). At this time, the formed sidewall barrier layer 105 is a sulfur compound that is nitrided, oxidized, carbonized or hydrogenated.

[0062] As another example, when the gating layer 1022 formed in step S1 is a doped sulfide compound and its doped elements include at least one of Si, As, Ge, V, Mo, Al, Cu, Ag, Au, Cr, Ti, Ta, Ni, Fe, Sc, W, Sn, Bi, As, Ga, and In, the plasma surface treatment process in step S3 can cause a portion of the doping elements in the gating layer 1022 to be migrated to the sidewalls of the gap 103 or to the interior of the gating layer 1022 to precipitate the doping elements or sulfide compounds. The precipitated doping elements or sulfide compounds react with the plasma to form a sidewall barrier layer 105. The sidewall barrier layer 105 thus formed may include at least one of compounds in which these doping elements are combined with N (nitrogen), O (oxygen), C (carbon), and H (hydrogen) (such as silicon oxide, silicon nitride, silicon carbide, metal oxide, metal nitride, etc.), nitrided / oxidized / carbonized / hydrogenated sulfide compounds, and nitrided / oxidized / carbonized / hydrogenated doped sulfide compounds.

[0063] It should be noted that, due to the different materials of the selection layer 1022 and the intermediate electrode 1023, in step S2, during the process of etching the intermediate electrode layer 1023 to the bottom electrode layer 1021 along the gap to expose the top surface of the bit line 101, the side walls of the selection layer 1022 are consumed more relative to the intermediate electrode 1023 and the bottom electrode 1021, and the side walls of the selection layer 1022 are recessed inward relative to the side walls of the intermediate electrode 1023 and the bottom electrode 1021 to form a groove 103a. In this embodiment, although the plasma needs to react with the selection layer 1022 on the side walls of the gap 103 in step S3 and consume a certain amount of the selection layer 1022, the side wall barrier layer 105 formed thereby can not only make up for the consumed thickness of the selection layer 1022, but also fill or fill the groove 103a.

[0064] Optionally, the ratio of the thickness W3 of the sidewall barrier layer 105 formed in this embodiment to the line width W2 of the gate layer 1022 surrounded by it is 1 / 50 to 1 / 3. And W3+W2 is equal to the line width W1 of the gate layer 1022 in the stack formed after etching in step S2 (e.g. Figure 3D shown).

[0065] In step S4, a second linear barrier layer 106 is formed on the sidewalls of each stack 102, as shown in FIG. Figure 3F As shown, the second linear barrier layer 106 can be a single-layer dielectric or a multi-layer dielectric, and its material includes, for example, silicon nitride. The second linear barrier layer 106 covers the inner surface of the gap 103 including the surface of the sidewall barrier layer 105, and also covers the surface of the hard mask layer 1026.

[0066] In step S5, first, a gap-filling layer 107 is deposited on the surface of the second linear barrier layer 106 by a suitable material deposition process such as chemical vapor deposition or high aspect ratio vapor deposition to fill the gap 103 between adjacent phase change memory cells. The deposited gap-filling layer 107 can fill the gap 103 completely or seal the gap 103 into a structure with an air gap (the air gap is not shown in the figure, and the air gap can reduce parasitic capacitance), as shown in FIG. Figure 3G As shown. The material of the gap filling layer 107 includes, for example, one or more combinations of silicon oxide, tetraethyl orthosilicate, low-k dielectric (including organic or inorganic porous materials), etc. Next, the top of the gap filling layer 107 is chemically mechanically polished until the top surface of each top electrode layer 1025 is exposed, as shown in FIG. Figure 3H As shown, the second linear barrier layer 106 and the hard mask layer 1026 on the top surface of the top electrode layer 1025 are removed at this time.

[0067] Among them, on the one hand, the sidewall barrier layer 105 blocks the elements in the gate layer 1022 from diffusing outward, and on the other hand, the sidewall barrier layer 105 enhances the coverage performance of the second linear barrier layer 106 and improves the adhesion between the gate layer 1022 and the second linear barrier layer 106 and the gap filling layer, thereby blocking the elements in the gate layer 1022 from diffusing outward and the elements in the external film layer of the gate layer 1022 from diffusing into the gate layer 1022, thereby ultimately improving the device performance.

[0068] Please refer to Figure 3I After step S5, word lines 108 can be further formed to electrically contact the top electrode layer 1025, with the word lines 108 extending in the X direction perpendicular to the Y direction. If only the stack 102 extending in the Y direction is formed in step S2, during the step of etching the word line layer on the top electrode layer 1025 to form the word lines 108, the stack 102 can be further etched from top to bottom to further divide the stack 102 by gaps extending in the X direction (not shown), forming a plurality of mutually spaced phase-change memory cells. Subsequently, sidewall barrier layers 105 can be further formed on the sidewalls of the gate layer 1022 exposed by the gaps extending in the X direction, using the method of step S3. This ensures that the gate layer 1022 of each phase-change memory cell is covered and protected by the sidewall barrier layers 105. Steps S4 and S5 can then be further performed to fill the gaps between the phase-change memory cells with insulating material, providing a flat process surface for subsequent processes.

[0069] This embodiment also provides a phase change memory, which is preferably formed using the phase change memory manufacturing method of this embodiment. Of course, those skilled in the art may also use any other suitable manufacturing method. The phase change memory includes a phase change memory stack layer, a sidewall barrier layer 105, and a gap fill layer 107.

[0070] The phase change memory stack layer may be formed on a substrate, and the substrate may include a base 100 and a bit line 101 formed on the base 100 .

[0071] The phase change memory stack layer is formed on the bit line 101 and includes a bottom electrode layer 1021, a selection layer 1022, an intermediate electrode layer 1023, a phase change memory layer 1024 and a top electrode layer 1025 stacked in sequence from bottom to top, and is divided into several stack bodies 102 from top to bottom by corresponding gaps 103, and each gap 103 exposes the side wall surface of the selection layer 1022; the gap 103 extends along the direction of the word line 108 and the direction of the bit line 101.

[0072] The sidewall barrier layer 105 is a single-layer film, which is formed by a chemical reaction between a plasma of at least one element selected from the group consisting of N (nitrogen), O (oxygen), C (carbon), and H (hydrogen) and the material of the gating layer 1022 on the sidewall of the gap 103. For details on the material, please refer to the relevant description in step S3 above and will not be repeated here.

[0073] Optionally, a ratio W3 / W2 of the thickness of the sidewall barrier layer 105 to the line width of the gate layer 1022 surrounded by the sidewall barrier layer 105 is 1 / 50 to 1 / 3.

[0074] The gap-filling layer 108 fills the gap 103 . Optionally, a top surface of the gap-filling layer 108 is flush with a top surface of the top electrode layer 1025 .

[0075] Optionally, the stack 102 further includes a first linear barrier layer 104, which covers the sidewalls of the top electrode layer 1025 and the phase change memory layer 1024 and exposes the sidewall surfaces of the stacked layers from the intermediate electrode layer 1023 to the bottom electrode layer 1021. The first linear barrier layer 104 can be a single layer or a composite structure of multiple layers stacked in sequence (for example, a stacked structure of a first sub-linear barrier layer 1041 and a second sub-linear barrier layer 1042).

[0076] The phase-change memory of this embodiment further includes a second linear barrier layer 106, which covers the surface of the stack 102 and the sidewall barrier layer 105. A gap-filling layer 107 is formed on the surface of the second linear barrier layer 106 and fills the gap 103. The top surface of the gap-filling layer 107 can be flush with the top surface of the top electrode layer 1025 of the stack 102. The second linear barrier layer 107 is a single-layer film or a composite structure in which multiple films are stacked in sequence.

[0077] The phase-change memory device and its manufacturing method of this embodiment utilizes a sidewall barrier layer formed on the sidewalls of a gate layer to prevent elements in the gate layer from diffusing outward and external elements from diffusing into the gate layer, thereby enhancing adhesion between the gate layer and film layers such as the second linear barrier layer in the gap between adjacent phase-change memory cells, thereby improving device performance. Furthermore, the plasma surface treatment process used to form the sidewall barrier layer can, as the sidewall barrier layer forms, cause the corresponding elements in the gate layer to be lost and / or altered, thereby changing the material properties of the gate layer and the material properties in the edge region. For example, this can increase the band gap Eg of the edge material of the gate tube formed by the gate layer, bringing the conductive filament of the gate tube closer to the center of the device, thereby improving the consistency of device performance. Furthermore, the plasma provided by the plasma can chemically react with the gate layer material on the sidewalls of the gap between adjacent phase-change memory cells to form the desired sidewall barrier layer, simplifying the sidewall barrier layer formation process. Example 2

[0078] This embodiment provides a method for manufacturing a phase change memory, which also includes Figure 2 For steps S1 to S5 shown in FIG, the cross-sectional structure diagram of the device in the manufacturing method can be referred to Figures 4A to 4B The main difference between this embodiment and the first embodiment is that in step S3, the selective process adopted is a selective atomic layer deposition process, that is, in step S3, a sidewall barrier layer 105 is deposited on the sidewall of the gating layer 1022 by the selective atomic deposition process. The material of the sidewall barrier layer 105 may include at least one of silicon nitride, silicon carbide, and silicon oxide.

[0079] Optionally, the selective atomic layer deposition process in step S3 of this embodiment may be set to a process temperature lower than 400° C. to avoid loss or change of elements in the gating layer 1022 caused by the process.

[0080] Due to the characteristics of the selective atomic deposition process, in step S3 of this embodiment, the sidewall barrier layer 105 can be controlled to be formed only on the exposed sidewalls of the gate layer 1022. On the one hand, this does not affect the performance and line width W1 of the gate layer 1022 remaining after step S2, so that the characteristic dimension W1 of the gate layer 1022 remains unchanged before and after step S3, ensuring that the deposition process of the sidewall barrier layer 105 does not cause poor performance of the gate layer 1022. On the other hand, the recess 103a formed on the sidewall of the gate layer 1022 is filled with the sidewall barrier layer 105, and the film thickness uniformity of the sidewall barrier layer 105 is good, thereby making the sidewall of the gap 103 smooth, which is conducive to improving the film thickness uniformity of the second linear barrier layer 106, and further improving the filling performance of the gap-filling layer 107. At the same time, the sidewall barrier layer 105 can prevent the elements in the selection layer 1022 from diffusing outward, and enhance the adhesion between the selection layer 1022 and the second linear barrier layer 106 and other film layers in the gap between the adjacent phase change memory cells, thereby preventing the elements in the selection layer 1022 from diffusing outward and preventing external elements from diffusing into the selection layer 1022, thereby improving device performance.

[0081] For steps S1 , S2 and S4 - S5 of the method for manufacturing the phase change memory of this embodiment, reference may be made to the description of the corresponding steps in the first embodiment, and will not be described in detail here.

[0082] This embodiment also provides a phase change memory formed by the phase change memory manufacturing method of this embodiment. The structural difference between the phase change memory and the phase change memory of Example 1 is only that the material of the sidewall barrier layer 105 is different. It is formed by a selective atomic layer deposition process, for example, one or more combinations of silicon nitride, silicon carbide, and silicon oxide. Example 3

[0083] This embodiment provides a method for manufacturing a phase change memory, which also includes Figure 2 For steps S1 to S5 shown in FIG, the cross-sectional structure diagram of the device in the manufacturing method can be referred to Figures 5A to 5B As shown. The main difference between this embodiment and the first embodiment is that in step S3, the selective process used includes a plasma surface treatment process performed first and a selective atomic layer deposition process performed later. That is, in step S3, a first sidewall barrier layer 1051 is first formed on the sidewall of the gate layer 1022 by the plasma surface treatment process, and then a second sidewall barrier layer 1052 is deposited on the surface of the first sidewall barrier layer 1051 by the selective atomic deposition process. The first sidewall barrier layer 1051 and the second sidewall barrier layer 1052 constitute the sidewall barrier layer 105 required on the sidewall of the gate layer 1022 in this embodiment.

[0084] Among them, the formation process and materials of the first side wall barrier layer 1051 can refer to the relevant description of the formation process and materials of its side wall barrier layer 105 in Example 1, and the formation process and materials of the second side wall barrier layer 1052 can refer to the relevant description of the formation process and materials of its side wall barrier layer 105 in Example 2, which will not be repeated here.

[0085] In this embodiment, a first sidewall barrier layer 1051 is first formed on the sidewalls of the gate layer 1022 through a plasma surface treatment process. This not only changes the material properties of the gate layer 1022, but also facilitates the formation of a thinner second sidewall barrier layer 1052, thereby reducing overall processing time. Furthermore, the first sidewall barrier layer 1051 and the second sidewall barrier layer 1052 form the sidewall barrier layer 105. Compared to the first and second embodiments, this further improves the adhesion between the gate layer 1022 and film layers such as the second linear barrier layer 106 in the gap 103, while also further enhancing the ability to block elements in the gate layer 1022 from diffusing outward and external elements from diffusing into the gate layer 1022, thereby further improving device performance.

[0086] For steps S1 , S2 and S4 - S5 of the method for manufacturing the phase change memory of this embodiment, reference may be made to the description of the corresponding steps in the first embodiment, and will not be described in detail here.

[0087] This embodiment also provides a phase-change memory formed using the phase-change memory manufacturing method of this embodiment. The structure of this phase-change memory differs from that of the phase-change memories of Embodiments 1 and 2 only in that the sidewall barrier layer 105 comprises a first sidewall barrier layer 1051 and a second sidewall barrier layer 1052, which sequentially cover the sidewalls of the gate layer 1022. The first sidewall barrier layer 1051 is formed by a plasma surface treatment process, and the second sidewall barrier layer 1052 is formed by a selective atomic layer deposition process. In other words, the first sidewall barrier layer 1051 is a film layer formed by a chemical reaction between a plasma containing at least one element of nitrogen, oxygen, carbon, and hydrogen and the material of the gate layer 1022 on the sidewalls of the gap 103.

[0088] Optionally, the ratio of the thickness of the sidewall barrier layer 105 to the line width of the gate layer 1022 surrounded by the sidewall barrier layer 105 is 1 / 50 to 1 / 3.

[0089] It should be understood that the above embodiments only illustrate the manufacture of one layer of phase change memory cells and the word lines and bit lines electrically connected thereto. When the architecture of the phase change memory to be manufactured by the present invention includes two layers of stacked phase change memory cells, the manufacturing method in the above embodiments can be used to firstly Figure 3I 、 Figure 4C or Figure 5CAfter manufacturing a lower layer of phase-change memory cells, an upper layer of phase-change memory cells and the required top bit lines thereon are manufactured on the lower layer of phase-change memory cells. The top bit lines can be parallel to the bit lines 101 and perpendicularly intersect the word lines 108. Alternatively, according to the manufacturing method of the above embodiment, a layer of lower layer of phase-change memory cells can be first manufactured in the substrate 100, and the formed bit lines 101 are electrically connected to the lower layer of phase-change memory cells.

[0090] Therefore, when the architecture of the phase change memory to be manufactured in the present invention includes three, four or more layers of phase change memory cells stacked along the Z direction, the sequential structure of bit line-phase change memory cell-word line... in the above embodiment can be repeated along the Z direction until the manufacture of all layers of phase change memory cells and their electrically connected word lines and bit lines is completed.

[0091] In addition, in the phase change memory and the manufacturing method thereof in other embodiments of the present invention, the first linear barrier layer 104 and / or the second linear barrier layer 106 may be omitted if the device performance design allows.

[0092] In summary, the phase-change memory device and its manufacturing method provided by the present invention utilizes a selective process to form a sidewall barrier layer on the sidewalls of the gate layer. This process, while preventing outward diffusion of elements in the gate layer, also enhances adhesion between the gate layer and film layers, such as the linear barrier layer, in the gaps between adjacent phase-change memory cells through the sidewall barrier layer, thereby preventing interdiffusion of elements from the various film layers in the phase-change memory cells along the gaps, thereby improving device performance. When the selective process includes a plasma surface treatment process, the plasma surface treatment process can, on the one hand, cause the loss or modification of elements in the gate layer, thereby changing the material properties of the gate layer, and, on the other hand, chemically react with the material of the gate layer on the sidewalls of the gaps between adjacent phase-change memory cells to form the desired sidewall barrier layer. When the selective process includes a selective atomic layer deposition process, the selective atomic layer deposition process can precisely control the film thickness and uniformity of the sidewall barrier layer, resulting in a smooth surface on the sidewalls of the gaps between adjacent phase-change memory cells. This, in turn, enhances the coverage of the linear barrier layer subsequently formed on the gap surface and the filling performance of the gap-filling layer filling the gap.

[0093] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0094] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", "fourth", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0095] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in their broadest sense. In addition, the word "and / or" should be understood to have the definition of a logical "and" or "or", that is, one or both can be selected; the word "or" should be understood to have the definition of a logical "or", not a logical "exclusive or" unless the context clearly indicates otherwise. In addition, the implementation of the method and / or apparatus in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

[0096] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a phase change memory, characterized in that: include: forming a phase change memory stack layer, wherein the phase change memory stack layer comprises a bottom electrode layer, a gating layer, an intermediate electrode layer, a phase change memory layer, and a top electrode layer stacked sequentially from bottom to top; Etching the phase change memory stack layer from top to bottom to form a stack body, with gaps between adjacent stack bodies, and the gaps exposing the sidewall surface of the gating layer; performing a plasma surface treatment process, wherein the plasma surface treatment process not only changes the material properties inside the gate layer but also provides plasma to chemically react with the material of the gate layer on the sidewalls of the gap to selectively form a first sidewall barrier layer on the sidewall surface of the gate layer; forming a second linear barrier layer covering an inner surface of the gap including a surface of the first sidewall barrier layer; A gap-filling layer is formed to fill the gap.

2. The manufacturing method according to claim 1, characterized in that After forming the first sidewall barrier layer and before forming the second linear barrier layer, a selective atomic layer deposition process is further performed to form a second sidewall barrier layer on the surface of the first sidewall barrier layer. The first sidewall barrier layer and the second sidewall barrier layer together constitute the sidewall barrier layer required on the sidewall surface of the gating layer.

3. The manufacturing method according to claim 2, characterized in that The plasma used in the plasma surface treatment process is a plasma including at least one element of nitrogen, oxygen, carbon, and hydrogen. The plasma surface treatment process causes the corresponding elements in the gating layer to be lost and / or changed to change the material properties of the gating layer; and / or the material of the sidewall barrier layer formed on the sidewall surface of the gating layer by the selective atomic layer deposition process includes at least one of silicon nitride, silicon carbide, and silicon oxide.

4. The manufacturing method according to claim 1, characterized in that The gating layer has doping elements, and the doping elements include at least one of Si, As, Ge, V, Mo, Al, Cu, Ag, Au, Cr, Ti, Ta, Ni, Fe, Sc, W, Sn, Bi, As, Ga, and In.

5. The manufacturing method according to claim 2, characterized in that The ratio of the thickness of the sidewall barrier layer to the line width of the gate layer surrounded by it is 1 / 50 to 1 / 3.

6. The manufacturing method according to claim 1, characterized in that The step of etching the phase change memory stack layer from top to bottom to form the stack body includes: Performing photolithography and etching on the top electrode layer and the phase change memory layer, and stopping at the top surface of the intermediate electrode layer to form a phase change structure, with gaps between adjacent phase change structures; forming a first linear barrier layer on the sidewall of the phase change structure; The first linear barrier layer, the middle electrode layer, the gate layer and the bottom electrode layer are etched downward along the gap and stopped on the top surface of the substrate below the bottom electrode layer to form each of the stacked bodies.

7. The manufacturing method according to claim 6, characterized in that The first linear barrier layer is a single-layer film or a composite structure of multiple films stacked in sequence, and the second linear barrier layer is a single-layer film or a composite structure of multiple films stacked in sequence.

8. A phase change memory, characterized in that: include: A phase-change memory stack layer, the phase-change memory stack layer comprising a bottom electrode layer, a gate layer, an intermediate electrode layer, a phase-change memory layer, and a top electrode layer stacked sequentially from bottom to top, wherein the phase-change memory stack layer is divided into a plurality of stack bodies along a top-to-bottom direction by corresponding gaps, wherein the gaps expose sidewall surfaces of the gate layer; a first sidewall barrier layer selectively formed on the sidewall surface of the gate layer by a plasma surface treatment process, wherein the first sidewall barrier layer is formed by a chemical reaction between plasma provided by the plasma surface treatment process and a material of the gate layer on the sidewall of the gap, and the plasma surface treatment process changes the material properties inside the gate layer while forming the first sidewall barrier layer; a second linear barrier layer covering an inner surface of the gap including a surface of the sidewall barrier layer; A gap-filling layer fills the gap and is located on a surface of the second linear barrier layer.

9. The phase change memory according to claim 8, wherein: The first sidewall barrier layer is a single-layer film, which is a film layer formed by a chemical reaction between a plasma of at least one element selected from nitrogen, oxygen, carbon, and hydrogen and the material of the gating layer on the sidewall of the gap; or, the sidewall barrier layer covering the sidewall of the gating layer is a composite structure formed by a multi-layer stack of films, which includes the first sidewall barrier layer and a second sidewall barrier layer covering the first sidewall barrier layer, the first sidewall barrier layer is a film layer formed by a chemical reaction between a plasma of at least one element selected from nitrogen, oxygen, carbon, and hydrogen and the material of the gating layer on the sidewall of the gap, and the second sidewall barrier layer is a film layer formed on the sidewall surface of the first sidewall barrier layer by a selective atomic layer deposition process.

10. The phase change memory according to claim 9, wherein: The ratio of the film thickness of the sidewall barrier layer to the line width of the gate layer surrounded by the sidewall barrier layer is 1 / 50 to 1 / 3.

11. The phase change memory according to claim 8, wherein: The stack also includes a first linear barrier layer, which covers the top electrode and the side walls of the phase change memory layer and exposes the side wall surface of the selection layer; wherein the first linear barrier layer is a composite structure of a single film or a multi-layer film stacked in sequence, and the second linear barrier layer is a composite structure of a single film or a multi-layer film stacked in sequence.

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