Phase-redundant power supply with ORING FET current sensing

Abstract

A power stage in a multi-phase switching power supply includes a current sensing transistor connected in series with an output inductor to sense a phase current of the power stage. In some embodiments, the current sensing transistor mirrors an output voltage disconnect transistor (ORing field effect transistor) for switchably connecting the power stage to an output voltage node. The current sensing transistor measures a portion of the inductor current flowing through the output inductor, wherein the inductor current is indicative of a phase current of the power stage. Accurate current sensing is achieved in the power stage without requiring temperature compensation of the current sensing value.

Description

Technical Field

[0001] The invention relates to a phase redundant power supply system, and in particular to a current sensor in the phase redundant power supply system. Background Art

[0002] Electronic systems, such as laptop computers, often contain power management integrated circuits that regulate the power usage of the electronic system. In addition, electronic systems that incorporate integrated circuits often use a voltage modulator to convert the main bus voltage of the power supply system power supply to the voltage required to drive one or more integrated circuits. For example, a 12 volt power supply voltage provided to an electronic system may need to be reduced to 1.8 volts to drive the integrated circuits in the electronic system. In another example, an advanced servo system includes a processor and local memory, which are coupled to components and execute embedded software to perform certain tasks. In practice, the processor power is provided by a voltage regulator, which converts the input voltage from the power supply (e.g., 12V) to a voltage value specified for the processor (e.g., 1.0V).

[0003] A switch mode power supply or switching modulator, also known as a DC to DC converter, is a type of voltage modulator that is commonly used to convert an input supply voltage to a desired output voltage at a voltage level selected by an integrated circuit. In one example, a 12 volt or 5 volt supply voltage can be stepped down to 1 volt to power an embedded processor. Switching modulators provide power functions through low-loss components such as capacitors, inductors, and transformers, turning on or off the power switch to transfer energy from the input to the output in a discrete package. Feedback control circuitry is used to modulate the energy transfer to maintain a regulated output voltage within the load limits required by the circuit.

[0004] Some switching modulators use pulse width modulation (PWM) to control the duty cycle of the power switch. That is, by adjusting the pulse width, the on-time of the power switch can be controlled at a given fixed frequency or variable frequency. A switching modulator using PWM control includes a PWM controller or modulator to drive a power block including a power switch, a drive circuit for the power switch, and an LC filter circuit. In some cases, the switching modulator is a single-phase converter, and the PWM controller generates a single-phase PWM clock signal to drive a single-phase power module. In other cases, the switching modulator is a multi-phase converter, and the multi-phase PWM controller generates clock signals with different phase shifts to drive multi-phase power modules, each clock signal driving a corresponding power module unit. A multi-phase PWM controller is necessary when the voltage modulator must transmit the modulated output voltage with high accuracy under a wide range of load conditions.

[0005] In electronic systems that contain voltage regulators, it is often necessary to measure the output current or load current of the voltage regulator to implement power management functions. In multi-phase converters, it is sometimes necessary to measure the load current at each power block unit associated with each clock phase, for example to determine the load balance between the power block units.

[0006] Advanced servo systems often require a high level of availability and protection against system failures, such as power outages. To ensure system reliability, advanced servo systems sometimes implement redundant servo systems, where a redundant server is provided to replace another server that detects an outage. Because the redundant server must have the same computing power as the primary server, providing redundant servers increases space and cost issues.

[0007] To be precise, the power supply is often the point of failure in a servo system. Therefore, redundant power supplies have been implemented in servo systems because they can usually be implemented at a lower cost and in less space. In servo systems using multiphase power supplies, N+2 phase redundant solutions are becoming more and more popular. That is, a multiphase power supply includes N phases required to provide the servo system, as well as two additional phases for redundancy. If a certain operating phase fails, the failed phase will simply be isolated from the system so that the remaining phases in the multiphase power supply continue to provide power uninterruptedly. Summary of the invention

[0008] The present invention relates to a power stage in a multi-phase switching power supply, which receives a pulse width modulation (PWM) signal and an input voltage associated with a phase of the power stage and provides an output voltage. The power stage comprises: a high-voltage side power switch and a low-voltage side power switch, which are connected in series between an input voltage node and a ground reference voltage and are controlled by a PWM signal; a switch output node between current terminals of the high-voltage side power switch and the low-voltage side power switch generates a switch output voltage, and the switch output node is coupled to a first terminal of an output inductor; a phase redundancy controller, which receives the PWM signal and generates a first control signal; an output voltage disconnect transistor, which is coupled between a second terminal of the output inductor and an output node providing the output voltage, and the output voltage disconnect transistor receives the first control signal from the phase redundancy controller, wherein the first control signal has a function of turning on the output voltage disconnect transistor. The phase redundant controller includes a first state of the output voltage disconnect transistor to connect the output inductor to the output node, and a second state of the output voltage disconnect transistor to disconnect the output inductor from the output node; and a current sensing transistor having a first current terminal coupled to the second terminal of the output inductor, and a second current terminal coupled to the first node through a sensing resistor, and a control terminal receiving a first control signal, the current sensing transistor having the same transistor structure as the output voltage disconnect transistor and a size that is a fraction of the output voltage disconnect transistor, wherein the current sensing transistor is turned on by the first control signal to conduct a portion of the inductor current flowing in the output inductor of the power stage, and the phase redundant controller receives a current sensing voltage signal measured by the sensing resistor to generate a current sensing signal indicative of the inductor current.

[0009] It also includes: an input voltage disconnect transistor coupled between the input voltage node and the input voltage, the input voltage disconnect transistor receiving a second control signal generated by the phase redundancy controller, wherein the second control signal has a first state to turn on the input voltage disconnect transistor, thereby connecting the high-voltage side power switch to the input voltage, and a second state to turn on the input voltage disconnect transistor to disconnect the high-voltage side power switch from the input voltage.

[0010] The output voltage disconnect transistor comprises a MOS transistor, the current sensing transistor comprises a MOS transistor having the same transistor structure as the output voltage disconnect transistor, and the transistor channel width of the current sensing transistor is a small fraction of the transistor channel width of the output voltage disconnect transistor.

[0011] The output voltage disconnect transistor and the current sensing transistor are formed on the same semiconductor substrate.

[0012] The output voltage disconnect transistor includes a trench MOS transistor formed in a first plurality of trench cells, and the current sensing transistor includes a trench MOS transistor formed in a second plurality of trench cells, which are a small portion of the first plurality of trench cells.

[0013] The sensing resistor is an independent resistor located outside the semiconductor substrate.

[0014] The current sensing transistor has a transistor channel width that is 1 / 1000 to 1 / 10,000 of a transistor channel width of the output voltage disconnect transistor.

[0015] The output node of the power stage is coupled to the output capacitor of the multi-phase switching power supply to form an LC filter circuit with the output inductor in response to the output voltage disconnecting transistor closing to generate a regulated output voltage with a substantially constant amplitude at the output voltage node of the multi-phase switching power supply, and the regulated output voltage is coupled to drive a load, wherein the first node includes a node at the load for sensing the regulated output voltage provided to the load.

[0016] The present invention also discloses a power stage in a multi-phase switching power supply, which receives a pulse width modulation (PWM) signal associated with the phase of the power stage and the input voltage, and provides an output voltage, and the power stage includes: a high-side power switch and a low-voltage side power switch. A switch output node between the current terminals of the high-side power switch and the low-voltage side power switch is connected in series between the input voltage node and the ground reference voltage and is controlled by the PWM signal, and the switch output voltage is generated by the switch output node, and the switch output node is coupled to the first terminal of the output inductor; a phase redundancy controller receives the PWM signal and generates a first control signal; and an output voltage disconnect transistor having a first current terminal coupled to the second terminal of the output inductor and a second current terminal coupled to the output node providing the output voltage, wherein the output voltage disconnect transistor receives the first control signal from the phase redundancy controller, wherein the signal has a first state to turn on the output voltage disconnect transistor, thereby connecting the output inductor to the output node and a second state to turn on the output voltage disconnect transistor, and disconnect the output inductor from the output node,

[0017] Therein, the phase redundant controller measures a voltage between a first current terminal and a second current terminal of an output voltage disconnect transistor, the voltage being indicative of an inductor current flowing in an output inductor of the power stage.

[0018] Where the output voltage turns off the transistor including a MOSFET device, the voltage represents the inductor current and the on-resistance of the MOSFET device.

[0019] The phase redundant controller generates a current sensing signal representing a voltage and applies temperature compensation to the current sensing signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following detailed description and accompanying drawings set forth various embodiments of the invention.

[0021] Figure 1 A schematic diagram of a multi-phase switching power supply implementing a phase redundancy scheme is shown, wherein the current sensing circuit and method of the present invention can be implemented in embodiments of the present invention.

[0022] Figure 2 A circuit diagram showing a method of measuring phase current by sensing the on-resistance of a low-side power switch in some examples.

[0023] Figure 3 A circuit diagram is shown of a method for providing sensing the direct current resistance (DCR) of an output inductor to measure phase current in some examples.

[0024] Figure 4 In some examples, a curve showing a change in the inductor current waveform according to the switching action of the power switch.

[0025] Figure 5 A schematic diagram showing a power stage in a multi-phase switching power supply using current sensing transistors to implement phase current sensing in some examples according to embodiments of the present invention.

[0026] Figure 6 A schematic diagram illustrating, in some embodiments, connecting a current sense transistor to an output voltage sense node.

[0027] FIG. 7 , including FIG. 7 ( a ) and FIG. 7 ( b ), shows a method of manufacturing a current sensing transistor in combination with an ORing field effect transistor (output voltage isolation transistor) in some embodiments.

[0028] Figure 8 A schematic diagram showing a power stage in a multi-phase switching power supply implementing phase current sensing at an ORing field effect transistor in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] According to an embodiment of the present invention, a multi-phase switching power supply implementing a phase redundancy scheme includes a current sensing transistor coupled in series with an output inductor in each power stage so as to sense the phase current of each power stage. In some embodiments, the current sensing transistor is a field effect transistor that reflects an output voltage disconnect transistor, referred to as an ORing field effect transistor or "ORing field effect tube", which is used to disconnect a faulty power stage from the remaining power stages in the multi-phase switching power supply. The current through the current sensing transistor is equal to the current through the ORing field effect tube multiplied by the width ratio of the two transistors. The current sensing transistor measures a portion of the inductor current of the output inductor in the LC filter circuit flowing through each power stage, wherein the inductor current indicates the load current of the power stage. In this way, accurate current sensing is achieved for each power stage without the need for temperature compensation of the current sensing value.

[0030] In another embodiment of the present invention, the phase current sensing in the power stage of the multi-phase switching power supply is implemented by monitoring the on-resistance RDSON of the ORing field effect transistor. Temperature compensation technology can be used to compensate for the temperature coefficient in the current sensing measurement.

[0031] Figure 1 A schematic diagram of a multi-phase switching power supply implementing a phase redundancy scheme, wherein the current sensing circuit and method described in the present invention can be implemented in an embodiment of the present invention. Figure 1 The multi-phase switching power supply 10 (“power supply 10”) receives an input voltage V IN (node ​​16), and generates a modulated output voltage V at the output node 24 for providing the load 26 OUT For example, the input voltage V IN The input voltage can be 12V, and the modulated output voltage V OUT It can be a 1.8V output voltage for driving a load, such as a CPU in a servo system. The multi-phase switching power supply 10 also receives other power supply voltages for powering support circuits in the power supply circuit. For example, a power supply VDD (e.g., 3.3V) (node ​​15) is provided to power the controller circuit, and a power supply PVcc (e.g., 5V) (node ​​18) is provided to power the drive circuit at the power supply stage. The multi-phase switching power supply 10 is capable of providing a high-precision modulated output voltage under a wide range of load conditions.

[0032] In the embodiment described in the present invention, the multi-phase switching power supply 10 implements a phase redundancy scheme, and includes one or more redundant phases (or power stages) in addition to the power stage required to meet the current demand. In the present embodiment, the power supply 10 includes two redundant power stages, and the power supply 10 is also referred to as an N+2 phase power supply, where N refers to the number of power stages required to meet the current demand of the load, and 2 refers to the additional power stage for redundancy. The two redundant power stages provide a high level of fault safety protection because the probability of two power stages failing in the power supply is very low. In the present embodiment, the N+2 phase power supply 10 includes a multi-phase controller 20 capable of driving N+2 power stages. The multi-phase controller 20 is sometimes referred to as an N+2 phase controller. The multi-phase controller 20 is coupled so as to provide a phase redundancy scheme with associated output inductors L1 to LN+2 and output capacitors C OUT Drive N+2 power stages SPS1 to SPSN+2. In the present embodiment, the power stage is implemented as an intelligent power stage, which has the ability to report certain operating parameters (e.g., sensing temperature) to the controller 20. The use of the intelligent power stage is for explanation only and is not intended to be limiting. In other embodiments, the switching power supply 10 can be implemented using only a power stage including a power switch and a drive circuit without the ability to report operating parameters.

[0033] In one example, a load 26 such as a CPU may require a current of 250 A. The current of 250 A can be provided by an 8-phase switching power supply. When a phase redundancy scheme is implemented, the switching power supply is configured as a 10-phase switching power supply, including 8 minimum phases and 2 additional phases to meet the load current requirements.

[0034] In operation, the N+2 power stages of the power supply 10 are activated to provide the load current demand. If any of the N+2 power stages SPS1 to SPSN+2 fails, the failed power stage is isolated and disconnected from the other power stages. The remaining N+1 power stages continue to operate uninterruptedly. The current demand is distributed across the remaining power stages so that the switching power supply 10 operates uninterruptedly. If the second power stage fails, the power supply 10 can still continue to operate using the remaining minimum number of phases to meet the current demand. Specifically, the N+2 power stages are switchably connected to a set of shared signals. If one power stage fails, the failed power stage is disconnected from all shared signals so that the remaining power stages continue to provide uninterrupted power. In some cases, the controller 20 may issue an alarm to the host system about the failed power stage.

[0035] More specifically, the power supply 10 includes power stages SPS1 to SPSN+2 driven by respective PWM signals PWM1 to PWMN+2. Each power stage SPSx includes a pair of power switches that are turned on and off by the corresponding PWM signal to regulate the output voltage V with reference to the target voltage.OUT The power switch in each power stage SPSx is alternately turned on and off to generate a switch output voltage SW at a switch output node 22. The switch output node 22 of each power stage SPSx is coupled to a respective output inductor Lx. The inductors Lx of all power stages are coupled to an output capacitor C OUT , forming an LC filter circuit for providing current to the output node 24 while maintaining a substantially constant output voltage V OUT Then, the output voltage V OUT Can be used to drive load 26.

[0036] The multi-phase controller 20 receives a signal indicating the modulated output voltage V at the load 26. OUT The feedback voltage V FB In some examples, the feedback voltage V FB It can be the voltage driving the load 26, or the output voltage V OUT The multi-phase controller 20 includes a circuit for implementing a feedback control loop of the switching power supply 10 to generate multi-phase PWM signals PWM1 to PWMN+2 to drive each power stage SPSx in the multi-phase power supply 10.

[0037] In an embodiment of the present invention, each power stage SPSx receives a corresponding PWMx signal from the controller 20 to control the switching of the power switch in the power stage. The power stage SPSx can also be configured to measure the local temperature of the power stage and provide a temperature sensing signal TMON to the controller. In this example, the temperature sensing signals TMON of all power stages SPS1 to SPSN+2 are connected together and provided to the controller 20 for collective monitoring as a signal TSEN. For example, the power stage with the highest junction temperature acts as the main stage. In this specification, the power stage SPSx can also be configured to measure the phase current provided by the power stage. The phase current of each power stage is measured as a signal IMON and reported to the controller 20 as a current sensing signal ISENPx. In some examples, the signal IMON is a differential signal with reference to a reference voltage REFIN provided by the controller 20 as a sensing signal ISENNx. In one example, the reference voltage REFIN is 1.2V.

[0038] The power stages SPS1 to SPSN+2 are switchably connected to a set of shared signals. Specifically, the shared signals include: input voltage V IN (node ​​16) (e.g. 12V), gate driver voltage PVcc (e.g. 5V), output voltage V OUT(node ​​24), reference voltage REFIN (node ​​12) and temperature sensing signal TMON (node ​​14). During operation, the N+2 power stages are connected to the shared signal. A faulty power stage disconnects from the power supply by disconnecting from the shared signal.

[0039] So configured, each power stage SPSx is connected to the shared signal through a set of switches or transistors. In some embodiments, due to high voltage and / or high current requirements, each power stage is connected to the input voltage V through a disconnect transistor implemented as a power field effect transistor (FET). IN and output voltage V OUT In an embodiment of the present invention, the input voltage disconnects the transistor, and the input voltage V IN The power switches connected to each power stage. The input voltage disconnect transistor is also called an E-Fuse or input voltage disconnect FET. In addition, an output voltage disconnect transistor connects the output inductor to the output voltage node of each power stage. The output voltage disconnect transistor is also called an ORing FET or output voltage disconnect FET. The power stage is connected to other shared signals (PVcc, TMON, REFIN) by disconnecting switches or transistors, which can be configured as FETs but not necessarily power transistors. For simplicity, Figure 1 The disconnect switches / transistors are not shown, but it is understood that each power stage SPSx can be switched to connect to Figure 1 The shared signal is shown in the dashed circle.

[0040] During operation, the controller 20 in the power supply 10 needs to accurately measure the output current or phase current provided by each power stage SPSx. For example, the phase current provided by each power stage is monitored in order to perform load balancing between the power stages. Load balancing is very important for optimizing the thermal performance of the power supply 10 to avoid a situation where one power stage conducts a much larger share of the load current than the other power stages. In another example, the host system operating the load typically requires accurate measurement of the load current provided to the load to determine whether the load operation needs to be adjusted. For example, where the load is a CPU, the host system can determine whether to use an overclocking mode based on the load current consumption and other factors. Finally, in some cases, the load may be operated based on a load line, and the controller 20 needs load current information to determine whether the output voltage V needs to be adjusted. OUT How much regulation is made is a function of the load current being carried out.

[0041] Figure 2 and Figure 3 A circuit diagram showing a method for measuring phase current at a power stage, in some examples. Figure 2is a circuit diagram showing some examples of how phase current is measured by sensing the on-resistance of the low-side power switch. Figure 3 is a circuit diagram showing a method in some examples for measuring phase current by sensing the DC resistance (DCR) of the output inductor. Figure 2 and Figure 3 The method for receiving a PWM signal and applying an LC filter (including an output inductor Lx and an output capacitor C OUT ) generates a switch output signal SW and an output voltage V OUT To simplify the discussion, Figure 1-3 Similar components in the drawings are given similar reference numerals.

[0042] See first Figure 2 The power stage 30 includes a driver logic circuit 32, which receives the PWM signal and provides gate drive signals to corresponding gate drivers 33 and 34. The gate drivers 33 and 34 are coupled to drive corresponding power switches Q3 and Q4. The power switches Q3 and Q4 (referred to as the high-side power switch and the low-side power switch, respectively) are connected in series to the input voltage V IN and the ground reference voltage. In this embodiment, the power switches Q3 and Q4 are NMOS transistors or N-type MOSFET transistors. The power switch Q3 is driven by the high-voltage side gate drive signal V HS The power switch Q4 is turned on to conduct current to charge the inductor Lx during the on-time of the PWM duty cycle. The power switch Q4 is driven by the low-side gate drive signal V LS is turned on to conduct current to the discharge inductor Lx during the off period of the PWM duty cycle.

[0043] Figure 4 Graph showing an inductor current waveform in response to a switching action of a power switch in some examples. Figure 4 , controls the high-side gate drive signal V of the high-side power switch Q3 HS (curve 45) responds to the PWM signal provided to the power stage to open and turn on. At the same time, the low-side gate drive signal V that controls the low-side power switch Q4 LS (curve 46) is turned on and off in response to the PWM signal, and is in the opposite phase to the power switch Q3. That is, the power switches Q3 and Q4 are turned on and off alternately. Therefore, the inductor Lx is charged and discharged by the on-off action of the power switches Q3 and Q4, and the inductor current IL (curve 47) presents a sawtooth waveform. When the power switch Q3 is turned on, the inductor current IL has an upward slope in the charging stage, and when the power switch Q4 is turned on, the inductor current IL has a downward slope in the charging stage. The inductor current is coupled to the output capacitor C OUT , charging and discharging the output capacitor.OUT The inductor current represents the phase current of the power stage.

[0044] like Figure 2 As shown, a common method for measuring phase current in the power stage is low-side current sensing. Low-side current sensing can measure the current at the low-side power switch Q4. In other words, the downward slope inductor current is measured and the upward slope inductor current is estimated to obtain the total inductor current of the power stage. In one example, the current flowing through the low-side power switch Q4 is measured by sensing the drain-to-source voltage across the power switch Q4 (for example, using a sense amplifier 36). The sensed current Ics represents the current flowing in the low-side power switch Q4, corresponding to Figure 4 Inductor current I L The sensed current Ics is then provided to the IMON reconstruction circuit 38 to estimate the upward slope inductor current and generate an estimated total inductor current IMON (node ​​17). The estimated total inductor current IMON can be provided by the power stage to a controller (e.g., controller 20) to perform management functions such as load balancing or current monitoring. In some cases, the inductor current signal IMON is a differential signal and is referenced to a reference voltage REFIN (node ​​12).

[0045] Sensing the inductor current at the low-side power switch Q4 has some disadvantages. Because the current Ics is sensed by measuring the on-resistance (RDSON) of transistor Q4, the current Ics tends to vary with the junction temperature of transistor Q4. To ensure accuracy, temperature compensation must be performed to account for changes in RDSON. In addition, the low-side sensing method estimates the upward slope inductor current. The upward slope inductor current can be estimated as:

[0046]

[0047] Where V L represents the voltage across the inductor, di represents the change in inductor current, and L represents the inductance Lx of the output inductor.

[0048] The upward slope inductor current is a function of the output inductor inductance Lx. As the inductance changes, the upward slope will also change. During operation, the inductance value is not constant for all current values. At high inductor currents, the inductance may decrease. Therefore, the IMON reconstruction circuit 38 will need to account for inductance changes, as well as RDSON changes. Therefore, the accuracy of the low-side current sensing method is limited.

[0049] like Figure 3 As shown in Figure 1, another method of measuring phase current in the power stage is inductor DCR (DC resistance) current sensing. That is, the phase current of the power stage is measured by using the DC resistance of the inductor (in Figure 3 The current flowing through the inductor Lx is measured by measuring the current (denoted as Rdcr in the figure). A filter circuit including a resistor Rsns and a capacitor Csns is connected in series with the inductor Lx to match the time constant of the inductor Lx with the DC resistance. SNS Measuring Current. Inductor DCR current sensing is affected by temperature changes and therefore requires temperature compensation for improved accuracy.

[0050] In an embodiment of the present invention, a circuit and method for measuring phase current in a multi-phase power supply in a power stage uses a current sensing transistor in series with an output inductor to sense the phase current in the power stage. In addition, in some embodiments, the current sensing transistor is mirrored into an output voltage disconnect transistor or ORing field effect transistor in the power stage to disconnect the power stage from the output voltage node in a phase redundancy scheme. In this way, accurate current sensing can be performed in the power stage using a simple circuit.

[0051] Figure 5 is a schematic diagram of a power stage in a multi-phase switching power supply using current sensing transistors to implement phase current sensing in an embodiment of the present invention. In an embodiment of the present invention, Figure 5 The power stage 50 shown can be used to implement Figure 1 Each power stage SPS1 to SPSN+2 in the Figure 5 The power stage 50 shown can be used to implement Figure 1 Each phase of the multi-phase switching power supply 10.

[0052] See also Figure 5 The power stage 50 includes power switches Q3 and Q4 driven by a driving circuit 52, a phase redundancy controller (PRC) 60, an input voltage disconnect transistor Q1 (E-Fuse), an output voltage disconnect transistor Q2 (ORing field effect transistor), and an output inductor Lx. The power stage 50 implements one phase of a multi-phase switching power supply, and an output node 56 of the power stage 50 is connected to the output voltage node of the multi-phase switching power supply so as to be connected to the output nodes of the power stages of other phases, and is connected to the output capacitor C OUT The output voltage nodes of the multiphase switching power supply are then coupled to drive the load.

[0053] The power stage 50 is derived from a multi-phase controller (eg Figure 1 The multi-phase controller 20 receives a PWM signal PWMx (node ​​62). The PWM signal PWMx is related to the phase of the power stage. The drive circuit 52 receives the PWMx signal and generates a high-side drive signal V HS , in order to drive the high-side power switch Q3 and the low-side gate drive signal V LS, thereby driving the low-side power switch Q4. The power switches Q3 and Q4 are alternately turned on and off to generate a switching output voltage SW (node ​​54), which is coupled to an LC filter formed by an output inductor Lx and an output capacitor COUT to generate an output voltage V at an output node 56. OUT . As mentioned above, and Figure 4 As shown, the power switch Q3 is driven by the high-voltage side gate drive signal V HS The power switch Q4 is turned on to conduct current to charge the inductor Lx during the on-time of the PWM duty cycle. The power switch Q4 is driven by the low-side gate drive signal V LS is turned on to conduct current to the discharge inductor Lx during the off period of the PWM duty cycle.

[0054] When implementing the power stage 50 in a multi-phase switching power supply, the power stage 50 is switchably connected to a set of signals shared with other power stages, as described above with reference to FIG. Figure 1 A disconnect switch or transistor is used to connect each power stage to the shared signal so that the corresponding power stage can be disconnected from the shared signal when a power stage fails. Figure 1 In the embodiment shown, each power stage is switchably connected to five shared signals: V IN 、V OUT , PVcc, TMON, and REFIN. Figure 5 In order to simplify the discussion, the power stage 50 is shown to be connected only to the shared signal V IN and V OUT For simplicity, other shared signals are omitted, but it should be understood that the power stage 50 includes connections to all shared signals in the multi-phase switching power supply.

[0055] In an embodiment of the present invention, the power stage 50 is switchably connected to the input voltage V via an input voltage disconnect transistor Q1 (also referred to as an E-Fuse). IN (Node 56). In this embodiment, resistor R5 is coupled between the E-Fuse (transistor Q1) and the input voltage V IN (node ​​56) to provide current sensing. Resistor R5 is optional and can be omitted in other embodiments. In other embodiments, current sensing can be performed at transistor Q1 instead of using resistor R5. The power stage 50 is also switchably connected to the output node 56 via an output voltage disconnect transistor Q2 (also known as an ORing field effect transistor). Specifically, the ORing field effect transistor (transistor Q2) is connected in series with the output inductor Lx of the power stage. In other words, transistor Q2 is connected between the terminal (node ​​55) of the output inductor Lx and the output node 56.

[0056] The input voltage disconnect transistor Q1 (E-Fuse) is controlled by the control signal HGATE (node ​​73) provided by the phase redundant controller 60. The output voltage disconnect transistor Q2 (ORing field effect transistor) is controlled by the control signal LGATE provided by the phase redundant controller 60. During normal operation, the control signals HGATE and LGATE are determined to be turned on, disconnecting transistors Q1 and Q2, and the power stage 50 is connected to the input voltage V IN and output node 56. If a fault condition is detected in power stage 50, phase redundancy controller 60 will de-evaluate control signals HGATE and LGATE, and disconnect transistors Q1 and Q2 will open to disconnect power stage 50 from input voltage V IN and output voltage V OUT It is noted that the power stage 50 includes other disconnect switches or transistors to disconnect the power stage from other shared signals. To simplify the discussion, Figure 5 Other isolation switches / transistors are not shown. By using the disconnect transistor, the faulty power stage can be disconnected from the multi-phase switching power supply to enable the power supply to maintain uninterrupted power supply operation using the remaining power stages.

[0057] In some examples, for the case where the power switch Q3 is short-circuited, the power stage 50 can detect the fault in two ways. If the driver circuit 52 and the power switch Q4 are still working, when the power switch Q4 is turned on, the phase redundancy controller 60 can sense the current in the resistor R5, which is an abnormal condition, and the controller 60 can indicate a fault condition. Alternatively, when the driver circuit 52 or the power switch Q4 cannot be turned on, the switch output voltage SW on the switch node 54 will remain at a high level. This situation is detected by the filter circuit formed by the resistors R2 and R3, the capacitor C1 and the diode D1. The filter circuit receives the switch output voltage SW and generates an output signal SWX (node ​​58) having a time constant determined by the resistance of the resistors R2 and R3 and the capacitance of the capacitor C1. The signal SWX is coupled to the comparator 66 for comparison with the voltage threshold THD (node ​​65). If the signal SWX increases above the voltage threshold THD, the comparator 66 determines that the output signal is faulty (node ​​68) to indicate a fault condition. Specifically, during normal operation, when the switch output voltage SW alternates between a high state and a low state based on the duty cycle of the PWMx signal, before the signal SWX is discharged, the signal SWX will be charged, but will not be charged to the voltage threshold THD. However, when the switch output voltage SW remains at a high level, the signal SWX will be charged and will eventually exceed the voltage threshold THD. Therefore, the comparator 66 will assert the fault signal. In response to the fault signal, the phase redundancy controller 60 will de-evaluate the HGATE and LGATE signals to open the E-Fuse and the ORing field effect transistor, thereby generating a fault signal from the input voltage V IN The power stage 50 is disconnected from the output node 56. In this way, the signal SWX generated by the filter circuit of resistors R1, R3 and capacitor C1 is used to signal when the duty cycle of the switching output voltage SW has exceeded the maximum allowed duty cycle.

[0058] In other examples, for the case where the power switch Q4 is shorted, the power stage 50 can detect the fault in two ways. If the drive circuit 52 and the power switch Q3 are still working, when the power switch Q3 is turned on, the phase redundancy controller 60 can sense the current in the resistor R5, which is an abnormal condition, and the controller 60 can issue a fault condition. Alternatively, in the case where the power switch Q4 is shorted, the current will discharge from the output node 56 to ground through the switch Q4. The phase redundancy controller 60 is configured to detect this negative current flowing in the transistor Q2. If a negative current is detected in the transistor Q2, the phase redundancy controller 60 will indicate a fault condition.

[0059] In an embodiment of the present invention, power switches Q3 and Q4 are MOSFET transistors, and disconnect transistors Q1 and Q2 are also MOSFET transistors. In addition, in one embodiment, transistors Q1, Q2, Q3 and Q4 are NMOS power transistors or N-type MOSFET transistors.

[0060] In an embodiment of the present invention, current sensing at the power stage 50 is implemented using a current sensing transistor Q5 that mirrors the output voltage disconnect transistor Q2 (ORing FET) and is a fraction of the size of the disconnect transistor Q2. Specifically, the current sensing transistor Q5 has a transistor width that is a fraction of the transistor width of the disconnect transistor Q2 (ORing FET). The current sensing transistor Q5 is substantially connected in parallel with transistor Q2 and is controlled by the same control signal LGATE. More specifically, the current sensing transistor Q5 is connected in series with the output inductor Lx and conducts a portion of the inductor current flowing from the inductor Lx to the output node 56. Because the O-type FET (transistor Q2) carries the entire inductor current - both the up-slope and down-slope current, the entire load current is monitored by monitoring the current of transistor Q2 using the mirror transistor Q5.

[0061] Specifically, the output inductor Lx has a first terminal (node ​​54) and a second terminal (node ​​55) connected to the switching output voltage SW. The output voltage disconnect transistor Q2 has a first current terminal (e.g., source) connected to the second terminal (node ​​55) of the output inductor Lx, a second current terminal (e.g., drain) connected to an output node 56 providing an output voltage, and a control terminal coupled to receive a control signal LGATE. The current sensing transistor Q5 has a first current terminal (e.g., source) connected to the second terminal (node ​​55) of the output inductor Lx, a second current terminal (e.g., drain) (node ​​57), and a control terminal coupled to receive a control signal LGATE. The second current terminal (node ​​57) of the current sensing transistor Q5 is connected to a voltage sensing node 80 through a resistor R1. In this specification, VOUT_sense node 80 is a sensed output voltage V at the load. OUT The output voltage V at the VOUT_ sensing node 80 OUT tends to have an output voltage V lower than that at the source (node ​​56) of transistor Q2, which is the output node of the power stage. OUTThe voltage level of the current sensing transistor Q5. The size of the current sensing transistor Q5 is a small portion of the output voltage disconnect transistor Q2. With such a configuration, the current sensing transistor Q5 conducts a portion of the load current flowing through the inductor Lx. The current flowing through the current sensing transistor Q5 is measured by the resistor R1. In the present embodiment, the voltage through the resistor R1 is measured by the phase redundant controller 60 to indicate the current flowing through the current sensing transistor Q5. For example, the voltages LCS+ and LCS- through the resistor R1 are measured by the phase redundant controller 60 and indicate the current conducted through the current sensing transistor Q5. The phase redundant controller 60 includes a current monitoring circuit 78, which receives the voltages LCS+ and LCS- and generates a current monitoring signal IMON (node ​​70) of the reference voltage REFIN (node ​​72). In some embodiments, the controller 60 converts the LCS+ and LCS- signals into current signals with a gain of 5μA / A. That is, when the 1kΩ sensing resistor R4 on the IMON pin is connected to the reference voltage REFIN, a voltage signal of 5mV / A can be provided as the IMON signal. The IMON signal and the REFIN signal can then be provided directly to a multiphase controller, such as Figure 1 A multi-phase controller 20 is shown.

[0062] In some embodiments, the ORing FET (transistor Q2) is a MOS transistor, and the current sensing transistor Q5 is a mirror MOS transistor that is a fraction of the size of the switch Q2. That is, transistors Q2 and Q5 have the same transistor channel length, and the current sensing transistor Q5 has a transistor channel width that is a fraction of the transistor channel width of transistor Q2 (ORing FET). In some embodiments, the ORing FET (transistor Q2) and the current sensing transistor Q5 have a size ratio (or width ratio) of 1000:1, 5000:1, or 10000:1. A suitable size ratio can be selected to determine the amount of phase current to be conducted and dissipated through transistor Q5.

[0063] In some embodiments, transistors Q2 and Q5 are constructed using the same transistor structure. For example, transistor Q2 can be constructed as a trench MOS transistor, and transistor Q5 is also constructed as a trench MOS transistor, but its size is a fraction of the trench MOS transistor. For example, transistor Q2 can be constructed using a first trench, and transistor Q5 can be constructed using a second trench, and the second number is a fraction of the first number.

[0064] In some embodiments, resistor R1 is a precision resistor that provides high-precision current sensing. In some embodiments, transistors Q2 and Q5 are formed on the same integrated circuit die, and resistor R1 is a discrete resistor formed outside the integrated circuit die. In other embodiments, resistor R1 can be a polysilicon resistor formed on the integrated circuit die. The resistance value of the polysilicon resistor can be adjusted to obtain the desired accuracy.

[0065] The current sensing method using a mirror current sensing transistor described in the present invention has significant accuracy advantages over traditional current sensing techniques. The mirror current sensing transistor measures the entire inductor current waveform, including the upward slope and the downward slope. This provides a particular advantage over the low-voltage side sensing method, in which the load current is sensed only on the low-voltage side power switch Q4 and the inductor upward slope current must be estimated. In addition, since the current sensing signal measured by the current sensing transistor is independent of temperature and independent of the inductance value, there is no need to temperature compensate the sensed current value. Since the current of the entire inductor is monitored in real time, changes in the inductance value of the output inductor are included in the current sensing measurement. No further compensation is required. The current sensing transistor Q5 may need to be calibrated to the ORing field effect transistor (transistor Q2). However, once calibrated, the current sensing transistor Q5 will mirror the ORing field effect transistor (transistor Q2) and conduct a portion of the phase current for current sensing.

[0066] As described above, current sensing transistor Q5 is connected to VOUT_SENSE node 80 through resistor R1. Figure 6 Schematic diagram showing the connection of a current sensing transistor to an output voltage sensing node in some embodiments. Figure 6 The output nodes 56 of each power stage are connected together to the output voltage node 82 (also referred to as the power output node) of the multi-phase switching power supply. Output capacitor C OUT connected to the power supply output node 82 to generate the output voltage V OUT . Output voltage V OUT Connected to drive load 26, such as CPU. Output voltage V OUT The connection or conductive line connected to the load 26 has a certain IR voltage drop. Therefore, the output voltage V at the load 26 OUT can be lower than the output voltage V at the power supply output node 82 OUT The output voltage at the load 26 is fed back to the multi-phase switching power supply so that the output voltage V OUT Specifically, the feedback voltage V FB is measured at the VOUT_SENSE node 80 at the load 26 .

[0067] In an embodiment of the present invention, resistor R1 is connected between current sensing transistor Q5 at load 26 and VOUT_SENSE node 80. In this way, the voltage drop across resistor R1 is minimized while providing sufficient headroom to sense the current in transistor Q5. Specifically, in a multi-phase switching power supply, resistor R1 or each power stage is connected to VOUT_SENSE node 80 in a fan-out configuration. The resistor R1 of the power stage is not connected to the VOUT_SENSE node 80 connected to the feedback voltage V FB on the sensing line 85 so as not to interfere with the feedback voltage.

[0068] FIG. 7 includes FIG. 7( a) and FIG. 7( b), which illustrate a method of forming a current sensing transistor in combination with an ORing field effect transistor (output voltage disconnect transistor) in some embodiments. Referring to FIG. 7( a), the ORing field effect transistor (transistor Q2) and the mirror current sensing transistor Q5 are constructed as MOS transistors having a common source connection (node ​​55) and a common gate connection (node ​​74). In some embodiments, the ORing field effect transistor (transistor Q2) and the mirror current sensing transistor Q5 are formed on the same integrated circuit die, as shown in FIG. 7( b). In other words, the ORing field effect transistor (transistor Q2) and the mirror current sensing transistor Q5 are formed on the same semiconductor substrate. FIG. 7( b) illustrates an exemplary embodiment of transistors Q2 and Q5 formed as vertical trench MOS transistors. In this case, transistors Q2 and Q5 can be formed using a common source (node ​​55) and a common gate connection (node ​​74). Transistor Q2 is formed using most trench cells on a wafer, while transistor Q5 is formed using a small portion or a small portion of trench cells on the same wafer. Therefore, the drain connection pad of transistor Q2 (node ​​56) occupies most of the trench cell, while the drain connection pad of transistor Q5 (node ​​57) occupies only a small part of the trench cell. In this way, transistor Q2 and transistor Q5 are both formed on the same integrated circuit wafer and both experience the same temperature offset. Therefore, transistor Q5 can achieve high-precision current sensing. The trench transistor structure shown in Figure 7 is only for explanation and is not intended to be limiting. In other embodiments, transistors Q2 and Q5 can be implemented using a lateral DMOS (LDMOS) process.

[0069] Figure 8 A schematic diagram showing a power stage in a multi-phase switching power supply implementing phase current sensing at an ORing field effect transistor in an embodiment of the present invention. Figure 8 The power stage 100 shown is manufactured in a manner similar to Figure 5 The power stage 50 is similar in manner, and similar elements are given similar reference numerals and will not be described again. Figure 8, the power stage 100 implements phase current sensing by measuring the on-resistance of the ORing field effect transistor (transistor Q2). In this way, there is no need to provide an additional mirror transistor. The on-resistance (RDSON) of transistor Q2 can be measured by measuring the voltage between the source (node ​​55) and the drain (node ​​56) of transistor Q2. In this embodiment, the voltages LCS+ and LCS– of the ORing field effect transistor (transistor Q2) are measured by the phase redundant controller 110 and indicate the inductor current flowing through the ORing field effect transistor. The phase redundant controller 110 includes a current monitoring circuit 118, which receives the voltages LCS+ and LCS- and generates a current monitoring signal IMON (node ​​70) of a reference voltage REFIN (node ​​72). The IMON signal and the REFIN signal can then be directly provided to a multi-phase controller, such as Figure 1 A multi-phase controller 20 is provided. In an embodiment of the present invention, the on-resistance (RDSON) of transistor Q2 may have a specific variation as a function of the junction temperature of the transistor. To improve the accuracy of current sensing, the current monitoring circuit 118 implements temperature compensation to correct for variations in RDSON as a function of temperature. In one example, the current monitoring circuit 118 applies temperature compensation based on a measured wafer temperature of an integrated circuit wafer on which transistor Q2 is implemented. In one embodiment, temperature compensation may be provided by co-packaging transistor Q2 with a phase redundant controller chip in a multi-chip package, which may provide the thermal coupling needed to correct for variations in RDSON with temperature. The temperature sensor may be implemented on the phase redundant controller integrated circuit.

[0070] The present invention may be implemented in a variety of ways, including as a process, an apparatus, a system, a composition of matter, a computer program product embodied on a computer-readable storage medium, and / or a processor, such as a hardware processor or processor device, which is configured to execute instructions stored in and / or provided by a memory coupled to the processor. In this specification, these implementations or any other form that the present invention may take may be referred to as techniques. In general, the order of the steps of the disclosed method may be changed within the scope of the present invention. Unless otherwise stated, components such as processors or memories described as being configured to perform tasks may be implemented as general components that are temporarily configured to perform tasks at a given time or as specific components manufactured to perform tasks. As used herein, the term "processor" refers to one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0071] The above provides a detailed description of one or more embodiments of the present invention and drawings that illustrate the principles of the present invention. The present invention is described in conjunction with these embodiments, but the present invention is not limited to any embodiment. The scope of the present invention is limited only by the claims, and the present invention includes many alternatives, modifications and equivalents. In order to provide a thorough understanding of the present invention, many specific details are set forth in the specification. These details are provided for illustrative purposes, and the present invention can be implemented according to the claims without some or all of these specific details. For the sake of clarity, technical materials known in the technical field related to the present invention are not described in detail to avoid unnecessary confusion of the present invention.

[0072] The above detailed description is provided to illustrate specific embodiments of the present invention, not to limit it. Many modifications and variations are possible within the scope of the present invention. The present invention is defined by the appended claims.

Claims

1. A power stage in a multi-phase switching power supply, receiving a pulse width modulation (PWM) signal associated with a phase of the power stage and an input voltage, and providing an output voltage, the power stage comprising: A high-side power switch and a low-side power switch are connected in series between an input voltage node and a ground reference voltage and are controlled by a PWM signal, a switch output node between current terminals of the high-side power switch and the low-side power switch generates a switch output voltage, and the switch output node is coupled to a first terminal of the output inductor; a phase redundant controller, receiving the PWM signal and generating a first control signal; an output voltage disconnect transistor coupled between the second terminal of the output inductor and an output node providing the output voltage, the output voltage disconnect transistor receiving a first control signal from the phase redundant controller, wherein the first control signal has a first state to turn on the output voltage disconnect transistor, connecting the output inductor to the output node, and a second state to turn on the output voltage disconnect transistor, so as to disconnect the output inductor from the output node; as well as a current sensing transistor having a first current terminal coupled to the second terminal of the output inductor and a second current terminal coupled to the first node through the sense resistor and a control terminal receiving the first control signal, the current sensing transistor having the same transistor structure as the output voltage disconnect transistor and having a size that is a fraction of the output voltage disconnect transistor, wherein the current sensing transistor is turned on by the first control signal so as to conduct a portion of the inductor current flowing in the output inductor of the power stage, and the phase redundant controller receives the current sensing voltage signal measured by the sensing resistor so as to generate a current sensing signal indicative of the inductor current; an input voltage disconnect transistor coupled between the input voltage node and the input voltage, the input voltage disconnect transistor receiving a second control signal generated by the phase redundancy controller, wherein the second control signal has a first state to turn on the input voltage disconnect transistor to connect the high side power switch to the input voltage, and a second state to turn on the input voltage disconnect transistor to disconnect the high side power switch from the input voltage; If a fault condition is detected in the power stage, the phase redundancy controller will de-evaluate the second control signal and the first control signal, disconnect the input voltage disconnect transistor and the output voltage disconnect transistor to disconnect the power stage from the input voltage and the output voltage.

2. The power stage of claim 1, wherein the output voltage disconnect transistor comprises a MOS transistor, the current sensing transistor comprises a MOS transistor having the same transistor structure as the output voltage disconnect transistor, and the transistor channel width of the current sensing transistor is a fraction of the transistor channel width of the output voltage disconnect transistor.

3. The power stage of claim 2, wherein the output voltage disconnect transistor and the current sensing transistor are formed on a same semiconductor substrate.

4. The power stage of claim 3, wherein the output voltage disconnect transistor comprises a trench MOS transistor formed in a first plurality of trench cells, and the current sense transistor comprises a trench MOS transistor formed in a second plurality of trench cells, the second plurality of trench cells being a portion of the first plurality of trench cells.

5. The power stage of claim 4, wherein the sensing resistor is an independent resistor located outside the semiconductor substrate.

6. The power stage of claim 1, wherein the current sensing transistor has a transistor channel width that is 1 / 1000 to 1 / 10,000 of a transistor channel width of the output voltage disconnect transistor.

7. The power stage of claim 1, wherein an output node of the power stage is coupled to an output capacitor of a multi-phase switching power supply to form an LC filter circuit with an output inductor in response to an output voltage disconnect transistor closing to produce a regulated output voltage having a substantially constant amplitude at an output voltage node of the multi-phase switching power supply, the regulated output voltage being coupled to drive a load, wherein the first node comprises a node at the load for sensing the regulated output voltage provided to the load.

8. A power stage for use in a multi-phase switching power supply, receiving a pulse width modulation (PWM) signal associated with a phase of the power stage and an input voltage, and providing an output voltage, the power stage comprising: a high side power switch and a low side power switch; A switch output node connected in series between an input voltage node and a ground reference voltage and controlled by a PWM signal generates a switch output voltage at a switch output node between current terminals of a high-side power switch and a low-side power switch, and the switch output node is coupled to a first terminal of an output inductor; A phase redundant controller receives the PWM signal and generates a first control signal; as well as an output voltage disconnect transistor having a first current terminal coupled to the second terminal of the output inductor and a second current terminal coupled to an output node providing the output voltage, the output voltage disconnect transistor receiving the first control signal from the phase redundant controller, wherein the first control signal has a first state to turn on the output voltage disconnect transistor to connect the output inductor to the output node and a second state to turn on the output voltage disconnect transistor to disconnect the output inductor from the output node, wherein the phase redundant controller measures a voltage between a first current terminal and a second current terminal of the output voltage disconnect transistor, the voltage being indicative of an inductor current flowing in an output inductor of the power stage; an input voltage disconnect transistor coupled between the input voltage node and the input voltage, the input voltage disconnect transistor receiving a second control signal generated by the phase redundancy controller, wherein the second control signal has a first state to turn on the input voltage disconnect transistor to connect the high side power switch to the input voltage, and a second state to turn on the input voltage disconnect transistor to disconnect the high side power switch from the input voltage; If a fault condition is detected in the power stage, the phase redundancy controller will de-evaluate the second control signal and the first control signal, disconnect the input voltage disconnect transistor and the output voltage disconnect transistor to disconnect the power stage from the input voltage and the output voltage.

9. The power stage of claim 8, wherein the output voltage disconnect transistor comprises a MOSFET device, the voltage across the MOSFET device being indicative of the inductor current and an on-resistance of the MOSFET device.

10. The power stage of claim 8, wherein the phase redundant controller generates a current sense signal represented as a voltage and applies temperature compensation to the current sense signal.

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